1/*
2 * MPC52xx PSC in SPI mode driver.
3 *
4 * Maintainer: Dragos Carp
5 *
6 * Copyright (C) 2006 TOPTICA Photonics AG.
7 *
8 * This program is free software; you can redistribute  it and/or modify it
9 * under  the terms of  the GNU General  Public License as published by the
10 * Free Software Foundation;  either version 2 of the  License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/types.h>
16#include <linux/errno.h>
17#include <linux/interrupt.h>
18#include <linux/of_address.h>
19#include <linux/of_platform.h>
20#include <linux/workqueue.h>
21#include <linux/completion.h>
22#include <linux/io.h>
23#include <linux/delay.h>
24#include <linux/spi/spi.h>
25#include <linux/fsl_devices.h>
26#include <linux/slab.h>
27
28#include <asm/mpc52xx.h>
29#include <asm/mpc52xx_psc.h>
30
31#define MCLK 20000000 /* PSC port MClk in hz */
32
33struct mpc52xx_psc_spi {
34	/* fsl_spi_platform data */
35	void (*cs_control)(struct spi_device *spi, bool on);
36	u32 sysclk;
37
38	/* driver internal data */
39	struct mpc52xx_psc __iomem *psc;
40	struct mpc52xx_psc_fifo __iomem *fifo;
41	unsigned int irq;
42	u8 bits_per_word;
43	u8 busy;
44
45	struct workqueue_struct *workqueue;
46	struct work_struct work;
47
48	struct list_head queue;
49	spinlock_t lock;
50
51	struct completion done;
52};
53
54/* controller state */
55struct mpc52xx_psc_spi_cs {
56	int bits_per_word;
57	int speed_hz;
58};
59
60/* set clock freq, clock ramp, bits per work
61 * if t is NULL then reset the values to the default values
62 */
63static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
64		struct spi_transfer *t)
65{
66	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
67
68	cs->speed_hz = (t && t->speed_hz)
69			? t->speed_hz : spi->max_speed_hz;
70	cs->bits_per_word = (t && t->bits_per_word)
71			? t->bits_per_word : spi->bits_per_word;
72	cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
73	return 0;
74}
75
76static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
77{
78	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
79	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
80	struct mpc52xx_psc __iomem *psc = mps->psc;
81	u32 sicr;
82	u16 ccr;
83
84	sicr = in_be32(&psc->sicr);
85
86	/* Set clock phase and polarity */
87	if (spi->mode & SPI_CPHA)
88		sicr |= 0x00001000;
89	else
90		sicr &= ~0x00001000;
91	if (spi->mode & SPI_CPOL)
92		sicr |= 0x00002000;
93	else
94		sicr &= ~0x00002000;
95
96	if (spi->mode & SPI_LSB_FIRST)
97		sicr |= 0x10000000;
98	else
99		sicr &= ~0x10000000;
100	out_be32(&psc->sicr, sicr);
101
102	/* Set clock frequency and bits per word
103	 * Because psc->ccr is defined as 16bit register instead of 32bit
104	 * just set the lower byte of BitClkDiv
105	 */
106	ccr = in_be16((u16 __iomem *)&psc->ccr);
107	ccr &= 0xFF00;
108	if (cs->speed_hz)
109		ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
110	else /* by default SPI Clk 1MHz */
111		ccr |= (MCLK / 1000000 - 1) & 0xFF;
112	out_be16((u16 __iomem *)&psc->ccr, ccr);
113	mps->bits_per_word = cs->bits_per_word;
114
115	if (mps->cs_control)
116		mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
117}
118
119static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
120{
121	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
122
123	if (mps->cs_control)
124		mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
125}
126
127#define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
128/* wake up when 80% fifo full */
129#define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
130
131static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
132						struct spi_transfer *t)
133{
134	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
135	struct mpc52xx_psc __iomem *psc = mps->psc;
136	struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
137	unsigned rb = 0;	/* number of bytes receieved */
138	unsigned sb = 0;	/* number of bytes sent */
139	unsigned char *rx_buf = (unsigned char *)t->rx_buf;
140	unsigned char *tx_buf = (unsigned char *)t->tx_buf;
141	unsigned rfalarm;
142	unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
143	unsigned recv_at_once;
144	int last_block = 0;
145
146	if (!t->tx_buf && !t->rx_buf && t->len)
147		return -EINVAL;
148
149	/* enable transmiter/receiver */
150	out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
151	while (rb < t->len) {
152		if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
153			rfalarm = MPC52xx_PSC_RFALARM;
154			last_block = 0;
155		} else {
156			send_at_once = t->len - sb;
157			rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
158			last_block = 1;
159		}
160
161		dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
162		for (; send_at_once; sb++, send_at_once--) {
163			/* set EOF flag before the last word is sent */
164			if (send_at_once == 1 && last_block)
165				out_8(&psc->ircr2, 0x01);
166
167			if (tx_buf)
168				out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
169			else
170				out_8(&psc->mpc52xx_psc_buffer_8, 0);
171		}
172
173
174		/* enable interrupts and wait for wake up
175		 * if just one byte is expected the Rx FIFO genererates no
176		 * FFULL interrupt, so activate the RxRDY interrupt
177		 */
178		out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
179		if (t->len - rb == 1) {
180			out_8(&psc->mode, 0);
181		} else {
182			out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
183			out_be16(&fifo->rfalarm, rfalarm);
184		}
185		out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
186		wait_for_completion(&mps->done);
187		recv_at_once = in_be16(&fifo->rfnum);
188		dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
189
190		send_at_once = recv_at_once;
191		if (rx_buf) {
192			for (; recv_at_once; rb++, recv_at_once--)
193				rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
194		} else {
195			for (; recv_at_once; rb++, recv_at_once--)
196				in_8(&psc->mpc52xx_psc_buffer_8);
197		}
198	}
199	/* disable transmiter/receiver */
200	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
201
202	return 0;
203}
204
205static void mpc52xx_psc_spi_work(struct work_struct *work)
206{
207	struct mpc52xx_psc_spi *mps =
208		container_of(work, struct mpc52xx_psc_spi, work);
209
210	spin_lock_irq(&mps->lock);
211	mps->busy = 1;
212	while (!list_empty(&mps->queue)) {
213		struct spi_message *m;
214		struct spi_device *spi;
215		struct spi_transfer *t = NULL;
216		unsigned cs_change;
217		int status;
218
219		m = container_of(mps->queue.next, struct spi_message, queue);
220		list_del_init(&m->queue);
221		spin_unlock_irq(&mps->lock);
222
223		spi = m->spi;
224		cs_change = 1;
225		status = 0;
226		list_for_each_entry (t, &m->transfers, transfer_list) {
227			if (t->bits_per_word || t->speed_hz) {
228				status = mpc52xx_psc_spi_transfer_setup(spi, t);
229				if (status < 0)
230					break;
231			}
232
233			if (cs_change)
234				mpc52xx_psc_spi_activate_cs(spi);
235			cs_change = t->cs_change;
236
237			status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
238			if (status)
239				break;
240			m->actual_length += t->len;
241
242			if (t->delay_usecs)
243				udelay(t->delay_usecs);
244
245			if (cs_change)
246				mpc52xx_psc_spi_deactivate_cs(spi);
247		}
248
249		m->status = status;
250		if (m->complete)
251			m->complete(m->context);
252
253		if (status || !cs_change)
254			mpc52xx_psc_spi_deactivate_cs(spi);
255
256		mpc52xx_psc_spi_transfer_setup(spi, NULL);
257
258		spin_lock_irq(&mps->lock);
259	}
260	mps->busy = 0;
261	spin_unlock_irq(&mps->lock);
262}
263
264static int mpc52xx_psc_spi_setup(struct spi_device *spi)
265{
266	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
267	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
268	unsigned long flags;
269
270	if (spi->bits_per_word%8)
271		return -EINVAL;
272
273	if (!cs) {
274		cs = kzalloc(sizeof *cs, GFP_KERNEL);
275		if (!cs)
276			return -ENOMEM;
277		spi->controller_state = cs;
278	}
279
280	cs->bits_per_word = spi->bits_per_word;
281	cs->speed_hz = spi->max_speed_hz;
282
283	spin_lock_irqsave(&mps->lock, flags);
284	if (!mps->busy)
285		mpc52xx_psc_spi_deactivate_cs(spi);
286	spin_unlock_irqrestore(&mps->lock, flags);
287
288	return 0;
289}
290
291static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
292		struct spi_message *m)
293{
294	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
295	unsigned long flags;
296
297	m->actual_length = 0;
298	m->status = -EINPROGRESS;
299
300	spin_lock_irqsave(&mps->lock, flags);
301	list_add_tail(&m->queue, &mps->queue);
302	queue_work(mps->workqueue, &mps->work);
303	spin_unlock_irqrestore(&mps->lock, flags);
304
305	return 0;
306}
307
308static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
309{
310	kfree(spi->controller_state);
311}
312
313static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
314{
315	struct mpc52xx_psc __iomem *psc = mps->psc;
316	struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
317	u32 mclken_div;
318	int ret;
319
320	/* default sysclk is 512MHz */
321	mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
322	ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
323	if (ret)
324		return ret;
325
326	/* Reset the PSC into a known state */
327	out_8(&psc->command, MPC52xx_PSC_RST_RX);
328	out_8(&psc->command, MPC52xx_PSC_RST_TX);
329	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
330
331	/* Disable interrupts, interrupts are based on alarm level */
332	out_be16(&psc->mpc52xx_psc_imr, 0);
333	out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
334	out_8(&fifo->rfcntl, 0);
335	out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
336
337	/* Configure 8bit codec mode as a SPI master and use EOF flags */
338	/* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
339	out_be32(&psc->sicr, 0x0180C800);
340	out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
341
342	/* Set 2ms DTL delay */
343	out_8(&psc->ctur, 0x00);
344	out_8(&psc->ctlr, 0x84);
345
346	mps->bits_per_word = 8;
347
348	return 0;
349}
350
351static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
352{
353	struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
354	struct mpc52xx_psc __iomem *psc = mps->psc;
355
356	/* disable interrupt and wake up the work queue */
357	if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
358		out_be16(&psc->mpc52xx_psc_imr, 0);
359		complete(&mps->done);
360		return IRQ_HANDLED;
361	}
362	return IRQ_NONE;
363}
364
365/* bus_num is used only for the case dev->platform_data == NULL */
366static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
367				u32 size, unsigned int irq, s16 bus_num)
368{
369	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
370	struct mpc52xx_psc_spi *mps;
371	struct spi_master *master;
372	int ret;
373
374	master = spi_alloc_master(dev, sizeof *mps);
375	if (master == NULL)
376		return -ENOMEM;
377
378	dev_set_drvdata(dev, master);
379	mps = spi_master_get_devdata(master);
380
381	/* the spi->mode bits understood by this driver: */
382	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
383
384	mps->irq = irq;
385	if (pdata == NULL) {
386		dev_warn(dev,
387			 "probe called without platform data, no cs_control function will be called\n");
388		mps->cs_control = NULL;
389		mps->sysclk = 0;
390		master->bus_num = bus_num;
391		master->num_chipselect = 255;
392	} else {
393		mps->cs_control = pdata->cs_control;
394		mps->sysclk = pdata->sysclk;
395		master->bus_num = pdata->bus_num;
396		master->num_chipselect = pdata->max_chipselect;
397	}
398	master->setup = mpc52xx_psc_spi_setup;
399	master->transfer = mpc52xx_psc_spi_transfer;
400	master->cleanup = mpc52xx_psc_spi_cleanup;
401	master->dev.of_node = dev->of_node;
402
403	mps->psc = ioremap(regaddr, size);
404	if (!mps->psc) {
405		dev_err(dev, "could not ioremap I/O port range\n");
406		ret = -EFAULT;
407		goto free_master;
408	}
409	/* On the 5200, fifo regs are immediately ajacent to the psc regs */
410	mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
411
412	ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
413				mps);
414	if (ret)
415		goto free_master;
416
417	ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
418	if (ret < 0) {
419		dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
420		goto free_irq;
421	}
422
423	spin_lock_init(&mps->lock);
424	init_completion(&mps->done);
425	INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
426	INIT_LIST_HEAD(&mps->queue);
427
428	mps->workqueue = create_singlethread_workqueue(
429		dev_name(master->dev.parent));
430	if (mps->workqueue == NULL) {
431		ret = -EBUSY;
432		goto free_irq;
433	}
434
435	ret = spi_register_master(master);
436	if (ret < 0)
437		goto unreg_master;
438
439	return ret;
440
441unreg_master:
442	destroy_workqueue(mps->workqueue);
443free_irq:
444	free_irq(mps->irq, mps);
445free_master:
446	if (mps->psc)
447		iounmap(mps->psc);
448	spi_master_put(master);
449
450	return ret;
451}
452
453static int mpc52xx_psc_spi_of_probe(struct platform_device *op)
454{
455	const u32 *regaddr_p;
456	u64 regaddr64, size64;
457	s16 id = -1;
458
459	regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
460	if (!regaddr_p) {
461		dev_err(&op->dev, "Invalid PSC address\n");
462		return -EINVAL;
463	}
464	regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
465
466	/* get PSC id (1..6, used by port_config) */
467	if (op->dev.platform_data == NULL) {
468		const u32 *psc_nump;
469
470		psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL);
471		if (!psc_nump || *psc_nump > 5) {
472			dev_err(&op->dev, "Invalid cell-index property\n");
473			return -EINVAL;
474		}
475		id = *psc_nump + 1;
476	}
477
478	return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
479				irq_of_parse_and_map(op->dev.of_node, 0), id);
480}
481
482static int mpc52xx_psc_spi_of_remove(struct platform_device *op)
483{
484	struct spi_master *master = spi_master_get(platform_get_drvdata(op));
485	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
486
487	flush_workqueue(mps->workqueue);
488	destroy_workqueue(mps->workqueue);
489	spi_unregister_master(master);
490	free_irq(mps->irq, mps);
491	if (mps->psc)
492		iounmap(mps->psc);
493	spi_master_put(master);
494
495	return 0;
496}
497
498static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
499	{ .compatible = "fsl,mpc5200-psc-spi", },
500	{ .compatible = "mpc5200-psc-spi", }, /* old */
501	{}
502};
503
504MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
505
506static struct platform_driver mpc52xx_psc_spi_of_driver = {
507	.probe = mpc52xx_psc_spi_of_probe,
508	.remove = mpc52xx_psc_spi_of_remove,
509	.driver = {
510		.name = "mpc52xx-psc-spi",
511		.of_match_table = mpc52xx_psc_spi_of_match,
512	},
513};
514module_platform_driver(mpc52xx_psc_spi_of_driver);
515
516MODULE_AUTHOR("Dragos Carp");
517MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
518MODULE_LICENSE("GPL");
519