Searched refs:control (Results 1 - 200 of 6000) sorted by relevance

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/linux-4.1.27/arch/x86/kernel/cpu/
H A Dpowerflags.c11 "fid", /* frequency id control */
12 "vid", /* voltage id control */
14 "tm", /* hardware thermal control */
15 "stc", /* software thermal control */
16 "100mhzsteps", /* 100 MHz multiplier control */
17 "hwpstate", /* hardware P-state control */
/linux-4.1.27/arch/sh/include/mach-common/mach/
H A Dhighlander.h12 #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
13 #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
19 #define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
20 #define PA_PCICD (PA_BCR+0x0010) /* PCI Conector detect control */
22 #define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
23 #define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
24 #define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
25 #define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
26 #define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */
27 #define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */
28 #define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
29 #define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
30 #define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
31 #define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
32 #define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
33 #define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */
34 #define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
35 #define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
37 #define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
38 #define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */
39 #define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
40 #define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
41 #define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
42 #define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
43 #define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */
44 #define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
45 #define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
46 #define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
47 #define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */
48 #define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
49 #define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
50 #define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */
51 #define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
52 #define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
53 #define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */
54 #define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
55 #define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */
56 #define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
57 #define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
58 #define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
59 #define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
60 #define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
61 #define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */
62 #define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */
63 #define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */
64 #define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
65 #define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
67 #define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
77 #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
78 #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
79 #define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */
80 #define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */
81 #define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */
82 #define PA_PCICD (PA_BCR+0x000a) /* PCI Conector detect control */
83 #define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
84 #define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */
85 #define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */
86 #define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */
87 #define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */
88 #define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */
89 #define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */
90 #define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */
91 #define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */
92 #define PA_EXTPLR (PA_BCR+0x001e) /* Extension Pin Polarity control */
93 #define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
94 #define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
95 #define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
96 #define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
97 #define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
98 #define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */
99 #define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */
100 #define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */
101 #define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
102 #define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
104 #define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */
105 #define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */
106 #define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */
107 #define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */
108 #define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */
109 #define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */
110 #define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
111 #define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
112 #define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
113 #define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */
114 #define PA_SMSMADR (PA_BCR+0x0502) /* 2-wire Serial Slave control */
115 #define PA_SMMR (PA_BCR+0x0504) /* 2-wire Serial Mode control */
116 #define PA_SMSADR1 (PA_BCR+0x0506) /* 2-wire Serial Address1 control */
117 #define PA_SMTRDR1 (PA_BCR+0x0546) /* 2-wire Serial Data1 control */
H A Dr2d.h15 #define PA_IRLMON 0xa4000002 /* Interrupt Status control */
16 #define PA_CFCTL 0xa4000004 /* CF Timing control */
17 #define PA_CFPOW 0xa4000006 /* CF Power control */
18 #define PA_DISPCTL 0xa4000008 /* Display Timing control */
19 #define PA_SDMPOW 0xa400000a /* SD Power control */
20 #define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */
21 #define PA_PCICD 0xa400000e /* PCI Extension detect control */
22 #define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */
24 #define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */
25 #define PA_R2D1_CFRST 0xa4000024 /* CF Reset control */
26 #define PA_R2D1_ADMRTS 0xa4000026 /* SD Reset control */
27 #define PA_R2D1_EXTRST 0xa4000028 /* Extension Reset control */
30 #define PA_R2DPLUS_CFRST 0xa4000022 /* CF Reset control */
31 #define PA_R2DPLUS_ADMRTS 0xa4000024 /* SD Reset control */
32 #define PA_R2DPLUS_EXTRST 0xa4000026 /* Extension Reset control */
36 #define PA_POWOFF 0xa4000030 /* Board Power OFF control */
38 #define PA_INPORT 0xa4000034 /* KEY Input Port control */
39 #define PA_OUTPORT 0xa4000036 /* LED control */
H A Durquell.h44 #define SLEDR_OFS 0x0130 /* LED control resister */
55 #define DDR3BUPCR_OFS 0x1050 /* DDR3 Backup control register */
56 #define SSICODECCR_OFS 0x1060 /* SSI-CODEC control register */
59 #define LATCHCR_OFS 0x3000 /* Latch control register */
/linux-4.1.27/include/uapi/linux/
H A Dtermios.h17 #define RTSXOFF 0x0001 /* RTS flow control on input */
18 #define CTSXON 0x0002 /* CTS flow control on output */
19 #define DTRXOFF 0x0004 /* DTR flow control on input */
20 #define DSRXON 0x0008 /* DCD flow control on output */
H A Dbcm933xx_hcs.h12 __u16 control; member in struct:bcm_hcs
/linux-4.1.27/sound/aoa/soundbus/i2sbus/
H A DMakefile2 snd-aoa-i2sbus-objs := core.o pcm.o control.o
H A Dcore.c86 i2sbus_control_remove_dev(i2sdev->control, i2sdev); i2sbus_release_dev()
153 struct i2sbus_control *control, i2sbus_add_dev()
160 static const char *rnames[] = { "i2sbus: %s (control)", i2sbus_add_dev()
230 dev->control = control; i2sbus_add_dev()
298 if (i2sbus_control_add_dev(dev->control, dev)) { i2sbus_add_dev()
299 printk(KERN_ERR "i2sbus: control layer didn't like bus\n"); i2sbus_add_dev()
309 i2sbus_control_cell(dev->control, dev, 1); i2sbus_add_dev()
310 i2sbus_control_enable(dev->control, dev); i2sbus_add_dev()
311 i2sbus_control_clock(dev->control, dev, 1); i2sbus_add_dev()
334 struct i2sbus_control *control = NULL; i2sbus_probe() local
336 err = i2sbus_control_init(dev, &control); i2sbus_probe()
339 if (!control) { i2sbus_probe()
347 got += i2sbus_add_dev(dev, control, np); i2sbus_probe()
353 i2sbus_control_destroy(control); i2sbus_probe()
357 dev_set_drvdata(&dev->ofdev.dev, control); i2sbus_probe()
364 struct i2sbus_control *control = dev_get_drvdata(&dev->ofdev.dev); i2sbus_remove() local
367 list_for_each_entry_safe(i2sdev, tmp, &control->list, item) i2sbus_remove()
376 struct i2sbus_control *control = dev_get_drvdata(&dev->ofdev.dev); i2sbus_suspend() local
381 list_for_each_entry(i2sdev, &control->list, item) { i2sbus_suspend()
404 struct i2sbus_control *control = dev_get_drvdata(&dev->ofdev.dev); i2sbus_resume() local
409 list_for_each_entry(i2sdev, &control->list, item) { i2sbus_resume()
152 i2sbus_add_dev(struct macio_dev *macio, struct i2sbus_control *control, struct device_node *np) i2sbus_add_dev() argument
/linux-4.1.27/include/sound/
H A Dseq_midi_emul.h49 unsigned char control[128]; /* Current value of all controls */ member in struct:snd_midi_channel
87 void (*control)(void *private_data, int type, struct snd_midi_channel *chan); member in struct:snd_midi_op
108 #define gm_bank_select control[0]
109 #define gm_modulation control[1]
110 #define gm_breath control[2]
111 #define gm_foot_pedal control[4]
112 #define gm_portamento_time control[5]
113 #define gm_data_entry control[6]
114 #define gm_volume control[7]
115 #define gm_balance control[8]
116 #define gm_pan control[10]
117 #define gm_expression control[11]
118 #define gm_effect_control1 control[12]
119 #define gm_effect_control2 control[13]
120 #define gm_slider1 control[16]
121 #define gm_slider2 control[17]
122 #define gm_slider3 control[18]
123 #define gm_slider4 control[19]
125 #define gm_bank_select_lsb control[32]
126 #define gm_modulation_wheel_lsb control[33]
127 #define gm_breath_lsb control[34]
128 #define gm_foot_pedal_lsb control[36]
129 #define gm_portamento_time_lsb control[37]
130 #define gm_data_entry_lsb control[38]
131 #define gm_volume_lsb control[39]
132 #define gm_balance_lsb control[40]
133 #define gm_pan_lsb control[42]
134 #define gm_expression_lsb control[43]
135 #define gm_effect_control1_lsb control[44]
136 #define gm_effect_control2_lsb control[45]
138 #define gm_sustain control[MIDI_CTL_SUSTAIN]
140 #define gm_portamento control[MIDI_CTL_PORTAMENTO]
141 #define gm_sostenuto control[MIDI_CTL_SOSTENUTO]
148 #define SNDRV_GM_BANK_SELECT(cp) (((cp)->control[0]<<7)|((cp)->control[32]))
149 #define SNDRV_GM_MODULATION_WHEEL(cp) (((cp)->control[1]<<7)|((cp)->control[33]))
150 #define SNDRV_GM_BREATH(cp) (((cp)->control[2]<<7)|((cp)->control[34]))
151 #define SNDRV_GM_FOOT_PEDAL(cp) (((cp)->control[4]<<7)|((cp)->control[36]))
152 #define SNDRV_GM_PORTAMENTO_TIME(cp) (((cp)->control[5]<<7)|((cp)->control[37]))
153 #define SNDRV_GM_DATA_ENTRY(cp) (((cp)->control[6]<<7)|((cp)->control[38]))
154 #define SNDRV_GM_VOLUME(cp) (((cp)->control[7]<<7)|((cp)->control[39]))
155 #define SNDRV_GM_BALANCE(cp) (((cp)->control[8]<<7)|((cp)->control[40]))
156 #define SNDRV_GM_PAN(cp) (((cp)->control[10]<<7)|((cp)->control[42]))
157 #define SNDRV_GM_EXPRESSION(cp) (((cp)->control[11]<<7)|((cp)->control[43]))
H A Dcs4231-regs.h36 #define CS4231_LEFT_INPUT 0x00 /* left input control */
37 #define CS4231_RIGHT_INPUT 0x01 /* right input control */
38 #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
39 #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
40 #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
41 #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
42 #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
43 #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
45 #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
46 #define CS4231_PIN_CTRL 0x0a /* pin control */
49 #define CS4231_LOOPBACK 0x0d /* loopback control */
56 #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
57 #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
60 #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
62 #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
66 #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
68 #define CS4231_MONO_CTRL 0x1a /* mono input/output control */
69 #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
70 #define AD1845_PWR_DOWN 0x1b /* power down control */
71 #define CS4235_LEFT_MASTER 0x1b /* left master output control */
74 #define CS4235_RIGHT_MASTER 0x1d /* right master output control */
121 /* definitions for interface control register - CS4231_IFACE_CTRL */
131 /* definitions for pin control register - CS4231_PIN_CTRL */
134 #define CS4231_XCTL1 0x40 /* external control #1 */
135 #define CS4231_XCTL0 0x80 /* external control #0 */
142 /* definitions for misc control register - CS4231_MISC_INFO */
163 #define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */
164 #define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */
H A Dalc5623.h5 /* Lineout/Speaker Amps Vmid ratio control */
H A Dtea6330t.h5 * Routines for control of TEA6330T circuit.
6 * Sound fader control circuit for car radios.
H A Dak4641.h16 * @gpio_power: GPIO to control external power to AK4641
H A Dmax9768.h13 * @mute_gpio: GPIO to MUTE pin. If not valid, control for mute won't be added
/linux-4.1.27/drivers/media/i2c/
H A Dadv7183_regs.h23 #define ADV7183_IN_CTRL 0x00 /* Input control */
25 #define ADV7183_OUT_CTRL 0x03 /* Output control */
26 #define ADV7183_EXT_OUT_CTRL 0x04 /* Extended output control */
33 #define ADV7183_ADI_CTRL 0x0E /* ADI control */
39 #define ADV7183_ANAL_CLAMP_CTRL 0x14 /* Analog clamp control */
40 #define ADV7183_DIGI_CLAMP_CTRL_1 0x15 /* Digital clamp control 1 */
41 #define ADV7183_SHAP_FILT_CTRL 0x17 /* Shaping filter control */
42 #define ADV7183_SHAP_FILT_CTRL_2 0x18 /* Shaping filter control 2 */
43 #define ADV7183_COMB_FILT_CTRL 0x19 /* Comb filter control */
44 #define ADV7183_ADI_CTRL_2 0x1D /* ADI control 2 */
45 #define ADV7183_PIX_DELAY_CTRL 0x27 /* Pixel delay control */
46 #define ADV7183_MISC_GAIN_CTRL 0x2B /* Misc gain control */
47 #define ADV7183_AGC_MODE_CTRL 0x2C /* AGC mode control */
48 #define ADV7183_CHRO_GAIN_CTRL_1 0x2D /* Chroma gain control 1 */
49 #define ADV7183_CHRO_GAIN_CTRL_2 0x2E /* Chroma gain control 2 */
50 #define ADV7183_LUMA_GAIN_CTRL_1 0x2F /* Luma gain control 1 */
51 #define ADV7183_LUMA_GAIN_CTRL_2 0x30 /* Luma gain control 2 */
52 #define ADV7183_VS_FIELD_CTRL_1 0x31 /* Vsync field control 1 */
53 #define ADV7183_VS_FIELD_CTRL_2 0x32 /* Vsync field control 2 */
54 #define ADV7183_VS_FIELD_CTRL_3 0x33 /* Vsync field control 3 */
55 #define ADV7183_HS_POS_CTRL_1 0x34 /* Hsync position control 1 */
56 #define ADV7183_HS_POS_CTRL_2 0x35 /* Hsync position control 2 */
57 #define ADV7183_HS_POS_CTRL_3 0x36 /* Hsync position control 3 */
59 #define ADV7183_NTSC_COMB_CTRL 0x38 /* NTSC comb control */
60 #define ADV7183_PAL_COMB_CTRL 0x39 /* PAL comb control */
61 #define ADV7183_ADC_CTRL 0x3A /* ADC control */
62 #define ADV7183_MAN_WIN_CTRL 0x3D /* Manual window control */
63 #define ADV7183_RESAMPLE_CTRL 0x41 /* Resample control */
91 #define ADV7183_LETTERBOX_CTRL_1 0xDC /* Letterbox control 1 */
92 #define ADV7183_LETTERBOX_CTRL_2 0xDD /* Letterbox control 2 */
104 #define ADV7183_IF_COMP_CTRL 0xF8 /* IF comp control */
105 #define ADV7183_VS_MODE_CTRL 0xF9 /* VS mode control */
H A Dsaa711x_regs.h242 "Analog input control 1"},
244 "Analog input control 2"},
246 "Analog input control 3"},
248 "Analog input control 4"},
256 "Sync control"},
258 "Luminance control"},
260 "Luminance brightness control"},
262 "Luminance contrast control"},
264 "Chrominance saturation control"},
266 "Chrominance hue control"},
268 "Chrominance control 1"},
270 "Chrominance gain control"},
272 "Chrominance control 2"},
274 "Mode/delay control"},
276 "RT signal control"},
278 "RT/X port output control"},
280 "Analog/ADC/compatibility control"},
288 "Raw data gain control",},
290 "Raw data offset control",},
307 "Analog input control 5"},
309 "Analog input control 6"},
311 "Analog input control 7"},
316 "Component brightness control"},
318 "Component contrast control"},
320 "Component saturation control"},
345 "Slicer control 1"},
371 "Global control 1"},
382 "I port FIFO flag control and arbitration"},
386 "Power save/ADC port control"},
394 "Task A: Task handling control"},
423 "Task A: Luminance brightness control"},
425 "Task A: Luminance contrast control"},
427 "Task A: Chrominance saturation control"},
448 "Task A: Vertical scaling mode control"},
470 "Task B: Task handling control"},
499 "Task B: Luminance brightness control"},
501 "Task B: Luminance contrast control"},
503 "Task B: Chrominance saturation control"},
524 "Task B: Vertical scaling mode control"},
H A Dtvp5150_reg.h16 #define TVP5150_COLOR_KIL_THSH_CTL 0x06 /* Color killer threshold control */
17 #define TVP5150_LUMA_PROC_CTL_1 0x07 /* Luminance processing control #1 */
18 #define TVP5150_LUMA_PROC_CTL_2 0x08 /* Luminance processing control #2 */
19 #define TVP5150_BRIGHT_CTL 0x09 /* Brightness control */
20 #define TVP5150_SATURATION_CTL 0x0a /* Color saturation control */
21 #define TVP5150_HUE_CTL 0x0b /* Hue control */
22 #define TVP5150_CONTRAST_CTL 0x0c /* Contrast control */
24 #define TVP5150_LUMA_PROC_CTL_3 0x0e /* Luminance processing control #3 */
40 #define TVP5150_CHROMA_PROC_CTL_1 0x1a /* Chrominance processing control #1 */
41 #define TVP5150_CHROMA_PROC_CTL_2 0x1b /* Chrominance processing control #2 */
130 #define TVP5150_FIFO_OUT_CTRL 0xcd /* FIFO output control */
/linux-4.1.27/fs/fuse/
H A DMakefile8 fuse-objs := dev.o dir.o file.o inode.o control.o
/linux-4.1.27/sound/usb/caiaq/
H A DMakefile1 snd-usb-caiaq-y := device.o audio.o midi.o control.o
/linux-4.1.27/drivers/s390/cio/
H A Dorb.h19 u32 key:4; /* flags, like key, suspend control, etc. */
20 u32 spnd:1; /* suspend control */
22 u32 mod:1; /* modification control */
23 u32 sync:1; /* synchronize control */
24 u32 fmt:1; /* format control */
25 u32 pfch:1; /* prefetch control */
26 u32 isic:1; /* initial-status-interruption control */
27 u32 alcc:1; /* address-limit-checking control */
28 u32 ssic:1; /* suppress-suspended-interr. control */
30 u32 c64:1; /* IDAW/QDIO 64 bit control */
31 u32 i2k:1; /* IDAW 2/4kB block size control */
35 u32 orbx:1; /* ORB extension control */
/linux-4.1.27/drivers/net/wireless/ath/ath9k/
H A Dar9003_mac.h75 u32 ctl3; /* DMA control 3 */
77 u32 ctl5; /* DMA control 5 */
79 u32 ctl7; /* DMA control 7 */
81 u32 ctl9; /* DMA control 9 */
82 u32 ctl10; /* DMA control 10 */
83 u32 ctl11; /* DMA control 11 */
84 u32 ctl12; /* DMA control 12 */
85 u32 ctl13; /* DMA control 13 */
86 u32 ctl14; /* DMA control 14 */
87 u32 ctl15; /* DMA control 15 */
88 u32 ctl16; /* DMA control 16 */
89 u32 ctl17; /* DMA control 17 */
90 u32 ctl18; /* DMA control 18 */
91 u32 ctl19; /* DMA control 19 */
92 u32 ctl20; /* DMA control 20 */
93 u32 ctl21; /* DMA control 21 */
94 u32 ctl22; /* DMA control 22 */
95 u32 ctl23; /* DMA control 23 */
/linux-4.1.27/drivers/media/usb/pvrusb2/
H A Dpvrusb2-ctrl.h33 /* Set the given control. */
36 /* Set/clear specific bits of the given control. */
39 /* Get the current value of the given control. */
42 /* Retrieve control's type */
45 /* Retrieve control's maximum value (int type) */
48 /* Retrieve control's minimum value (int type) */
51 /* Retrieve control's default value (any type) */
54 /* Retrieve control's enumeration count (enum only) */
57 /* Retrieve control's valid mask bits (bit mask only) */
60 /* Retrieve the control's name */
63 /* Retrieve the control's desc */
66 /* Retrieve a control enumeration or bit mask value */
70 /* Return true if control is writable */
73 /* Return V4L flags value for control (or zero if there is no v4l control
74 actually under this control) */
77 /* Return V4L ID for this control or zero if none */
80 /* Return true if control has custom symbolic representation */
/linux-4.1.27/include/media/
H A Dv4l2-ctrls.h39 /** union v4l2_ctrl_ptr - A pointer to a control value.
58 /** struct v4l2_ctrl_ops - The control operations that the driver has to provide.
59 * @g_volatile_ctrl: Get a new value for this control. Generally only relevant
60 * for volatile (and usually read-only) controls such as a control
64 * @try_ctrl: Test whether the control's value is valid. Only relevant when
66 * @s_ctrl: Actually set the new control value. s_ctrl is compulsory. The
76 /** struct v4l2_ctrl_type_ops - The control type operations that the driver has to provide.
95 /** struct v4l2_ctrl - The control structure.
97 * @ev_subs: The list of control event subscriptions.
98 * @handler: The handler that owns the control.
101 * @done: Internal flag: set for each processed control.
102 * @is_new: Set when the user specified a new value for this control. It
107 * @is_private: If set, then this control is private to its handler and it
110 * @is_auto: If set, then this control selects whether the other cluster
114 * @is_int: If set, then this control has a simple integer value (i.e. it
116 * @is_string: If set, then this control has type V4L2_CTRL_TYPE_STRING.
117 * @is_ptr: If set, then this control is an array and/or has type >= V4L2_CTRL_COMPOUND_TYPES
120 * @is_array: If set, then this control contains an N-dimensional array.
124 * control's value changes.
126 * of the auto control that determines if that control is in
127 * manual mode. So if the value of the auto control equals this
130 * @ops: The control ops.
131 * @type_ops: The control type ops.
132 * @id: The control ID.
133 * @name: The control name.
134 * @type: The control type.
135 * @minimum: The control's minimum value.
136 * @maximum: The control's maximum value.
137 * @default_value: The control's default value.
138 * @step: The control's step value for non-menu controls.
140 * @elem_size: The size in bytes of the control.
143 * @menu_skip_mask: The control's skip mask for menu controls. This makes it
153 * @flags: The control's flags.
154 * @cur: The control's current value.
155 * @val: The control's new s32 value.
156 * @val64: The control's new s64 value.
157 * @priv: The control's private pointer. For use by the driver. It is
158 * untouched by the control framework. Note that this pointer is
159 * not freed when the control is deleted. Should this be needed
213 /** struct v4l2_ctrl_ref - The control reference.
216 * @ctrl: The actual control information.
219 * Each control handler has a list of these refs. The list_head is used to
220 * keep a sorted-by-control-ID list of all controls, while the next pointer
221 * is used to link the control in the hash's bucket.
230 /** struct v4l2_ctrl_handler - The control handler keeps track of all the
234 * @lock: Lock to control access to this handler and its controls.
237 * @ctrl_refs: The list of control references.
238 * @cached: The last found control reference. It is common that the same
239 * control is needed multiple times, so this is a simple
241 * @buckets: Buckets for the hashing. Allows for quick control lookup.
242 * @notify: A notify callback that is called whenever the control changes value.
247 * @error: The error code of the first failed control addition.
263 * @ops: The control ops.
264 * @type_ops: The control type ops. Only needed for compound controls.
265 * @id: The control ID.
266 * @name: The control name.
267 * @type: The control type.
268 * @min: The control's minimum value.
269 * @max: The control's maximum value.
270 * @step: The control's step value for non-menu controls.
271 * @def: The control's default value.
273 * @elem_size: The size in bytes of the control.
274 * @flags: The control's flags.
275 * @menu_skip_mask: The control's skip mask for menu controls. This makes it
285 * @is_private: If set, then this control is private to its handler and it
307 /** v4l2_ctrl_fill() - Fill in the control fields based on the control ID.
318 * control handling only. Once all drivers are converted to use the new
319 * control framework this function will no longer be exported.
325 /** v4l2_ctrl_handler_init_class() - Initialize the control handler.
326 * @hdl: The control handler.
331 * are allocated) or the control lookup becomes slower (not enough
365 * the control list.
366 * @hdl: The control handler.
373 * associated with the control.
374 * @ctrl: The control to lock.
382 * associated with the control.
383 * @ctrl: The control to unlock.
391 * to the handler to initialize the hardware to the current control values.
392 * @hdl: The control handler.
401 * @hdl: The control handler.
402 * @prefix: The prefix to use when logging the control values. If the
415 * control.
416 * @hdl: The control handler.
417 * @cfg: The control's configuration data.
418 * @priv: The control's driver-specific private data.
426 /** v4l2_ctrl_new_std() - Allocate and initialize a new standard V4L2 non-menu control.
427 * @hdl: The control handler.
428 * @ops: The control ops.
429 * @id: The control ID.
430 * @min: The control's minimum value.
431 * @max: The control's maximum value.
432 * @step: The control's step value
433 * @def: The control's default value.
435 * If the &v4l2_ctrl struct could not be allocated, or the control
439 * If @id refers to a menu control, then this function will return NULL.
447 /** v4l2_ctrl_new_std_menu() - Allocate and initialize a new standard V4L2 menu control.
448 * @hdl: The control handler.
449 * @ops: The control ops.
450 * @id: The control ID.
451 * @max: The control's maximum value.
452 * @mask: The control's skip mask for menu controls. This makes it
458 * @def: The control's default value.
463 * If @id refers to a non-menu control, then this function will return NULL.
469 /** v4l2_ctrl_new_std_menu_items() - Create a new standard V4L2 menu control
471 * @hdl: The control handler.
472 * @ops: The control ops.
473 * @id: The control ID.
474 * @max: The control's maximum value.
475 * @mask: The control's skip mask for menu controls. This makes it
481 * @def: The control's default value.
485 * menu of this control.
492 /** v4l2_ctrl_new_int_menu() - Create a new standard V4L2 integer menu control.
493 * @hdl: The control handler.
494 * @ops: The control ops.
495 * @id: The control ID.
496 * @max: The control's maximum value.
497 * @def: The control's default value.
498 * @qmenu_int: The control's menu entries.
503 * If @id refers to a non-integer-menu control, then this function will return NULL.
509 /** v4l2_ctrl_add_ctrl() - Add a control from another handler to this handler.
510 * @hdl: The control handler.
511 * @ctrl: The control to add.
513 * It will return NULL if it was unable to add the control reference.
514 * If the control already belonged to the handler, then it will do
522 * @hdl: The control handler.
523 * @add: The control handler whose controls you want to add to
524 * the @hdl control handler.
538 * @ctrl: The control that is filtered.
550 * @controls: The cluster control array of size @ncontrols.
558 * @controls: The cluster control array of size @ncontrols. The first control
559 * must be the 'auto' control (e.g. autogain, autoexposure, etc.)
560 * @manual_val: The value for the first control in the cluster that equals the
562 * @set_volatile: If true, then all controls except the first auto control will
565 * Use for control groups where one control selects some automatic feature and
572 * When the autofoo control is set to automatic, then any manual controls
573 * are set to inactive and any reads will call g_volatile_ctrl (if the control
576 * When the autofoo control is set to manual, then any manual controls will
581 * on the autofoo control and V4L2_CTRL_FLAG_INACTIVE on the foo control(s)
588 /** v4l2_ctrl_find() - Find a control with the given ID.
589 * @hdl: The control handler.
590 * @id: The control ID to find.
597 /** v4l2_ctrl_activate() - Make the control active or inactive.
598 * @ctrl: The control to (de)activate.
599 * @active: True if the control should become active.
606 * This function assumes that the control handler is locked.
610 /** v4l2_ctrl_grab() - Mark the control as grabbed or not grabbed.
611 * @ctrl: The control to (de)activate.
612 * @grabbed: True if the control should become grabbed.
620 * This function assumes that the control handler is not locked and will
630 /** v4l2_ctrl_modify_range() - Update the range of a control.
631 * @ctrl: The control to update.
632 * @min: The control's minimum value.
633 * @max: The control's maximum value.
634 * @step: The control's step value
635 * @def: The control's default value.
637 * Update the range of a control on the fly. This works for control types
642 * control type.
644 * This function assumes that the control handler is not locked and will
659 /** v4l2_ctrl_notify() - Function to set a notify callback for a control.
660 * @ctrl: The control.
664 * This function sets a callback function for the control. If @ctrl is NULL,
673 /** v4l2_ctrl_get_name() - Get the name of the control
674 * @id: The control ID.
676 * This function returns the name of the given control ID or NULL if it isn't
677 * a known control.
681 /** v4l2_ctrl_get_menu() - Get the menu string array of the control
682 * @id: The control ID.
685 * given control ID or NULL if it isn't a known menu control.
689 /** v4l2_ctrl_get_int_menu() - Get the integer menu array of the control
690 * @id: The control ID.
693 * This function returns the integer array of the given control ID or NULL if it
694 * if it isn't a known integer menu control.
698 /** v4l2_ctrl_g_ctrl() - Helper function to get the control's value from within a driver.
699 * @ctrl: The control.
701 * This returns the control's value safely by going through the control
702 * framework. This function will lock the control's handler, so it cannot be
711 /** v4l2_ctrl_s_ctrl() - Helper function to set the control's value from within a driver.
712 * @ctrl: The control.
715 * This set the control's new value safely by going through the control
716 * framework. This function will lock the control's handler, so it cannot be
732 /** v4l2_ctrl_g_ctrl_int64() - Helper function to get a 64-bit control's value from within a driver.
733 * @ctrl: The control.
735 * This returns the control's value safely by going through the control
736 * framework. This function will lock the control's handler, so it cannot be
746 /** v4l2_ctrl_s_ctrl_int64() - Helper function to set a 64-bit control's value from within a driver.
747 * @ctrl: The control.
750 * This set the control's new value safely by going through the control
751 * framework. This function will lock the control's handler, so it cannot be
770 /** v4l2_ctrl_s_ctrl_string() - Helper function to set a control's string value from within a driver.
771 * @ctrl: The control.
774 * This set the control's new string safely by going through the control
775 * framework. This function will lock the control's handler, so it cannot be
791 /* Internal helper functions that deal with control events. */
801 control events. */
805 /* Can be used as a poll function that just polls for control events. */
830 /* Can be used as a subscribe_event function that just subscribes control
835 /* Log all controls owned by subdev's control handler. */
/linux-4.1.27/arch/m32r/include/asm/opsput/
H A Dopsput_lan.h29 * ICUCR3: control register for CFIREQ# interrupt
30 * ICUCR4: control register for CFC Card insert interrupt
31 * ICUCR5: control register for CFC Card eject interrupt
32 * ICUCR6: control register for external interrupt
33 * ICUCR11: control register for MMC Card insert/eject interrupt
34 * ICUCR13: control register for SC error interrupt
35 * ICUCR14: control register for SC receive interrupt
36 * ICUCR15: control register for SC send interrupt
37 * ICUCR16: control register for SIO0 receive interrupt
38 * ICUCR17: control register for SIO0 send interrupt
/linux-4.1.27/arch/powerpc/boot/
H A Dmv64x60_i2c.c75 static int mv64x60_i2c_control(int control, int status) mv64x60_i2c_control() argument
77 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); mv64x60_i2c_control()
81 static int mv64x60_i2c_read_byte(int control, int status) mv64x60_i2c_read_byte() argument
83 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); mv64x60_i2c_read_byte()
89 static int mv64x60_i2c_write_byte(int data, int control, int status) mv64x60_i2c_write_byte() argument
92 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); mv64x60_i2c_write_byte()
101 int control; mv64x60_i2c_read() local
118 control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN; mv64x60_i2c_read()
120 if (mv64x60_i2c_control(control, status) < 0) mv64x60_i2c_read()
125 control = MV64x60_I2C_CONTROL_TWSIEN; mv64x60_i2c_read()
127 if (mv64x60_i2c_write_byte(data, control, status) < 0) mv64x60_i2c_read()
131 control = MV64x60_I2C_CONTROL_TWSIEN; mv64x60_i2c_read()
134 if (mv64x60_i2c_write_byte(offset >> 8, control, status) < 0) mv64x60_i2c_read()
137 if (mv64x60_i2c_write_byte(offset, control, status) < 0) mv64x60_i2c_read()
141 control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN; mv64x60_i2c_read()
143 if (mv64x60_i2c_control(control, status) < 0) mv64x60_i2c_read()
148 control = MV64x60_I2C_CONTROL_TWSIEN; mv64x60_i2c_read()
150 if (mv64x60_i2c_write_byte(data, control, status) < 0) mv64x60_i2c_read()
154 control = MV64x60_I2C_CONTROL_ACK | MV64x60_I2C_CONTROL_TWSIEN; mv64x60_i2c_read()
158 data = mv64x60_i2c_read_byte(control, status); mv64x60_i2c_read()
167 control = MV64x60_I2C_CONTROL_TWSIEN; mv64x60_i2c_read()
169 data = mv64x60_i2c_read_byte(control, status); mv64x60_i2c_read()
175 control = MV64x60_I2C_CONTROL_STOP | MV64x60_I2C_CONTROL_TWSIEN; mv64x60_i2c_read()
177 if (mv64x60_i2c_control(control, status) < 0) mv64x60_i2c_read()
/linux-4.1.27/drivers/media/usb/hdpvr/
H A DMakefile1 hdpvr-objs := hdpvr-control.o hdpvr-core.o hdpvr-video.o hdpvr-i2c.o
/linux-4.1.27/sound/firewire/oxfw/
H A DMakefile1 snd-oxfw-objs := oxfw-command.o oxfw-stream.o oxfw-control.o oxfw-pcm.o \
H A Doxfw-control.c39 buf[5] = 0x10; /* control attribute: current */ oxfw_mute_command()
42 buf[8] = 0x01; /* control selector: mute */ oxfw_mute_command()
43 buf[9] = 0x01; /* control data length */ oxfw_mute_command()
97 buf[5] = attribute; /* control attribute */ oxfw_volume_command()
100 buf[8] = 0x02; /* control selector: volume */ oxfw_volume_command()
101 buf[9] = 0x02; /* control data length */ oxfw_volume_command()
134 static int oxfw_mute_get(struct snd_kcontrol *control, oxfw_mute_get() argument
137 struct snd_oxfw *oxfw = control->private_data; oxfw_mute_get()
144 static int oxfw_mute_put(struct snd_kcontrol *control, oxfw_mute_put() argument
147 struct snd_oxfw *oxfw = control->private_data; oxfw_mute_put()
164 static int oxfw_volume_info(struct snd_kcontrol *control, oxfw_volume_info() argument
167 struct snd_oxfw *oxfw = control->private_data; oxfw_volume_info()
179 static int oxfw_volume_get(struct snd_kcontrol *control, oxfw_volume_get() argument
182 struct snd_oxfw *oxfw = control->private_data; oxfw_volume_get()
191 static int oxfw_volume_put(struct snd_kcontrol *control, oxfw_volume_put() argument
194 struct snd_oxfw *oxfw = control->private_data; oxfw_volume_put()
/linux-4.1.27/arch/arm/mach-rpc/include/mach/
H A Dacornfb.h98 case 1: vidc->control |= VIDC20_CTRL_PIX_CK; break; acornfb_vidc20_find_rates()
99 case 2: vidc->control |= VIDC20_CTRL_PIX_CK2; break; acornfb_vidc20_find_rates()
100 case 3: vidc->control |= VIDC20_CTRL_PIX_CK3; break; acornfb_vidc20_find_rates()
101 case 4: vidc->control |= VIDC20_CTRL_PIX_CK4; break; acornfb_vidc20_find_rates()
102 case 5: vidc->control |= VIDC20_CTRL_PIX_CK5; break; acornfb_vidc20_find_rates()
103 case 6: vidc->control |= VIDC20_CTRL_PIX_CK6; break; acornfb_vidc20_find_rates()
104 case 7: vidc->control |= VIDC20_CTRL_PIX_CK7; break; acornfb_vidc20_find_rates()
105 case 8: vidc->control |= VIDC20_CTRL_PIX_CK8; break; acornfb_vidc20_find_rates()
118 vidc->control |= VIDC20_CTRL_FIFO_24; acornfb_vidc20_find_rates()
120 vidc->control |= VIDC20_CTRL_FIFO_28; acornfb_vidc20_find_rates()
126 vidc->control |= VIDC20_CTRL_FIFO_16; acornfb_vidc20_find_rates()
128 vidc->control |= VIDC20_CTRL_FIFO_20; acornfb_vidc20_find_rates()
130 vidc->control |= VIDC20_CTRL_FIFO_24; acornfb_vidc20_find_rates()
132 vidc->control |= VIDC20_CTRL_FIFO_28; acornfb_vidc20_find_rates()
/linux-4.1.27/tools/testing/selftests/powerpc/pmu/ebb/
H A Dreg.h29 #define SPRN_BESCR 806 /* Branch event status & control register */
30 #define SPRN_BESCRS 800 /* Branch event status & control set (1 bits set to 1) */
31 #define SPRN_BESCRSU 801 /* Branch event status & control set upper */
32 #define SPRN_BESCRR 802 /* Branch event status & control REset (1 bits set to 0) */
33 #define SPRN_BESCRRU 803 /* Branch event status & control REset upper */
/linux-4.1.27/drivers/media/usb/gspca/
H A Dstk1135.h21 #define STK1135_REG_GCTRL 0x000 /* GPIO control */
22 #define STK1135_REG_ICTRL 0x004 /* Interrupt control */
24 #define STK1135_REG_RMCTL 0x00c /* Remote wakeup control */
30 #define STK1135_REG_SCTRL 0x100 /* Sensor control register */
31 #define STK1135_REG_DCTRL 0x104 /* Decimation control register */
34 #define STK1135_REG_TCTRL 0x120 /* Test data control */
36 #define STK1135_REG_SICTL 0x200 /* Serial interface control register */
39 #define STK1135_REG_SCSI 0x20c /* Software control serial interface */
42 #define STK1135_REG_ASIC 0x2fc /* Alternate serial interface control */
45 #define STK1135_REG_TCP1 0x350 /* Timing control parameter 1 */
/linux-4.1.27/sound/pci/oxygen/
H A Dak4396.h12 /* control 1 */
21 /* control 2 */
35 /* control 3 */
H A Dcm9780.h9 /* jack control */
27 /* mixer control */
/linux-4.1.27/drivers/macintosh/
H A Dwindfarm_pm121.c2 * Windfarm PowerMac thermal control. iMac G5 iSight
17 * The algorithm used is the PID control algorithm, used the same way
25 * controls with a tiny difference. The control-ids of hard-drive-fan
36 * OD Fan control correction.
46 * HD Fan control correction.
56 * CPU Fan control correction.
70 * control value. The correction is computed in the following way :
74 * ref_value is the value of the reference control. If new_min is
81 * control : cpu-fan
87 * control : optical-drive-fan
98 * The various control loops found in Darwin config file are:
100 * HD Fan control loop.
103 * control : hard-drive-fan
113 * control : hard-drive-fan
122 * OD Fan control loop.
125 * control : optical-drive-fan
135 * control : optical-drive-fan
144 * GPU Fan control loop.
147 * control : hard-drive-fan
157 * control : cpu-fan
166 * KODIAK (aka northbridge) Fan control loop.
169 * control : optical-drive-fan
179 * control : hard-drive-fan
188 * CPU Fan control loop.
190 * control : cpu-fan
195 * CPU Slew control loop.
197 * control : cpufreq-clamp
248 /* Set to kick the control loop into life */
260 LOOP_GPU, /* control = hd or cpu, but luckily,
262 LOOP_HD, /* control = hd */
263 LOOP_KODIAK, /* control = hd or od */
264 LOOP_OD, /* control = od */
355 /* Since each loop handles only one control and we want to avoid
356 * writing virtual control, we store the control correction with the
370 /* GPU Fan control loop */
385 /* HD Fan control loop */
400 /* KODIAK Fan control loop */
415 /* OD Fan control loop */
438 /* State data used by the system fans control loop
455 /* State data used by the cpu fans control loop
521 struct wf_control *control = NULL; pm121_create_sys_fans() local
540 control = controls[param->control_id]; pm121_create_sys_fans()
558 if(control) pm121_create_sys_fans()
560 pid_param.min = control->ops->get_min(control); pm121_create_sys_fans()
561 pid_param.max = control->ops->get_max(control); pm121_create_sys_fans()
565 * Perhaps goto fail if control == NULL above? pm121_create_sys_fans()
573 pr_debug("pm121: %s Fan control loop initialized.\n" pm121_create_sys_fans()
581 control the same control */ pm121_create_sys_fans()
584 loop_names[loop_id], control ? control->name : "uninitialized value"); pm121_create_sys_fans()
586 if (control) pm121_create_sys_fans()
587 wf_control_set_max(control); pm121_create_sys_fans()
595 struct wf_control *control; pm121_sys_fans_tick() local
602 control = controls[param->control_id]; pm121_sys_fans_tick()
636 control->name, (int)new_setpoint); pm121_sys_fans_tick()
638 if (control && pm121_failure_state == 0) { pm121_sys_fans_tick()
639 rc = control->ops->set_value(control, st->setpoint); pm121_sys_fans_tick()
642 control->name, rc); pm121_sys_fans_tick()
691 "CPU control loop (%d)\n", piddata->history_len); pm121_create_cpu_fans()
711 pr_debug("pm121: CPU Fan control initialized.\n"); pm121_create_cpu_fans()
804 pr_debug("pm121: creating control loops !\n"); pm121_tick()
867 * the control loop levels, but we don't want to keep it clear pm121_tick()
955 pr_debug("pm121: new control %s detected\n", pm121_notify()
1051 MODULE_DESCRIPTION("Thermal control logic for iMac G5 (iSight)");
H A Dwindfarm_pm81.c2 * Windfarm PowerMac thermal control. iMac G5
9 * The algorithm used is the PID control algorithm, used the same
14 * The various control loops found in Darwin config file are:
19 * System Fans control loop. Different based on models. In addition to the
20 * usual PID algorithm, the control loop gets 2 additional pairs of linear
25 * - the linked control (second control) gets the target value as-is
27 * - the main control (first control) gets the target value scaled with
29 * - the value of the target of the CPU Fan control loop is retrieved,
31 * the scaled target is applied to the main control.
69 * CPU Fan control loop. The loop is identical for all models. it
71 * systems fan control loop target result (the one before it gets scaled
72 * by the System Fans control loop itself). Then, the max value of the
80 * CPU Slew control loop. Not implemented. The cpufreq driver in linux is
85 * WARNING ! The CPU control loop requires the CPU tmax for the current
142 /* Set to kick the control loop into life */
159 /* Parameters for the System Fans control loop. Parameters
177 /* State data used by the system fans control loop
191 * Configs for SMU System Fan control loop
246 /* State data used by the cpu fans control loop
316 DBG("wf: System Fan control initialized.\n"); wf_smu_create_sys_fans()
436 "CPU control loop (%d)\n", piddata->history_len); wf_smu_create_cpu_fans()
456 DBG("wf: CPU Fan control initialized.\n"); wf_smu_create_cpu_fans()
549 DBG("wf: creating control loops !\n"); wf_smu_tick()
603 * the control loop levels, but we don't want to keep it clear wf_smu_tick()
681 DBG("wf: new control %s detected\n", wf_smu_notify()
761 /* Destroy control loops state structures */ wf_smu_remove()
810 MODULE_DESCRIPTION("Thermal control logic for iMac G5");
/linux-4.1.27/sound/pci/emu10k1/
H A Dp17v.h100 #define P17V_CAPTURE_VOL_H 0x4c /* P17v capture volume control */
101 #define P17V_CAPTURE_VOL_L 0x4d /* P17v capture volume control */
107 #define P17V_MIXER_AC97_10K1_VOL_L 0x61 /* 10K to Mixer_AC97 input volume control */
108 #define P17V_MIXER_AC97_10K1_VOL_H 0x62 /* 10K to Mixer_AC97 input volume control */
109 #define P17V_MIXER_AC97_P17V_VOL_L 0x63 /* P17V to Mixer_AC97 input volume control */
110 #define P17V_MIXER_AC97_P17V_VOL_H 0x64 /* P17V to Mixer_AC97 input volume control */
111 #define P17V_MIXER_AC97_SRP_REC_VOL_L 0x65 /* SRP Record to Mixer_AC97 input volume control */
112 #define P17V_MIXER_AC97_SRP_REC_VOL_H 0x66 /* SRP Record to Mixer_AC97 input volume control */
114 #define P17V_MIXER_Spdif_10K1_VOL_L 0x69 /* 10K to Mixer_Spdif input volume control */
115 #define P17V_MIXER_Spdif_10K1_VOL_H 0x6A /* 10K to Mixer_Spdif input volume control */
116 #define P17V_MIXER_Spdif_P17V_VOL_L 0x6B /* P17V to Mixer_Spdif input volume control */
117 #define P17V_MIXER_Spdif_P17V_VOL_H 0x6C /* P17V to Mixer_Spdif input volume control */
118 #define P17V_MIXER_Spdif_SRP_REC_VOL_L 0x6D /* SRP Record to Mixer_Spdif input volume control */
119 #define P17V_MIXER_Spdif_SRP_REC_VOL_H 0x6E /* SRP Record to Mixer_Spdif input volume control */
121 #define P17V_MIXER_I2S_10K1_VOL_L 0x71 /* 10K to Mixer_I2S input volume control */
122 #define P17V_MIXER_I2S_10K1_VOL_H 0x72 /* 10K to Mixer_I2S input volume control */
123 #define P17V_MIXER_I2S_P17V_VOL_L 0x73 /* P17V to Mixer_I2S input volume control */
124 #define P17V_MIXER_I2S_P17V_VOL_H 0x74 /* P17V to Mixer_I2S input volume control */
125 #define P17V_MIXER_I2S_SRP_REC_VOL_L 0x75 /* SRP Record to Mixer_I2S input volume control */
126 #define P17V_MIXER_I2S_SRP_REC_VOL_H 0x76 /* SRP Record to Mixer_I2S input volume control */
136 #define P17V_AC97_OUT_MASTER_VOL_L 0x80 /* AC97 Output master volume control */
137 #define P17V_AC97_OUT_MASTER_VOL_H 0x81 /* AC97 Output master volume control */
138 #define P17V_SPDIF_OUT_MASTER_VOL_L 0x82 /* SPDIF Output master volume control */
139 #define P17V_SPDIF_OUT_MASTER_VOL_H 0x83 /* SPDIF Output master volume control */
140 #define P17V_I2S_OUT_MASTER_VOL_L 0x84 /* I2S Output master volume control */
141 #define P17V_I2S_OUT_MASTER_VOL_H 0x85 /* I2S Output master volume control */
/linux-4.1.27/drivers/net/wimax/i2400m/
H A DMakefile6 control.o \
/linux-4.1.27/drivers/s390/char/
H A Dsclp_cpi_sys.h2 * SCLP control program identification sysfs interface
/linux-4.1.27/drivers/crypto/caam/
H A Dctrl.h2 * CAAM control-plane driver backend public-level include definitions
/linux-4.1.27/arch/sparc/include/uapi/asm/
H A Dsockios.h4 /* Socket-level I/O control calls. */
/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/mfd/
H A Dpalmas.h13 /* External control pins */
/linux-4.1.27/include/uapi/asm-generic/
H A Dsockios.h4 /* Socket-level I/O control calls. */
H A Dtermbits.h14 tcflag_t c_cflag; /* control mode flags */
17 cc_t c_cc[NCCS]; /* control characters */
23 tcflag_t c_cflag; /* control mode flags */
26 cc_t c_cc[NCCS]; /* control characters */
34 tcflag_t c_cflag; /* control mode flags */
37 cc_t c_cc[NCCS]; /* control characters */
161 #define CRTSCTS 020000000000 /* flow control */
H A Dtermios.h25 unsigned short c_cflag; /* control mode flags */
28 unsigned char c_cc[NCC]; /* control characters */
/linux-4.1.27/arch/mn10300/include/uapi/asm/
H A Dsockios.h4 /* Socket-level I/O control calls. */
H A Dtermbits.h14 tcflag_t c_cflag; /* control mode flags */
17 cc_t c_cc[NCCS]; /* control characters */
23 tcflag_t c_cflag; /* control mode flags */
26 cc_t c_cc[NCCS]; /* control characters */
34 tcflag_t c_cflag; /* control mode flags */
37 cc_t c_cc[NCCS]; /* control characters */
161 #define CTVB 004000000000 /* VisioBraille Terminal flow control */
163 #define CRTSCTS 020000000000 /* flow control */
/linux-4.1.27/arch/parisc/include/uapi/asm/
H A Dsockios.h4 /* Socket-level I/O control calls. */
H A Dtermbits.h14 tcflag_t c_cflag; /* control mode flags */
17 cc_t c_cc[NCCS]; /* control characters */
23 tcflag_t c_cflag; /* control mode flags */
26 cc_t c_cc[NCCS]; /* control characters */
34 tcflag_t c_cflag; /* control mode flags */
37 cc_t c_cc[NCCS]; /* control characters */
162 #define CRTSCTS 020000000000 /* flow control */
H A Dtermios.h18 unsigned short c_cflag; /* control mode flags */
21 unsigned char c_cc[NCC]; /* control characters */
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/mfd/
H A Dpalmas.h13 /* External control pins */
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/mfd/
H A Dpalmas.h13 /* External control pins */
/linux-4.1.27/arch/avr32/include/uapi/asm/
H A Dsockios.h4 /* Socket-level I/O control calls. */
H A Dtermbits.h14 tcflag_t c_cflag; /* control mode flags */
17 cc_t c_cc[NCCS]; /* control characters */
23 tcflag_t c_cflag; /* control mode flags */
26 cc_t c_cc[NCCS]; /* control characters */
34 tcflag_t c_cflag; /* control mode flags */
37 cc_t c_cc[NCCS]; /* control characters */
160 #define CRTSCTS 020000000000 /* flow control */
H A Dtermios.h25 unsigned short c_cflag; /* control mode flags */
28 unsigned char c_cc[NCC]; /* control characters */
/linux-4.1.27/arch/cris/include/uapi/asm/
H A Dsockios.h4 /* Socket-level I/O control calls. */
H A Dtermios.h20 unsigned short c_cflag; /* control mode flags */
23 unsigned char c_cc[NCC]; /* control characters */
/linux-4.1.27/arch/frv/include/uapi/asm/
H A Dsockios.h4 /* Socket-level I/O control calls. */
H A Dtermbits.h14 tcflag_t c_cflag; /* control mode flags */
17 cc_t c_cc[NCCS]; /* control characters */
23 tcflag_t c_cflag; /* control mode flags */
26 cc_t c_cc[NCCS]; /* control characters */
34 tcflag_t c_cflag; /* control mode flags */
37 cc_t c_cc[NCCS]; /* control characters */
161 #define CTVB 004000000000 /* VisioBraille Terminal flow control */
163 #define CRTSCTS 020000000000 /* flow control */
H A Dtermios.h18 unsigned short c_cflag; /* control mode flags */
21 unsigned char c_cc[NCC]; /* control characters */
/linux-4.1.27/arch/m32r/include/uapi/asm/
H A Dsockios.h4 /* Socket-level I/O control calls. */
H A Dtermbits.h14 tcflag_t c_cflag; /* control mode flags */
17 cc_t c_cc[NCCS]; /* control characters */
23 tcflag_t c_cflag; /* control mode flags */
26 cc_t c_cc[NCCS]; /* control characters */
34 tcflag_t c_cflag; /* control mode flags */
37 cc_t c_cc[NCCS]; /* control characters */
160 #define CTVB 004000000000 /* VisioBraille Terminal flow control */
162 #define CRTSCTS 020000000000 /* flow control */
H A Dtermios.h18 unsigned short c_cflag; /* control mode flags */
21 unsigned char c_cc[NCC]; /* control characters */
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/mfd/
H A Dpalmas.h13 /* External control pins */
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A Deseries-gpio.h45 /* e7xx IrDA power control */
48 /* e740 audio control GPIOs */
53 /* e750 audio control GPIOs */
58 /* e800 audio control GPIOs */
H A Dmainstone.h46 #define MST_MSCWR1_CAMERA_ON (1 << 15) /* Camera interface power control */
47 #define MST_MSCWR1_CAMERA_SEL (1 << 14) /* Camera interface mux control */
48 #define MST_MSCWR1_LCD_CTL (1 << 13) /* General-purpose LCD control */
49 #define MST_MSCWR1_MS_ON (1 << 12) /* Memory Stick power control */
50 #define MST_MSCWR1_MMC_ON (1 << 11) /* MultiMediaCard* power control */
51 #define MST_MSCWR1_MS_SEL (1 << 10) /* SD/MS multiplexer control */
63 #define MST_MSCWR1_GREENLED (1 << 3) /* LED D1 control */
69 #define MST_MSCWR2_USB_OTG_SEL (1 << 5) /* USB On The Go control */
70 #define MST_MSCWR2_nUSBC_SC (1 << 4) /* USB client soft connect control */
71 #define MST_MSCWR2_I2S_SPKROFF (1 << 3) /* I2S CODEC amplifier control */
72 #define MST_MSCWR2_AC97_SPKROFF (1 << 2) /* AC97 CODEC amplifier control */
73 #define MST_MSCWR2_RADIO_PWR (1 << 1) /* Radio module power control */
H A Dtosa_bt.h2 * Tosa bluetooth built-in chip control.
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/mfd/
H A Dpalmas.h13 /* External control pins */
/linux-4.1.27/include/dt-bindings/mfd/
H A Dpalmas.h13 /* External control pins */
/linux-4.1.27/include/linux/i2c/
H A Dmax6639.h6 /* platform data for the MAX6639 temperature sensor and fan control */
/linux-4.1.27/include/linux/mfd/da9055/
H A Dpdata.h31 * GPI muxed pin to control
36 * GPI muxed pin to control
41 * Regulator mode control bits value (GPI offset) that
46 * Regulator mode control bits value (GPI offset) that
/linux-4.1.27/drivers/staging/iio/frequency/
H A Dad9834.c91 if (st->control & AD9834_MODE) { ad9834_write()
97 st->control |= AD9834_OPBITEN; ad9834_write()
99 st->control &= ~AD9834_OPBITEN; ad9834_write()
101 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); ad9834_write()
106 st->control |= AD9834_PIN_SW; ad9834_write()
108 st->control &= ~AD9834_PIN_SW; ad9834_write()
109 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); ad9834_write()
115 st->control &= ~(this_attr->address | AD9834_PIN_SW); ad9834_write()
117 st->control |= this_attr->address; ad9834_write()
118 st->control &= ~AD9834_PIN_SW; ad9834_write()
123 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); ad9834_write()
128 st->control &= ~AD9834_RESET; ad9834_write()
130 st->control |= AD9834_RESET; ad9834_write()
132 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); ad9834_write()
160 st->control &= ~AD9834_MODE; ad9834_store_wavetype()
162 st->control &= ~AD9834_OPBITEN; ad9834_store_wavetype()
165 st->control &= ~AD9834_OPBITEN; ad9834_store_wavetype()
166 st->control |= AD9834_MODE; ad9834_store_wavetype()
167 } else if (st->control & AD9834_OPBITEN) { ad9834_store_wavetype()
170 st->control |= AD9834_MODE; ad9834_store_wavetype()
173 st->control &= ~AD9834_MODE; ad9834_store_wavetype()
174 st->control |= AD9834_OPBITEN; ad9834_store_wavetype()
182 !(st->control & AD9834_MODE)) { ad9834_store_wavetype()
183 st->control &= ~AD9834_MODE; ad9834_store_wavetype()
184 st->control |= AD9834_OPBITEN; ad9834_store_wavetype()
195 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); ad9834_store_wavetype()
214 else if (st->control & AD9834_OPBITEN) ad9834_show_out0_wavetype_available()
234 if (st->control & AD9834_MODE) ad9834_show_out1_wavetype_available()
381 st->control = AD9834_B28 | AD9834_RESET; ad9834_probe()
384 st->control |= AD9834_DIV2; ad9834_probe()
387 st->control |= AD9834_SIGN_PIB; ad9834_probe()
389 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); ad9834_probe()
/linux-4.1.27/arch/mips/include/uapi/asm/
H A Dsockios.h2 * Socket-level I/O control calls.
15 /* Socket-level I/O control calls. */
/linux-4.1.27/arch/powerpc/platforms/chrp/
H A Dgg2.h42 #define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */
44 #define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */
45 #define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */
47 #define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */
56 #define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */
57 #define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */
/linux-4.1.27/drivers/rtc/
H A Drtc-m48t35.c29 u8 control; member in struct:m48t35_rtc
53 u8 control; m48t35_read_time() local
62 control = readb(&priv->reg->control); m48t35_read_time()
63 writeb(control | M48T35_RTC_READ, &priv->reg->control); m48t35_read_time()
70 writeb(control, &priv->reg->control); m48t35_read_time()
97 u8 control; m48t35_set_time() local
127 control = readb(&priv->reg->control); m48t35_set_time()
128 writeb(control | M48T35_RTC_SET, &priv->reg->control); m48t35_set_time()
135 writeb(control, &priv->reg->control); m48t35_set_time()
H A Drtc-ds1672.c85 buf[5] = 0; /* set control reg to enable counting */ ds1672_set_mmss()
116 {/* read control */ ds1672_get_control()
124 /* read control register */ ds1672_get_control()
138 u8 control; show_control() local
141 err = ds1672_get_control(client, &control); show_control()
145 return sprintf(buf, "%s\n", (control & DS1672_REG_CONTROL_EOSC) show_control()
149 static DEVICE_ATTR(control, S_IRUGO, show_control, NULL);
160 u8 control; ds1672_probe() local
178 /* read control register */ ds1672_probe()
179 err = ds1672_get_control(client, &control); ds1672_probe()
181 dev_warn(&client->dev, "Unable to read the control register\n"); ds1672_probe()
184 if (control & DS1672_REG_CONTROL_EOSC) ds1672_probe()
H A Drtc-ds3232.c46 #define DS3232_REG_SR 0x0F /* control/status register */
71 int control, stat; ds3232_check_rtc_status() local
93 control = i2c_smbus_read_byte_data(client, DS3232_REG_CR); ds3232_check_rtc_status()
94 if (control < 0) ds3232_check_rtc_status()
95 return control; ds3232_check_rtc_status()
97 control &= ~(DS3232_REG_CR_A1IE | DS3232_REG_CR_A2IE); ds3232_check_rtc_status()
98 control |= DS3232_REG_CR_INTCN; ds3232_check_rtc_status()
100 return i2c_smbus_write_byte_data(client, DS3232_REG_CR, control); ds3232_check_rtc_status()
195 int control, stat; ds3232_read_alarm() local
208 control = ret; ds3232_read_alarm()
224 alarm->enabled = !!(control & DS3232_REG_CR_A1IE); ds3232_read_alarm()
241 int control, stat; ds3232_set_alarm() local
259 control = ret; ds3232_set_alarm()
260 control &= ~(DS3232_REG_CR_A1IE | DS3232_REG_CR_A2IE); ds3232_set_alarm()
261 ret = i2c_smbus_write_byte_data(client, DS3232_REG_CR, control); ds3232_set_alarm()
278 control |= DS3232_REG_CR_A1IE; ds3232_set_alarm()
279 ret = i2c_smbus_write_byte_data(client, DS3232_REG_CR, control); ds3232_set_alarm()
289 int control; ds3232_update_alarm() local
312 control = i2c_smbus_read_byte_data(client, DS3232_REG_CR); ds3232_update_alarm()
313 if (control < 0) ds3232_update_alarm()
318 control |= DS3232_REG_CR_A1IE; ds3232_update_alarm()
321 control &= ~(DS3232_REG_CR_A1IE); ds3232_update_alarm()
322 i2c_smbus_write_byte_data(client, DS3232_REG_CR, control); ds3232_update_alarm()
367 int stat, control; ds3232_work() local
376 control = i2c_smbus_read_byte_data(client, DS3232_REG_CR); ds3232_work()
377 if (control < 0) { ds3232_work()
382 control &= ~(DS3232_REG_CR_A1IE); ds3232_work()
384 control); ds3232_work()
/linux-4.1.27/sound/core/seq/
H A Dseq_midi_emul.c53 int control, int value);
149 ev->data.control.param, ev->data.control.value); snd_midi_process_event()
152 chan->midi_program = ev->data.control.value; snd_midi_process_event()
155 chan->midi_pitchbend = ev->data.control.value; snd_midi_process_event()
156 if (ops->control) snd_midi_process_event()
157 ops->control(drv, MIDI_CTL_PITCHBEND, chan); snd_midi_process_event()
160 chan->midi_pressure = ev->data.control.value; snd_midi_process_event()
161 if (ops->control) snd_midi_process_event()
162 ops->control(drv, MIDI_CTL_CHAN_PRESSURE, chan); snd_midi_process_event()
166 if (ev->data.control.param < 32) { snd_midi_process_event()
168 chan->control[ev->data.control.param + 32] = snd_midi_process_event()
169 ev->data.control.value & 0x7f; snd_midi_process_event()
171 ev->data.control.param, snd_midi_process_event()
172 ((ev->data.control.value>>7) & 0x7f)); snd_midi_process_event()
175 ev->data.control.param, snd_midi_process_event()
176 ev->data.control.value); snd_midi_process_event()
181 chan->control[MIDI_CTL_MSB_DATA_ENTRY] snd_midi_process_event()
182 = (ev->data.control.value >> 7) & 0x7f; snd_midi_process_event()
183 chan->control[MIDI_CTL_LSB_DATA_ENTRY] snd_midi_process_event()
184 = ev->data.control.value & 0x7f; snd_midi_process_event()
185 chan->control[MIDI_CTL_NONREG_PARM_NUM_MSB] snd_midi_process_event()
186 = (ev->data.control.param >> 7) & 0x7f; snd_midi_process_event()
187 chan->control[MIDI_CTL_NONREG_PARM_NUM_LSB] snd_midi_process_event()
188 = ev->data.control.param & 0x7f; snd_midi_process_event()
194 chan->control[MIDI_CTL_MSB_DATA_ENTRY] snd_midi_process_event()
195 = (ev->data.control.value >> 7) & 0x7f; snd_midi_process_event()
196 chan->control[MIDI_CTL_LSB_DATA_ENTRY] snd_midi_process_event()
197 = ev->data.control.value & 0x7f; snd_midi_process_event()
198 chan->control[MIDI_CTL_REGIST_PARM_NUM_MSB] snd_midi_process_event()
199 = (ev->data.control.param >> 7) & 0x7f; snd_midi_process_event()
200 chan->control[MIDI_CTL_REGIST_PARM_NUM_LSB] snd_midi_process_event()
201 = ev->data.control.param & 0x7f; snd_midi_process_event()
268 struct snd_midi_channel *chan, int control, int value) do_control()
272 if (control >= ARRAY_SIZE(chan->control)) do_control()
276 if ((control >=64 && control <=69) || (control >= 80 && control <= 83)) { do_control()
280 chan->control[control] = value; do_control()
282 switch (control) { do_control()
319 chan->control[MIDI_CTL_LSB_DATA_ENTRY] = 0; do_control()
375 if (ops->control) do_control()
376 ops->control(drv, control, chan); do_control()
424 type = (chan->control[MIDI_CTL_REGIST_PARM_NUM_MSB] << 8) | rpn()
425 chan->control[MIDI_CTL_REGIST_PARM_NUM_LSB]; rpn()
426 val = (chan->control[MIDI_CTL_MSB_DATA_ENTRY] << 7) | rpn()
427 chan->control[MIDI_CTL_LSB_DATA_ENTRY]; rpn()
585 chset->channels[i].control[MIDI_CTL_MSB_BANK] = 127; sysex()
587 chset->channels[i].control[MIDI_CTL_MSB_BANK] = 0; sysex()
630 * Initialise a single midi channel control block.
651 * Allocate and initialise a set of midi channel control blocks.
710 memset(chan->control, 0, sizeof(chan->control)); snd_midi_reset_controllers()
267 do_control(struct snd_midi_op *ops, void *drv, struct snd_midi_channel_set *chset, struct snd_midi_channel *chan, int control, int value) do_control() argument
H A Dseq_midi_event.c322 ev->data.control.channel = dev->buf[0] & 0x0f; one_param_ctrl_event()
323 ev->data.control.value = dev->buf[1]; one_param_ctrl_event()
329 ev->data.control.channel = dev->buf[0] & 0x0f; pitchbend_ctrl_event()
330 ev->data.control.value = (int)dev->buf[2] * 128 + (int)dev->buf[1] - 8192; pitchbend_ctrl_event()
333 /* encode midi control change */ two_param_ctrl_event()
336 ev->data.control.channel = dev->buf[0] & 0x0f; two_param_ctrl_event()
337 ev->data.control.param = dev->buf[1]; two_param_ctrl_event()
338 ev->data.control.value = dev->buf[2]; two_param_ctrl_event()
344 ev->data.control.value = dev->buf[1]; one_param_event()
350 ev->data.control.value = (int)dev->buf[2] * 128 + (int)dev->buf[1]; songpos_event()
379 /* data.note.channel and data.control.channel is identical */ snd_midi_event_decode()
423 buf[0] = ev->data.control.value & 0x7f; one_param_decode()
429 int value = ev->data.control.value + 8192; pitchbend_decode()
434 /* decode midi control change */ two_param_decode()
437 buf[0] = ev->data.control.param & 0x7f; two_param_decode()
438 buf[1] = ev->data.control.value & 0x7f; two_param_decode()
444 buf[0] = ev->data.control.value & 0x7f; songpos_decode()
445 buf[1] = (ev->data.control.value >> 7) & 0x7f; songpos_decode()
448 /* decode 14bit control */ extra_decode_ctrl14()
455 cmd = MIDI_CMD_CONTROL|(ev->data.control.channel & 0x0f); extra_decode_ctrl14()
456 if (ev->data.control.param < 0x20) { extra_decode_ctrl14()
466 buf[idx++] = ev->data.control.param; extra_decode_ctrl14()
467 buf[idx++] = (ev->data.control.value >> 7) & 0x7f; extra_decode_ctrl14()
470 buf[idx++] = ev->data.control.param + 0x20; extra_decode_ctrl14()
471 buf[idx++] = ev->data.control.value & 0x7f; extra_decode_ctrl14()
480 buf[idx++] = ev->data.control.param & 0x7f; extra_decode_ctrl14()
481 buf[idx++] = ev->data.control.value & 0x7f; extra_decode_ctrl14()
507 cmd = MIDI_CMD_CONTROL|(ev->data.control.channel & 0x0f); extra_decode_xrpn()
508 bytes[0] = (ev->data.control.param & 0x3f80) >> 7; extra_decode_xrpn()
509 bytes[1] = ev->data.control.param & 0x007f; extra_decode_xrpn()
510 bytes[2] = (ev->data.control.value & 0x3f80) >> 7; extra_decode_xrpn()
511 bytes[3] = ev->data.control.value & 0x007f; extra_decode_xrpn()
/linux-4.1.27/arch/m32r/include/asm/m32700ut/
H A Dm32700ut_lan.h29 * ICUCR3: control register for CFIREQ# interrupt
30 * ICUCR4: control register for CFC Card insert interrupt
31 * ICUCR5: control register for CFC Card eject interrupt
32 * ICUCR6: control register for external interrupt
33 * ICUCR11: control register for MMC Card insert/eject interrupt
34 * ICUCR13: control register for SC error interrupt
35 * ICUCR14: control register for SC receive interrupt
36 * ICUCR15: control register for SC send interrupt
37 * ICUCR16: control register for SIO0 receive interrupt
38 * ICUCR17: control register for SIO0 send interrupt
/linux-4.1.27/drivers/media/i2c/soc_camera/
H A Dov772x.c37 #define GAIN 0x00 /* AGC - Gain control gain setting */
41 #define COM1 0x04 /* Common control 1 */
46 #define COM2 0x09 /* Common control 2 */
49 #define COM3 0x0C /* Common control 3 */
50 #define COM4 0x0D /* Common control 4 */
51 #define COM5 0x0E /* Common control 5 */
52 #define COM6 0x0F /* Common control 6 */
55 #define COM7 0x12 /* Common control 7 */
56 #define COM8 0x13 /* Common control 8 */
57 #define COM9 0x14 /* Common control 9 */
58 #define COM10 0x15 /* Common control 10 */
68 #define COM11 0x20 /* Common control 11 */
84 #define HREF 0x32 /* Image start and size control */
95 #define COM12 0x3D /* Common control 12 */
96 #define COM13 0x3E /* Common control 13 */
97 #define COM14 0x3F /* Common control 14 */
98 #define COM15 0x40 /* Common control 15*/
99 #define COM16 0x41 /* Common control 16 */
105 #define LCC0 0x46 /* Lens correction control 0 */
113 #define LC_CTR 0x46 /* Lens correction control */
122 #define AREF0 0x4E /* Sensor reference control */
123 #define AREF1 0x4F /* Sensor reference current control */
124 #define AREF2 0x50 /* Analog reference control */
125 #define AREF3 0x51 /* ADC reference control */
126 #define AREF4 0x52 /* ADC reference control */
127 #define AREF5 0x53 /* ADC reference control */
128 #define AREF6 0x54 /* Analog reference control */
129 #define AREF7 0x55 /* Analog reference control */
133 #define AWB_CTRL0 0x63 /* AWB control byte 0 */
134 #define DSP_CTRL1 0x64 /* DSP control byte 1 */
135 #define DSP_CTRL2 0x65 /* DSP control byte 2 */
136 #define DSP_CTRL3 0x66 /* DSP control byte 3 */
137 #define DSP_CTRL4 0x67 /* DSP control byte 4 */
139 #define AWB_CTRL1 0x69 /* AWB control 1 */
140 #define AWB_CTRL2 0x6A /* AWB control 2 */
141 #define AWB_CTRL3 0x6B /* AWB control 3 */
142 #define AWB_CTRL4 0x6C /* AWB control 4 */
143 #define AWB_CTRL5 0x6D /* AWB control 5 */
144 #define AWB_CTRL6 0x6E /* AWB control 6 */
145 #define AWB_CTRL7 0x6F /* AWB control 7 */
146 #define AWB_CTRL8 0x70 /* AWB control 8 */
147 #define AWB_CTRL9 0x71 /* AWB control 9 */
148 #define AWB_CTRL10 0x72 /* AWB control 10 */
149 #define AWB_CTRL11 0x73 /* AWB control 11 */
150 #define AWB_CTRL12 0x74 /* AWB control 12 */
151 #define AWB_CTRL13 0x75 /* AWB control 13 */
152 #define AWB_CTRL14 0x76 /* AWB control 14 */
153 #define AWB_CTRL15 0x77 /* AWB control 15 */
154 #define AWB_CTRL16 0x78 /* AWB control 16 */
155 #define AWB_CTRL17 0x79 /* AWB control 17 */
156 #define AWB_CTRL18 0x7A /* AWB control 18 */
157 #define AWB_CTRL19 0x7B /* AWB control 19 */
158 #define AWB_CTRL20 0x7C /* AWB control 20 */
159 #define AWB_CTRL21 0x7D /* AWB control 21 */
177 #define EDGE_STRNGT 0x8F /* Edge strength control when manual mode */
178 #define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */
179 #define DNSOFF 0x91 /* Auto De-noise threshold control */
188 #define MTX_CTRL 0x9A /* Matrix control */
189 #define BRIGHT 0x9B /* Brightness control */
194 #define SCAL0 0xA0 /* Scaling control 0 */
195 #define SCAL1 0xA1 /* Scaling control 1 */
196 #define SCAL2 0xA2 /* Scaling control 2 */
197 #define FIFODLYM 0xA3 /* FIFO manual mode delay control */
198 #define FIFODLYA 0xA4 /* FIFO auto mode delay control */
199 #define SDE 0xA6 /* Special digital effect control */
200 #define USAT 0xA7 /* U component saturation control */
201 #define VSAT 0xA8 /* V component saturation control */
203 #define HUE0 0xA9 /* Hue control 0 */
204 #define HUE1 0xAA /* Hue control 1 */
210 #define DSPAUTO 0xAC /* DSP auto function ON/OFF control */
242 /* PLL frequency control */
254 #define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */
255 #define AFR_SPPED 0x40 /* Auto frame rate control speed selection */
256 /* Auto frame rate max rate control */
261 /* Auto frame rate active point control */
266 /* AEC max step control */
280 /* RGB output format control */
286 /* Output format control */
300 #define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */
357 #define AWB_ACTRL 0x80 /* AWB auto threshold control */
358 #define DENOISE_ACTRL 0x40 /* De-noise auto threshold control */
359 #define EDGE_ACTRL 0x20 /* Edge enhancement auto strength control */
360 #define UV_ACTRL 0x10 /* UV adjust auto slope control */
361 #define SCAL0_ACTRL 0x08 /* Auto scaling factor control */
362 #define SCAL1_2_ACTRL 0x04 /* Auto scaling factor control */
828 /* COM7: Sensor resolution and output format control. */ ov772x_set_params()
/linux-4.1.27/drivers/net/ethernet/ti/
H A Dnetcp_sgmii.c74 u32 control; netcp_sgmii_config() local
79 control = 0x21; netcp_sgmii_config()
85 control = 1; netcp_sgmii_config()
90 control = 0x20; netcp_sgmii_config()
95 control = 0x1; netcp_sgmii_config()
117 sgmii_write_reg(sgmii_ofs, SGMII_CTL_REG(port), control); netcp_sgmii_config()
120 if (control & SGMII_REG_CONTROL_AUTONEG) netcp_sgmii_config()
/linux-4.1.27/drivers/pci/
H A Dats.c191 u16 control, status; pci_enable_pri() local
199 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); pci_enable_pri()
201 if ((control & PCI_PRI_CTRL_ENABLE) || pci_enable_pri()
209 control |= PCI_PRI_CTRL_ENABLE; pci_enable_pri()
210 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); pci_enable_pri()
224 u16 control; pci_disable_pri() local
231 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); pci_disable_pri()
232 control &= ~PCI_PRI_CTRL_ENABLE; pci_disable_pri()
233 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); pci_disable_pri()
246 u16 control; pci_reset_pri() local
253 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); pci_reset_pri()
254 if (control & PCI_PRI_CTRL_ENABLE) pci_reset_pri()
257 control |= PCI_PRI_CTRL_RESET; pci_reset_pri()
259 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); pci_reset_pri()
278 u16 control, supported; pci_enable_pasid() local
285 pci_read_config_word(pdev, pos + PCI_PASID_CTRL, &control); pci_enable_pasid()
288 if (control & PCI_PASID_CTRL_ENABLE) pci_enable_pasid()
297 control = PCI_PASID_CTRL_ENABLE | features; pci_enable_pasid()
299 pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control); pci_enable_pasid()
312 u16 control = 0; pci_disable_pasid() local
319 pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control); pci_disable_pasid()
/linux-4.1.27/sound/soc/codecs/
H A Dtlv320aic3x.h34 /* Audio serial data interface control register A */
36 /* Audio serial data interface control register B */
38 /* Audio serial data interface control register C */
42 /* Audio codec digital filter control register */
47 /* ADC PGA Gain control registers */
50 /* MIC3 control registers */
53 /* Line1 Input control registers */
58 /* Line2 Input control registers */
72 /* DAC Power and Left High Power Output control registers */
75 /* Right High Power Output control registers */
79 /* DAC Output Switching control registers */
83 /* DAC Digital control registers */
86 /* Left High Power Output control registers */
94 /* Left High Power COM control registers */
102 /* Right High Power Output control registers */
110 /* Right High Power COM control registers */
118 /* Mono Line Output Plus/Minus control registers */
128 /* Left Line Output Plus/Minus control registers */
136 /* Right Line Output Plus/Minus control registers */
151 /* Clock generation control register */
169 /* Audio serial data interface control register A bits */
H A Dssm2602.h64 #define LINVOL_LIN_VOL 0x01F /* Left Channel PGA Volume control */
69 #define RINVOL_RIN_VOL 0x01F /* Right Channel PGA Volume control */
74 #define LOUT1V_LHP_VOL 0x07F /* Left Channel Headphone volume control */
79 #define ROUT1V_RHP_VOL 0x07F /* Right Channel Headphone volume control */
84 #define APANA_ENABLE_MIC_BOOST 0x001 /* Primary Microphone Amplifier gain booster control */
91 #define APANA_ENABLE_MIC_BOOST2 0x100 /* Secondary Microphone Amplifier gain booster control */
112 #define IFACE_IFACE_FORMAT 0x003 /* Digital Audio input format control */
113 #define IFACE_AUDIO_DATA_LEN 0x00C /* Audio Data word length control */
115 #define IFACE_DAC_LR_SWAP 0x020 /* Swap DAC data control */
117 #define IFACE_BCLK_INVERT 0x080 /* Bit Clock Inversion control */
122 #define SRATE_SAMPLE_RATE 0x03C /* Clock setting condition (Sampling rate control) */
H A Dtlv320aic23.h34 /* Left (right) line input volume control register */
41 /* Left (right) channel headphone volume control register */
47 /* Analog audio path control register */
56 /* Digital audio path control register */
63 /* Power control down register */
85 /* Sample rate control register */
/linux-4.1.27/drivers/media/pci/cx25821/
H A Dcx25821-reg.h62 #define DEV_CNTRL2 0x040000 /* Device control */
921 #define FLD_GP_OUT 0x000000FF /* GPIO: GP_OUT control */
1055 #define TEST_BUS_CTL1 0x110040 /* Test bus control register #1 */
1058 #define TEST_BUS_CTL2 0x110044 /* Test bus control register #2 */
1065 #define PAD_CTRL 0x110068 /* Pad drive strength control */
1068 #define MBIST_CTRL 0x110050 /* SRAM memory built-in self test control */
1097 #define VID_A_VIP_CTL 0x130080 /* Video A VIP format control */
1107 #define VID_A_VBI_CTL 0x130088 /* Video A VBI miscellaneous control */
1125 #define VID_B_VIP_CTL 0x130180 /* Video B VIP format control */
1155 #define VID_DST_A_GPCNT_CTL 0x130030 /* Video A general purpose control */
1156 #define VID_DST_B_GPCNT_CTL 0x130130 /* Video B general purpose control */
1157 #define VID_DST_C_GPCNT_CTL 0x130230 /* Video C general purpose control */
1158 #define VID_DST_D_GPCNT_CTL 0x130330 /* Video D general purpose control */
1159 #define VID_DST_E_GPCNT_CTL 0x130430 /* Video E general purpose control */
1160 #define VID_DST_F_GPCNT_CTL 0x130530 /* Video F general purpose control */
1161 #define VID_DST_G_GPCNT_CTL 0x130630 /* Video G general purpose control */
1162 #define VID_DST_H_GPCNT_CTL 0x130730 /* Video H general purpose control */
1166 #define VID_DST_A_DMA_CTL 0x130040 /* Video A DMA control */
1167 #define VID_DST_B_DMA_CTL 0x130140 /* Video B DMA control */
1168 #define VID_DST_C_DMA_CTL 0x130240 /* Video C DMA control */
1169 #define VID_DST_D_DMA_CTL 0x130340 /* Video D DMA control */
1170 #define VID_DST_E_DMA_CTL 0x130440 /* Video E DMA control */
1171 #define VID_DST_F_DMA_CTL 0x130540 /* Video F DMA control */
1172 #define VID_DST_G_DMA_CTL 0x130640 /* Video G DMA control */
1173 #define VID_DST_H_DMA_CTL 0x130740 /* Video H DMA control */
1180 #define VID_DST_A_VIP_CTL 0x130080 /* Video A VIP control */
1181 #define VID_DST_B_VIP_CTL 0x130180 /* Video B VIP control */
1182 #define VID_DST_C_VIP_CTL 0x130280 /* Video C VIP control */
1183 #define VID_DST_D_VIP_CTL 0x130380 /* Video D VIP control */
1184 #define VID_DST_E_VIP_CTL 0x130480 /* Video E VIP control */
1185 #define VID_DST_F_VIP_CTL 0x130580 /* Video F VIP control */
1186 #define VID_DST_G_VIP_CTL 0x130680 /* Video G VIP control */
1187 #define VID_DST_H_VIP_CTL 0x130780 /* Video H VIP control */
1204 #define VID_SRC_A_GPCNT_CTL 0x130804 /* Video A general purpose control */
1205 #define VID_SRC_B_GPCNT_CTL 0x130904 /* Video B general purpose control */
1206 #define VID_SRC_C_GPCNT_CTL 0x130A04 /* Video C general purpose control */
1207 #define VID_SRC_D_GPCNT_CTL 0x130B04 /* Video D general purpose control */
1208 #define VID_SRC_E_GPCNT_CTL 0x130C04 /* Video E general purpose control */
1209 #define VID_SRC_F_GPCNT_CTL 0x130D04 /* Video F general purpose control */
1210 #define VID_SRC_I_GPCNT_CTL 0x130E04 /* Video I general purpose control */
1211 #define VID_SRC_J_GPCNT_CTL 0x130F04 /* Video J general purpose control */
1226 #define VID_SRC_A_DMA_CTL 0x13080C /* Video A DMA control */
1227 #define VID_SRC_B_DMA_CTL 0x13090C /* Video B DMA control */
1228 #define VID_SRC_C_DMA_CTL 0x130A0C /* Video C DMA control */
1229 #define VID_SRC_D_DMA_CTL 0x130B0C /* Video D DMA control */
1230 #define VID_SRC_E_DMA_CTL 0x130C0C /* Video E DMA control */
1231 #define VID_SRC_F_DMA_CTL 0x130D0C /* Video F DMA control */
1232 #define VID_SRC_I_DMA_CTL 0x130E0C /* Video I DMA control */
1233 #define VID_SRC_J_DMA_CTL 0x130F0C /* Video J DMA control */
1240 #define VID_SRC_A_FMT_CTL 0x130810 /* Video A format control */
1241 #define VID_SRC_B_FMT_CTL 0x130910 /* Video B format control */
1242 #define VID_SRC_C_FMT_CTL 0x130A10 /* Video C format control */
1243 #define VID_SRC_D_FMT_CTL 0x130B10 /* Video D format control */
1244 #define VID_SRC_E_FMT_CTL 0x130C10 /* Video E format control */
1245 #define VID_SRC_F_FMT_CTL 0x130D10 /* Video F format control */
1246 #define VID_SRC_I_FMT_CTL 0x130E10 /* Video I format control */
1247 #define VID_SRC_J_FMT_CTL 0x130F10 /* Video J format control */
1251 #define VID_SRC_A_ACTIVE_CTL1 0x130814 /* Video A active control 1 */
1252 #define VID_SRC_B_ACTIVE_CTL1 0x130914 /* Video B active control 1 */
1253 #define VID_SRC_C_ACTIVE_CTL1 0x130A14 /* Video C active control 1 */
1254 #define VID_SRC_D_ACTIVE_CTL1 0x130B14 /* Video D active control 1 */
1255 #define VID_SRC_E_ACTIVE_CTL1 0x130C14 /* Video E active control 1 */
1256 #define VID_SRC_F_ACTIVE_CTL1 0x130D14 /* Video F active control 1 */
1257 #define VID_SRC_I_ACTIVE_CTL1 0x130E14 /* Video I active control 1 */
1258 #define VID_SRC_J_ACTIVE_CTL1 0x130F14 /* Video J active control 1 */
1262 #define VID_SRC_A_ACTIVE_CTL2 0x130818 /* Video A active control 2 */
1263 #define VID_SRC_B_ACTIVE_CTL2 0x130918 /* Video B active control 2 */
1264 #define VID_SRC_C_ACTIVE_CTL2 0x130A18 /* Video C active control 2 */
1265 #define VID_SRC_D_ACTIVE_CTL2 0x130B18 /* Video D active control 2 */
1266 #define VID_SRC_E_ACTIVE_CTL2 0x130C18 /* Video E active control 2 */
1267 #define VID_SRC_F_ACTIVE_CTL2 0x130D18 /* Video F active control 2 */
1268 #define VID_SRC_I_ACTIVE_CTL2 0x130E18 /* Video I active control 2 */
1269 #define VID_SRC_J_ACTIVE_CTL2 0x130F18 /* Video J active control 2 */
1291 #define AUD_A_GPCNT_CTL 0x140014 /* Audio Int A gp control */
1304 #define AUD_B_GPCNT_CTL 0x140114 /* Audio Int B gp control */
1317 #define AUD_C_GPCNT_CTL 0x140214 /* Audio Int C gp control */
1330 #define AUD_D_GPCNT_CTL 0x140314 /* Audio Int D gp control */
1342 #define AUD_E_GPCNT_CTL 0x140414 /* Audio Int E gp control */
1365 #define AUD_INT_DMA_CTL 0x140500 /* Audio Int DMA control */
1478 #define I2C1_CTRL 0x180008 /* I2C #1 control */
1516 #define I2C2_CTRL 0x190008 /* I2C #2 control */
1533 #define I2C3_CTRL 0x1A0008 /* I2C #3 control */
/linux-4.1.27/drivers/net/irda/
H A Dgirbil-sir.c42 #define GIRBIL_ECHO 0x08 /* Echo control characters */
122 u8 control[2]; girbil_change_speed() local
142 control[0] = GIRBIL_9600; girbil_change_speed()
145 control[0] = GIRBIL_19200; girbil_change_speed()
148 control[0] = GIRBIL_38400; girbil_change_speed()
151 control[0] = GIRBIL_57600; girbil_change_speed()
154 control[0] = GIRBIL_115200; girbil_change_speed()
157 control[1] = GIRBIL_LOAD; girbil_change_speed()
159 /* Write control bytes */ girbil_change_speed()
160 sirdev_raw_write(dev, control, 2); girbil_change_speed()
204 u8 control = GIRBIL_TXEN | GIRBIL_RXEN; girbil_reset() local
224 /* Write control byte */ girbil_reset()
225 sirdev_raw_write(dev, &control, 1); girbil_reset()
H A Dact200l-sir.c139 u8 control[3]; act200l_change_speed() local
150 control[0] = ACT200L_REG8 | (ACT200L_9600 & 0x0f); act200l_change_speed()
151 control[1] = ACT200L_REG9 | ((ACT200L_9600 >> 4) & 0x0f); act200l_change_speed()
154 control[0] = ACT200L_REG8 | (ACT200L_19200 & 0x0f); act200l_change_speed()
155 control[1] = ACT200L_REG9 | ((ACT200L_19200 >> 4) & 0x0f); act200l_change_speed()
158 control[0] = ACT200L_REG8 | (ACT200L_38400 & 0x0f); act200l_change_speed()
159 control[1] = ACT200L_REG9 | ((ACT200L_38400 >> 4) & 0x0f); act200l_change_speed()
162 control[0] = ACT200L_REG8 | (ACT200L_57600 & 0x0f); act200l_change_speed()
163 control[1] = ACT200L_REG9 | ((ACT200L_57600 >> 4) & 0x0f); act200l_change_speed()
166 control[0] = ACT200L_REG8 | (ACT200L_115200 & 0x0f); act200l_change_speed()
167 control[1] = ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f); act200l_change_speed()
170 control[2] = ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE; act200l_change_speed()
172 /* Write control bytes */ act200l_change_speed()
173 sirdev_raw_write(dev, control, 3); act200l_change_speed()
196 static const u8 control[9] = { act200l_reset() local
223 /* Write control bytes */ act200l_reset()
224 sirdev_raw_write(dev, control, sizeof(control)); act200l_reset()
H A Dmcp2120-sir.c98 u8 control[2]; mcp2120_change_speed() local
114 control[0] = MCP2120_9600; mcp2120_change_speed()
118 control[0] = MCP2120_19200; mcp2120_change_speed()
122 control[0] = MCP2120_38400; mcp2120_change_speed()
126 control[0] = MCP2120_57600; mcp2120_change_speed()
130 control[0] = MCP2120_115200; mcp2120_change_speed()
134 control[1] = MCP2120_COMMIT; mcp2120_change_speed()
136 /* Write control bytes */ mcp2120_change_speed()
137 sirdev_raw_write(dev, control, 2); mcp2120_change_speed()
/linux-4.1.27/drivers/usb/class/
H A Dcdc-acm.h31 * Output control lines.
38 * Input control lines and line errors.
84 struct usb_interface *control; /* control interface */ member in struct:acm
107 unsigned int ctrlin; /* input control lines (DCD, DSR, RI, break, overruns) */
108 unsigned int ctrlout; /* output control lines (DTR, RTS) */
109 struct async_icount iocount; /* counters for control line changes */
116 unsigned int ctrl_caps; /* control capabilities from the class specific header */
118 unsigned int combined_interfaces:1; /* control and data collapsed */
/linux-4.1.27/arch/powerpc/include/asm/
H A Ddbdma.h12 * DBDMA control/status registers. All little-endian.
15 unsigned int control; /* lets you change bits in status */ member in struct:dbdma_regs
31 /* Bits in control and status registers */
65 #define KEY_STREAM1 0x100 /* control/status stream */
72 /* Interrupt control values in command field */
78 /* Branch control values in command field */
84 /* Wait control values in command field */
96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
102 out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
H A Dheathrow.h19 /* offset from ohare base for feature control register */
20 #define HEATHROW_MBCR 0x34 /* Media bay control */
21 #define HEATHROW_FCR 0x38 /* Feature control */
22 #define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */
25 * Bits in feature control register.
H A Dohare.h13 /* offset from ohare base for feature control register */
18 * Bits in feature control register.
41 * Bits to set in the feature control register on PowerBooks.
47 * A magic value to put into the feature control register of the
H A Dreg_8xx.h7 /* Cache control on the MPC8xx is provided through some additional
10 #define SPRN_IC_CST 560 /* Instruction cache control/status */
13 #define SPRN_DC_CST 568 /* Data cache control/status */
/linux-4.1.27/drivers/media/usb/dvb-usb-v2/
H A Drtl28xxu.h152 #define USB_SYSCTL 0x2000 /* USB system control */
153 #define USB_SYSCTL_0 0x2000 /* USB system control */
154 #define USB_SYSCTL_1 0x2001 /* USB system control */
155 #define USB_SYSCTL_2 0x2002 /* USB system control */
156 #define USB_SYSCTL_3 0x2003 /* USB system control */
159 #define USB_CTRL 0x2010 /* USB control */
171 #define USB_EP0_CTL 0x2108 /* EP 0 control */
182 #define USB_EPA_CTL 0x2148 /* EP A control */
183 #define USB_EPA_CTL_0 0x2148 /* EP A control */
184 #define USB_EPA_CTL_1 0x2149 /* EP A control */
185 #define USB_EPA_CTL_2 0x214A /* EP A control */
186 #define USB_EPA_CTL_3 0x214B /* EP A control */
203 #define USB_VDRCTRL 0x2F10 /* UTMI vendor signal control */
209 #define USB_TSTCTL 0x2F88 /* test control */
210 #define USB_TSTCTL2 0x2F8C /* test control 2 */
224 /* demod control registers */
226 #define SYS_DEMOD_CTL 0x3000 /* control register for DVB-T demodulator */
232 #define SYS_GPIO_DIR 0x3004 /* direction control for GPIO */
245 #define SYS_IRRC_CR 0x3030 /* IR control */
250 #define SYS_I2CMCR 0x3044 /* I2C master control */
/linux-4.1.27/drivers/staging/iio/accel/
H A Dadis16203.h17 #define ADIS16203_ALM_CTRL 0x28 /* Alarm control */
19 #define ADIS16203_GPIO_CTRL 0x32 /* General-purpose digital input/output control */
20 #define ADIS16203_MSC_CTRL 0x34 /* Miscellaneous control */
21 #define ADIS16203_SMPL_PRD 0x36 /* Internal sample period (rate) control */
23 #define ADIS16203_SLP_CNT 0x3A /* Operation, sleep mode control */
H A Dadis16201.h26 #define ADIS16201_ALM_CTRL 0x28 /* Alarm control */
28 #define ADIS16201_GPIO_CTRL 0x32 /* General-purpose digital input/output control */
29 #define ADIS16201_MSC_CTRL 0x34 /* Miscellaneous control */
30 #define ADIS16201_SMPL_PRD 0x36 /* Internal sample period (rate) control */
32 #define ADIS16201_SLP_CNT 0x3A /* Operation, sleep mode control */
H A Dadis16204.h24 #define ADIS16204_ALM_CTRL 0x28 /* Alarm control */
27 #define ADIS16204_GPIO_CTRL 0x32 /* General-purpose digital input/output control */
28 #define ADIS16204_MSC_CTRL 0x34 /* Miscellaneous control */
29 #define ADIS16204_SMPL_PRD 0x36 /* Internal sample period (rate) control */
31 #define ADIS16204_SLP_CNT 0x3A /* Operation, sleep mode control */
H A Dadis16209.h42 /* Alarm control */
46 /* General-purpose digital input/output control */
48 /* Miscellaneous control */
50 /* Internal sample period (rate) control */
54 /* Operation, sleep mode control */
H A Dadis16240.h58 /* Alarm control */
60 /* Capture, external trigger control */
64 /* Capture, configuration and control */
66 /* General-purpose digital input/output control */
68 /* Miscellaneous control */
70 /* Internal sample period (rate) control */
/linux-4.1.27/drivers/acpi/acpica/
H A Ddscontrol.c3 * Module Name: dscontrol - Support for execution control opcodes -
59 * op - The control Op
63 * DESCRIPTION: Handles all control ops encountered during control method
83 * There is no need to allocate a new control state. acpi_ds_exec_begin_control_op()
86 if (walk_state->control_state->control. acpi_ds_exec_begin_control_op()
102 * IF/WHILE: Create a new control state to manage these acpi_ds_exec_begin_control_op()
115 control_state->control.aml_predicate_start = acpi_ds_exec_begin_control_op()
117 control_state->control.package_end = acpi_ds_exec_begin_control_op()
119 control_state->control.opcode = op->common.aml_opcode; acpi_ds_exec_begin_control_op()
121 /* Push the control state on this walk's control stack */ acpi_ds_exec_begin_control_op()
155 * op - The control Op
159 * DESCRIPTION: Handles all control ops encountered during control method
186 * Pop the control state that was created at the start acpi_ds_exec_end_control_op()
213 control_state->control.loop_count++; acpi_ds_exec_end_control_op()
214 if (control_state->control.loop_count > acpi_ds_exec_end_control_op()
226 control_state->control.aml_predicate_start; acpi_ds_exec_end_control_op()
235 /* Pop this control state and free it */ acpi_ds_exec_end_control_op()
338 /* End the control method execution right now */ acpi_ds_exec_end_control_op()
369 /* Pop and delete control states until we find a while */ acpi_ds_exec_end_control_op()
372 (walk_state->control_state->control.opcode != acpi_ds_exec_end_control_op()
389 walk_state->control_state->control.package_end; acpi_ds_exec_end_control_op()
402 ACPI_ERROR((AE_INFO, "Unknown control opcode=0x%X Op=%p", acpi_ds_exec_end_control_op()
/linux-4.1.27/drivers/thermal/
H A Darmada_thermal.c49 void __iomem *control; member in struct:armada_thermal_priv
78 reg = readl_relaxed(priv->control); armadaxp_init_sensor()
80 writel(reg, priv->control); armadaxp_init_sensor()
85 writel(reg, priv->control); armadaxp_init_sensor()
88 reg = readl_relaxed(priv->control); armadaxp_init_sensor()
89 writel((reg | PMU_TDC0_SW_RST_MASK), priv->control); armadaxp_init_sensor()
91 writel(reg, priv->control); armadaxp_init_sensor()
104 reg = readl_relaxed(priv->control); armada370_init_sensor()
106 writel(reg, priv->control); armada370_init_sensor()
111 writel(reg, priv->control); armada370_init_sensor()
114 writel(reg, priv->control); armada370_init_sensor()
124 reg = readl(priv->control + 4); armada375_init_sensor()
129 writel(reg, priv->control + 4); armada375_init_sensor()
133 writel(reg, priv->control + 4); armada375_init_sensor()
140 unsigned long reg = readl_relaxed(priv->control); armada380_init_sensor()
145 writel(reg, priv->control); armada380_init_sensor()
277 priv->control = devm_ioremap_resource(&pdev->dev, res); armada_thermal_probe()
278 if (IS_ERR(priv->control)) armada_thermal_probe()
279 return PTR_ERR(priv->control); armada_thermal_probe()
H A Ddove_thermal.c48 void __iomem *control; member in struct:dove_thermal_priv
57 reg = readl_relaxed(priv->control); dove_init_sensor()
70 writel(reg, priv->control); dove_init_sensor()
73 reg = readl_relaxed(priv->control); dove_init_sensor()
74 writel((reg | PMU_TDC0_SW_RST_MASK), priv->control); dove_init_sensor()
75 writel(reg, priv->control); dove_init_sensor()
102 reg = readl_relaxed(priv->control + PMU_TEMP_DIOD_CTRL1_REG); dove_get_temp()
147 priv->control = devm_ioremap_resource(&pdev->dev, res); dove_thermal_probe()
148 if (IS_ERR(priv->control)) dove_thermal_probe()
149 return PTR_ERR(priv->control); dove_thermal_probe()
/linux-4.1.27/drivers/net/wireless/b43/
H A Dphy_ht.h10 #define B43_PHY_HT_BANDCTL 0x009 /* Band control */
15 #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
19 #define B43_PHY_HT_IQLOCAL_CMDGCTL 0x0C2 /* I/Q LO cal command G control */
38 #define B43_PHY_HT_TXPCTL_CMD_C1 0x1E7 /* TX power control command */
40 #define B43_PHY_HT_TXPCTL_CMD_C1_COEFF 0x2000 /* Power control coefficients */
41 #define B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN 0x4000 /* Hardware TX power control enable */
42 #define B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN 0x8000 /* TX power control enable */
43 #define B43_PHY_HT_TXPCTL_N 0x1E8 /* TX power control N num */
48 #define B43_PHY_HT_TXPCTL_IDLE_TSSI 0x1E9 /* TX power control idle TSSI */
54 #define B43_PHY_HT_TXPCTL_TARG_PWR 0x1EA /* TX power control target power */
101 #define B43_PHY_HT_TXPCTL_IDLE_TSSI2 B43_PHY_EXTG(0x165) /* TX power control idle TSSI */
104 #define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */
H A Dphy_ac.h8 #define B43_PHY_AC_BANDCTL 0x003 /* Band control */
15 #define B43_PHY_AC_CLASSCTL 0x140 /* Classifier control */
H A Dlo.h10 /* Local Oscillator control value-pair. */
23 * control values is calibrated for. */
26 /* The set of control values for the LO. */
40 * Used for building hardware power control tables. */
48 /* List of calibrated control values (struct b43_lo_calib). */
H A Dphy_n.h15 #define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
142 #define B43_NPHY_CRSCTL B43_PHY_N(0x047) /* CRS control */
188 #define B43_NPHY_RFCTL_CMD B43_PHY_N(0x078) /* RF control (command) */
201 #define B43_NPHY_RFCTL_RSSIO1 B43_PHY_N(0x07A) /* RF control (RSSI others 1) */
205 #define B43_NPHY_RFCTL_RSSIO1_RSSICTL 0x0030 /* RSSI control */
209 #define B43_NPHY_RFCTL_RXG1 B43_PHY_N(0x07B) /* RF control (RX gain 1) */
210 #define B43_NPHY_RFCTL_TXG1 B43_PHY_N(0x07C) /* RF control (TX gain 1) */
211 #define B43_NPHY_RFCTL_RSSIO2 B43_PHY_N(0x07D) /* RF control (RSSI others 2) */
215 #define B43_NPHY_RFCTL_RSSIO2_RSSICTL 0x0030 /* RSSI control */
219 #define B43_NPHY_RFCTL_RXG2 B43_PHY_N(0x07E) /* RF control (RX gain 2) */
220 #define B43_NPHY_RFCTL_TXG2 B43_PHY_N(0x07F) /* RF control (TX gain 2) */
221 #define B43_NPHY_RFCTL_RSSIO3 B43_PHY_N(0x080) /* RF control (RSSI others 3) */
225 #define B43_NPHY_RFCTL_RSSIO3_RSSICTL 0x0030 /* RSSI control */
229 #define B43_NPHY_RFCTL_RXG3 B43_PHY_N(0x081) /* RF control (RX gain 3) */
230 #define B43_NPHY_RFCTL_TXG3 B43_PHY_N(0x082) /* RF control (TX gain 3) */
231 #define B43_NPHY_RFCTL_RSSIO4 B43_PHY_N(0x083) /* RF control (RSSI others 4) */
235 #define B43_NPHY_RFCTL_RSSIO4_RSSICTL 0x0030 /* RSSI control */
239 #define B43_NPHY_RFCTL_RXG4 B43_PHY_N(0x084) /* RF control (RX gain 4) */
240 #define B43_NPHY_RFCTL_TXG4 B43_PHY_N(0x085) /* RF control (TX gain 4) */
243 #define B43_NPHY_C1_TXCTL B43_PHY_N(0x08B) /* Core 1 TX control */
244 #define B43_NPHY_C2_TXCTL B43_PHY_N(0x08C) /* Core 2 TX control */
245 #define B43_NPHY_AFECTL_OVER1 B43_PHY_N(0x08F) /* AFE control override 1 */
246 #define B43_NPHY_SCRAM_SIGCTL B43_PHY_N(0x090) /* Scram signal control */
249 #define B43_NPHY_SCRAM_SIGCTL_SCM 0x0080 /* Scram control mode */
250 #define B43_NPHY_SCRAM_SIGCTL_SICE 0x0100 /* Scram index control enable */
253 #define B43_NPHY_RFCTL_INTC1 B43_PHY_N(0x091) /* RF control (intc 1) */
254 #define B43_NPHY_RFCTL_INTC2 B43_PHY_N(0x092) /* RF control (intc 2) */
255 #define B43_NPHY_RFCTL_INTC3 B43_PHY_N(0x093) /* RF control (intc 3) */
256 #define B43_NPHY_RFCTL_INTC4 B43_PHY_N(0x094) /* RF control (intc 4) */
266 #define B43_NPHY_RXCTL B43_PHY_N(0x0A0) /* RX control */
289 #define B43_NPHY_AFECTL_OVER B43_PHY_N(0x0A5) /* AFE control override */
290 #define B43_NPHY_AFECTL_C1 B43_PHY_N(0x0A6) /* AFE control core 1 */
291 #define B43_NPHY_AFECTL_C2 B43_PHY_N(0x0A7) /* AFE control core 2 */
292 #define B43_NPHY_AFECTL_C3 B43_PHY_N(0x0A8) /* AFE control core 3 */
293 #define B43_NPHY_AFECTL_C4 B43_PHY_N(0x0A9) /* AFE control core 4 */
294 #define B43_NPHY_AFECTL_DACGAIN1 B43_PHY_N(0x0AA) /* AFE control DAC gain 1 */
295 #define B43_NPHY_AFECTL_DACGAIN2 B43_PHY_N(0x0AB) /* AFE control DAC gain 2 */
296 #define B43_NPHY_AFECTL_DACGAIN3 B43_PHY_N(0x0AC) /* AFE control DAC gain 3 */
297 #define B43_NPHY_AFECTL_DACGAIN4 B43_PHY_N(0x0AD) /* AFE control DAC gain 4 */
300 #define B43_NPHY_CLASSCTL B43_PHY_N(0x0B0) /* Classifier control */
312 #define B43_NPHY_MLCTL B43_PHY_N(0x0B7) /* ML control */
319 #define B43_NPHY_BPHY_CTL1 B43_PHY_N(0x0BE) /* B PHY control 1 */
320 #define B43_NPHY_BPHY_CTL2 B43_PHY_N(0x0BF) /* B PHY control 2 */
328 #define B43_NPHY_IQLOCAL_CMDGCTL B43_PHY_N(0x0C2) /* I/Q LO cal command G control */
338 #define B43_NPHY_GPIO_CLKCTL B43_PHY_N(0x0CB) /* GPIO clock control */
355 #define B43_NPHY_BPHY_CTL3 B43_PHY_N(0x0DC) /* B PHY control 3 */
360 #define B43_NPHY_BPHY_CTL4 B43_PHY_N(0x0DD) /* B PHY control 4 */
375 #define B43_NPHY_RFCTL_OVER B43_PHY_N(0x0EC) /* RF control override */
380 #define B43_NPHY_RADAR_BLNKCTL B43_PHY_N(0x0EE) /* Radar blank control */
381 #define B43_NPHY_A0RADAR_FIFOCTL B43_PHY_N(0x0EF) /* Antenna 0 radar FIFO control */
382 #define B43_NPHY_A1RADAR_FIFOCTL B43_PHY_N(0x0F0) /* Antenna 1 radar FIFO control */
390 #define B43_NPHY_RFCTL_LUT_TRSW_LO1 B43_PHY_N(0x0F8) /* RF control LUT TRSW lower 1 */
391 #define B43_NPHY_RFCTL_LUT_TRSW_UP1 B43_PHY_N(0x0F9) /* RF control LUT TRSW upper 1 */
392 #define B43_NPHY_RFCTL_LUT_TRSW_LO2 B43_PHY_N(0x0FA) /* RF control LUT TRSW lower 2 */
393 #define B43_NPHY_RFCTL_LUT_TRSW_UP2 B43_PHY_N(0x0FB) /* RF control LUT TRSW upper 2 */
394 #define B43_NPHY_RFCTL_LUT_TRSW_LO3 B43_PHY_N(0x0FC) /* RF control LUT TRSW lower 3 */
395 #define B43_NPHY_RFCTL_LUT_TRSW_UP3 B43_PHY_N(0x0FD) /* RF control LUT TRSW upper 3 */
396 #define B43_NPHY_RFCTL_LUT_TRSW_LO4 B43_PHY_N(0x0FE) /* RF control LUT TRSW lower 4 */
397 #define B43_NPHY_RFCTL_LUT_TRSW_UP4 B43_PHY_N(0x0FF) /* RF control LUT TRSW upper 4 */
398 #define B43_NPHY_RFCTL_LUT_LNAPA1 B43_PHY_N(0x100) /* RF control LUT LNA PA 1 */
399 #define B43_NPHY_RFCTL_LUT_LNAPA2 B43_PHY_N(0x101) /* RF control LUT LNA PA 2 */
400 #define B43_NPHY_RFCTL_LUT_LNAPA3 B43_PHY_N(0x102) /* RF control LUT LNA PA 3 */
401 #define B43_NPHY_RFCTL_LUT_LNAPA4 B43_PHY_N(0x103) /* RF control LUT LNA PA 4 */
409 #define B43_NPHY_SIGSTARTBIT_CTL B43_PHY_N(0x10B) /* Sig start bit control */
411 #define B43_NPHY_RFCTL_CST0 B43_PHY_N(0x10D) /* RF control core swap table 0 */
412 #define B43_NPHY_RFCTL_CST1 B43_PHY_N(0x10E) /* RF control core swap table 1 */
413 #define B43_NPHY_RFCTL_CST2O B43_PHY_N(0x10F) /* RF control core swap table 2 + others */
414 #define B43_NPHY_BPHY_CTL5 B43_PHY_N(0x111) /* B PHY control 5 */
490 #define B43_NPHY_RFCTL_DBG B43_PHY_N(0x14E) /* RF control debug */
501 #define B43_NPHY_RADAR_SRCCTL B43_PHY_N(0x158) /* Radar search control */
620 #define B43_NPHY_CRSCTL_U B43_PHY_N(0x1D9) /* CRS control U */
624 #define B43_NPHY_CRSCTL_L B43_PHY_N(0x1DD) /* CRS control L */
634 #define B43_NPHY_TXPCTL_CMD B43_PHY_N(0x1E7) /* TX power control command */
637 #define B43_NPHY_TXPCTL_CMD_COEFF 0x2000 /* Power control coefficients */
638 #define B43_NPHY_TXPCTL_CMD_HWPCTLEN 0x4000 /* Hardware TX power control enable */
639 #define B43_NPHY_TXPCTL_CMD_PCTLEN 0x8000 /* TX power control enable */
640 #define B43_NPHY_TXPCTL_N B43_PHY_N(0x1E8) /* TX power control N num */
645 #define B43_NPHY_TXPCTL_ITSSI B43_PHY_N(0x1E9) /* TX power control idle TSSI */
651 #define B43_NPHY_TXPCTL_TPWR B43_PHY_N(0x1EA) /* TX power control target power */
656 #define B43_NPHY_TXPCTL_BIDX B43_PHY_N(0x1EB) /* TX power control base index */
662 #define B43_NPHY_TXPCTL_PIDX B43_PHY_N(0x1EC) /* TX power control power index */
667 #define B43_NPHY_C1_TXPCTL_STAT B43_PHY_N(0x1ED) /* Core 1 TX power control status */
668 #define B43_NPHY_C2_TXPCTL_STAT B43_PHY_N(0x1EE) /* Core 2 TX power control status */
695 #define B43_NPHY_RX_SIGCTL B43_PHY_N(0x204) /* RX signal control */
717 #define B43_NPHY_FINERX2_CGC B43_PHY_N(0x221) /* Fine RX 2 clock gate control */
719 #define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power control init */
/linux-4.1.27/arch/x86/math-emu/
H A Dcontrol_w.h19 #define CW_RC _Const_(0x0C00) /* rounding control */
20 #define CW_PC _Const_(0x0300) /* precision control */
36 /* p 15-5: Precision control bits affect only the following:
/linux-4.1.27/sound/aoa/codecs/
H A Dtas.h11 #define TAS_REG_MCS 0x01 /* main control */
31 #define TAS_REG_ACR 0x40 /* analog control */
41 #define TAS_REG_MCS2 0x43 /* main control 2 */
H A Donyx.h59 /* bits 1-5 control channel bits 1-5 */
66 /* control channel bits 24-29, high 2 bits reserved */
72 /* lower 4 bits control bits 32-35 of channel control and word length */
/linux-4.1.27/arch/mips/pci/
H A Dops-mace.c44 u32 control = mace->pci.control; mace_pci_read_config() local
47 mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT; mace_pci_read_config()
62 mace->pci.control = control; mace_pci_read_config()
/linux-4.1.27/arch/xtensa/include/uapi/asm/
H A Dsockios.h4 * Socket-level I/O control calls. Copied from MIPS.
19 /* Socket-level I/O control calls. */
/linux-4.1.27/include/linux/platform_data/
H A Dmax3421-hcd.h16 * At this point, the only control the max3421-hcd driver cares about is
17 * to control Vbus (5V to the peripheral).
H A Dserial-sccnxp.h46 #define DIR_OP 24 /* Special signal for control RS-485.
51 /* Routing control signal 'sig' to line 'line' */
82 /* Modem control lines configuration */
/linux-4.1.27/arch/m68k/include/asm/
H A Dmac_baboon.h12 * bit 5 : slot 2 power control
13 * bit 6 : slot 1 power control
H A Dmcfqspi.h20 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
21 * @setup: setup the control; allocate gpio's, etc. May be NULL.
22 * @teardown: finish with the control; free gpio's, etc. May be NULL.
42 * @cs_control: platform dependent chip select control.
H A Dm54xxpci.h33 #define PCIGSCR (CONFIG_MBAR + 0xb60) /* Global status/control */
36 #define PCITCR (CONFIG_MBAR + 0xb6c) /* Target control */
41 #define PCIICR (CONFIG_MBAR + 0xb84) /* Initiator control */
47 #define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */
55 #define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */
62 #define PCIRTCR (CONFIG_MBAR + 0x8488) /* RX transaction control */
69 #define PCIRFCR (CONFIG_MBAR + 0x84c8) /* RX FIFO control */
74 #define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */
78 * Definitions for the Global status and control register.
H A Didprom.h24 /* Sun3: in control space */
H A Dkexec.h10 /* Maximum address we can use for the control code buffer */
/linux-4.1.27/include/linux/can/platform/
H A Dsja1000.h11 /* output control register */
31 u8 ocr; /* output control register */
/linux-4.1.27/drivers/scsi/
H A Daha152x.h15 #define SCSISEQ (HOSTIOPORT0+0x00) /* SCSI sequence control */
16 #define SXFRCTL0 (HOSTIOPORT0+0x01) /* SCSI transfer control 0 */
17 #define SXFRCTL1 (HOSTIOPORT0+0x02) /* SCSI transfer control 1 */
19 #define SCSIRATE (HOSTIOPORT0+0x04) /* SCSI rate control */
30 #define SCSITEST (HOSTIOPORT0+0x0e) /* SCSI test control */
35 #define DMACNTRL0 (HOSTIOPORT1+0x12) /* DMA control 0 */
36 #define DMACNTRL1 (HOSTIOPORT1+0x13) /* DMA control 1 */
40 #define BRSTCNTRL (HOSTIOPORT1+0x18) /* burst control */
52 #define O_DMACNTRL1 0x13 /* DMA control 1 */
58 #define O_TC_DMACNTRL1 0x03 /* DMA control 1 */
63 /* SCSI sequence control */
73 /* SCSI transfer control 0 */
81 /* SCSI transfer control 1 */
119 /* SCSI rate control */
186 /* SCSI TEST control */
219 /* DMA control 0 */
228 /* DMA control 1 */
239 /* BURST control */
/linux-4.1.27/drivers/usb/gadget/udc/
H A Dmv_u3d.h75 /* ep control register */
138 u32 portsc; /* port status and control register*/
144 /* control enpoint enable registers */
146 u32 epxoutcr0; /* ep out control 0 register */
147 u32 epxoutcr1; /* ep out control 1 register */
148 u32 epxincr0; /* ep in control 0 register */
149 u32 epxincr1; /* ep in control 1 register */
160 /* vendor unique control registers */
162 u32 ctrlepenable; /* control endpoint enable register */
176 u32 ltssm; /* LTSSM control register */
177 u32 pipe; /* PIPE control register */
178 u32 linkcr0; /* link control 0 register */
179 u32 linkcr1; /* link control 1 register */
182 u32 usblink; /* usb link control register */
190 struct epxcr epcr[16]; /* ep control register */
207 /* TRB control data structure */
219 u32 dir:1; /* Working at data stage of control endpoint
231 struct mv_u3d_trb_ctrl ctrl; /* TRB control data */
/linux-4.1.27/drivers/video/backlight/
H A Dtdo24m.c93 CMD1(0xcf, 0x02), /* Blanking period control (1) */
94 CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
95 CMD1(0xd1, 0x01), /* CKV timing control on/off */
96 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
97 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
98 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
99 CMD1(0xd5, 0x14), /* ASW timing control (2) */
106 CMD1(0xd6, 0x02), /* Blanking period control (1) */
107 CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
108 CMD1(0xd8, 0x01), /* CKV timing control on/off */
109 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
110 CMD2(0xde, 0x05, 0x0a), /* OEV timing control */
111 CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */
112 CMD1(0xe0, 0x0a), /* ASW timing control (2) */
135 CMD1(0xcf, 0x02), /* Blanking period control (1) */
136 CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
137 CMD1(0xd1, 0x01), /* CKV timing control on/off */
138 CMD2(0xd2, 0x00, 0x1e), /* CKV 1,2 timing control */
139 CMD2(0xd3, 0x14, 0x28), /* OEV timing control */
140 CMD2(0xd4, 0x28, 0x64), /* ASW timing control (1) */
141 CMD1(0xd5, 0x28), /* ASW timing control (2) */
148 CMD2(0xb8, 0xff, 0xf9), /* Output control */
153 CMD1(0xbf, 0x10), /* Drive system change control */
/linux-4.1.27/arch/um/drivers/
H A Ddaemon_user.c55 pri->control = socket(AF_UNIX, SOCK_STREAM, 0); connect_to_switch()
56 if (pri->control < 0) { connect_to_switch()
58 printk(UM_KERN_ERR "daemon_open : control socket failed, " connect_to_switch()
63 if (connect(pri->control, (struct sockaddr *) ctl_addr, connect_to_switch()
66 printk(UM_KERN_ERR "daemon_open : control connect failed, " connect_to_switch()
97 n = write(pri->control, &req, sizeof(req)); connect_to_switch()
99 printk(UM_KERN_ERR "daemon_open : control setup request " connect_to_switch()
105 n = read(pri->control, sun, sizeof(*sun)); connect_to_switch()
121 close(pri->control); connect_to_switch()
166 close(pri->control); daemon_remove()
167 pri->control = -1; daemon_remove()
H A Ddaemon.h20 int control; member in struct:daemon_data
/linux-4.1.27/drivers/phy/
H A Dphy-omap-control.c2 * omap-control-phy.c - The PHY part of control module.
31 * @dev: the control module device
46 dev_err(dev, "%s: invalid control phy device\n", __func__); omap_control_pcie_pcs()
64 * omap_control_phy_power - power on/off the phy using control module reg
65 * @dev: the control module device
81 dev_err(dev, "%s: invalid control phy device\n", __func__); omap_control_phy_power()
204 * @dev: the control module device
220 dev_err(dev, "Invalid control phy device\n"); omap_control_usb_set_mode()
238 dev_vdbg(dev, "invalid omap control usb mode\n"); omap_control_usb_set_mode()
252 .compatible = "ti,control-phy-otghs",
256 .compatible = "ti,control-phy-usb2",
260 .compatible = "ti,control-phy-pipe3",
264 .compatible = "ti,control-phy-pcie",
268 .compatible = "ti,control-phy-usb2-dra7",
272 .compatible = "ti,control-phy-usb2-am437",
340 .name = "omap-control-phy",
/linux-4.1.27/drivers/staging/media/lirc/
H A Dlirc_parallel.h19 #define LIRC_PORT_IRQ LIRC_LP_CONTROL /* control port */
/linux-4.1.27/arch/metag/kernel/
H A Dda.c2 * Meta DA JTAG debugger control.
/linux-4.1.27/arch/mips/include/asm/mach-bcm63xx/
H A Dbcm63xx_iudma.h14 /* control */
/linux-4.1.27/include/linux/
H A Dsonet.h1 /* sonet.h - SONET/SHD physical layer control */
H A Deeprom_93xx46.h13 * optional hooks to control additional logic
H A Dcpufreq-dt.h15 * True when each CPU has its own clock to control its
H A Dds17287rtc.h32 #define DS_B1_XCTRL4A 0x4a /* extendec control register 4a */
33 #define DS_B1_XCTRL4B 0x4b /* extendec control register 4b */
41 /* extended control register 4a */
53 /* extended control register 4b */
/linux-4.1.27/arch/s390/include/asm/
H A Dctl_reg.h57 unsigned long lap : 1; /* Low-address-protection control */
59 unsigned long edat : 1; /* Enhanced-DAT-enablement control */
61 unsigned long afp : 1; /* AFP-register control */
62 unsigned long vx : 1; /* Vector enablement control */
H A Dkexec.h25 /* Maximum address we can use for the control pages */
29 /* Allocate control page with GFP_DMA */
32 /* Maximum address we can use for the crash control pages */
48 * tod_cmp, tod_reg, control regs, and prefix
/linux-4.1.27/arch/sh/include/uapi/asm/
H A Dsockios.h4 /* Socket-level I/O control calls. */
/linux-4.1.27/arch/mn10300/include/asm/
H A Dintctl-regs.h37 /* non-maskable interrupt control */
39 #define NMICR GxICR(NMIIRQ) /* NMI control register */
44 /* maskable interrupt control */
67 #define XIRQxICR(X) GxICR((X)) /* external interrupt control regs */
/linux-4.1.27/arch/ia64/include/uapi/asm/
H A Dsockios.h5 * Socket-level I/O control calls.
H A Dtermios.h25 unsigned short c_cflag; /* control mode flags */
28 unsigned char c_cc[NCC]; /* control characters */
H A Dfpu.h26 #define FPSF_PC(x) (((x) & 0x3) << 2) /* precision control */
27 #define FPSF_RC(x) (((x) & 0x3) << 4) /* rounding control */
38 /* floating-point rounding control: */
/linux-4.1.27/arch/alpha/include/uapi/asm/
H A Dsockios.h4 /* Socket-level I/O control calls. */
/linux-4.1.27/drivers/staging/rtl8712/
H A Drtl871x_led.h72 SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
74 SW_LED_MODE2, /* SW control 1 LED via GPIO0,
76 SW_LED_MODE3, /* SW control 1 LED via GPIO0,
81 HW_LED, /* HW control 2 LEDs, LED0 and LED1 (there are 4 different
82 * control modes, see MAC.CONFIG1 for details.)*/
106 /* add for led control */
113 /* add for led control */
/linux-4.1.27/drivers/net/ethernet/altera/
H A Daltera_msgdma.c45 msgdma_csroffs(control)); msgdma_reset()
67 msgdma_csroffs(control)); msgdma_reset()
87 tse_clear_bit(priv->rx_dma_csr, msgdma_csroffs(control), msgdma_disable_rxirq()
93 tse_set_bit(priv->rx_dma_csr, msgdma_csroffs(control), msgdma_enable_rxirq()
99 tse_clear_bit(priv->tx_dma_csr, msgdma_csroffs(control), msgdma_disable_txirq()
105 tse_set_bit(priv->tx_dma_csr, msgdma_csroffs(control), msgdma_enable_txirq()
133 msgdma_descroffs(control)); msgdma_tx_buffer()
167 u32 control = (MSGDMA_DESC_CTL_END_ON_EOP msgdma_add_rx_desc() local
183 csrwr32(control, priv->rx_dma_desc, msgdma_descroffs(control)); msgdma_add_rx_desc()
/linux-4.1.27/arch/x86/kvm/
H A Dsvm.c235 vmcb->control.clean = 0; mark_all_dirty()
240 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) mark_all_clean()
246 vmcb->control.clean &= ~(1 << bit); mark_dirty()
264 c = &svm->vmcb->control; recalc_intercepts()
265 h = &svm->nested.hsave->control; recalc_intercepts()
286 vmcb->control.intercept_cr |= (1U << bit); set_cr_intercept()
295 vmcb->control.intercept_cr &= ~(1U << bit); clr_cr_intercept()
304 return vmcb->control.intercept_cr & (1U << bit); is_cr_intercept()
311 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ) set_dr_intercepts()
335 vmcb->control.intercept_dr = 0; clr_dr_intercepts()
344 vmcb->control.intercept_exceptions |= (1U << bit); set_exception_intercept()
353 vmcb->control.intercept_exceptions &= ~(1U << bit); clr_exception_intercept()
362 vmcb->control.intercept |= (1ULL << bit); set_intercept()
371 vmcb->control.intercept &= ~(1ULL << bit); clr_intercept()
494 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) svm_get_interrupt_shadow()
504 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; svm_set_interrupt_shadow()
506 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; svm_set_interrupt_shadow()
514 if (svm->vmcb->control.next_rip != 0) { skip_emulated_instruction()
516 svm->next_rip = svm->vmcb->control.next_rip; skip_emulated_instruction()
563 svm->vmcb->control.event_inj = nr svm_queue_exception()
567 svm->vmcb->control.event_inj_err = error_code; svm_queue_exception()
849 svm->vmcb->control.lbr_ctl = 1; svm_enable_lbrv()
860 svm->vmcb->control.lbr_ctl = 0; svm_disable_lbrv()
1035 return svm->vmcb->control.tsc_offset; svm_read_tsc_offset()
1044 g_tsc_offset = svm->vmcb->control.tsc_offset - svm_write_tsc_offset()
1045 svm->nested.hsave->control.tsc_offset; svm_write_tsc_offset()
1046 svm->nested.hsave->control.tsc_offset = offset; svm_write_tsc_offset()
1049 svm->vmcb->control.tsc_offset, svm_write_tsc_offset()
1052 svm->vmcb->control.tsc_offset = offset + g_tsc_offset; svm_write_tsc_offset()
1067 svm->vmcb->control.tsc_offset += adjustment; svm_adjust_tsc_offset()
1069 svm->nested.hsave->control.tsc_offset += adjustment; svm_adjust_tsc_offset()
1072 svm->vmcb->control.tsc_offset - adjustment, svm_adjust_tsc_offset()
1073 svm->vmcb->control.tsc_offset); svm_adjust_tsc_offset()
1089 struct vmcb_control_area *control = &svm->vmcb->control; init_vmcb() local
1137 control->iopm_base_pa = iopm_base; init_vmcb()
1138 control->msrpm_base_pa = __pa(svm->msrpm); init_vmcb()
1139 control->int_ctl = V_INTR_MASKING_MASK; init_vmcb()
1178 control->nested_ctl = 1; init_vmcb()
1193 control->pause_filter_count = 3000; init_vmcb()
1660 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; new_asid()
1664 svm->vmcb->control.asid = sd->next_asid++; new_asid()
1707 u64 fault_address = svm->vmcb->control.exit_info_2; pf_interception()
1713 error_code = svm->vmcb->control.exit_info_1; pf_interception()
1719 svm->vmcb->control.insn_bytes, pf_interception()
1720 svm->vmcb->control.insn_len); pf_interception()
1897 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ io_interception()
1909 svm->next_rip = svm->vmcb->control.exit_info_2; io_interception()
1970 svm->vmcb->control.nested_cr3 = root; nested_svm_set_tdp_cr3()
1980 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) { nested_svm_inject_npf_exit()
1985 svm->vmcb->control.exit_code = SVM_EXIT_NPF; nested_svm_inject_npf_exit()
1986 svm->vmcb->control.exit_code_hi = 0; nested_svm_inject_npf_exit()
1987 svm->vmcb->control.exit_info_1 = (1ULL << 32); nested_svm_inject_npf_exit()
1988 svm->vmcb->control.exit_info_2 = fault->address; nested_svm_inject_npf_exit()
1991 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL; nested_svm_inject_npf_exit()
1992 svm->vmcb->control.exit_info_1 |= fault->error_code; nested_svm_inject_npf_exit()
1998 if (svm->vmcb->control.exit_info_1 & (2ULL << 32)) nested_svm_inject_npf_exit()
1999 svm->vmcb->control.exit_info_1 &= ~1; nested_svm_inject_npf_exit()
2045 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; nested_svm_check_exception()
2046 svm->vmcb->control.exit_code_hi = 0; nested_svm_check_exception()
2047 svm->vmcb->control.exit_info_1 = error_code; nested_svm_check_exception()
2048 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; nested_svm_check_exception()
2077 svm->vmcb->control.exit_code = SVM_EXIT_INTR; nested_svm_intr()
2078 svm->vmcb->control.exit_info_1 = 0; nested_svm_intr()
2079 svm->vmcb->control.exit_info_2 = 0; nested_svm_intr()
2105 svm->vmcb->control.exit_code = SVM_EXIT_NMI; nested_svm_nmi()
2147 port = svm->vmcb->control.exit_info_1 >> 16; nested_svm_intercept_ioio()
2148 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >> nested_svm_intercept_ioio()
2172 write = svm->vmcb->control.exit_info_1 & 1; nested_svm_exit_handled_msr()
2189 u32 exit_code = svm->vmcb->control.exit_code; nested_svm_exit_special()
2221 u32 exit_code = svm->vmcb->control.exit_code; nested_svm_intercept()
2281 struct vmcb_control_area *dst = &dst_vmcb->control; copy_vmcb_control_area()
2282 struct vmcb_control_area *from = &from_vmcb->control; copy_vmcb_control_area()
2316 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, nested_svm_vmexit()
2317 vmcb->control.exit_info_1, nested_svm_vmexit()
2318 vmcb->control.exit_info_2, nested_svm_vmexit()
2319 vmcb->control.exit_int_info, nested_svm_vmexit()
2320 vmcb->control.exit_int_info_err, nested_svm_vmexit()
2353 nested_vmcb->control.int_ctl = vmcb->control.int_ctl; nested_svm_vmexit()
2354 nested_vmcb->control.int_vector = vmcb->control.int_vector; nested_svm_vmexit()
2355 nested_vmcb->control.int_state = vmcb->control.int_state; nested_svm_vmexit()
2356 nested_vmcb->control.exit_code = vmcb->control.exit_code; nested_svm_vmexit()
2357 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; nested_svm_vmexit()
2358 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; nested_svm_vmexit()
2359 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; nested_svm_vmexit()
2360 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; nested_svm_vmexit()
2361 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; nested_svm_vmexit()
2362 nested_vmcb->control.next_rip = vmcb->control.next_rip; nested_svm_vmexit()
2372 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { nested_svm_vmexit()
2373 struct vmcb_control_area *nc = &nested_vmcb->control; nested_svm_vmexit()
2375 nc->exit_int_info = vmcb->control.event_inj; nested_svm_vmexit()
2376 nc->exit_int_info_err = vmcb->control.event_inj_err; nested_svm_vmexit()
2379 nested_vmcb->control.tlb_ctl = 0; nested_svm_vmexit()
2380 nested_vmcb->control.event_inj = 0; nested_svm_vmexit()
2381 nested_vmcb->control.event_inj_err = 0; nested_svm_vmexit()
2385 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; nested_svm_vmexit()
2387 /* Restore the original control entries */ nested_svm_vmexit()
2417 svm->vmcb->control.exit_int_info = 0; nested_svm_vmexit()
2458 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); nested_svm_vmrun_msrpm()
2465 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) nested_vmcb_checks()
2468 if (vmcb->control.asid == 0) nested_vmcb_checks()
2471 if (vmcb->control.nested_ctl && !npt_enabled) nested_vmcb_checks()
2492 nested_vmcb->control.exit_code = SVM_EXIT_ERR; nested_svm_vmrun()
2493 nested_vmcb->control.exit_code_hi = 0; nested_svm_vmrun()
2494 nested_vmcb->control.exit_info_1 = 0; nested_svm_vmrun()
2495 nested_vmcb->control.exit_info_2 = 0; nested_svm_vmrun()
2504 nested_vmcb->control.int_ctl, nested_svm_vmrun()
2505 nested_vmcb->control.event_inj, nested_svm_vmrun()
2506 nested_vmcb->control.nested_ctl); nested_svm_vmrun()
2508 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, nested_svm_vmrun()
2509 nested_vmcb->control.intercept_cr >> 16, nested_svm_vmrun()
2510 nested_vmcb->control.intercept_exceptions, nested_svm_vmrun()
2511 nested_vmcb->control.intercept); nested_svm_vmrun()
2546 if (nested_vmcb->control.nested_ctl) { nested_svm_vmrun()
2548 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; nested_svm_vmrun()
2585 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; nested_svm_vmrun()
2586 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; nested_svm_vmrun()
2589 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; nested_svm_vmrun()
2590 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; nested_svm_vmrun()
2591 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; nested_svm_vmrun()
2592 svm->nested.intercept = nested_vmcb->control.intercept; nested_svm_vmrun()
2595 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; nested_svm_vmrun()
2596 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) nested_svm_vmrun()
2610 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; nested_svm_vmrun()
2611 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; nested_svm_vmrun()
2612 svm->vmcb->control.int_state = nested_vmcb->control.int_state; nested_svm_vmrun()
2613 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; nested_svm_vmrun()
2614 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; nested_svm_vmrun()
2615 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; nested_svm_vmrun()
2713 svm->vmcb->control.exit_code = SVM_EXIT_ERR; vmrun_interception()
2714 svm->vmcb->control.exit_code_hi = 0; vmrun_interception()
2715 svm->vmcb->control.exit_info_1 = 0; vmrun_interception()
2716 svm->vmcb->control.exit_info_2 = 0; vmrun_interception()
2749 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; clgi_interception()
2802 int int_type = svm->vmcb->control.exit_int_info & task_switch_interception()
2804 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; task_switch_interception()
2806 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; task_switch_interception()
2808 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; task_switch_interception()
2812 tss_selector = (u16)svm->vmcb->control.exit_info_1; task_switch_interception()
2814 if (svm->vmcb->control.exit_info_2 & task_switch_interception()
2817 else if (svm->vmcb->control.exit_info_2 & task_switch_interception()
2831 if (svm->vmcb->control.exit_info_2 & task_switch_interception()
2835 (u32)svm->vmcb->control.exit_info_2; task_switch_interception()
2888 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); invlpg_interception()
2928 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; check_selective_cr0_intercepted()
2946 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) cr_interception()
2949 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; cr_interception()
2950 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE) cr_interception()
2953 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; cr_interception()
3029 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; dr_interception()
3030 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; dr_interception()
3068 return vmcb->control.tsc_offset + svm_read_l1_tsc()
3078 *data = svm->vmcb->control.tsc_offset + svm_get_msr()
3279 if (svm->vmcb->control.exit_info_1) msr_interception()
3291 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; interrupt_window_interception()
3399 struct vmcb_control_area *control = &svm->vmcb->control; dump_vmcb() local
3403 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); dump_vmcb()
3404 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); dump_vmcb()
3405 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); dump_vmcb()
3406 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); dump_vmcb()
3407 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); dump_vmcb()
3408 pr_err("%-20s%016llx\n", "intercepts:", control->intercept); dump_vmcb()
3409 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); dump_vmcb()
3410 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); dump_vmcb()
3411 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); dump_vmcb()
3412 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); dump_vmcb()
3413 pr_err("%-20s%d\n", "asid:", control->asid); dump_vmcb()
3414 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); dump_vmcb()
3415 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); dump_vmcb()
3416 pr_err("%-20s%08x\n", "int_vector:", control->int_vector); dump_vmcb()
3417 pr_err("%-20s%08x\n", "int_state:", control->int_state); dump_vmcb()
3418 pr_err("%-20s%08x\n", "exit_code:", control->exit_code); dump_vmcb()
3419 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); dump_vmcb()
3420 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); dump_vmcb()
3421 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); dump_vmcb()
3422 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); dump_vmcb()
3423 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); dump_vmcb()
3424 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); dump_vmcb()
3425 pr_err("%-20s%08x\n", "event_inj:", control->event_inj); dump_vmcb()
3426 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); dump_vmcb()
3427 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl); dump_vmcb()
3428 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); dump_vmcb()
3503 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; svm_get_exit_info() local
3505 *info1 = control->exit_info_1; svm_get_exit_info()
3506 *info2 = control->exit_info_2; svm_get_exit_info()
3513 u32 exit_code = svm->vmcb->control.exit_code; handle_exit()
3531 svm->vmcb->control.exit_info_1, handle_exit()
3532 svm->vmcb->control.exit_info_2, handle_exit()
3533 svm->vmcb->control.exit_int_info, handle_exit()
3534 svm->vmcb->control.exit_int_info_err, handle_exit()
3548 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { handle_exit()
3551 = svm->vmcb->control.exit_code; handle_exit()
3557 if (is_external_interrupt(svm->vmcb->control.exit_int_info) && handle_exit()
3563 __func__, svm->vmcb->control.exit_int_info, handle_exit()
3600 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; svm_inject_nmi()
3608 struct vmcb_control_area *control; svm_inject_irq() local
3610 control = &svm->vmcb->control; svm_inject_irq()
3611 control->int_vector = irq; svm_inject_irq()
3612 control->int_ctl &= ~V_INTR_PRIO_MASK; svm_inject_irq()
3613 control->int_ctl |= V_IRQ_MASK | svm_inject_irq()
3614 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); svm_inject_irq()
3627 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | svm_set_irq()
3672 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && svm_nmi_allowed()
3706 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) svm_interrupt_allowed()
3759 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; svm_flush_tlb()
3776 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; sync_cr8_to_lapic()
3790 svm->vmcb->control.int_ctl &= ~V_TPR_MASK; sync_lapic_to_cr8()
3791 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; sync_lapic_to_cr8()
3798 u32 exitintinfo = svm->vmcb->control.exit_int_info; svm_complete_interrupts()
3844 u32 err = svm->vmcb->control.exit_int_info_err; svm_complete_interrupts()
3861 struct vmcb_control_area *control = &svm->vmcb->control; svm_cancel_injection() local
3863 control->exit_int_info = control->event_inj; svm_cancel_injection()
3864 control->exit_int_info_err = control->event_inj_err; svm_cancel_injection()
3865 control->event_inj = 0; svm_cancel_injection()
3985 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM); svm_vcpu_run()
3987 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) svm_vcpu_run()
3994 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) svm_vcpu_run()
4001 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; svm_vcpu_run()
4004 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) svm_vcpu_run()
4016 if (unlikely(svm->vmcb->control.exit_code == svm_vcpu_run()
4036 svm->vmcb->control.nested_cr3 = root; set_tdp_cr3()
4275 vmcb->control.exit_info_1 = 1; svm_check_intercept()
4277 vmcb->control.exit_info_1 = 0; svm_check_intercept()
4313 vmcb->control.exit_info_1 = exit_info; svm_check_intercept()
4314 vmcb->control.exit_info_2 = info->next_rip; svm_check_intercept()
4324 vmcb->control.next_rip = info->next_rip; svm_check_intercept()
4325 vmcb->control.exit_code = icpt_info.exit_code; svm_check_intercept()
/linux-4.1.27/sound/core/
H A Dcontrol.c2 * Routines for driver control interface
31 #include <sound/control.h>
121 struct snd_kcontrol *control; snd_ctl_release() local
131 list_for_each_entry(control, &card->controls, list) snd_ctl_release()
132 for (idx = 0; idx < control->count; idx++) snd_ctl_release()
133 if (control->vd[idx].owner == ctl) snd_ctl_release()
134 control->vd[idx].owner = NULL; snd_ctl_release()
145 * snd_ctl_notify - Send notification to user-space for a control change
195 * snd_ctl_new - create a new control instance with some elements
196 * @kctl: the pointer to store new control instance
197 * @count: the number of elements in this control
198 * @access: the default access flags for elements in this control
201 * Allocates a memory object for a new control instance. The instance has
233 * snd_ctl_new1 - create a control instance from the template
297 * snd_ctl_free_one - release the control instance
298 * @kcontrol: the control instance
300 * Releases the control instance created via snd_ctl_new()
302 * Don't call this after the control was added to the card.
319 /* Make sure that the ids assigned to the control do not wrap around */ snd_ctl_remove_numid_conflict()
340 dev_err(card->dev, "unable to allocate new control numid\n"); snd_ctl_find_hole()
348 * snd_ctl_add - add the control instance to the card
350 * @kcontrol: the control instance to add
352 * Adds the control instance created via snd_ctl_new() or
356 * It frees automatically the control which cannot be added.
379 dev_err(card->dev, "control %i:%i:%i:%s:%i is already present\n", snd_ctl_add()
411 * snd_ctl_replace - replace the control instance of the card
413 * @kcontrol: the control instance to replace
414 * @add_on_replace: add the control if not already added
416 * Replaces the given control. If the given control does not exist
417 * and the add_on_replace flag is set, the control is added. If the
418 * control exists, it is destroyed first.
420 * It frees automatically the control which cannot be added or replaced.
478 * snd_ctl_remove - remove the control from the card and release it
480 * @kcontrol: the control instance to remove
482 * Removes the control from the card and then releases the instance.
506 * snd_ctl_remove_id - remove the control of the given id and release it
508 * @id: the control id to remove
510 * Finds the control instance with the given id, removes it from the
533 * snd_ctl_remove_user_ctl - remove and release the unlocked user control
534 * @file: active control handle
535 * @id: the control id to remove
537 * Finds the control instance with the given id, removes it from the
574 * snd_ctl_activate_id - activate/inactivate the control of the given id
576 * @id: the control id to activate/inactivate
579 * Finds the control instance with the given id, and activate or
580 * inactivate the control together with notification, if changed.
622 * snd_ctl_rename_id - replace the id of a control on the card
627 * Finds the control with the old id from the card, and replaces the
652 * snd_ctl_find_numid - find the control instance with the given number-id
656 * Finds the control instance with the given number-id from the card.
679 * snd_ctl_find_id - find the control instance with the given id
683 * Finds the control instance with the given id from the card.
866 struct snd_ctl_elem_value *control) snd_ctl_elem_read()
874 kctl = snd_ctl_find_id(card, &control->id); snd_ctl_elem_read()
878 index_offset = snd_ctl_get_ioff(kctl, &control->id); snd_ctl_elem_read()
882 snd_ctl_build_ioff(&control->id, kctl, index_offset); snd_ctl_elem_read()
883 result = kctl->get(kctl, control); snd_ctl_elem_read()
894 struct snd_ctl_elem_value *control; snd_ctl_elem_read_user() local
897 control = memdup_user(_control, sizeof(*control)); snd_ctl_elem_read_user()
898 if (IS_ERR(control)) snd_ctl_elem_read_user()
899 return PTR_ERR(control); snd_ctl_elem_read_user()
904 result = snd_ctl_elem_read(card, control); snd_ctl_elem_read_user()
907 if (copy_to_user(_control, control, sizeof(*control))) snd_ctl_elem_read_user()
909 kfree(control); snd_ctl_elem_read_user()
914 struct snd_ctl_elem_value *control) snd_ctl_elem_write()
922 kctl = snd_ctl_find_id(card, &control->id); snd_ctl_elem_write()
926 index_offset = snd_ctl_get_ioff(kctl, &control->id); snd_ctl_elem_write()
933 snd_ctl_build_ioff(&control->id, kctl, index_offset); snd_ctl_elem_write()
934 result = kctl->put(kctl, control); snd_ctl_elem_write()
937 struct snd_ctl_elem_id id = control->id; snd_ctl_elem_write()
950 struct snd_ctl_elem_value *control; snd_ctl_elem_write_user() local
954 control = memdup_user(_control, sizeof(*control)); snd_ctl_elem_write_user()
955 if (IS_ERR(control)) snd_ctl_elem_write_user()
956 return PTR_ERR(control); snd_ctl_elem_write_user()
962 result = snd_ctl_elem_write(card, file, control); snd_ctl_elem_write_user()
965 if (copy_to_user(_control, control, sizeof(*control))) snd_ctl_elem_write_user()
967 kfree(control); snd_ctl_elem_write_user()
1231 /* Delete a control to replace them if needed. */ snd_ctl_elem_add()
1240 * The number of userspace controls are counted control by control, snd_ctl_elem_add()
1246 /* Check the number of elements for this userspace control. */ snd_ctl_elem_add()
1264 * this userspace control. snd_ctl_elem_add()
1278 * Keep memory object for this userspace control. After passing this snd_ctl_elem_add()
1281 * Note that these elements in this control are locked. snd_ctl_elem_add()
1295 /* Set private data for this userspace control. */ snd_ctl_elem_add()
1602 * register the device-specific control-ioctls.
1620 * snd_ctl_register_ioctl - register the device-specific control-ioctls
1634 * control-ioctls
1645 * de-register the device-specific control-ioctls.
1669 * snd_ctl_unregister_ioctl - de-register the device-specific control-ioctls
1681 * control-ioctls
1747 * registration of the control device
1758 * disconnection of the control device
1781 struct snd_kcontrol *control; snd_ctl_dev_free() local
1785 control = snd_kcontrol(card->controls.next); snd_ctl_dev_free()
1786 snd_ctl_remove(card, control); snd_ctl_dev_free()
1794 * create control core:
1821 * Frequently used control callbacks/helpers
1831 * boolean control with a single mono channel.
1851 * boolean control with stereo two channels.
1865 * snd_ctl_enum_info - fills the info structure for an enumerated control
1867 * @channels: the number of the control's channels; often one
1868 * @items: the number of control values; also the size of @names
1869 * @names: an array containing the names of all control values
1872 * If the control's accessibility is not the default (readable and writable),
865 snd_ctl_elem_read(struct snd_card *card, struct snd_ctl_elem_value *control) snd_ctl_elem_read() argument
913 snd_ctl_elem_write(struct snd_card *card, struct snd_ctl_file *file, struct snd_ctl_elem_value *control) snd_ctl_elem_write() argument
/linux-4.1.27/arch/sparc/include/asm/
H A Dswift.h10 /* Swift is so brain damaged, here is the mmu control register. */
16 #define SWIFT_PMC 0x00180000 /* Page mode control */
18 #define SWIFT_PC 0x00020000 /* Parity control */
19 #define SWIFT_AP 0x00010000 /* Graphics page mode control (TCX/SX) */
22 #define SWIFT_RC 0x00003c00 /* DRAM refresh control */
H A Dsbi.h24 /* 0x0020 */ u32 stb0; /* Streaming buf control for slot 0 */
25 /* 0x0024 */ u32 stb1; /* Streaming buf control for slot 1 */
26 /* 0x0028 */ u32 stb2; /* Streaming buf control for slot 2 */
27 /* 0x002c */ u32 stb3; /* Streaming buf control for slot 3 */
/linux-4.1.27/arch/sparc/kernel/
H A Dpsycho_common.c37 u64 control; psycho_check_stc_error() local
57 control = upa_readq(strbuf->strbuf_control); psycho_check_stc_error()
58 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control); psycho_check_stc_error()
74 upa_writeq(control, strbuf->strbuf_control); psycho_check_stc_error()
205 u64 control, iommu_tag[16], iommu_data[16]; psycho_check_iommu_error() local
210 control = upa_readq(iommu->iommu_control); psycho_check_iommu_error()
211 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) { psycho_check_iommu_error()
214 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR; psycho_check_iommu_error()
215 upa_writeq(control, iommu->iommu_control); psycho_check_iommu_error()
217 switch ((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) { psycho_check_iommu_error()
403 u64 control; psycho_iommu_init() local
415 control = upa_readq(iommu->iommu_control); psycho_iommu_init()
416 control |= PSYCHO_IOMMU_CTRL_DENAB; psycho_iommu_init()
417 upa_writeq(control, iommu->iommu_control); psycho_iommu_init()
429 control = upa_readq(iommu->iommu_control); psycho_iommu_init()
430 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ); psycho_iommu_init()
431 control |= PSYCHO_IOMMU_CTRL_ENAB; psycho_iommu_init()
435 control |= PSYCHO_IOMMU_TSBSZ_64K; psycho_iommu_init()
438 control |= PSYCHO_IOMMU_TSBSZ_128K; psycho_iommu_init()
444 upa_writeq(control, iommu->iommu_control); psycho_iommu_init()
/linux-4.1.27/arch/mips/oprofile/
H A Dop_model_mipsxx.c144 unsigned int control[4]; member in struct:mipsxx_register_config
155 /* Compute the performance counter control word. */ mipsxx_reg_setup()
157 reg.control[i] = 0; mipsxx_reg_setup()
163 reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) | mipsxx_reg_setup()
166 reg.control[i] |= M_PERFCTL_KERNEL; mipsxx_reg_setup()
168 reg.control[i] |= M_PERFCTL_USER; mipsxx_reg_setup()
170 reg.control[i] |= M_PERFCTL_EXL; mipsxx_reg_setup()
172 reg.control[i] |= M_PERFCTL_COUNT_ALL_THREADS; mipsxx_reg_setup()
212 w_c0_perfctrl3(WHAT | reg.control[3]); mipsxx_cpu_start()
214 w_c0_perfctrl2(WHAT | reg.control[2]); mipsxx_cpu_start()
216 w_c0_perfctrl1(WHAT | reg.control[1]); mipsxx_cpu_start()
218 w_c0_perfctrl0(WHAT | reg.control[0]); mipsxx_cpu_start()
245 unsigned int control; mipsxx_perfcount_handler() local
255 control = r_c0_perfctrl ## n(); \ mipsxx_perfcount_handler()
257 if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \ mipsxx_perfcount_handler()
/linux-4.1.27/sound/soc/
H A Dsoc-ops.c37 * @kcontrol: mixer control
38 * @uinfo: control element information
41 * mixer control.
57 * @kcontrol: mixer control
58 * @ucontrol: control element information
91 * @kcontrol: mixer control
92 * @ucontrol: control element information
178 * @kcontrol: mixer control
179 * @uinfo: control element information
181 * Callback to provide information about a single mixer control, or a double
182 * mixer control that spans 2 registers.
211 * @kcontrol: mixer control
212 * @uinfo: control element information
214 * Callback to provide information about a single mixer control, or a double
215 * mixer control that spans 2 registers of the SX TLV type. SX TLV controls
228 /* Max represents the number of levels in an SX control not the snd_soc_info_volsw_sx()
239 * @kcontrol: mixer control
240 * @ucontrol: control element information
242 * Callback to get the value of a single mixer control, or a double mixer
243 * control that spans 2 registers.
299 * @kcontrol: mixer control
300 * @ucontrol: control element information
302 * Callback to set the value of a single mixer control, or a double mixer
303 * control that spans 2 registers.
361 * @kcontrol: mixer control
362 * @ucontrol: control element information
364 * Callback to get the value of a single mixer control, or a double mixer
365 * control that spans 2 registers.
406 * @kcontrol: mixer control
407 * @uinfo: control element information
409 * Callback to set the value of a double mixer control that spans 2 registers.
452 * @kcontrol: mixer control
453 * @uinfo: control element information
456 * mixer control.
483 * @kcontrol: mixer control
484 * @ucontrol: control element information
486 * Callback to set the value, within a range, for a single mixer control.
535 * @kcontrol: mixer control
536 * @ucontrol: control element information
538 * Callback to get the value, within a range, of a single mixer control.
589 * snd_soc_limit_volume - Set new limit to an existing volume control.
591 * @codec: where to look for the control
592 * @name: Name of the control
795 * @kcontrol: mreg control
796 * @uinfo: control element information
798 * Callback to provide information of a control that can
820 * @kcontrol: mreg control
821 * @ucontrol: control element information
823 * Callback to get the value of a control that can span
825 * signed value in a MSB/LSB manner. The control supports
869 * @kcontrol: mreg control
870 * @ucontrol: control element information
872 * Callback to set the value of a control that can span
874 * signed value in a MSB/LSB manner. The control supports
915 * @kcontrol: mixer control
916 * @ucontrol: control element information
918 * Callback get the value of a strobe mixer control.
951 * @kcontrol: mixer control
952 * @ucontrol: control element information
955 * in one pass of a single mixer enum control.
/linux-4.1.27/drivers/usb/serial/
H A Doti6858.c36 * - test/implement flow control
77 /* format of the control packet */
97 u8 control; /* settings of flow control lines */ member in struct:oti6858_control_pkt
118 && ((a)->control == (priv)->pending_setup.control) \
183 u8 control; member in struct:oti6858_private::__anon10444
229 new_setup->control = priv->pending_setup.control; setup_line()
408 u8 frame_fmt, control; oti6858_set_termios() local
417 control = priv->pending_setup.control; oti6858_set_termios()
472 control &= ~CONTROL_MASK; oti6858_set_termios()
474 control |= (CONTROL_DTR_HIGH | CONTROL_RTS_HIGH); oti6858_set_termios()
476 /* change control lines if we are switching to or from B0 */ oti6858_set_termios()
479 control = priv->line_control; oti6858_set_termios()
484 if (control != priv->line_control) { oti6858_set_termios()
485 control = priv->line_control; oti6858_set_termios()
487 set_control_lines(serial->dev, control); oti6858_set_termios()
495 || control != priv->pending_setup.control oti6858_set_termios()
498 priv->pending_setup.control = control; oti6858_set_termios()
530 buf->control = 0x4c; /* DTR, RTS */ oti6858_open()
540 priv->pending_setup.control = buf->control; oti6858_open()
589 u8 control; oti6858_tiocmset() local
596 control = priv->pending_setup.control; oti6858_tiocmset()
598 control |= CONTROL_RTS_HIGH; oti6858_tiocmset()
600 control |= CONTROL_DTR_HIGH; oti6858_tiocmset()
602 control &= ~CONTROL_RTS_HIGH; oti6858_tiocmset()
604 control &= ~CONTROL_DTR_HIGH; oti6858_tiocmset()
606 if (control != priv->pending_setup.control) oti6858_tiocmset()
607 priv->pending_setup.control = control; oti6858_tiocmset()
/linux-4.1.27/drivers/pcmcia/
H A Di82365.h38 #define I365_POWER 0x02 /* Power and RESETDRV control */
39 #define I365_INTCTL 0x03 /* Interrupt and general control */
41 #define I365_CSCINT 0x05 /* Card status change interrupt control */
43 #define I365_IOCTL 0x07 /* I/O control */
44 #define I365_GENCTL 0x16 /* Card detect and general control */
45 #define I365_GBLCTL 0x1E /* Global control register */
72 step has independent Vpp1/Vpp2 control, and the DF step has only
73 Vpp1 control, plus 3V control */
/linux-4.1.27/arch/mips/include/asm/mach-pmcs-msp71xx/
H A Dmsp_usb.h56 u32 timer0_ctrl; /* 0x84: General-purpose timer 0 control */
58 u32 timer1_ctrl; /* 0x8c: General-purpose timer 1 control */
74 u32 hcsparams; /* 0x4: Host control structural parameters */
75 u32 hccparams; /* 0x8: Host control capability parameters */
78 u32 dccparams; /* 0x24: Device control capability parameters */
97 u32 port_sc1; /* 0x84: Port status & control 1 */
99 u32 otgsc; /* 0xa4: OTG status & control */
110 u32 port_sc1; /* 0x84: Port status & control 1 */
112 u32 otgsc; /* 0xa4: OTG status & control */
/linux-4.1.27/include/net/irda/
H A Dirlap_frame.h85 __u8 control; member in struct:disc_frame
90 __u8 control; member in struct:xid_frame
101 __u8 control; member in struct:test_frame
108 __u8 control; member in struct:ua_frame
115 __u8 control; member in struct:dm_frame
120 __u8 control; member in struct:rd_frame
125 __u8 control; member in struct:rr_frame
130 __u8 control; member in struct:i_frame
135 __u8 control; member in struct:snrm_frame
/linux-4.1.27/drivers/ata/
H A Dpata_oldpiix.c69 int control = 0; oldpiix_set_piomode() local
85 control |= 1; /* TIME */ oldpiix_set_piomode()
87 control |= 2; /* IE */ oldpiix_set_piomode()
91 control |= 4; /* PPE */ oldpiix_set_piomode()
101 idetm_data |= control; oldpiix_set_piomode()
104 idetm_data |= (control << 4); oldpiix_set_piomode()
145 unsigned int control; oldpiix_set_dmamode() local
153 control = 3; /* IORDY|TIME0 */ oldpiix_set_dmamode()
156 control |= 4; /* PPE enable */ oldpiix_set_dmamode()
163 control |= 8; /* PIO cycles in PIO0 */ oldpiix_set_dmamode()
165 /* Mask out the relevant control and timing bits we will load. Also oldpiix_set_dmamode()
169 idetm_data |= control; oldpiix_set_dmamode()
172 idetm_data |= (control << 4); oldpiix_set_dmamode()
226 * and then hand over control to libata, for it to do the rest.
/linux-4.1.27/sound/synth/emux/
H A Demux_nrpn.c26 * conversion from NRPN/control parameters to Emu8000 raw parameters
31 int control; member in struct:nrpn_conv_table
48 * convert NRPN/control values
58 if (table[i].control == type) { send_converted_effect()
295 if (chan->control[MIDI_CTL_NONREG_PARM_NUM_MSB] == 127 && snd_emux_nrpn()
296 chan->control[MIDI_CTL_NONREG_PARM_NUM_LSB] <= 26) { snd_emux_nrpn()
300 val = (chan->control[MIDI_CTL_MSB_DATA_ENTRY] << 7) | snd_emux_nrpn()
301 chan->control[MIDI_CTL_LSB_DATA_ENTRY]; snd_emux_nrpn()
305 port, chan, chan->control[MIDI_CTL_NONREG_PARM_NUM_LSB], snd_emux_nrpn()
311 chan->control[MIDI_CTL_NONREG_PARM_NUM_MSB] == 1) { snd_emux_nrpn()
315 val = chan->control[MIDI_CTL_MSB_DATA_ENTRY]; snd_emux_nrpn()
318 port, chan, chan->control[MIDI_CTL_NONREG_PARM_NUM_LSB], snd_emux_nrpn()
326 * XG control effects; still experimental
367 chan->control[param], snd_emux_xg_control()
/linux-4.1.27/tools/virtio/
H A Dvirtio_test.c29 /* copy used for control */
36 int control; member in struct:vdev_info
72 r = ioctl(dev->control, VHOST_SET_FEATURES, &features); vhost_vq_setup()
75 r = ioctl(dev->control, VHOST_SET_VRING_NUM, &state); vhost_vq_setup()
78 r = ioctl(dev->control, VHOST_SET_VRING_BASE, &state); vhost_vq_setup()
80 r = ioctl(dev->control, VHOST_SET_VRING_ADDR, &addr); vhost_vq_setup()
83 r = ioctl(dev->control, VHOST_SET_VRING_KICK, &file); vhost_vq_setup()
86 r = ioctl(dev->control, VHOST_SET_VRING_CALL, &file); vhost_vq_setup()
121 dev->control = open("/dev/vhost-test", O_RDWR); vdev_info_init()
122 assert(dev->control >= 0); vdev_info_init()
123 r = ioctl(dev->control, VHOST_SET_OWNER, NULL); vdev_info_init()
134 r = ioctl(dev->control, VHOST_SET_MEM_TABLE, dev->mem); vdev_info_init()
162 r = ioctl(dev->control, VHOST_TEST_RUN, &test); run_test()
203 r = ioctl(dev->control, VHOST_TEST_RUN, &test); run_test()
/linux-4.1.27/net/bluetooth/
H A Dl2cap_core.c63 static void l2cap_tx(struct l2cap_chan *chan, struct l2cap_ctrl *control,
904 static void __unpack_enhanced_control(u16 enh, struct l2cap_ctrl *control) __unpack_enhanced_control() argument
906 control->reqseq = (enh & L2CAP_CTRL_REQSEQ) >> L2CAP_CTRL_REQSEQ_SHIFT; __unpack_enhanced_control()
907 control->final = (enh & L2CAP_CTRL_FINAL) >> L2CAP_CTRL_FINAL_SHIFT; __unpack_enhanced_control()
911 control->sframe = 1; __unpack_enhanced_control()
912 control->poll = (enh & L2CAP_CTRL_POLL) >> L2CAP_CTRL_POLL_SHIFT; __unpack_enhanced_control()
913 control->super = (enh & L2CAP_CTRL_SUPERVISE) >> L2CAP_CTRL_SUPER_SHIFT; __unpack_enhanced_control()
915 control->sar = 0; __unpack_enhanced_control()
916 control->txseq = 0; __unpack_enhanced_control()
919 control->sframe = 0; __unpack_enhanced_control()
920 control->sar = (enh & L2CAP_CTRL_SAR) >> L2CAP_CTRL_SAR_SHIFT; __unpack_enhanced_control()
921 control->txseq = (enh & L2CAP_CTRL_TXSEQ) >> L2CAP_CTRL_TXSEQ_SHIFT; __unpack_enhanced_control()
923 control->poll = 0; __unpack_enhanced_control()
924 control->super = 0; __unpack_enhanced_control()
928 static void __unpack_extended_control(u32 ext, struct l2cap_ctrl *control) __unpack_extended_control() argument
930 control->reqseq = (ext & L2CAP_EXT_CTRL_REQSEQ) >> L2CAP_EXT_CTRL_REQSEQ_SHIFT; __unpack_extended_control()
931 control->final = (ext & L2CAP_EXT_CTRL_FINAL) >> L2CAP_EXT_CTRL_FINAL_SHIFT; __unpack_extended_control()
935 control->sframe = 1; __unpack_extended_control()
936 control->poll = (ext & L2CAP_EXT_CTRL_POLL) >> L2CAP_EXT_CTRL_POLL_SHIFT; __unpack_extended_control()
937 control->super = (ext & L2CAP_EXT_CTRL_SUPERVISE) >> L2CAP_EXT_CTRL_SUPER_SHIFT; __unpack_extended_control()
939 control->sar = 0; __unpack_extended_control()
940 control->txseq = 0; __unpack_extended_control()
943 control->sframe = 0; __unpack_extended_control()
944 control->sar = (ext & L2CAP_EXT_CTRL_SAR) >> L2CAP_EXT_CTRL_SAR_SHIFT; __unpack_extended_control()
945 control->txseq = (ext & L2CAP_EXT_CTRL_TXSEQ) >> L2CAP_EXT_CTRL_TXSEQ_SHIFT; __unpack_extended_control()
947 control->poll = 0; __unpack_extended_control()
948 control->super = 0; __unpack_extended_control()
966 static u32 __pack_extended_control(struct l2cap_ctrl *control) __pack_extended_control() argument
970 packed = control->reqseq << L2CAP_EXT_CTRL_REQSEQ_SHIFT; __pack_extended_control()
971 packed |= control->final << L2CAP_EXT_CTRL_FINAL_SHIFT; __pack_extended_control()
973 if (control->sframe) { __pack_extended_control()
974 packed |= control->poll << L2CAP_EXT_CTRL_POLL_SHIFT; __pack_extended_control()
975 packed |= control->super << L2CAP_EXT_CTRL_SUPER_SHIFT; __pack_extended_control()
978 packed |= control->sar << L2CAP_EXT_CTRL_SAR_SHIFT; __pack_extended_control()
979 packed |= control->txseq << L2CAP_EXT_CTRL_TXSEQ_SHIFT; __pack_extended_control()
985 static u16 __pack_enhanced_control(struct l2cap_ctrl *control) __pack_enhanced_control() argument
989 packed = control->reqseq << L2CAP_CTRL_REQSEQ_SHIFT; __pack_enhanced_control()
990 packed |= control->final << L2CAP_CTRL_FINAL_SHIFT; __pack_enhanced_control()
992 if (control->sframe) { __pack_enhanced_control()
993 packed |= control->poll << L2CAP_CTRL_POLL_SHIFT; __pack_enhanced_control()
994 packed |= control->super << L2CAP_CTRL_SUPER_SHIFT; __pack_enhanced_control()
997 packed |= control->sar << L2CAP_CTRL_SAR_SHIFT; __pack_enhanced_control()
998 packed |= control->txseq << L2CAP_CTRL_TXSEQ_SHIFT; __pack_enhanced_control()
1005 struct l2cap_ctrl *control, __pack_control()
1009 put_unaligned_le32(__pack_extended_control(control), __pack_control()
1012 put_unaligned_le16(__pack_enhanced_control(control), __pack_control()
1026 u32 control) l2cap_create_sframe_pdu()
1045 put_unaligned_le32(control, skb_put(skb, L2CAP_EXT_CTRL_SIZE)); l2cap_create_sframe_pdu()
1047 put_unaligned_le16(control, skb_put(skb, L2CAP_ENH_CTRL_SIZE)); l2cap_create_sframe_pdu()
1059 struct l2cap_ctrl *control) l2cap_send_sframe()
1064 BT_DBG("chan %p, control %p", chan, control); l2cap_send_sframe()
1066 if (!control->sframe) l2cap_send_sframe()
1073 !control->poll) l2cap_send_sframe()
1074 control->final = 1; l2cap_send_sframe()
1076 if (control->super == L2CAP_SUPER_RR) l2cap_send_sframe()
1078 else if (control->super == L2CAP_SUPER_RNR) l2cap_send_sframe()
1081 if (control->super != L2CAP_SUPER_SREJ) { l2cap_send_sframe()
1082 chan->last_acked_seq = control->reqseq; l2cap_send_sframe()
1086 BT_DBG("reqseq %d, final %d, poll %d, super %d", control->reqseq, l2cap_send_sframe()
1087 control->final, control->poll, control->super); l2cap_send_sframe()
1090 control_field = __pack_extended_control(control); l2cap_send_sframe()
1092 control_field = __pack_enhanced_control(control); l2cap_send_sframe()
1101 struct l2cap_ctrl control; l2cap_send_rr_or_rnr() local
1105 memset(&control, 0, sizeof(control)); l2cap_send_rr_or_rnr()
1106 control.sframe = 1; l2cap_send_rr_or_rnr()
1107 control.poll = poll; l2cap_send_rr_or_rnr()
1110 control.super = L2CAP_SUPER_RNR; l2cap_send_rr_or_rnr()
1112 control.super = L2CAP_SUPER_RR; l2cap_send_rr_or_rnr()
1114 control.reqseq = chan->buffer_seq; l2cap_send_rr_or_rnr()
1115 l2cap_send_sframe(chan, &control); l2cap_send_rr_or_rnr()
1836 struct l2cap_ctrl *control; l2cap_streaming_send() local
1850 control = &bt_cb(skb)->l2cap; l2cap_streaming_send()
1852 control->reqseq = 0; l2cap_streaming_send()
1853 control->txseq = chan->next_tx_seq; l2cap_streaming_send()
1855 __pack_control(chan, control, skb); l2cap_streaming_send()
1864 BT_DBG("Sent txseq %u", control->txseq); l2cap_streaming_send()
1874 struct l2cap_ctrl *control; l2cap_ertm_send() local
1895 control = &bt_cb(skb)->l2cap; l2cap_ertm_send()
1898 control->final = 1; l2cap_ertm_send()
1900 control->reqseq = chan->buffer_seq; l2cap_ertm_send()
1902 control->txseq = chan->next_tx_seq; l2cap_ertm_send()
1904 __pack_control(chan, control, skb); l2cap_ertm_send()
1932 BT_DBG("Sent txseq %u", control->txseq); l2cap_ertm_send()
1943 struct l2cap_ctrl control; l2cap_ertm_resend() local
1967 control = bt_cb(skb)->l2cap; l2cap_ertm_resend()
1977 control.reqseq = chan->buffer_seq; l2cap_ertm_resend()
1979 control.final = 1; l2cap_ertm_resend()
1981 control.final = 0; l2cap_ertm_resend()
1999 put_unaligned_le32(__pack_extended_control(&control), l2cap_ertm_resend()
2002 put_unaligned_le16(__pack_enhanced_control(&control), l2cap_ertm_resend()
2016 BT_DBG("Resent txseq %d", control.txseq); l2cap_ertm_resend()
2023 struct l2cap_ctrl *control) l2cap_retransmit()
2025 BT_DBG("chan %p, control %p", chan, control); l2cap_retransmit()
2027 l2cap_seq_list_append(&chan->retrans_list, control->reqseq); l2cap_retransmit()
2032 struct l2cap_ctrl *control) l2cap_retransmit_all()
2036 BT_DBG("chan %p, control %p", chan, control); l2cap_retransmit_all()
2038 if (control->poll) l2cap_retransmit_all()
2048 if (bt_cb(skb)->l2cap.txseq == control->reqseq || l2cap_retransmit_all()
2067 struct l2cap_ctrl control; l2cap_send_ack() local
2075 memset(&control, 0, sizeof(control)); l2cap_send_ack()
2076 control.sframe = 1; l2cap_send_ack()
2081 control.super = L2CAP_SUPER_RNR; l2cap_send_ack()
2082 control.reqseq = chan->buffer_seq; l2cap_send_ack()
2083 l2cap_send_sframe(chan, &control); l2cap_send_ack()
2104 control.super = L2CAP_SUPER_RR; l2cap_send_ack()
2105 control.reqseq = chan->buffer_seq; l2cap_send_ack()
2106 l2cap_send_sframe(chan, &control); l2cap_send_ack()
2556 struct l2cap_ctrl control; l2cap_send_srej() local
2561 memset(&control, 0, sizeof(control)); l2cap_send_srej()
2562 control.sframe = 1; l2cap_send_srej()
2563 control.super = L2CAP_SUPER_SREJ; l2cap_send_srej()
2568 control.reqseq = seq; l2cap_send_srej()
2569 l2cap_send_sframe(chan, &control); l2cap_send_srej()
2579 struct l2cap_ctrl control; l2cap_send_srej_tail() local
2586 memset(&control, 0, sizeof(control)); l2cap_send_srej_tail()
2587 control.sframe = 1; l2cap_send_srej_tail()
2588 control.super = L2CAP_SUPER_SREJ; l2cap_send_srej_tail()
2589 control.reqseq = chan->srej_list.tail; l2cap_send_srej_tail()
2590 l2cap_send_sframe(chan, &control); l2cap_send_srej_tail()
2595 struct l2cap_ctrl control; l2cap_send_srej_list() local
2601 memset(&control, 0, sizeof(control)); l2cap_send_srej_list()
2602 control.sframe = 1; l2cap_send_srej_list()
2603 control.super = L2CAP_SUPER_SREJ; l2cap_send_srej_list()
2613 control.reqseq = seq; l2cap_send_srej_list()
2614 l2cap_send_sframe(chan, &control); l2cap_send_srej_list()
2662 struct l2cap_ctrl *control, l2cap_tx_state_xmit()
2665 BT_DBG("chan %p, control %p, skbs %p, event %d", chan, control, skbs, l2cap_tx_state_xmit()
2710 l2cap_process_reqseq(chan, control->reqseq); l2cap_tx_state_xmit()
2734 struct l2cap_ctrl *control, l2cap_tx_state_wait_f()
2737 BT_DBG("chan %p, control %p, skbs %p, event %d", chan, control, skbs, l2cap_tx_state_wait_f()
2780 l2cap_process_reqseq(chan, control->reqseq); l2cap_tx_state_wait_f()
2785 if (control && control->final) { l2cap_tx_state_wait_f()
2811 static void l2cap_tx(struct l2cap_chan *chan, struct l2cap_ctrl *control, l2cap_tx() argument
2814 BT_DBG("chan %p, control %p, skbs %p, event %d, state %d", l2cap_tx()
2815 chan, control, skbs, event, chan->tx_state); l2cap_tx()
2819 l2cap_tx_state_xmit(chan, control, skbs, event); l2cap_tx()
2822 l2cap_tx_state_wait_f(chan, control, skbs, event); l2cap_tx()
2831 struct l2cap_ctrl *control) l2cap_pass_to_tx()
2833 BT_DBG("chan %p, control %p", chan, control); l2cap_pass_to_tx()
2834 l2cap_tx(chan, control, NULL, L2CAP_EV_RECV_REQSEQ_AND_FBIT); l2cap_pass_to_tx()
2838 struct l2cap_ctrl *control) l2cap_pass_to_tx_fbit()
2840 BT_DBG("chan %p, control %p", chan, control); l2cap_pass_to_tx_fbit()
2841 l2cap_tx(chan, control, NULL, L2CAP_EV_RECV_FBIT); l2cap_pass_to_tx_fbit()
3166 /* use extended control field */ l2cap_txwin_setup()
5750 struct l2cap_ctrl control; l2cap_send_i_or_rr_or_rnr() local
5754 memset(&control, 0, sizeof(control)); l2cap_send_i_or_rr_or_rnr()
5755 control.sframe = 1; l2cap_send_i_or_rr_or_rnr()
5756 control.final = 1; l2cap_send_i_or_rr_or_rnr()
5757 control.reqseq = chan->buffer_seq; l2cap_send_i_or_rr_or_rnr()
5761 control.super = L2CAP_SUPER_RNR; l2cap_send_i_or_rr_or_rnr()
5762 l2cap_send_sframe(chan, &control); l2cap_send_i_or_rr_or_rnr()
5777 control.super = L2CAP_SUPER_RR; l2cap_send_i_or_rr_or_rnr()
5778 l2cap_send_sframe(chan, &control); l2cap_send_i_or_rr_or_rnr()
5802 struct l2cap_ctrl *control) l2cap_reassemble_sdu()
5806 switch (control->sar) { l2cap_reassemble_sdu()
5935 struct l2cap_ctrl *control) l2cap_handle_srej()
5939 BT_DBG("chan %p, control %p", chan, control); l2cap_handle_srej()
5941 if (control->reqseq == chan->next_tx_seq) { l2cap_handle_srej()
5942 BT_DBG("Invalid reqseq %d, disconnecting", control->reqseq); l2cap_handle_srej()
5947 skb = l2cap_ertm_seq_in_queue(&chan->tx_q, control->reqseq); l2cap_handle_srej()
5951 control->reqseq); l2cap_handle_srej()
5963 if (control->poll) { l2cap_handle_srej()
5964 l2cap_pass_to_tx(chan, control); l2cap_handle_srej()
5967 l2cap_retransmit(chan, control); l2cap_handle_srej()
5972 chan->srej_save_reqseq = control->reqseq; l2cap_handle_srej()
5975 l2cap_pass_to_tx_fbit(chan, control); l2cap_handle_srej()
5977 if (control->final) { l2cap_handle_srej()
5978 if (chan->srej_save_reqseq != control->reqseq || l2cap_handle_srej()
5981 l2cap_retransmit(chan, control); l2cap_handle_srej()
5983 l2cap_retransmit(chan, control); l2cap_handle_srej()
5986 chan->srej_save_reqseq = control->reqseq; l2cap_handle_srej()
5993 struct l2cap_ctrl *control) l2cap_handle_rej()
5997 BT_DBG("chan %p, control %p", chan, control); l2cap_handle_rej()
5999 if (control->reqseq == chan->next_tx_seq) { l2cap_handle_rej()
6000 BT_DBG("Invalid reqseq %d, disconnecting", control->reqseq); l2cap_handle_rej()
6005 skb = l2cap_ertm_seq_in_queue(&chan->tx_q, control->reqseq); l2cap_handle_rej()
6016 l2cap_pass_to_tx(chan, control); l2cap_handle_rej()
6018 if (control->final) { l2cap_handle_rej()
6020 l2cap_retransmit_all(chan, control); l2cap_handle_rej()
6022 l2cap_retransmit_all(chan, control); l2cap_handle_rej()
6116 struct l2cap_ctrl *control, l2cap_rx_state_recv()
6122 BT_DBG("chan %p, control %p, skb %p, event %d", chan, control, skb, l2cap_rx_state_recv()
6127 switch (l2cap_classify_txseq(chan, control->txseq)) { l2cap_rx_state_recv()
6129 l2cap_pass_to_tx(chan, control); l2cap_rx_state_recv()
6133 control->txseq); l2cap_rx_state_recv()
6138 control->txseq); l2cap_rx_state_recv()
6143 err = l2cap_reassemble_sdu(chan, skb, control); l2cap_rx_state_recv()
6147 if (control->final) { l2cap_rx_state_recv()
6150 control->final = 0; l2cap_rx_state_recv()
6151 l2cap_retransmit_all(chan, control); l2cap_rx_state_recv()
6160 l2cap_pass_to_tx(chan, control); l2cap_rx_state_recv()
6168 control->txseq); l2cap_rx_state_recv()
6183 l2cap_send_srej(chan, control->txseq); l2cap_rx_state_recv()
6188 l2cap_pass_to_tx(chan, control); l2cap_rx_state_recv()
6199 l2cap_pass_to_tx(chan, control); l2cap_rx_state_recv()
6200 if (control->final) { l2cap_rx_state_recv()
6205 control->final = 0; l2cap_rx_state_recv()
6206 l2cap_retransmit_all(chan, control); l2cap_rx_state_recv()
6210 } else if (control->poll) { l2cap_rx_state_recv()
6223 l2cap_pass_to_tx(chan, control); l2cap_rx_state_recv()
6224 if (control && control->poll) { l2cap_rx_state_recv()
6232 l2cap_handle_rej(chan, control); l2cap_rx_state_recv()
6235 l2cap_handle_srej(chan, control); l2cap_rx_state_recv()
6250 struct l2cap_ctrl *control, l2cap_rx_state_srej_sent()
6254 u16 txseq = control->txseq; l2cap_rx_state_srej_sent()
6257 BT_DBG("chan %p, control %p, skb %p, event %d", chan, control, skb, l2cap_rx_state_srej_sent()
6265 l2cap_pass_to_tx(chan, control); l2cap_rx_state_srej_sent()
6276 l2cap_pass_to_tx(chan, control); l2cap_rx_state_srej_sent()
6297 l2cap_pass_to_tx(chan, control); l2cap_rx_state_srej_sent()
6298 l2cap_send_srej(chan, control->txseq); l2cap_rx_state_srej_sent()
6311 l2cap_pass_to_tx(chan, control); l2cap_rx_state_srej_sent()
6312 l2cap_send_srej_list(chan, control->txseq); l2cap_rx_state_srej_sent()
6316 l2cap_pass_to_tx(chan, control); l2cap_rx_state_srej_sent()
6332 l2cap_pass_to_tx(chan, control); l2cap_rx_state_srej_sent()
6333 if (control->final) { l2cap_rx_state_srej_sent()
6338 control->final = 0; l2cap_rx_state_srej_sent()
6339 l2cap_retransmit_all(chan, control); l2cap_rx_state_srej_sent()
6343 } else if (control->poll) { l2cap_rx_state_srej_sent()
6363 l2cap_pass_to_tx(chan, control); l2cap_rx_state_srej_sent()
6364 if (control->poll) { l2cap_rx_state_srej_sent()
6377 l2cap_handle_rej(chan, control); l2cap_rx_state_srej_sent()
6380 l2cap_handle_srej(chan, control); l2cap_rx_state_srej_sent()
6407 struct l2cap_ctrl *control, l2cap_rx_state_wait_p()
6412 BT_DBG("chan %p, control %p, skb %p, event %d", chan, control, skb, l2cap_rx_state_wait_p()
6415 if (!control->poll) l2cap_rx_state_wait_p()
6418 l2cap_process_reqseq(chan, control->reqseq); l2cap_rx_state_wait_p()
6428 chan->next_tx_seq = control->reqseq; l2cap_rx_state_wait_p()
6441 return l2cap_rx_state_recv(chan, control, NULL, event); l2cap_rx_state_wait_p()
6445 struct l2cap_ctrl *control, l2cap_rx_state_wait_f()
6450 if (!control->final) l2cap_rx_state_wait_f()
6456 l2cap_process_reqseq(chan, control->reqseq); l2cap_rx_state_wait_f()
6466 chan->next_tx_seq = control->reqseq; l2cap_rx_state_wait_f()
6477 err = l2cap_rx_state_recv(chan, control, skb, event); l2cap_rx_state_wait_f()
6491 static int l2cap_rx(struct l2cap_chan *chan, struct l2cap_ctrl *control, l2cap_rx() argument
6496 BT_DBG("chan %p, control %p, skb %p, event %d, state %d", chan, l2cap_rx()
6497 control, skb, event, chan->rx_state); l2cap_rx()
6499 if (__valid_reqseq(chan, control->reqseq)) { l2cap_rx()
6502 err = l2cap_rx_state_recv(chan, control, skb, event); l2cap_rx()
6505 err = l2cap_rx_state_srej_sent(chan, control, skb, l2cap_rx()
6509 err = l2cap_rx_state_wait_p(chan, control, skb, event); l2cap_rx()
6512 err = l2cap_rx_state_wait_f(chan, control, skb, event); l2cap_rx()
6520 control->reqseq, chan->next_tx_seq, l2cap_rx()
6528 static int l2cap_stream_rx(struct l2cap_chan *chan, struct l2cap_ctrl *control, l2cap_stream_rx() argument
6533 BT_DBG("chan %p, control %p, skb %p, state %d", chan, control, skb, l2cap_stream_rx()
6536 if (l2cap_classify_txseq(chan, control->txseq) == l2cap_stream_rx()
6538 l2cap_pass_to_tx(chan, control); l2cap_stream_rx()
6545 l2cap_reassemble_sdu(chan, skb, control); l2cap_stream_rx()
6560 chan->last_acked_seq = control->txseq; l2cap_stream_rx()
6561 chan->expected_tx_seq = __next_seq(chan, control->txseq); l2cap_stream_rx()
6568 struct l2cap_ctrl *control = &bt_cb(skb)->l2cap; l2cap_data_rcv() local
6584 if (!control->sframe && control->sar == L2CAP_SAR_START) l2cap_data_rcv()
6595 if (!control->sframe) { l2cap_data_rcv()
6599 control->sar, control->reqseq, control->final, l2cap_data_rcv()
6600 control->txseq); l2cap_data_rcv()
6605 if (control->final && chan->tx_state != L2CAP_TX_STATE_WAIT_F) l2cap_data_rcv()
6610 err = l2cap_rx(chan, control, skb, event); l2cap_data_rcv()
6612 err = l2cap_stream_rx(chan, control, skb); l2cap_data_rcv()
6628 control->reqseq, control->final, control->poll, l2cap_data_rcv()
6629 control->super); l2cap_data_rcv()
6638 if (control->final && (control->poll || l2cap_data_rcv()
6642 event = rx_func_to_event[control->super]; l2cap_data_rcv()
6643 if (l2cap_rx(chan, control, skb, event)) l2cap_data_rcv()
6816 * provide flow control mechanism. */ l2cap_data_channel()
1004 __pack_control(struct l2cap_chan *chan, struct l2cap_ctrl *control, struct sk_buff *skb) __pack_control() argument
1025 l2cap_create_sframe_pdu(struct l2cap_chan *chan, u32 control) l2cap_create_sframe_pdu() argument
1058 l2cap_send_sframe(struct l2cap_chan *chan, struct l2cap_ctrl *control) l2cap_send_sframe() argument
2022 l2cap_retransmit(struct l2cap_chan *chan, struct l2cap_ctrl *control) l2cap_retransmit() argument
2031 l2cap_retransmit_all(struct l2cap_chan *chan, struct l2cap_ctrl *control) l2cap_retransmit_all() argument
2661 l2cap_tx_state_xmit(struct l2cap_chan *chan, struct l2cap_ctrl *control, struct sk_buff_head *skbs, u8 event) l2cap_tx_state_xmit() argument
2733 l2cap_tx_state_wait_f(struct l2cap_chan *chan, struct l2cap_ctrl *control, struct sk_buff_head *skbs, u8 event) l2cap_tx_state_wait_f() argument
2830 l2cap_pass_to_tx(struct l2cap_chan *chan, struct l2cap_ctrl *control) l2cap_pass_to_tx() argument
2837 l2cap_pass_to_tx_fbit(struct l2cap_chan *chan, struct l2cap_ctrl *control) l2cap_pass_to_tx_fbit() argument
5801 l2cap_reassemble_sdu(struct l2cap_chan *chan, struct sk_buff *skb, struct l2cap_ctrl *control) l2cap_reassemble_sdu() argument
5934 l2cap_handle_srej(struct l2cap_chan *chan, struct l2cap_ctrl *control) l2cap_handle_srej() argument
5992 l2cap_handle_rej(struct l2cap_chan *chan, struct l2cap_ctrl *control) l2cap_handle_rej() argument
6115 l2cap_rx_state_recv(struct l2cap_chan *chan, struct l2cap_ctrl *control, struct sk_buff *skb, u8 event) l2cap_rx_state_recv() argument
6249 l2cap_rx_state_srej_sent(struct l2cap_chan *chan, struct l2cap_ctrl *control, struct sk_buff *skb, u8 event) l2cap_rx_state_srej_sent() argument
6406 l2cap_rx_state_wait_p(struct l2cap_chan *chan, struct l2cap_ctrl *control, struct sk_buff *skb, u8 event) l2cap_rx_state_wait_p() argument
6444 l2cap_rx_state_wait_f(struct l2cap_chan *chan, struct l2cap_ctrl *control, struct sk_buff *skb, u8 event) l2cap_rx_state_wait_f() argument
/linux-4.1.27/drivers/net/wireless/ath/ath5k/
H A Ddesc.h24 * struct ath5k_hw_rx_ctl - Common hardware RX control descriptor
25 * @rx_control_0: RX control word 0
26 * @rx_control_1: RX control word 1
33 /* RX control word 1 fields/flags */
151 * struct ath5k_hw_2w_tx_ctl - 5210/5211 hardware 2-word TX control descriptor
152 * @tx_control_0: TX control word 0
153 * @tx_control_1: TX control word 1
160 /* TX control word 0 fields/flags */
182 /* TX control word 1 fields/flags */
207 * struct ath5k_hw_4w_tx_ctl - 5212 hardware 4-word TX control descriptor
208 * @tx_control_0: TX control word 0
209 * @tx_control_1: TX control word 1
210 * @tx_control_2: TX control word 2
211 * @tx_control_3: TX control word 3
220 /* TX control word 0 fields/flags */
233 /* TX control word 1 fields/flags */
248 /* TX control word 2 fields/flags */
260 /* TX control word 3 fields/flags */
/linux-4.1.27/drivers/dma/
H A Dep93xx_dma.c149 * @runtime_ctrl: M2M runtime values for the control register.
307 static void m2p_set_control(struct ep93xx_dma_chan *edmac, u32 control) m2p_set_control() argument
309 writel(control, edmac->regs + M2P_CONTROL); m2p_set_control()
312 * write to the control register. m2p_set_control()
320 u32 control; m2p_hw_setup() local
324 control = M2P_CONTROL_CH_ERROR_INT | M2P_CONTROL_ICE m2p_hw_setup()
326 m2p_set_control(edmac, control); m2p_hw_setup()
338 u32 control; m2p_hw_shutdown() local
340 control = readl(edmac->regs + M2P_CONTROL); m2p_hw_shutdown()
341 control &= ~(M2P_CONTROL_STALLINT | M2P_CONTROL_NFBINT); m2p_hw_shutdown()
342 m2p_set_control(edmac, control); m2p_hw_shutdown()
382 u32 control = readl(edmac->regs + M2P_CONTROL); m2p_hw_submit() local
385 control |= M2P_CONTROL_STALLINT; m2p_hw_submit()
389 control |= M2P_CONTROL_NFBINT; m2p_hw_submit()
392 m2p_set_control(edmac, control); m2p_hw_submit()
398 u32 control; m2p_hw_interrupt() local
427 control = readl(edmac->regs + M2P_CONTROL); m2p_hw_interrupt()
428 control &= ~(M2P_CONTROL_STALLINT | M2P_CONTROL_NFBINT); m2p_hw_interrupt()
429 m2p_set_control(edmac, control); m2p_hw_interrupt()
450 u32 control = 0; m2m_hw_setup() local
454 writel(control, edmac->regs + M2M_CONTROL); m2m_hw_setup()
465 control = (5 << M2M_CONTROL_PWSC_SHIFT); m2m_hw_setup()
466 control |= M2M_CONTROL_NO_HDSK; m2m_hw_setup()
469 control |= M2M_CONTROL_DAH; m2m_hw_setup()
470 control |= M2M_CONTROL_TM_TX; m2m_hw_setup()
471 control |= M2M_CONTROL_RSS_SSPTX; m2m_hw_setup()
473 control |= M2M_CONTROL_SAH; m2m_hw_setup()
474 control |= M2M_CONTROL_TM_RX; m2m_hw_setup()
475 control |= M2M_CONTROL_RSS_SSPRX; m2m_hw_setup()
486 control = (3 << M2M_CONTROL_PWSC_SHIFT); m2m_hw_setup()
487 control |= M2M_CONTROL_DAH; m2m_hw_setup()
488 control |= M2M_CONTROL_TM_TX; m2m_hw_setup()
490 control = (2 << M2M_CONTROL_PWSC_SHIFT); m2m_hw_setup()
491 control |= M2M_CONTROL_SAH; m2m_hw_setup()
492 control |= M2M_CONTROL_TM_RX; m2m_hw_setup()
495 control |= M2M_CONTROL_NO_HDSK; m2m_hw_setup()
496 control |= M2M_CONTROL_RSS_IDE; m2m_hw_setup()
497 control |= M2M_CONTROL_PW_16; m2m_hw_setup()
504 writel(control, edmac->regs + M2M_CONTROL); m2m_hw_setup()
540 u32 control = readl(edmac->regs + M2M_CONTROL); m2m_hw_submit() local
547 control &= ~M2M_CONTROL_PW_MASK; m2m_hw_submit()
548 control |= edmac->runtime_ctrl; m2m_hw_submit()
551 control |= M2M_CONTROL_DONEINT; m2m_hw_submit()
555 control |= M2M_CONTROL_NFBINT; m2m_hw_submit()
562 control |= M2M_CONTROL_ENABLE; m2m_hw_submit()
563 writel(control, edmac->regs + M2M_CONTROL); m2m_hw_submit()
570 control |= M2M_CONTROL_START; m2m_hw_submit()
571 writel(control, edmac->regs + M2M_CONTROL); m2m_hw_submit()
592 u32 control; m2m_hw_interrupt() local
629 control = readl(edmac->regs + M2M_CONTROL); m2m_hw_interrupt()
630 control |= M2M_CONTROL_START; m2m_hw_interrupt()
631 writel(control, edmac->regs + M2M_CONTROL); m2m_hw_interrupt()
647 control = readl(edmac->regs + M2M_CONTROL); m2m_hw_interrupt()
648 control &= ~(M2M_CONTROL_DONEINT | M2M_CONTROL_NFBINT m2m_hw_interrupt()
650 writel(control, edmac->regs + M2M_CONTROL); m2m_hw_interrupt()
/linux-4.1.27/drivers/parport/
H A Dparport_atari.c8 * with 8 output data lines (D0 - D7), 1 output control line (STROBE)
51 unsigned char control = 0; parport_atari_read_control() local
56 control = PARPORT_CONTROL_STROBE; parport_atari_read_control()
58 return control; parport_atari_read_control()
62 parport_atari_write_control(struct parport *p, unsigned char control) parport_atari_write_control() argument
68 if (control & PARPORT_CONTROL_STROBE) parport_atari_write_control()
H A Dparport_mfc3.c52 * control register.
99 static unsigned char control_pc_to_mfc3(unsigned char control) control_pc_to_mfc3() argument
103 if (control & PARPORT_CONTROL_SELECT) /* XXX: What is SELECP? */ control_pc_to_mfc3()
105 if (control & PARPORT_CONTROL_INIT) /* INITP */ control_pc_to_mfc3()
107 if (control & PARPORT_CONTROL_AUTOFD) /* AUTOLF */ control_pc_to_mfc3()
109 if (control & PARPORT_CONTROL_STROBE) /* Strobe */ control_pc_to_mfc3()
114 static unsigned char control_mfc3_to_pc(unsigned char control) control_mfc3_to_pc() argument
119 if (control & 128) /* /INITP */ control_mfc3_to_pc()
121 if (control & 64) /* /AUTOLF */ control_mfc3_to_pc()
123 if (control & 32) /* /SELECT_IN */ control_mfc3_to_pc()
128 static void mfc3_write_control(struct parport *p, unsigned char control) mfc3_write_control() argument
130 DPRINTK(KERN_DEBUG "write_control %02x\n",control); mfc3_write_control()
131 pia(p)->ppra = (pia(p)->ppra & 0x1f) | control_pc_to_mfc3(control); mfc3_write_control()
/linux-4.1.27/drivers/hwmon/
H A Dpcf8591.c43 * The PCF8591 control byte
83 u8 control; member in struct:pcf8591_data
131 i2c_smbus_write_byte_data(client, data->control, data->aout); set_out0_output()
142 return sprintf(buf, "%u\n", !(!(data->control & PCF8591_CONTROL_AOEF))); show_out0_enable()
160 data->control |= PCF8591_CONTROL_AOEF; set_out0_enable()
162 data->control &= ~PCF8591_CONTROL_AOEF; set_out0_enable()
163 i2c_smbus_write_byte(client, data->control); set_out0_enable()
261 data->control = PCF8591_INIT_CONTROL; pcf8591_init_client()
264 i2c_smbus_write_byte_data(client, data->control, data->aout); pcf8591_init_client()
281 if ((data->control & PCF8591_CONTROL_AICH_MASK) != channel) { pcf8591_read_channel()
282 data->control = (data->control & ~PCF8591_CONTROL_AICH_MASK) pcf8591_read_channel()
284 i2c_smbus_write_byte(client, data->control); pcf8591_read_channel()
/linux-4.1.27/drivers/net/wireless/ti/wl1251/
H A Dtx.c84 struct ieee80211_tx_info *control, u16 fc) wl1251_tx_control()
86 *(u16 *)&tx_hdr->control = 0; wl1251_tx_control()
88 tx_hdr->control.rate_policy = 0; wl1251_tx_control()
91 tx_hdr->control.packet_type = 0; wl1251_tx_control()
94 if ((control->flags & IEEE80211_TX_CTL_NO_ACK) || wl1251_tx_control()
95 (control->flags & IEEE80211_TX_CTL_INJECTED)) { wl1251_tx_control()
96 tx_hdr->control.rate_policy = 1; wl1251_tx_control()
97 tx_hdr->control.ack_policy = 1; wl1251_tx_control()
100 tx_hdr->control.tx_complete = 1; wl1251_tx_control()
105 tx_hdr->control.qos = 1; wl1251_tx_control()
149 struct ieee80211_tx_info *control) wl1251_tx_fill_hdr()
168 rate = ieee80211_get_tx_rate(wl->hw, control); wl1251_tx_fill_hdr()
175 wl1251_tx_control(tx_hdr, control, fc); wl1251_tx_fill_hdr()
183 struct ieee80211_tx_info *control) wl1251_tx_send_packet()
194 if (control->control.hw_key && wl1251_tx_send_packet()
195 control->control.hw_key->cipher == WLAN_CIPHER_SUITE_TKIP) { wl1251_tx_send_packet()
314 if (info->control.hw_key) { wl1251_tx_frame()
318 idx = info->control.hw_key->hw_key_idx; wl1251_tx_frame()
441 if (info->control.hw_key && wl1251_tx_packet_cb()
442 info->control.hw_key->cipher == WLAN_CIPHER_SUITE_TKIP) { wl1251_tx_packet_cb()
569 /* control->flags = 0; FIXME */ wl1251_tx_flush()
83 wl1251_tx_control(struct tx_double_buffer_desc *tx_hdr, struct ieee80211_tx_info *control, u16 fc) wl1251_tx_control() argument
148 wl1251_tx_fill_hdr(struct wl1251 *wl, struct sk_buff *skb, struct ieee80211_tx_info *control) wl1251_tx_fill_hdr() argument
182 wl1251_tx_send_packet(struct wl1251 *wl, struct sk_buff *skb, struct ieee80211_tx_info *control) wl1251_tx_send_packet() argument
/linux-4.1.27/drivers/macintosh/ams/
H A Dams-i2c.c28 #define AMS_CTRL1 0x02 /* read control 1 (number of values) */
29 #define AMS_CTRL2 0x03 /* read control 2 (offset?) */
30 #define AMS_CTRL3 0x04 /* read control 3 (size of each value?) */
38 #define AMS_FREEFALL 0x24 /* freefall int control */
39 #define AMS_SHOCK 0x25 /* shock int control */
42 #define AMS_CTRLX 0x28 /* control X */
43 #define AMS_CTRLY 0x29 /* control Y */
44 #define AMS_CTRLZ 0x2A /* control Z */
/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/reset-controller/
H A Dstih407-resets.h9 /* Powerdown requests control 0 */
16 /* Powerdown requests control 1 */
/linux-4.1.27/include/video/
H A Dsh_mobile_hdmi.h36 #define HDMI_OUTPUT_PUSH_PULL (1 << 4) /* System control : output mode */
37 #define HDMI_OUTPUT_POLARITY_HI (1 << 5) /* System control : output polarity */
H A Dplatform_lcd.h6 * Generic platform-device LCD power control interface.
/linux-4.1.27/arch/powerpc/platforms/powernv/
H A Dopal-power.c2 * PowerNV OPAL power control for graceful shutdown handling
40 pr_err("OPAL: power control type unexpected %016llx\n", type); opal_power_control_event()
/linux-4.1.27/arch/s390/include/uapi/asm/
H A Dtermios.h24 unsigned short c_cflag; /* control mode flags */
27 unsigned char c_cc[NCC]; /* control characters */
H A Dtape390.h3 * enables user programs to display messages and control encryption
19 * - 1 format control byte, and
22 * Format control byte:
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/reset-controller/
H A Dstih407-resets.h9 /* Powerdown requests control 0 */
16 /* Powerdown requests control 1 */
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/reset-controller/
H A Dstih407-resets.h9 /* Powerdown requests control 0 */
16 /* Powerdown requests control 1 */
/linux-4.1.27/arch/m32r/include/asm/m32104ut/
H A Dm32104ut_pld.h63 * ICUCR3: control register for CFIREQ# interrupt
64 * ICUCR4: control register for CFC Card insert interrupt
65 * ICUCR5: control register for CFC Card eject interrupt
66 * ICUCR6: control register for external interrupt
67 * ICUCR11: control register for MMC Card insert/eject interrupt
68 * ICUCR13: control register for SC error interrupt
69 * ICUCR14: control register for SC receive interrupt
70 * ICUCR15: control register for SC send interrupt
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/reset-controller/
H A Dstih407-resets.h9 /* Powerdown requests control 0 */
16 /* Powerdown requests control 1 */
/linux-4.1.27/arch/arm/mach-s3c24xx/
H A Danubis.h6 * ANUBIS - CPLD control constants
18 /* CTRL2 - NAND WP control, IDE Reset assert/check */
H A Dosiris.h6 * OSIRIS - CPLD control constants
17 /* CTRL0 - NAND WP control */
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/reset-controller/
H A Dstih407-resets.h9 /* Powerdown requests control 0 */
16 /* Powerdown requests control 1 */
/linux-4.1.27/include/dt-bindings/reset-controller/
H A Dstih407-resets.h9 /* Powerdown requests control 0 */
16 /* Powerdown requests control 1 */
/linux-4.1.27/drivers/media/i2c/m5mols/
H A Dm5mols.h170 * @handle: control handler
171 * @auto_exposure: auto/manual exposure control
172 * @exposure_bias: exposure compensation control
173 * @exposure: manual exposure control
174 * @metering: exposure metering control
175 * @auto_iso: auto/manual ISO sensitivity control
176 * @iso: manual ISO sensitivity control
177 * @auto_wb: auto white balance control
178 * @lock_3a: 3A lock control
179 * @colorfx: color effect control
180 * @saturation: saturation control
181 * @zoom: zoom control
182 * @wdr: wide dynamic range control
183 * @stabilization: image stabilization control
184 * @jpeg_quality: JPEG compression quality control
193 * @ctrl_sync: 1 when the control handler state is restored in H/W
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88e1xxx.h17 #define MII_GBCR 9 /* 1000Base-T control register */
20 /* 1000Base-T control register fields */
68 /* PHY specific control register fields */
74 /* Extended PHY specific control register fields */
/linux-4.1.27/arch/unicore32/include/mach/
H A Dregs-rtc.h2 * PKUnity Real-Time Clock (RTC) control registers
/linux-4.1.27/drivers/atm/
H A Dtonga.h9 #define PCI_TONGA_CTRL 0x60 /* control register */
/linux-4.1.27/include/net/
H A Dgue.h24 * For a control message, proto/ctype is interpreted as a type of
25 * control message. For data messages, proto/ctype is the IP protocol
37 control:1, member in struct:guehdr::__anon12653::__anon12654
41 control:1,
/linux-4.1.27/arch/powerpc/include/uapi/asm/
H A Dsockios.h11 /* Socket-level I/O control calls. */
/linux-4.1.27/arch/m32r/include/asm/
H A Dcachectl.h2 * cachectl.h -- defines for M32R cache control system calls
/linux-4.1.27/arch/arm/mm/
H A Dproc-v6.S147 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
148 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
149 mrc p15, 0, r9, c1, c0, 0 @ control register
169 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
171 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
172 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
174 mov r0, r9 @ control register
187 * on. Return in r0 the new CP15 C1 control register setting.
190 * Harvard cache control instructions insead of the unified cache
191 * control instructions.
213 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
225 mrc p15, 0, r0, c1, c0, 0 @ read control register
232 * (setting the undocumented bit 31 in the auxiliary control register
233 * and the FI bit in the control register) disables hit-under-miss
239 mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
241 mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
/linux-4.1.27/arch/arm/mach-davinci/include/mach/
H A Dclock.h4 * Clock control driver for DaVinci - header file
/linux-4.1.27/arch/arm/mach-integrator/
H A Dcm.h2 * access the core module control register.
/linux-4.1.27/include/linux/mfd/
H A Dretu.h19 #define RETU_REG_CC1 0x0d /* Common control register 1 */
/linux-4.1.27/arch/sh/include/asm/
H A Dbarrier.h13 * A brief note on ctrl_barrier(), the control register write barrier.
16 * modification of a control register in order for the changes to take
21 * write barrier, as it's not necessary for control registers.
/linux-4.1.27/arch/arm/mach-omap2/
H A Dclkt2xxx_dpll.c2 * OMAP2-specific DPLL control functions
27 * Enable DPLL automatic idle control. The DPLL will enter low-power
44 * Disable DPLL automatic idle control. No return value.
/linux-4.1.27/net/lapb/
H A Dlapb_subr.c108 * This routine is the centralised routine for parsing the control
165 frame->control[0] = skb->data[0]; lapb_decode()
166 frame->control[1] = skb->data[1]; lapb_decode()
177 frame->control[0] = skb->data[0]; lapb_decode()
178 frame->control[1] = skb->data[1]; lapb_decode()
186 frame->control[0] = skb->data[0]; lapb_decode()
187 frame->control[1] = 0x00; lapb_decode()
214 frame->control[0] = skb->data[0]; lapb_decode()
263 * the LAPB control block.
278 *dptr++ = lapb->frmr_data.control[0]; lapb_transmit_frmr()
279 *dptr++ = lapb->frmr_data.control[1]; lapb_transmit_frmr()
294 *dptr++ = lapb->frmr_data.control[0]; lapb_transmit_frmr()
/linux-4.1.27/net/atm/
H A Dmpc.h19 struct atm_vcc *mpoad_vcc; /* control channel to mpoad */
20 uint8_t mps_ctrl_addr[ATM_ESA_LEN]; /* MPS control ATM address */
21 uint8_t our_ctrl_addr[ATM_ESA_LEN]; /* MPC's control ATM address */
/linux-4.1.27/net/netfilter/
H A Dxt_cgroup.c2 * Xtables module to match the process control group.
5 * policies in contrast to global policies based on control groups.
23 MODULE_DESCRIPTION("Xtables: process control group matching");
/linux-4.1.27/include/linux/amba/
H A Dserial.h36 #define UART010_LCRH 0x08 /* Line control register, high byte. */
38 #define UART010_LCRM 0x0C /* Line control register, middle byte. */
40 #define UART010_LCRL 0x10 /* Line control register, low byte. */
45 #define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */
49 #define UART011_LCRH 0x2c /* Line control register. */
50 #define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */
57 #define UART011_DMACR 0x48 /* DMA control register. */
58 #define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */
63 #define ST_UART011_ITCR 0x80 /* Integration test control register. */
65 #define ST_UART011_ABCR 0x100 /* Autobaud control register. */
89 #define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */
90 #define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */
/linux-4.1.27/net/mac80211/
H A Drate.c30 "Default rate control algorithm for mac80211 to use");
99 /* Get the rate control algorithm. */
235 info->control.rates[0].idx = 0; __rate_control_send_low()
246 info->control.rates[0].idx = i; __rate_control_send_low()
251 info->control.rates[0].count = __rate_control_send_low()
255 info->control.skip_table = 1; __rate_control_send_low()
276 info->control.rates[0].idx = mcast_rate - 1; rate_control_send_low()
287 rc_send_low_basicrate(&info->control.rates[0].idx, rate_control_send_low()
426 * allow the frame to be transmitted with whatever the rate control rate_idx_match_mask()
469 info->control.rts_cts_rate_idx = baserate; rate_fixup_ratelist()
495 info->control.use_cts_prot) rate_fixup_ratelist()
507 if (info->control.use_rts) { rate_fixup_ratelist()
509 info->control.use_cts_prot = false; rate_fixup_ratelist()
521 if (info->control.short_preamble && rate_fixup_ratelist()
527 info->control.use_cts_prot && rate_fixup_ratelist()
542 if (sta && !info->control.skip_table) rate_control_fill_sta_table()
548 if (i < ARRAY_SIZE(info->control.rates) && rate_control_fill_sta_table()
549 info->control.rates[i].idx >= 0 && rate_control_fill_sta_table()
550 info->control.rates[i].count) { rate_control_fill_sta_table()
551 if (rates != info->control.rates) rate_control_fill_sta_table()
552 rates[i] = info->control.rates[i]; rate_control_fill_sta_table()
556 if (info->control.use_rts) rate_control_fill_sta_table()
558 else if (info->control.use_cts_prot) rate_control_fill_sta_table()
678 info->control.rates[i].idx = -1; rate_control_get_rate()
679 info->control.rates[i].flags = 0; rate_control_get_rate()
680 info->control.rates[i].count = 0; rate_control_get_rate()
692 info->control.rates, rate_control_get_rate()
693 ARRAY_SIZE(info->control.rates)); rate_control_get_rate()
739 "Failed to select rate control algorithm\n"); ieee80211_init_rate_ctrl_alg()
746 wiphy_debug(local->hw.wiphy, "Selected rate control algorithm '%s'\n", ieee80211_init_rate_ctrl_alg()
/linux-4.1.27/sound/usb/
H A Dmixer_quirks.c37 #include <sound/control.h>
51 unsigned int unitid, control, cmask; member in struct:std_mono_table
66 unsigned int control, snd_create_std_mono_ctl_offset()
83 cval->control = control; snd_create_std_mono_ctl_offset()
95 /* Create control */ snd_create_std_mono_ctl_offset()
113 /* Add control to mixer */ snd_create_std_mono_ctl_offset()
119 unsigned int control, snd_create_std_mono_ctl()
125 return snd_create_std_mono_ctl_offset(mixer, unitid, control, cmask, snd_create_std_mono_ctl()
138 err = snd_create_std_mono_ctl(mixer, t->unitid, t->control, snd_create_std_mono_table()
175 * Sound Blaster remote control configuration
177 * format of remote control data:
213 /* the Mute button actually changes the mixer control */ snd_usb_soundblaster_remote_complete()
265 err = snd_hwdep_new(mixer->chip->card, "SB remote control", 0, &hwdep); snd_usb_soundblaster_remote_init()
269 "%s remote control", mixer->chip->card->shortname); snd_usb_soundblaster_remote_init()
999 unsigned int control, cmask; snd_ftu_create_volume_ctls() local
1006 control = out + 1; snd_ftu_create_volume_ctls()
1012 err = snd_create_std_mono_ctl(mixer, id, control, snd_ftu_create_volume_ctls()
1023 err = snd_create_std_mono_ctl(mixer, id, control, snd_ftu_create_volume_ctls()
1034 /* This control needs a volume quirk, see mixer.c */ snd_ftu_create_effect_volume_ctl()
1040 const unsigned int control = 2; snd_ftu_create_effect_volume_ctl() local
1043 return snd_create_std_mono_ctl(mixer, id, control, cmask, val_type, snd_ftu_create_effect_volume_ctl()
1047 /* This control needs a volume quirk, see mixer.c */ snd_ftu_create_effect_duration_ctl()
1053 const unsigned int control = 3; snd_ftu_create_effect_duration_ctl() local
1056 return snd_create_std_mono_ctl(mixer, id, control, cmask, val_type, snd_ftu_create_effect_duration_ctl()
1060 /* This control needs a volume quirk, see mixer.c */ snd_ftu_create_effect_feedback_ctl()
1066 const unsigned int control = 4; snd_ftu_create_effect_feedback_ctl() local
1069 return snd_create_std_mono_ctl(mixer, id, control, cmask, val_type, snd_ftu_create_effect_feedback_ctl()
1081 const unsigned int control = 7; snd_ftu_create_effect_return_ctls() local
1087 err = snd_create_std_mono_ctl(mixer, id, control, snd_ftu_create_effect_return_ctls()
1105 const unsigned int control = 9; snd_ftu_create_effect_send_ctls() local
1111 err = snd_create_std_mono_ctl(mixer, id, control, cmask, snd_ftu_create_effect_send_ctls()
1121 err = snd_create_std_mono_ctl(mixer, id, control, cmask, snd_ftu_create_effect_send_ctls()
1176 cval->control << 8, snd_emuusb_set_samplerate()
1185 /* C400/C600 volume controls, this control needs a volume quirk, see mixer.c */ snd_c400_create_vol_ctls()
1196 const int control = 1; snd_c400_create_vol_ctls() local
1223 err = snd_create_std_mono_ctl_offset(mixer, id, control, snd_c400_create_vol_ctls()
1234 /* This control needs a volume quirk, see mixer.c */ snd_c400_create_effect_volume_ctl()
1240 const unsigned int control = 3; snd_c400_create_effect_volume_ctl() local
1243 return snd_create_std_mono_ctl(mixer, id, control, cmask, val_type, snd_c400_create_effect_volume_ctl()
1247 /* This control needs a volume quirk, see mixer.c */ snd_c400_create_effect_duration_ctl()
1253 const unsigned int control = 4; snd_c400_create_effect_duration_ctl() local
1256 return snd_create_std_mono_ctl(mixer, id, control, cmask, val_type, snd_c400_create_effect_duration_ctl()
1260 /* This control needs a volume quirk, see mixer.c */ snd_c400_create_effect_feedback_ctl()
1266 const unsigned int control = 5; snd_c400_create_effect_feedback_ctl() local
1269 return snd_create_std_mono_ctl(mixer, id, control, cmask, val_type, snd_c400_create_effect_feedback_ctl()
1283 const int control = 1; snd_c400_create_effect_vol_ctls() local
1308 err = snd_create_std_mono_ctl(mixer, id, control, snd_c400_create_effect_vol_ctls()
1328 const int control = 1; snd_c400_create_effect_ret_vol_ctls() local
1350 err = snd_create_std_mono_ctl_offset(mixer, id, control, snd_c400_create_effect_ret_vol_ctls()
1403 .control = 1,
1410 .control = 2,
1417 .control = 2,
1425 .control = 1,
1432 .control = 2,
1439 .control = 2,
1447 .control = 1,
1454 .control = 2,
1461 .control = 2,
1812 case 0: /* remote control */ snd_usb_mixer_rc_memory_change()
64 snd_create_std_mono_ctl_offset(struct usb_mixer_interface *mixer, unsigned int unitid, unsigned int control, unsigned int cmask, int val_type, unsigned int idx_off, const char *name, snd_kcontrol_tlv_rw_t *tlv_callback) snd_create_std_mono_ctl_offset() argument
117 snd_create_std_mono_ctl(struct usb_mixer_interface *mixer, unsigned int unitid, unsigned int control, unsigned int cmask, int val_type, const char *name, snd_kcontrol_tlv_rw_t *tlv_callback) snd_create_std_mono_ctl() argument
/linux-4.1.27/drivers/media/platform/soc_camera/
H A Dsoc_camera_platform.c57 return soc_camera_set_power(p->icd->control, &p->icd->sdesc->subdev_desc, NULL, on); soc_camera_platform_s_power()
156 /* soc-camera convention: control's drvdata points to the subdev */ soc_camera_platform_probe()
158 /* Set the control device reference */ soc_camera_platform_probe()
159 icd->control = &pdev->dev; soc_camera_platform_probe()
175 p->icd->control = NULL; soc_camera_platform_remove()
/linux-4.1.27/drivers/media/usb/dvb-usb/
H A Dfriio.h23 * LED x3 (+LNB) control: PIC 16F676
46 /* For control msg with data argument */
54 /* LED & LNB control via PIC. */
55 /* basically, it's serial control with clock and strobe. */
56 /* write the below 4bit control data to the reg 0x00 at the I2C addr 0x00 */

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