Lines Matching refs:control

27 * Marvell Berlin CPU control bindings
29 CPU control register allows various operations on CPUs, like resetting them
43 * Marvell Berlin2 chip control binding
45 Marvell Berlin SoCs have a chip control register set providing several
48 chip control registers, so there should be a single DT node only providing the
57   BG2/BG2CD: chip control register set
58   BG2Q: chip control register set and cpu pll registers
60 * Marvell Berlin2 system control binding
62 Marvell Berlin SoCs have a system control register set providing several
70 - reg: address and length of the system control register set
74 As clock related registers are spread among the chip control registers, the
75 chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
94 Pin control registers are part of both register sets, chip control and system
95 control. The pins controlled are organized in groups, so no actual pin
111 A reset controller is part of the chip control registers set. The chip control
120 chip: chip-control@ea0000 {