637 	unsigned long control;       /* control register */  in sm501fb_set_par_crt()  local
647 	control = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);  in sm501fb_set_par_crt()
649 	control &= (SM501_DC_CRT_CONTROL_PIXEL_MASK |  in sm501fb_set_par_crt()
659 		control |= SM501_DC_CRT_CONTROL_HSP;  in sm501fb_set_par_crt()
662 		control |= SM501_DC_CRT_CONTROL_VSP;  in sm501fb_set_par_crt()
664 	if ((control & SM501_DC_CRT_CONTROL_SEL) == 0) {  in sm501fb_set_par_crt()
681 	control |= SM501_FIFO_3;	/* fill if >3 free slots */  in sm501fb_set_par_crt()
685 		control |= SM501_DC_CRT_CONTROL_8BPP;  in sm501fb_set_par_crt()
689 		control |= SM501_DC_CRT_CONTROL_16BPP;  in sm501fb_set_par_crt()
694 		control |= SM501_DC_CRT_CONTROL_32BPP;  in sm501fb_set_par_crt()
702 	control |= SM501_DC_CRT_CONTROL_SEL;	/* CRT displays CRT data */  in sm501fb_set_par_crt()
703 	control |= SM501_DC_CRT_CONTROL_TE;	/* enable CRT timing */  in sm501fb_set_par_crt()
704 	control |= SM501_DC_CRT_CONTROL_ENABLE;	/* enable CRT plane */  in sm501fb_set_par_crt()
707 	dev_dbg(fbi->dev, "new control is %08lx\n", control);  in sm501fb_set_par_crt()
709 	smc501_writel(control, fbi->regs + SM501_DC_CRT_CONTROL);  in sm501fb_set_par_crt()
717 	unsigned long control;  in sm501fb_panel_power()  local
721 	control = smc501_readl(ctrl_reg);  in sm501fb_panel_power()
723 	if (to && (control & SM501_DC_PANEL_CONTROL_VDD) == 0) {  in sm501fb_panel_power()
726 		control |= SM501_DC_PANEL_CONTROL_VDD;	/* FPVDDEN */  in sm501fb_panel_power()
727 		smc501_writel(control, ctrl_reg);  in sm501fb_panel_power()
731 		control |= SM501_DC_PANEL_CONTROL_DATA;	/* DATA */  in sm501fb_panel_power()
732 		smc501_writel(control, ctrl_reg);  in sm501fb_panel_power()
740 				control &= ~SM501_DC_PANEL_CONTROL_BIAS;  in sm501fb_panel_power()
742 				control |= SM501_DC_PANEL_CONTROL_BIAS;  in sm501fb_panel_power()
744 			smc501_writel(control, ctrl_reg);  in sm501fb_panel_power()
751 				control &= ~SM501_DC_PANEL_CONTROL_FPEN;  in sm501fb_panel_power()
753 				control |= SM501_DC_PANEL_CONTROL_FPEN;  in sm501fb_panel_power()
755 			smc501_writel(control, ctrl_reg);  in sm501fb_panel_power()
759 	} else if (!to && (control & SM501_DC_PANEL_CONTROL_VDD) != 0) {  in sm501fb_panel_power()
763 				control |= SM501_DC_PANEL_CONTROL_FPEN;  in sm501fb_panel_power()
765 				control &= ~SM501_DC_PANEL_CONTROL_FPEN;  in sm501fb_panel_power()
767 			smc501_writel(control, ctrl_reg);  in sm501fb_panel_power()
774 				control |= SM501_DC_PANEL_CONTROL_BIAS;  in sm501fb_panel_power()
776 				control &= ~SM501_DC_PANEL_CONTROL_BIAS;  in sm501fb_panel_power()
778 			smc501_writel(control, ctrl_reg);  in sm501fb_panel_power()
783 		control &= ~SM501_DC_PANEL_CONTROL_DATA;  in sm501fb_panel_power()
784 		smc501_writel(control, ctrl_reg);  in sm501fb_panel_power()
788 		control &= ~SM501_DC_PANEL_CONTROL_VDD;  in sm501fb_panel_power()
789 		smc501_writel(control, ctrl_reg);  in sm501fb_panel_power()
807 	unsigned long control;  in sm501fb_set_par_pnl()  local
824 	control = smc501_readl(fbi->regs + SM501_DC_PANEL_CONTROL);  in sm501fb_set_par_pnl()
825 	control &= (SM501_DC_PANEL_CONTROL_GAMMA |  in sm501fb_set_par_pnl()
837 	control |= SM501_FIFO_3;	/* fill if >3 free slots */  in sm501fb_set_par_pnl()
841 		control |= SM501_DC_PANEL_CONTROL_8BPP;  in sm501fb_set_par_pnl()
845 		control |= SM501_DC_PANEL_CONTROL_16BPP;  in sm501fb_set_par_pnl()
850 		control |= SM501_DC_PANEL_CONTROL_32BPP;  in sm501fb_set_par_pnl()
871 	control |= SM501_DC_PANEL_CONTROL_TE;	/* enable PANEL timing */  in sm501fb_set_par_pnl()
872 	control |= SM501_DC_PANEL_CONTROL_EN;	/* enable PANEL gfx plane */  in sm501fb_set_par_pnl()
875 		control |= SM501_DC_PANEL_CONTROL_HSP;  in sm501fb_set_par_pnl()
878 		control |= SM501_DC_PANEL_CONTROL_VSP;  in sm501fb_set_par_pnl()
880 	smc501_writel(control, fbi->regs + SM501_DC_PANEL_CONTROL);  in sm501fb_set_par_pnl()