Searched refs:SCC (Results 1 - 83 of 83) sorted by relevance

/linux-4.1.27/arch/powerpc/include/asm/
H A Dhydra.h47 char SCC[0x1000]; member in struct:Hydra
61 #define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */
63 #define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */
64 #define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */
66 #define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */
H A Dcpm1.h280 /* SCC Event and Mask register.
366 /* SCC Event register as used by Ethernet.
375 /* SCC Mode Register (PMSR) as used by Ethernet.
391 /* SCC as UART
421 /* SCC Event and Mask registers when it is used as a UART.
435 /* The SCC PMSR when used as a UART.
451 /* CPM Transparent mode SCC.
555 #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
H A Dcpm.h114 * Common to SCC and FCC.
133 * Common to SCC and FCC.
150 /* Buffer descriptor control/status used by Transparent mode SCC.
H A Dcpm2.h301 /* SCC Event and Mask register.
389 /* SCC Event register as used by Ethernet.
398 /* SCC Mode Register (PSMR) as used by Ethernet.
414 /* SCC as UART
445 /* SCC Event and Mask registers when it is used as a UART.
459 /* The SCC PSMR when used as a UART.
475 /* CPM Transparent mode SCC.
845 * CMXSCR - CMX SCC Clock Route Register
H A Dpmac_feature.h155 * enable/disable an SCC side. Pass the node corresponding to the
158 * if param is ored with PMAC_SCC_FLAG_XMON, then the SCC is locked enabled
/linux-4.1.27/drivers/tty/serial/cpm_uart/
H A Dcpm_uart_cpm1.h2 * Driver for CPM (SCC/SMC) serial ports
H A Dcpm_uart_cpm2.h2 * Driver for CPM (SCC/SMC) serial ports
H A Dcpm_uart.h2 * Driver for CPM (SCC/SMC) serial ports
H A Dcpm_uart_cpm1.c2 * Driver for CPM (SCC/SMC) serial ports; CPM1 definitions
H A Dcpm_uart_cpm2.c2 * Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
H A Dcpm_uart_core.c2 * Driver for CPM (SCC/SMC) serial ports; core driver
622 * MRBLR can be changed while an SMC/SCC is operating only cpm_uart_set_termios()
628 * SMC/SCC receiver is disabled. cpm_uart_set_termios()
1486 MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
/linux-4.1.27/arch/mips/include/asm/dec/
H A Dkn02ba.h38 #define KN02BA_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */
39 #define KN02BA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
H A Dkn03.h43 #define KN03_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */
44 #define KN03_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
H A Dioasic_addrs.h30 #define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */
32 #define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE) /* SCC #1 (3min, 3max+) */
111 * FLOPPY and ISDN bits (otherwise unused) and has a different SCC
H A Dinterrupts.h40 #define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */
41 #define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */
H A Dioasic_ints.h26 * unused) and has a different SCC wiring.
H A Dkn02ca.h40 #define KN02CA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
/linux-4.1.27/arch/m68k/include/asm/
H A Dmac_iop.h90 struct { /* SCC registers */
91 __u8 sccb_cmd; /* SCC B command reg */
93 __u8 scca_cmd; /* SCC A command reg */
95 __u8 sccb_data; /* SCC B data */
97 __u8 scca_data; /* SCC A data */
H A Dm68360_regs.h41 /* quicc32 mask/event SCC register */
58 * General SCC mode register (GSMR)
144 #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
152 #define INTR_SCC1 0x40000000 /* SCC port 1 */
153 #define INTR_SCC2 0x20000000 /* SCC port 2 */
154 #define INTR_SCC3 0x10000000 /* SCC port 3 */
155 #define INTR_SCC4 0x08000000 /* SCC port 4 */
H A Dmac_psc.h5 * by the VIAs (Ethernet, DSP, SCC, Sound). This includes nine DMA
17 * 5. SCC Channel A Receive
18 * 6. SCC Channel B Receive
19 * 7. SCC Channel A Transmit
H A Dmvme147hw.h95 /* SCC interrupts, for MVME147 */
H A Dmvme16xhw.h64 /* SCC interrupts, for MVME162 */
H A Dm68360_quicc.h256 /* SCC registers */
301 } scc_gsmr; /* SCC general mode reg */
304 volatile unsigned short scc_todr; /* SCC transmit on demand */
305 volatile unsigned short scc_dsr; /* SCC data sync reg */
306 volatile unsigned short scc_scce; /* SCC event reg */
308 volatile unsigned short scc_sccm; /* SCC mask reg */
310 volatile unsigned char scc_sccs; /* SCC status reg */
H A Dmac_via.h38 #define VIA1A_vSccWrReq 0x80 /* SCC write. (input)
39 * [CHRP] SCC WREQ: Reflects the state of the
40 * Wait/Request pins from the SCC.
47 * signal from port B of the SCC appear on
69 * signal from port A of the SCC appear
76 * drive the SCC's /RTxCA pin.
78 * the SCC cell.
H A Datarihw.h90 ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */
91 ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */
99 ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */
440 ** SCC Z8530
444 struct SCC struct
454 # define atari_scc ((*(volatile struct SCC*)SCC_BAS))
457 # define st_escc ((*(volatile struct SCC*)0xfffffa31))
460 /* TT SCC DMA Controller (same chip as SCSI DMA) */
H A Dbvme6000hw.h119 /* SCC interrupts */
H A Dm68360_pram.h81 * SCC parameter RAM
141 * SCC parameter RAM
193 * SCC parameter RAM
229 (overlaid on tx bd[5] of SCC channel[2])
240 (overlaid on tx bd[6,7] of SCC channel[2])
315 * SCC parameter RAM
392 * SCC parameter RAM
H A Dcommproc.h343 /* SCC Event and Mask register.
483 /* SCC Event register as used by Ethernet.
492 /* SCC Mode Register (PMSR) as used by Ethernet.
541 /* SCC as UART
572 /* SCC Event and Mask registers when it is used as a UART.
586 /* The SCC PMSR when used as a UART.
602 /* CPM Transparent mode SCC.
663 #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
H A Datariints.h82 /* SCC interrupts */
H A Dm68360_enet.h114 /* SCC Parameter Ram */
/linux-4.1.27/include/linux/
H A Dscc.h26 /* SCC channel control structure for KISS */
46 /* SCC channel structure */
63 char enhanced; /* Enhanced SCC support */
H A Dfs_uart_pd.h66 if(strstr(fpi->fs_type, "SCC")) fs_uart_get_id()
H A Dfs_enet_pd.h156 if(strstr(fpi->fs_type, "SCC")) fs_get_id()
/linux-4.1.27/include/uapi/linux/
H A Dscc.h9 #define PA0HZP 0x00 /* hardware type for PA0HZP SCC card and compatible */
14 #define BAYCOM 0x10 /* hardware type for BayCom (U)SCC */
108 /* SCC statistical information */
/linux-4.1.27/arch/m68k/include/uapi/asm/
H A Dbootinfo-mac.h19 #define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */
44 #define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */
/linux-4.1.27/include/linux/platform_data/
H A Dserial-sccnxp.h2 * NXP (Philips) SCC+++(SCN+++) serial driver
/linux-4.1.27/arch/m68k/mac/
H A Dmacints.c33 * 4 - SCC
62 * 4 - SCC IOP
72 * - slot 1: SCC channel A interrupt
73 * - slot 2: SCC channel B interrupt
H A Diop.c19 * 990429 (jmt) - Initial implementation, just enough to knock the SCC IOP
64 * on the SCC IOP there is one channel for each serial port. Each channel has
134 * The SCC IOP controls both serial ports (A and B) as its two functions.
271 printk("IOP: detected SCC IOP at %p\n", iop_base[IOP_NUM_SCC]); iop_init()
H A Dpsc.c5 * by the VIAs (Ethernet, DSP, SCC).
H A Dconfig.c623 * The PowerBooks all the same "Combo" custom IC for SCSI and SCC
893 printk(KERN_DEBUG " Videological 0x%lx phys. 0x%lx, SCC at 0x%lx\n", mac_identify()
/linux-4.1.27/include/linux/can/platform/
H A Dti_hecc.h24 * @scc_ram_offset: SCC RAM offset
/linux-4.1.27/arch/m68k/atari/
H A Dataints.c17 * Corrected a bug in atari_add_isr() which rejected all SCC
62 * TT-MFP, SCC, and finally VME interrupts. Vector numbers for the latter can
297 if (ATARIHW_PRESENT(SCC) && !atari_SCC_reset_done) { atari_init_IRQ()
307 * needs them?) MFP and SCC are atari_init_IRQ()
310 tt_scu.vme_mask = 0x60; /* enable MFP and SCC ints */ atari_init_IRQ()
H A Dconfig.c88 /* ++roman: This is a more elaborate test for an SCC chip, since the plain
89 * Medusa board generates DTACK at the SCC's standard addresses, but a SCC
322 ATARIHW_SET(SCC); config_atari()
323 printk("SCC "); config_atari()
647 ATARIHW_ANNOUNCE(SCC, "Serial Communications Controller SCC 8530"); atari_get_hardware_list()
648 ATARIHW_ANNOUNCE(ST_ESCC, "Extended Serial Communications Controller SCC 85230"); atari_get_hardware_list()
654 ATARIHW_ANNOUNCE(SCC_DMA, "DMA Controller for SCC"); atari_get_hardware_list()
H A Ddebug.c23 /* Can be set somewhere, if a SCC master reset has already be done and should
158 * SCC serial ports. They're used by the debugging interface, kgdb, and the
305 /* SCC Modem2 serial port */ atari_debug_setup()
/linux-4.1.27/arch/m68k/68360/
H A Dhead-ram.S377 .long 0 /* (User-Defined Vectors 29) CPM SCC 4 - 91. */
378 .long 0 /* (User-Defined Vectors 30) CPM SCC 3 - 92. */
379 .long 0 /* (User-Defined Vectors 31) CPM SCC 2 - 93. */
380 .long 0 /* (User-Defined Vectors 32) CPM SCC 1 - 94. */
H A Dhead-rom.S388 .long 0 /* (User-Defined Vectors 29) CPM SCC 4 - 91. */
389 .long 0 /* (User-Defined Vectors 30) CPM SCC 3 - 92. */
390 .long 0 /* (User-Defined Vectors 31) CPM SCC 2 - 93. */
391 .long 0 /* (User-Defined Vectors 32) CPM SCC 1 - 94. */
/linux-4.1.27/arch/arm/mach-vexpress/
H A Dtc2_pm.c34 /* SCC conf registers */
214 * SCC registers. We need to extract runtime information like tc2_pm_init()
235 * A subset of the SCC registers is also used to communicate tc2_pm_init()
/linux-4.1.27/drivers/net/ethernet/freescale/fs_enet/
H A Dmac-scc.c2 * Ethernet on Serial Communications Controller (SCC) driver for Motorola MPC8xx and MPC82xx.
86 * Delay to wait for SCC reset command to complete (in us)
374 dev_warn(fep->dev, "SCC timeout on graceful transmit stop\n"); stop()
460 dev_warn(fep->dev, "SCC ERROR(s) 0x%x\n", int_events); ev_error()
/linux-4.1.27/arch/sparc/include/asm/
H A Dturbosparc.h48 * |IOClk|SNP|AXClk| RAH | WS | RSV |SBC|WT|uS2|SE|SCC|
/linux-4.1.27/arch/metag/include/uapi/asm/
H A Dptrace.h18 /* SCC bit (indicates split 16x16 condition flags) */
/linux-4.1.27/drivers/net/wan/
H A Dwanxlfw.S422 movew %d1, CR // Init SCC RX and TX params
427 orl #0x00000030, SCC_GSMR_L(%a2) // enable SCC
436 clrw SCC_SCCM(%a0) // no SCC interrupts
654 /****************************** SCC interrupts ************************/
657 orl #0, SCC1_REGS + SCC_SCCE; // confirm SCC events
663 orl #0, SCC2_REGS + SCC_SCCE; // confirm SCC events
669 orl #0, SCC3_REGS + SCC_SCCE; // confirm SCC events
675 orl #0, SCC4_REGS + SCC_SCCE; // confirm SCC events
H A Dz85230.h247 * Interrupt handling functions for this SCC
378 struct z8530_channel chanA; /* SCC channel A */
379 struct z8530_channel chanB; /* SCC channel B */
H A Dsdla.c277 #define Z80_SCC_OK '3' /* SCC is on board */
278 #define Z80_SCC_BAD '4' /* SCC was not found */
300 printk("%s: SCC bad\n", dev->name); sdla_cpuspeed()
H A Ddscc4.c264 /* SCC registers definitions */
324 /* SCC events */
784 * SCC 0-3 private rx/tx irq structures dscc4_init_one()
856 /* No interrupts, SCC core disabled. Let's relax */ dscc4_init_registers()
1086 * NB: the datasheet "...CEC will stay active if the SCC is in dscc4_open()
/linux-4.1.27/drivers/net/hamradio/
H A Dscc.c15 * SCC.C - Linux driver for Z8530 based HDLC cards for AX.25 *
37 ! before you connect a radio to the SCC board and start to transmit or !
41 allowance/licence from the designer of the SCC Board and/or the
186 "AX.25: Z8530 SCC driver version "VERSION".dl1bke\n";
661 /* Find the SCC generating the interrupt by polling all attached SCCs scc_isr()
716 /* ----> set SCC channel speed <---- */
738 /* ----> initialize a SCC channel <---- */
891 /* * SCC timer functions * */
993 /* ----> SCC timer interrupt handler and friends. <---- */
1484 /* Special SCC cards */ z8530_init()
1740 0, "AX.25 SCC", scc_net_ioctl()
2105 /* * Init SCC driver * */
2184 MODULE_SUPPORTED_DEVICE("Z8530 based SCC cards for Amateur Radio");
H A Ddmascc.c2 * Driver for high-speed SCC boards (those with DMA support)
79 /* SCC chips supported */
276 MODULE_DESCRIPTION("Driver for high-speed SCC boards");
493 /* Reset SCC */ setup_adapter()
499 /* WR7' not present. This is an ordinary Z8530 SCC. */ setup_adapter()
508 /* TX FIFO full. This is a Z85C30 SCC with a 1-byte FIFO. */ setup_adapter()
1170 Same algorithm for SCC and ESCC. See 2.4.7.1 and 2.4.7.4. */ rx_isr()
H A Dz8530.h222 /* Z85C30/Z85230 Enhanced SCC register definitions */
/linux-4.1.27/arch/powerpc/platforms/powermac/
H A Dudbg_scc.c127 /* If SCC was the OF output port, read the BRG value, else udbg_scc_init()
/linux-4.1.27/net/ax25/
H A Dax25_ds_subr.c124 * either SCC changing, PI config or KISS as required. Currently
/linux-4.1.27/drivers/tty/serial/
H A Dzs.h22 struct zs_scc *scc; /* Containing SCC. */
37 * Per-SCC state for locking and the interrupt handler.
H A Dzs.c19 * DIN-7 MJ-4 signal SCC
24 * DB-25 MMJ-6 signal SCC
98 #define ZS_CHAN_IO_OFFSET 1 /* The SCC resides on the high byte
730 * the SCC would, was it allowed to. zs_interrupt()
981 return "Z85C30 SCC"; zs_type()
H A Dpmac_zilog.c740 * Turn power on or off to the SCC and associated stuff
784 * FixZeroBug....Works around a bug in the SCC receiving channel.
793 * The SCC is initialized (hardware or software).
800 * the SCC in synchronous loopback mode with a fast clock before programming
843 * the SCC. Returns a delay in ms where you need to wait before
853 /* Power up the SCC & underlying hardware (modem/irda) */ __pmz_startup()
1193 /* Switch SCC to 19200 */ pmz_irda_setup()
H A Dsccnxp.c2 * NXP (Philips) SCC+++(SCN+++) serial driver
/linux-4.1.27/drivers/rtc/
H A Drtc-imxdi.c69 #define DSR_SAD (1 << 19) /* SCC alarm detected */
99 #define DTCR_SAIE (1 << 3) /* SCC enabled */
/linux-4.1.27/drivers/net/can/
H A Dti_hecc.c134 #define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */
135 #define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */
147 #define HECC_CANMC_SCM BIT(13) /* SCC compat mode */
380 /* SCC compat mode NOT supported (and not needed too) */ ti_hecc_reset()
/linux-4.1.27/drivers/usb/host/
H A Dohci-pci.c103 /* Check for Toshiba SCC OHCI which has big endian registers
H A Dfhci-hcd.c311 /* allocate memory for SCC data structure */ fhci_create_lld()
314 fhci_err(fhci, "no memory for SCC data struct\n"); fhci_create_lld()
H A Dohci.h507 * Spider (aka SCC) cell southbridge are "mixed" endian, that is,
/linux-4.1.27/arch/m68k/kernel/
H A Dhead.S247 * USE_SCC_B: Use the SCC port A (Serial2) for serial debug.
248 * USE_SCC_A: Use the SCC port B (Modem2) for serial debug.
252 * MAC_USE_SCC_A: Use SCC port A (modem) for serial debug.
253 * MAC_USE_SCC_B: Use SCC port B (printer) for serial debug.
2729 * from the MFP or a serial port of the SCC
2738 /* Initialisation table for SCC with 3.6864 MHz PCLK */
2761 /* Initialisation table for SCC with 7.9872 MHz PCLK */
2824 * a0 = address of SCC
2828 * a0 = address of SCC
2863 /* Reset SCC register pointer */
2865 /* Reset SCC device: write register pointer then register value */
2902 /* Reset SCC register pointer */
2904 /* Reset SCC device: write register pointer then register value */
3082 /* 162/172; it's an SCC */
/linux-4.1.27/drivers/macintosh/
H A Dmacio_asic.c263 /* Fix SCC */ macio_add_missing_resources()
268 printk(KERN_INFO "macio: fixed SCC irqs on gatwick\n"); macio_add_missing_resources()
/linux-4.1.27/arch/m68k/bvme6000/
H A Dconfig.c133 /* PRI, SYSCON?, Level3, SCC clks from xtal */ config_bvme6000()
/linux-4.1.27/drivers/nfc/
H A Dport100.c39 + 2) /* data[0] CC, data[1] SCC */
45 * Max extended frame payload len, excluding CC and SCC
70 #define PORT100_FRAME_CMD(f) (f->data[1]) /* SCC */
/linux-4.1.27/arch/arm/mach-imx/
H A Dclk-imx35.c270 * SCC is needed to boot via mmc after a watchdog reset. The clock code mx35_clocks_init()
/linux-4.1.27/drivers/ata/
H A Dpata_samsung_cf.c11 * PATA driver for Toshiba SCC controller
/linux-4.1.27/drivers/staging/dgap/
H A Ddgap.h1097 unsigned short fepdev; /* U SCC device base address */
1144 unsigned char scc[16]; /* U SCC registers */
/linux-4.1.27/drivers/target/
H A Dtarget_core_spc.c1391 * MAINTENANCE_IN from SCC-2 spc_parse_cdb()
1409 * MAINTENANCE_OUT from SCC-2 spc_parse_cdb()
/linux-4.1.27/drivers/isdn/hardware/mISDN/
H A Dw6692.c454 pr_debug("%s: SCC SQR %02X\n", card->name, v1); handle_statusD()
/linux-4.1.27/drivers/isdn/hisax/
H A Dw6692.c527 debugl1(cs, "W6692 SCC SQR=0x%02X", v1); W6692_interrupt()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dgk104.c669 { 0x14, "SCC" },
/linux-4.1.27/drivers/net/ethernet/intel/e1000e/
H A Dmac.c370 er32(SCC); e1000e_clear_hw_cntrs_base()
H A Dnetdev.c4715 adapter->stats.scc += er32(SCC); e1000e_update_stats()
/linux-4.1.27/drivers/net/ethernet/intel/e1000/
H A De1000_main.c3649 adapter->stats.scc += er32(SCC); e1000_update_stats()
H A De1000_hw.c4706 temp = er32(SCC); e1000_clear_hw_cntrs()

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