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Searched refs:REG_WRITE (Results 1 – 133 of 133) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/gma500/
Dmdfld_dsi_dpi.c134 REG_WRITE(pipeconf_reg, BIT(31)); in dsi_set_pipe_plane_enable_state()
141 REG_WRITE(dspcntr_reg, dspcntr); in dsi_set_pipe_plane_enable_state()
157 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in dsi_set_pipe_plane_enable_state()
243 REG_WRITE(gen_data_reg, 0x00008036); in mdfld_dsi_tpo_ic_init()
245 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
249 REG_WRITE(gen_data_reg, 0x005a5af0); in mdfld_dsi_tpo_ic_init()
251 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
255 REG_WRITE(gen_data_reg, 0x005a5af1); in mdfld_dsi_tpo_ic_init()
257 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
261 REG_WRITE(gen_data_reg, 0x005a5afc); in mdfld_dsi_tpo_ic_init()
[all …]
Dmdfld_intel_display.c143 REG_WRITE(dspcntr_reg, dspcntr); in mdfld__intel_plane_set_alpha()
201 REG_WRITE(map->stride, crtc->primary->fb->pitches[0]); in mdfld__intel_pipe_set_base()
220 REG_WRITE(map->cntr, dspcntr); in mdfld__intel_pipe_set_base()
224 REG_WRITE(map->linoff, offset); in mdfld__intel_pipe_set_base()
226 REG_WRITE(map->surf, start); in mdfld__intel_pipe_set_base()
254 REG_WRITE(map->cntr, in mdfld_disable_crtc()
257 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_disable_crtc()
268 REG_WRITE(map->conf, temp); in mdfld_disable_crtc()
281 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
289 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
[all …]
Doaktrail_hdmi.c288 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); in oaktrail_crtc_hdmi_mode_set()
293 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
294 REG_WRITE(DPLL_DIV_CTRL, 0x00000000); in oaktrail_crtc_hdmi_mode_set()
295 REG_WRITE(DPLL_STATUS, 0x1); in oaktrail_crtc_hdmi_mode_set()
310 REG_WRITE(DPLL_CTRL, 0x00000008); in oaktrail_crtc_hdmi_mode_set()
311 REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr)); in oaktrail_crtc_hdmi_mode_set()
312 REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1)); in oaktrail_crtc_hdmi_mode_set()
313 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
314 REG_WRITE(DPLL_UPDATE, 0x80000000); in oaktrail_crtc_hdmi_mode_set()
315 REG_WRITE(DPLL_CLK_ENABLE, 0x80050102); in oaktrail_crtc_hdmi_mode_set()
[all …]
Dcdv_device.c46 REG_WRITE(vga_reg, VGA_DISP_DISABLE); in cdv_disable_vga()
146 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | in cdv_set_brightness()
327 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); in cdv_restore_display_registers()
328 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); in cdv_restore_display_registers()
331 REG_WRITE(DPIO_CFG, 0); in cdv_restore_display_registers()
332 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); in cdv_restore_display_registers()
336 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()
342 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); in cdv_restore_display_registers()
348 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); in cdv_restore_display_registers()
349 REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]); in cdv_restore_display_registers()
[all …]
Dgma_display.c86 REG_WRITE(map->stride, crtc->primary->fb->pitches[0]); in gma_pipe_set_base()
110 REG_WRITE(map->cntr, dspcntr); in gma_pipe_set_base()
119 REG_WRITE(map->base, offset + start); in gma_pipe_set_base()
122 REG_WRITE(map->base, offset); in gma_pipe_set_base()
124 REG_WRITE(map->surf, start); in gma_pipe_set_base()
154 REG_WRITE(palreg + 4 * i, in gma_crtc_load_lut()
228 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
232 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
236 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
245 REG_WRITE(map->cntr, in gma_crtc_dpms()
[all …]
Dcdv_intel_display.c149 REG_WRITE(SB_ADDR, reg); in cdv_sb_read()
150 REG_WRITE(SB_PCKT, in cdv_sb_read()
184 REG_WRITE(SB_ADDR, reg); in cdv_sb_write()
185 REG_WRITE(SB_DATA, val); in cdv_sb_write()
186 REG_WRITE(SB_PCKT, in cdv_sb_write()
211 REG_WRITE(DPIO_CFG, 0); in cdv_sb_reset()
213 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); in cdv_sb_reset()
236 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()
482 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
490 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); in cdv_disable_sr()
[all …]
Dpsb_intel_display.c219 REG_WRITE(PFIT_CONTROL, 0); in psb_intel_crtc_mode_set()
224 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
225 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
255 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()
259 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
260 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
266 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
272 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in psb_intel_crtc_mode_set()
274 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in psb_intel_crtc_mode_set()
276 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in psb_intel_crtc_mode_set()
[all …]
Dcdv_intel_crt.c64 REG_WRITE(reg, temp); in cdv_intel_crt_dpms()
109 REG_WRITE(dpll_md_reg, in cdv_intel_crt_mode_set()
124 REG_WRITE(adpa_reg, adpa); in cdv_intel_crt_mode_set()
158 REG_WRITE(PORT_HOTPLUG_EN, hotplug_en); in cdv_intel_crt_detect_hotplug()
174 REG_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); in cdv_intel_crt_detect_hotplug()
177 REG_WRITE(PORT_HOTPLUG_EN, orig); in cdv_intel_crt_detect_hotplug()
Dpsb_intel_lvds.c159 REG_WRITE(BLC_PWM_CTL, in psb_lvds_pwm_set_brightness()
203 REG_WRITE(BLC_PWM_CTL, in psb_intel_lvds_set_backlight()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
243 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
321 REG_WRITE(BLC_PWM_CTL, lvds_priv->saveBLC_PWM_CTL); in psb_intel_lvds_restore()
322 REG_WRITE(PFIT_CONTROL, lvds_priv->savePFIT_CONTROL); in psb_intel_lvds_restore()
323 REG_WRITE(PFIT_PGM_RATIOS, lvds_priv->savePFIT_PGM_RATIOS); in psb_intel_lvds_restore()
324 REG_WRITE(LVDSPP_ON, lvds_priv->savePP_ON); in psb_intel_lvds_restore()
325 REG_WRITE(LVDSPP_OFF, lvds_priv->savePP_OFF); in psb_intel_lvds_restore()
327 REG_WRITE(PP_CYCLE, lvds_priv->savePP_CYCLE); in psb_intel_lvds_restore()
[all …]
Doaktrail_lvds.c56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in oaktrail_lvds_set_power()
67 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in oaktrail_lvds_set_power()
122 REG_WRITE(LVDS, lvds_port); in oaktrail_lvds_mode_set()
141 REG_WRITE(PFIT_CONTROL, 0); in oaktrail_lvds_mode_set()
147 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
151 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | in oaktrail_lvds_mode_set()
154 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | in oaktrail_lvds_mode_set()
157 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
159 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); in oaktrail_lvds_mode_set()
Doaktrail_crtc.c336 REG_WRITE(DSPARB, 0x3f80); in oaktrail_crtc_dpms()
337 REG_WRITE(DSPFW1, 0x3f8f0404); in oaktrail_crtc_dpms()
338 REG_WRITE(DSPFW2, 0x04040f04); in oaktrail_crtc_dpms()
339 REG_WRITE(DSPFW3, 0x0); in oaktrail_crtc_dpms()
340 REG_WRITE(DSPFW4, 0x04040404); in oaktrail_crtc_dpms()
341 REG_WRITE(DSPFW5, 0x04040404); in oaktrail_crtc_dpms()
342 REG_WRITE(DSPFW6, 0x78); in oaktrail_crtc_dpms()
343 REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040); in oaktrail_crtc_dpms()
427 REG_WRITE(PFIT_CONTROL, 0); in oaktrail_crtc_mode_set()
622 REG_WRITE(map->stride, crtc->primary->fb->pitches[0]); in oaktrail_pipe_set_base()
[all …]
Dmdfld_dsi_pkg_sender.c171 REG_WRITE(intr_stat_reg, mask); in handle_dsi_error()
176 REG_WRITE(intr_stat_reg, mask); in handle_dsi_error()
236 REG_WRITE(ctrl_reg, val); in send_short_pkg()
272 REG_WRITE(data_reg, b4 << 24 | b3 << 16 | b2 << 8 | b1); in send_long_pkg()
294 REG_WRITE(data_reg, b3 << 16 | b2 << 8 | b1); in send_long_pkg()
300 REG_WRITE(ctrl_reg, val); in send_long_pkg()
541 REG_WRITE(sender->mipi_intr_stat_reg, BIT(29)); in __read_panel_data()
560 REG_WRITE(sender->mipi_intr_stat_reg, BIT(29)); in __read_panel_data()
656 REG_WRITE(MIPI_PORT_CONTROL(pipe), mipi_val); in mdfld_dsi_pkg_sender_init()
Dcdv_intel_dp.c394 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_on()
408 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_off()
428 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_on()
461 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_off()
489 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_backlight_on()
505 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_backlight_off()
606 REG_WRITE(ch_data + i, in cdv_intel_dp_aux_ch()
610 REG_WRITE(ch_ctl, in cdv_intel_dp_aux_ch()
627 REG_WRITE(ch_ctl, in cdv_intel_dp_aux_ch()
1029 REG_WRITE(PIPE_GMCH_DATA_M(pipe), in cdv_intel_dp_set_m_n()
[all …]
Dpsb_lid.c40 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); in psb_lid_timer_func()
56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); in psb_lid_timer_func()
Dcdv_intel_hdmi.c88 REG_WRITE(hdmi_priv->hdmi_reg, hdmib); in cdv_hdmi_mode_set()
102 REG_WRITE(hdmi_priv->hdmi_reg, hdmib & ~HDMIB_PORT_EN); in cdv_hdmi_dpms()
104 REG_WRITE(hdmi_priv->hdmi_reg, hdmib | HDMIB_PORT_EN); in cdv_hdmi_dpms()
123 REG_WRITE(hdmi_priv->hdmi_reg, hdmi_priv->save_HDMIB); in cdv_hdmi_restore()
Dcdv_intel_lvds.c145 REG_WRITE(BLC_PWM_CTL,
184 REG_WRITE(BLC_PWM_CTL, in cdv_intel_lvds_set_backlight()
209 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in cdv_intel_lvds_set_power()
220 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in cdv_intel_lvds_set_power()
386 REG_WRITE(PFIT_CONTROL, pfit_control); in cdv_intel_lvds_mode_set()
772 REG_WRITE(BLC_PWM_CTL2, pwm); in cdv_intel_lvds_init()
Dintel_i2c.c69 REG_WRITE(chan->reg, reserved | clock_bits); in set_clock()
91 REG_WRITE(chan->reg, reserved | data_bits); in set_data()
Doaktrail_device.c94 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); in oaktrail_set_brightness()
95 REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl); in oaktrail_set_brightness()
135 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); in device_backlight_init()
136 REG_WRITE(BLC_PWM_CTL, value | (value << 16)); in device_backlight_init()
Dmdfld_device.c385 REG_WRITE(mipi_reg, temp); in mdfld_restore_display_registers()
394 REG_WRITE(device_ready_reg, temp); in mdfld_restore_display_registers()
400 REG_WRITE(device_ready_reg, temp); in mdfld_restore_display_registers()
Dpsb_device.c98 REG_WRITE(BLC_PWM_CTL, in psb_backlight_setup()
Dpsb_drv.h868 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) macro
877 REG_WRITE(reg, val); in REGISTER_WRITE_WITH_AUX()
Dmdfld_dsi_output.h51 REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end))
Dpsb_irq.c299 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); in psb_irq_handler()
Dpsb_intel_sdvo.c1821 REG_WRITE(sdvo->sdvo_reg, sdvo->saveSDVO); in psb_intel_sdvo_restore()
/linux-4.1.27/drivers/net/dsa/
Dmv88e6123_61_65.c64 REG_WRITE(REG_GLOBAL, 0x04, 0x0000); in mv88e6123_61_65_setup_global()
70 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); in mv88e6123_61_65_setup_global()
81 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); in mv88e6123_61_65_setup_global()
86 REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); in mv88e6123_61_65_setup_global()
91 REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); in mv88e6123_61_65_setup_global()
96 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); in mv88e6123_61_65_setup_global()
105 REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); in mv88e6123_61_65_setup_global()
115 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); in mv88e6123_61_65_setup_global()
120 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff); in mv88e6123_61_65_setup_global()
124 REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); in mv88e6123_61_65_setup_global()
[all …]
Dmv88e6171.c48 REG_WRITE(REG_GLOBAL, 0x04, 0x6000); in mv88e6171_setup_global()
54 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); in mv88e6171_setup_global()
66 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1111)); in mv88e6171_setup_global()
68 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); in mv88e6171_setup_global()
73 REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); in mv88e6171_setup_global()
78 REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); in mv88e6171_setup_global()
83 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); in mv88e6171_setup_global()
92 REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); in mv88e6171_setup_global()
102 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); in mv88e6171_setup_global()
107 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff); in mv88e6171_setup_global()
[all …]
Dmv88e6131.c55 REG_WRITE(REG_GLOBAL, 0x04, 0x4400); in mv88e6131_setup_global()
61 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); in mv88e6131_setup_global()
69 REG_WRITE(REG_GLOBAL, 0x19, 0x8100); in mv88e6131_setup_global()
75 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0); in mv88e6131_setup_global()
82 REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f)); in mv88e6131_setup_global()
84 REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f)); in mv88e6131_setup_global()
89 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); in mv88e6131_setup_global()
96 REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); in mv88e6131_setup_global()
107 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); in mv88e6131_setup_global()
112 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff); in mv88e6131_setup_global()
[all …]
Dmv88e6352.c57 REG_WRITE(REG_GLOBAL, 0x04, 0x6000); in mv88e6352_setup_global()
63 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); in mv88e6352_setup_global()
74 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); in mv88e6352_setup_global()
79 REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); in mv88e6352_setup_global()
84 REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); in mv88e6352_setup_global()
89 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); in mv88e6352_setup_global()
98 REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); in mv88e6352_setup_global()
107 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); in mv88e6352_setup_global()
112 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7f); in mv88e6352_setup_global()
116 REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); in mv88e6352_setup_global()
[all …]
Dmv88e6060.c53 #define REG_WRITE(addr, reg, val) \ macro
92 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); in mv88e6060_switch_reset()
99 REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); in mv88e6060_switch_reset()
122 REG_WRITE(REG_GLOBAL, 0x04, 0x0800); in mv88e6060_setup_global()
128 REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); in mv88e6060_setup_global()
142 REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); in mv88e6060_setup_port()
149 REG_WRITE(addr, 0x06, in mv88e6060_setup_port()
160 REG_WRITE(addr, 0x0b, 1 << p); in mv88e6060_setup_port()
191 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); in mv88e6060_set_addr()
192 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); in mv88e6060_set_addr()
[all …]
Dmv88e6xxx.c171 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); in mv88e6xxx_config_prio()
172 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); in mv88e6xxx_config_prio()
173 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); in mv88e6xxx_config_prio()
174 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); in mv88e6xxx_config_prio()
175 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); in mv88e6xxx_config_prio()
176 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); in mv88e6xxx_config_prio()
177 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); in mv88e6xxx_config_prio()
178 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); in mv88e6xxx_config_prio()
181 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); in mv88e6xxx_config_prio()
188 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); in mv88e6xxx_set_addr_direct()
[all …]
Dmv88e6xxx.h328 #define REG_WRITE(addr, reg, val) \ macro
/linux-4.1.27/drivers/net/wireless/ath/
Dkey.c26 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
57 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); in ath_hw_keyreset()
58 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); in ath_hw_keyreset()
59 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); in ath_hw_keyreset()
60 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); in ath_hw_keyreset()
61 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); in ath_hw_keyreset()
62 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); in ath_hw_keyreset()
63 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); in ath_hw_keyreset()
64 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); in ath_hw_keyreset()
69 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); in ath_hw_keyreset()
[all …]
Dhw.c24 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro
123 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); in ath_hw_setbssidmask()
126 REG_WRITE(ah, AR_STA_ID1, id1); in ath_hw_setbssidmask()
128 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(common->bssidmask)); in ath_hw_setbssidmask()
129 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(common->bssidmask + 4)); in ath_hw_setbssidmask()
148 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ath_hw_cycle_counters_update()
157 REG_WRITE(ah, AR_CCCNT, 0); in ath_hw_cycle_counters_update()
158 REG_WRITE(ah, AR_RFCNT, 0); in ath_hw_cycle_counters_update()
159 REG_WRITE(ah, AR_RCCNT, 0); in ath_hw_cycle_counters_update()
160 REG_WRITE(ah, AR_TFCNT, 0); in ath_hw_cycle_counters_update()
[all …]
/linux-4.1.27/drivers/net/wireless/ath/ath9k/
Dar9002_phy.c101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
152 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
249 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); in ar9002_hw_spur_mitigate()
256 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); in ar9002_hw_spur_mitigate()
286 REG_WRITE(ah, AR_PHY_TIMING11, newVal); in ar9002_hw_spur_mitigate()
289 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); in ar9002_hw_spur_mitigate()
307 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar9002_hw_spur_mitigate()
308 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar9002_hw_spur_mitigate()
341 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar9002_hw_spur_mitigate()
[all …]
Dar9003_wow.c44 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_set_powermode_wow_sleep()
62 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); in ath9k_hw_set_powermode_wow_sleep()
64 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT); in ath9k_hw_set_powermode_wow_sleep()
92 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); in ath9k_wow_create_keep_alive_pattern()
111 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0); in ath9k_wow_create_keep_alive_pattern()
118 REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]); in ath9k_wow_create_keep_alive_pattern()
139 REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i), in ath9k_hw_wow_apply_pattern()
146 REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val); in ath9k_hw_wow_apply_pattern()
235 REG_WRITE(ah, AR_WOW_PATTERN, in ath9k_hw_wow_wakeup()
237 REG_WRITE(ah, AR_MAC_PCU_WOW4, in ath9k_hw_wow_wakeup()
[all …]
Dar9003_aic.c111 REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00); in ar9003_aic_gain_table()
112 REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438); in ar9003_aic_gain_table()
155 REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000), in ar9003_aic_gain_table()
160 REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), in ar9003_aic_gain_table()
171 REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000), in ar9003_aic_cal_start()
176 REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), 0); in ar9003_aic_cal_start()
180 REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B0, in ar9003_aic_cal_start()
190 REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B1, in ar9003_aic_cal_start()
197 REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B0, in ar9003_aic_cal_start()
206 REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B1, in ar9003_aic_cal_start()
[all …]
Dhw.c118 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
324 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
325 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
[all …]
Dar5008_phy.c73 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
218 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
250 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
318 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); in ar5008_hw_spur_mitigate()
325 REG_WRITE(ah, AR_PHY_SPUR_REG, new); in ar5008_hw_spur_mitigate()
336 REG_WRITE(ah, AR_PHY_TIMING11, new); in ar5008_hw_spur_mitigate()
354 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar5008_hw_spur_mitigate()
355 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar5008_hw_spur_mitigate()
388 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar5008_hw_spur_mitigate()
[all …]
Dar9003_mci.c48 REG_WRITE(ah, address, bit_position); in ar9003_mci_wait_for_interrupt()
58 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_wait_for_interrupt()
61 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_RX_MSG); in ar9003_mci_wait_for_interrupt()
234 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); in ar9003_mci_prep_interface()
235 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, in ar9003_mci_prep_interface()
237 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_prep_interface()
272 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF); in ar9003_mci_prep_interface()
273 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF); in ar9003_mci_prep_interface()
274 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF); in ar9003_mci_prep_interface()
275 REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF); in ar9003_mci_prep_interface()
[all …]
Dar9002_hw.c219 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), in ar9002_hw_configpcipowersave()
225 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ar9002_hw_configpcipowersave()
226 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ar9002_hw_configpcipowersave()
229 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); in ar9002_hw_configpcipowersave()
230 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); in ar9002_hw_configpcipowersave()
231 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); in ar9002_hw_configpcipowersave()
237 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); in ar9002_hw_configpcipowersave()
239 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ar9002_hw_configpcipowersave()
240 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ar9002_hw_configpcipowersave()
241 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); in ar9002_hw_configpcipowersave()
[all …]
Dmac.c32 REG_WRITE(ah, AR_IMR_S0, in ath9k_hw_set_txq_interrupts()
35 REG_WRITE(ah, AR_IMR_S1, in ath9k_hw_set_txq_interrupts()
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_set_txq_interrupts()
54 REG_WRITE(ah, AR_QTXDP(q), txdp); in ath9k_hw_puttxbuf()
61 REG_WRITE(ah, AR_Q_TXE, 1 << q); in ath9k_hw_txstart()
123 REG_WRITE(ah, AR_TXCFG, in ath9k_hw_updatetxtriglevel()
146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); in ath9k_hw_abort_tx_dma()
166 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_abort_tx_dma()
177 REG_WRITE(ah, AR_Q_TXD, 1 << q); in ath9k_hw_stop_dma_queue()
187 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_stop_dma_queue()
[all …]
Dbtcoex.c271 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode); in ath9k_hw_btcoex_enable_3wire()
272 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); in ath9k_hw_btcoex_enable_3wire()
276 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, btcoex->wlan_weight[0]); in ath9k_hw_btcoex_enable_3wire()
277 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, btcoex->wlan_weight[1]); in ath9k_hw_btcoex_enable_3wire()
279 REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), in ath9k_hw_btcoex_enable_3wire()
282 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex->bt_coex_weights); in ath9k_hw_btcoex_enable_3wire()
289 REG_WRITE(ah, 0x50040, val); in ath9k_hw_btcoex_enable_3wire()
305 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i), in ath9k_hw_btcoex_enable_mci()
320 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i), in ath9k_hw_btcoex_disable_mci()
371 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); in ath9k_hw_btcoex_disable()
[all …]
Dar9003_phy.c223 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
232 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
238 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
665 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); in ar9003_hw_set_channel_regs()
671 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
673 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
689 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_init_bb()
699 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
700 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
705 REG_WRITE(ah, AR_SELFGEN_MASK, tx); in ar9003_hw_set_chain_masks()
[all …]
Dani.c139 REG_WRITE(ah, AR_PHY_ERR_1, 0); in ath9k_ani_restart()
140 REG_WRITE(ah, AR_PHY_ERR_2, 0); in ath9k_ani_restart()
141 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_ani_restart()
142 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_ani_restart()
469 REG_WRITE(ah, AR_FILT_OFDM, 0); in ath9k_enable_mib_counters()
470 REG_WRITE(ah, AR_FILT_CCK, 0); in ath9k_enable_mib_counters()
471 REG_WRITE(ah, AR_MIBC, in ath9k_enable_mib_counters()
474 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in ath9k_enable_mib_counters()
475 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in ath9k_enable_mib_counters()
487 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); in ath9k_hw_disable_mib_counters()
[all …]
Dar9003_rtt.c40 REG_WRITE(ah, AR_PHY_RTT_CTRL, 1); in ar9003_hw_rtt_enable()
45 REG_WRITE(ah, AR_PHY_RTT_CTRL, 0); in ar9003_hw_rtt_disable()
78 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
83 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
87 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
96 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_load_hist_entry()
150 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_fill_hist_entry()
154 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); in ar9003_hw_rtt_fill_hist_entry()
Dar9002_calib.c60 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9002_hw_setup_calibration()
65 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); in ar9002_hw_setup_calibration()
69 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); in ar9002_hw_setup_calibration()
302 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_gaincal_calibrate()
309 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_gaincal_calibrate()
357 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_dccal_calibrate()
363 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_dccal_calibrate()
485 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); in ar9271_hw_pa_cal()
493 REG_WRITE(ah, AR9285_AN_RF2G6, regVal); in ar9271_hw_pa_cal()
500 REG_WRITE(ah, AR9285_AN_RF2G6, regVal); in ar9271_hw_pa_cal()
[all …]
Deeprom_9287.c378 REG_WRITE(ah, 0xa270, tmpVal); in ar9287_eeprom_olpc_set_pdadcs()
385 REG_WRITE(ah, 0xb270, tmpVal); in ar9287_eeprom_olpc_set_pdadcs()
394 REG_WRITE(ah, 0xa398, tmpVal); in ar9287_eeprom_olpc_set_pdadcs()
404 REG_WRITE(ah, 0xb398, tmpVal); in ar9287_eeprom_olpc_set_pdadcs()
510 REG_WRITE(ah, in ath9k_hw_set_ar9287_power_cal_table()
538 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_ar9287_power_cal_table()
807 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, in ath9k_hw_ar9287_set_txpower()
813 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, in ath9k_hw_ar9287_set_txpower()
821 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, in ath9k_hw_ar9287_set_txpower()
826 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, in ath9k_hw_ar9287_set_txpower()
[all …]
Dar9003_mac.c23 REG_WRITE(hw, AR_CR, 0); in ar9003_hw_rx_enable()
234 REG_WRITE(ah, AR_ISR_S2, isr2); in ar9003_hw_get_isr()
269 REG_WRITE(ah, AR_ISR_S0, s0); in ar9003_hw_get_isr()
271 REG_WRITE(ah, AR_ISR_S1, s1); in ar9003_hw_get_isr()
296 REG_WRITE(ah, AR_ISR_S5, s5); in ar9003_hw_get_isr()
305 REG_WRITE(ah, AR_ISR, isr); in ar9003_hw_get_isr()
338 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); in ar9003_hw_get_isr()
339 REG_WRITE(ah, AR_RC, 0); in ar9003_hw_get_isr()
347 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); in ar9003_hw_get_isr()
466 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK); in ath9k_hw_set_rx_bufsize()
[all …]
Dar9003_calib.c53 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9003_hw_setup_calibration()
354 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
391 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
408 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, in ar9003_hw_dynamic_osdac_selection()
410 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3, in ar9003_hw_dynamic_osdac_selection()
412 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3, in ar9003_hw_dynamic_osdac_selection()
430 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, in ar9003_hw_dynamic_osdac_selection()
432 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3, in ar9003_hw_dynamic_osdac_selection()
434 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3, in ar9003_hw_dynamic_osdac_selection()
452 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, in ar9003_hw_dynamic_osdac_selection()
[all …]
Dar9002_mac.c24 REG_WRITE(ah, AR_CR, AR_CR_RXE); in ar9002_hw_rx_enable()
82 REG_WRITE(ah, AR_ISR_S2, isr2); in ar9002_hw_get_isr()
113 REG_WRITE(ah, AR_ISR_S0, s0_s); in ar9002_hw_get_isr()
115 REG_WRITE(ah, AR_ISR_S1, s1_s); in ar9002_hw_get_isr()
160 REG_WRITE(ah, AR_ISR_S5, s5_s); in ar9002_hw_get_isr()
166 REG_WRITE(ah, AR_ISR, isr); in ar9002_hw_get_isr()
195 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); in ar9002_hw_get_isr()
196 REG_WRITE(ah, AR_RC, 0); in ar9002_hw_get_isr()
204 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); in ar9002_hw_get_isr()
Deeprom_def.c525 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff); in ath9k_hw_def_set_board_values()
538 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, in ath9k_hw_def_set_board_values()
541 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, in ath9k_hw_def_set_board_values()
613 REG_WRITE(ah, AR_PHY_RF_CTL4, in ath9k_hw_def_set_board_values()
919 REG_WRITE(ah, in ath9k_hw_set_def_power_cal_table()
926 REG_WRITE(ah, in ath9k_hw_set_def_power_cal_table()
942 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_def_power_cal_table()
1242 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, in ath9k_hw_def_set_txpower()
1247 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, in ath9k_hw_def_set_txpower()
1256 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, in ath9k_hw_def_set_txpower()
[all …]
Deeprom_4k.c416 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, in ath9k_hw_set_4k_power_cal_table()
431 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_4k_power_cal_table()
691 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, in ath9k_hw_4k_set_txpower()
696 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, in ath9k_hw_4k_set_txpower()
703 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, in ath9k_hw_4k_set_txpower()
708 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, in ath9k_hw_4k_set_txpower()
715 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, in ath9k_hw_4k_set_txpower()
720 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, in ath9k_hw_4k_set_txpower()
728 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, in ath9k_hw_4k_set_txpower()
737 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, in ath9k_hw_4k_set_txpower()
[all …]
Dar9003_eeprom.c3693 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_ant_ctrl_apply()
3704 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); in ar9003_hw_ant_ctrl_apply()
3721 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_ant_ctrl_apply()
3745 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg); in ar9003_hw_drive_strength_apply()
3758 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg); in ar9003_hw_drive_strength_apply()
3765 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg); in ar9003_hw_drive_strength_apply()
3876 REG_WRITE(ah, pmu_reg, pmu_set); in is_pmu_set()
3894 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); in ar9003_hw_internal_regulator_apply()
3917 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set); in ar9003_hw_internal_regulator_apply()
3923 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); in ar9003_hw_internal_regulator_apply()
[all …]
Dar9003_hw.c1025 REG_WRITE(ah, 0x570c, val); in ar9003_hw_configpcipowersave()
1033 REG_WRITE(ah, AR_WA, ah->WARegVal); in ar9003_hw_configpcipowersave()
1044 REG_WRITE(ah, in ar9003_hw_configpcipowersave()
Deeprom.c21 REG_WRITE(ah, reg, val); in ath9k_hw_analog_shift_regwrite()
Dar9003_paprd.c769 REG_WRITE(ah, reg, paprd_table_val[i]); in ar9003_paprd_populate_single_table()
Dhtc_drv_init.c499 REG_WRITE(ah, reg_offset, val); in ath9k_reg_rmw()
Dhw.h79 #define REG_WRITE(_ah, _reg, _val) \ macro
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/
Dmarb_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
284 REG_WRITE( reg_##scope##_##reg, \
297 REG_WRITE( reg_##scope##_##reg, \
309 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
320 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dstrcop_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dirq_nmi_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dconfig_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dreg_rdwr.h12 #ifndef REG_WRITE
13 #define REG_WRITE(type, addr, val) \ macro
Drt_trace_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dmarb_bp_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Data_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dbif_slave_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dbif_core_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dser_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Deth_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dsser_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Ddma_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dextmem_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dbif_dma_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
Dmarb_bar_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
306 REG_WRITE( reg_##scope##_##reg, \
319 REG_WRITE( reg_##scope##_##reg, \
331 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
342 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dstrmux_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dl2cache_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dclkgen_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dmarb_foo_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
432 REG_WRITE( reg_##scope##_##reg, \
445 REG_WRITE( reg_##scope##_##reg, \
457 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
468 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dtimer_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dddr2_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dpinmux_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dpio_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dintr_vect_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dgio_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
/linux-4.1.27/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
Dmarb_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
284 REG_WRITE( reg_##scope##_##reg, \
297 REG_WRITE( reg_##scope##_##reg, \
309 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
320 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dstrmux_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dconfig_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dmarb_bp_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dtimer_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dbif_slave_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dintr_vect_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dgio_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dbif_core_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dpinmux_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Dbif_dma_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
Diop_version_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_sap_in_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_sap_out_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_sw_spu_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_sw_cpu_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_sw_mpu_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_sw_cfg_defs.h22 REG_WRITE( reg_##scope##_##reg, \
35 REG_WRITE( reg_##scope##_##reg, \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/iop/
Diop_version_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_scrc_out_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_scrc_in_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_fifo_in_extra_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_fifo_out_extra_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_trigger_grp_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_mpu_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_sap_in_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_crc_par_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_fifo_in_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_timer_grp_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_fifo_out_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_dmc_out_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_sap_out_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_dmc_in_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_spu_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_sw_spu_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_sw_cpu_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_sw_mpu_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
Diop_sw_cfg_defs.h25 REG_WRITE( reg_##scope##_##reg, \
38 REG_WRITE( reg_##scope##_##reg, \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
/linux-4.1.27/drivers/net/wireless/cw1200/
Dfwio.c83 #define REG_WRITE(reg, val) \ in cw1200_load_firmware_cw1200() macro
135 REG_WRITE(ST90TDS_SRAM_BASE_ADDR_REG_ID, 0xFFF20000); in cw1200_load_firmware_cw1200()
136 REG_WRITE(ST90TDS_AHB_DPORT_REG_ID, 0xEAFFFFFE); in cw1200_load_firmware_cw1200()
141 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32); in cw1200_load_firmware_cw1200()
145 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32); in cw1200_load_firmware_cw1200()
263 #undef REG_WRITE in cw1200_load_firmware_cw1200()
/linux-4.1.27/arch/x86/mm/
Dpf_in.h29 REG_WRITE, /* write from reg to addr */ enumerator
Dmmio-mod.c185 case REG_WRITE: in pre()
Dpf_in.c156 CHECK_OP_TYPE(opcode, reg_wop, REG_WRITE); in get_ins_type()
/linux-4.1.27/drivers/media/usb/dvb-usb-v2/
Dce6230.h47 REG_WRITE = 0xcf, /* wr f */ enumerator
Dce6230.c48 case REG_WRITE: in ce6230_ctrl_msg()
/linux-4.1.27/arch/cris/arch-v32/mach-fs/
Dpinmux.c188 REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_gio + 8 * port, in crisv32_pinmux_set()
190 REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_iop + 8 * port, in crisv32_pinmux_set()
/linux-4.1.27/drivers/leds/
Dleds-dac124s085.c36 #define REG_WRITE (0 << 12) macro
/linux-4.1.27/arch/cris/arch-v32/mach-a3/
Dpinmux.c228 REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_gio_pa + 4 * port, in crisv32_pinmux_set()
230 REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_iop_pa + 4 * port, in crisv32_pinmux_set()
/linux-4.1.27/arch/cris/arch-v32/drivers/mach-a3/
Dgpio.c835 REG_WRITE(reg_gio_rw_pwm0_ctrl, REG_ADDR(gio, regi_gio, rw_pwm0_ctrl) + in gpio_pwm_set_mode()
851 REG_WRITE(reg_gio_rw_pwm0_var, REG_ADDR(gio, regi_gio, rw_pwm0_var) + in gpio_pwm_set_period()
866 REG_WRITE(reg_gio_rw_pwm0_data, REG_ADDR(gio, regi_gio, rw_pwm0_data) + in gpio_pwm_set_duty()