73 		REG_WRITE(ah, INI_RA(array, r, 0), data[r]);  in ar5008_write_bank6()
218 			REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,  in ar5008_hw_set_channel()
221 			REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,  in ar5008_hw_set_channel()
250 	REG_WRITE(ah, AR_PHY(0x37), reg32);  in ar5008_hw_set_channel()
318 	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);  in ar5008_hw_spur_mitigate()
325 	REG_WRITE(ah, AR_PHY_SPUR_REG, new);  in ar5008_hw_spur_mitigate()
336 	REG_WRITE(ah, AR_PHY_TIMING11, new);  in ar5008_hw_spur_mitigate()
354 		REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);  in ar5008_hw_spur_mitigate()
355 		REG_WRITE(ah, chan_mask_reg[i], chan_mask);  in ar5008_hw_spur_mitigate()
388 	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);  in ar5008_hw_spur_mitigate()
389 	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);  in ar5008_hw_spur_mitigate()
399 	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);  in ar5008_hw_spur_mitigate()
400 	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);  in ar5008_hw_spur_mitigate()
410 	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);  in ar5008_hw_spur_mitigate()
411 	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);  in ar5008_hw_spur_mitigate()
421 	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);  in ar5008_hw_spur_mitigate()
422 	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);  in ar5008_hw_spur_mitigate()
432 	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);  in ar5008_hw_spur_mitigate()
433 	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);  in ar5008_hw_spur_mitigate()
443 	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);  in ar5008_hw_spur_mitigate()
444 	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);  in ar5008_hw_spur_mitigate()
454 	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);  in ar5008_hw_spur_mitigate()
455 	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);  in ar5008_hw_spur_mitigate()
465 	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);  in ar5008_hw_spur_mitigate()
466 	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);  in ar5008_hw_spur_mitigate()
563 	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);  in ar5008_hw_init_bb()
582 			REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);  in ar5008_hw_init_chain_masks()
583 			REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);  in ar5008_hw_init_chain_masks()
590 		REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);  in ar5008_hw_init_chain_masks()
591 		REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);  in ar5008_hw_init_chain_masks()
598 	REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);  in ar5008_hw_init_chain_masks()
607 		REG_WRITE(ah, AR_PHY_ANALOG_SWAP,  in ar5008_hw_init_chain_masks()
642 		REG_WRITE(ah, AR_PCU_MISC_MODE2, val);  in ar5008_hw_override_ini()
651 	REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);  in ar5008_hw_override_ini()
660 		REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);  in ar5008_hw_override_ini()
685 	REG_WRITE(ah, AR_PHY_TURBO, phymode);  in ar5008_hw_set_channel_regs()
691 	REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);  in ar5008_hw_set_channel_regs()
692 	REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);  in ar5008_hw_set_channel_regs()
717 	REG_WRITE(ah, AR_PHY(0), 0x00000007);  in ar5008_hw_process_ini()
720 	REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);  in ar5008_hw_process_ini()
725 	REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);  in ar5008_hw_process_ini()
736 		REG_WRITE(ah, reg, val);  in ar5008_hw_process_ini()
768 		REG_WRITE(ah, reg, val);  in ar5008_hw_process_ini()
821 	REG_WRITE(ah, AR_PHY_MODE, rfMode);  in ar5008_hw_set_rfmode()
826 	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);  in ar5008_hw_mark_phy_inactive()
865 	REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);  in ar5008_hw_rfbus_req()
876 	REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);  in ar5008_hw_rfbus_done()
884 		REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);  in ar5008_restore_chainmask()
885 		REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);  in ar5008_restore_chainmask()
1232 	REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);  in ar5008_hw_set_radar_params()
1233 	REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);  in ar5008_hw_set_radar_params()