Lines Matching refs:REG_WRITE
118 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
324 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
325 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
327 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ath9k_hw_disablepcie()
354 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
365 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
374 REG_WRITE(ah, regAddr[i], regHold[i]); in ath9k_hw_chip_test()
604 REG_WRITE(ah, AR_WA, ah->WARegVal); in __ath9k_hw_init()
706 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); in ath9k_hw_init_qos()
707 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); in ath9k_hw_init_qos()
709 REG_WRITE(ah, AR_QOS_NO_ACK, in ath9k_hw_init_qos()
714 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); in ath9k_hw_init_qos()
715 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); in ath9k_hw_init_qos()
716 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); in ath9k_hw_init_qos()
717 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); in ath9k_hw_init_qos()
718 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); in ath9k_hw_init_qos()
799 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); in ath9k_hw_init_pll()
805 REG_WRITE(ah, AR_RTC_PLL_CONTROL, in ath9k_hw_init_pll()
810 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); in ath9k_hw_init_pll()
823 REG_WRITE(ah, AR_RTC_PLL_CONTROL, in ath9k_hw_init_pll()
859 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
862 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | in ath9k_hw_init_pll()
888 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
891 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
894 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
902 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ath9k_hw_init_pll()
911 REG_WRITE(ah, 0x50040, 0x304); in ath9k_hw_init_pll()
916 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); in ath9k_hw_init_pll()
954 REG_WRITE(ah, AR_IMR, imr_reg); in ath9k_hw_init_interrupt_masks()
956 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_init_interrupt_masks()
959 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); in ath9k_hw_init_interrupt_masks()
960 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); in ath9k_hw_init_interrupt_masks()
961 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
967 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
968 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
969 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
970 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
978 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); in ath9k_hw_set_sifs_time()
985 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); in ath9k_hw_setslottime()
1114 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); in ath9k_hw_init_global_settings()
1193 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); in ath9k_hw_set_dma()
1221 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); in ath9k_hw_set_dma()
1306 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_ar9330_reset_war()
1326 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset()
1330 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset()
1346 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); in ath9k_hw_set_reset()
1351 REG_WRITE(ah, AR_RC, val); in ath9k_hw_set_reset()
1354 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset()
1369 REG_WRITE(ah, AR_RTC_RC, rst_flags); in ath9k_hw_set_reset()
1380 REG_WRITE(ah, AR_RTC_RC, 0); in ath9k_hw_set_reset()
1387 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset()
1400 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_power_on()
1404 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset_power_on()
1408 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset_power_on()
1410 REG_WRITE(ah, AR_RTC_RESET, 0); in ath9k_hw_set_reset_power_on()
1417 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset_power_on()
1419 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_set_reset_power_on()
1438 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_reg()
1442 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_reset_reg()
1586 REG_WRITE(ah, AR_NAV, 0); in ath9k_hw_check_nav()
1666 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); in ath9k_hw_reset_opmode()
1668 REG_WRITE(ah, AR_ISR, ~0); in ath9k_hw_reset_opmode()
1669 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); in ath9k_hw_reset_opmode()
1683 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); in ath9k_hw_init_queues()
1707 REG_WRITE(ah, AR_CFG, mask); in ath9k_hw_init_desc()
1715 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); in ath9k_hw_init_desc()
1717 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1725 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1879 REG_WRITE(ah, in ath9k_hw_reset()
1893 REG_WRITE(ah, in ath9k_hw_reset()
1967 REG_WRITE(ah, AR_OBS, 8); in ath9k_hw_reset()
1996 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); in ath9k_hw_reset()
2053 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); in ath9k_set_power_sleep()
2067 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); in ath9k_set_power_sleep()
2077 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_sleep()
2093 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_set_power_network_sleep()
2121 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_network_sleep()
2131 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_power_awake()
2243 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); in ath9k_hw_beaconinit()
2244 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - in ath9k_hw_beaconinit()
2246 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - in ath9k_hw_beaconinit()
2258 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2259 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2260 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2277 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); in ath9k_hw_set_sta_beacon_timers()
2278 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2279 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2307 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2308 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2310 REG_WRITE(ah, AR_SLEEP1, in ath9k_hw_set_sta_beacon_timers()
2319 REG_WRITE(ah, AR_SLEEP2, in ath9k_hw_set_sta_beacon_timers()
2322 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); in ath9k_hw_set_sta_beacon_timers()
2323 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); in ath9k_hw_set_sta_beacon_timers()
2332 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); in ath9k_hw_set_sta_beacon_timers()
2627 REG_WRITE(ah, addr, tmp); in ath9k_hw_gpio_cfg_output_mux()
2734 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); in ath9k_hw_setantenna()
2765 REG_WRITE(ah, AR_RX_FILTER, bits); in ath9k_hw_setrxfilter()
2772 REG_WRITE(ah, AR_PHY_ERR, phybits); in ath9k_hw_setrxfilter()
2872 REG_WRITE(ah, AR_MCAST_FIL0, filter0); in ath9k_hw_setmcastfilter()
2873 REG_WRITE(ah, AR_MCAST_FIL1, filter1); in ath9k_hw_setmcastfilter()
2881 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); in ath9k_hw_write_associd()
2882 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | in ath9k_hw_write_associd()
2911 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); in ath9k_hw_settsf64()
2912 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); in ath9k_hw_settsf64()
2923 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); in ath9k_hw_reset_tsf()
2945 REG_WRITE(ah, AR_2040_MODE, macmode); in ath9k_hw_set11nmac2040()
3045 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, in ath9k_hw_gen_timer_start()
3047 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, in ath9k_hw_gen_timer_start()