101 				REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,  in ar9002_hw_set_channel()
104 				REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,  in ar9002_hw_set_channel()
152 	REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);  in ar9002_hw_set_channel()
249 	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);  in ar9002_hw_spur_mitigate()
256 	REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);  in ar9002_hw_spur_mitigate()
286 	REG_WRITE(ah, AR_PHY_TIMING11, newVal);  in ar9002_hw_spur_mitigate()
289 	REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);  in ar9002_hw_spur_mitigate()
307 		REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);  in ar9002_hw_spur_mitigate()
308 		REG_WRITE(ah, chan_mask_reg[i], chan_mask);  in ar9002_hw_spur_mitigate()
341 	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);  in ar9002_hw_spur_mitigate()
342 	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);  in ar9002_hw_spur_mitigate()
352 	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);  in ar9002_hw_spur_mitigate()
353 	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);  in ar9002_hw_spur_mitigate()
363 	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);  in ar9002_hw_spur_mitigate()
364 	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);  in ar9002_hw_spur_mitigate()
374 	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);  in ar9002_hw_spur_mitigate()
375 	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);  in ar9002_hw_spur_mitigate()
385 	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);  in ar9002_hw_spur_mitigate()
386 	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);  in ar9002_hw_spur_mitigate()
396 	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);  in ar9002_hw_spur_mitigate()
397 	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);  in ar9002_hw_spur_mitigate()
407 	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);  in ar9002_hw_spur_mitigate()
408 	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);  in ar9002_hw_spur_mitigate()
418 	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);  in ar9002_hw_spur_mitigate()
419 	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);  in ar9002_hw_spur_mitigate()
555 	REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);  in ar9002_hw_antdiv_comb_conf_set()
574 		REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);  in ar9002_hw_set_bt_ant_diversity()
576 		REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM);  in ar9002_hw_set_bt_ant_diversity()
589 		REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);  in ar9002_hw_set_bt_ant_diversity()
595 		REG_WRITE(ah, AR_PHY_SWITCH_COM, 0);  in ar9002_hw_set_bt_ant_diversity()
611 	REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);  in ar9002_hw_set_bt_ant_diversity()
616 	REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);  in ar9002_hw_set_bt_ant_diversity()
690 	REG_WRITE(ah, AR_CR, AR_CR_RXD);  in ar9002_hw_tx99_start()
691 	REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);  in ar9002_hw_tx99_start()
692 	REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20);  in ar9002_hw_tx99_start()
693 	REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);  in ar9002_hw_tx99_start()
694 	REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum);  in ar9002_hw_tx99_start()
695 	REG_WRITE(ah, AR_TIME_OUT, 0x00000400);  in ar9002_hw_tx99_start()
696 	REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);  in ar9002_hw_tx99_start()