Searched refs:REG_RD (Results 1 - 107 of 107) sorted by relevance

/linux-4.1.27/arch/cris/arch-v32/lib/
H A Ddelay.c24 u32 t0 = REG_RD(timer, regi_timer0, r_time); cris_delay10ns()
25 while (REG_RD(timer, regi_timer0, r_time) - t0 < n10ns) cris_delay10ns()
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/
H A Ddma.h76 do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
82 do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
88 do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
94 do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
101 do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \
H A Dirq_nmi_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dstrcop_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dconfig_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Drt_trace_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Data_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dbif_slave_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dmarb_bp_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dmarb_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
276 #ifndef REG_RD
277 #define REG_RD( scope, inst, reg ) \ macro
H A Dbif_core_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Deth_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dextmem_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dser_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dsser_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dbif_dma_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Ddma_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
/linux-4.1.27/drivers/cpufreq/
H A Dcris-artpec3-cpufreq.c26 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); cris_freq_get_cpu_frequency()
33 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); cris_freq_target()
81 REG_RD(ddr2, regi_ddr2_ctrl, rw_cfg); cris_sdram_freq_notifier()
H A Dcris-etraxfs-cpufreq.c26 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl); cris_freq_get_cpu_frequency()
33 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl); cris_freq_target()
81 REG_RD(bif_core, regi_bif_core, rw_sdram_timing); cris_sdram_freq_notifier()
/linux-4.1.27/arch/cris/include/arch-v32/arch/
H A Dtimex.h21 ((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100)
/linux-4.1.27/arch/cris/boot/compressed/
H A Dmisc.c134 rs = REG_RD(ser, regi_ser, rs_stat_din); serout()
243 xoff = REG_RD(ser, regi_ser, rw_xoff); serial_setup()
251 tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl); serial_setup()
252 rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl); serial_setup()
253 tr_baud = REG_RD(ser, regi_ser, rw_tr_baud_div); serial_setup()
254 rec_baud = REG_RD(ser, regi_ser, rw_rec_baud_div); serial_setup()
295 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); decompress_kernel()
301 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); decompress_kernel()
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
H A Diop_version_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_sap_in_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_sap_out_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_sw_spu_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_sw_cfg_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_sw_cpu_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_sw_mpu_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
/linux-4.1.27/arch/cris/arch-v32/mach-a3/
H A Darbiter.c527 REG_RD(marb_foo, regi_marb_foo, r_masked_intr); crisv32_foo_arbiter_irq()
540 masked_intr = REG_RD(marb_foo, regi_marb_foo, r_masked_intr); crisv32_foo_arbiter_irq()
554 r_clients = REG_RD(marb_foo_bp, watch->instance, r_brk_clients); crisv32_foo_arbiter_irq()
555 r_addr = REG_RD(marb_foo_bp, watch->instance, r_brk_addr); crisv32_foo_arbiter_irq()
556 r_op = REG_RD(marb_foo_bp, watch->instance, r_brk_op); crisv32_foo_arbiter_irq()
557 r_first = REG_RD(marb_foo_bp, watch->instance, r_brk_first_client); crisv32_foo_arbiter_irq()
558 r_size = REG_RD(marb_foo_bp, watch->instance, r_brk_size); crisv32_foo_arbiter_irq()
583 REG_RD(marb_bar, regi_marb_bar, r_masked_intr); crisv32_bar_arbiter_irq()
596 masked_intr = REG_RD(marb_bar, regi_marb_bar, r_masked_intr); crisv32_bar_arbiter_irq()
610 r_clients = REG_RD(marb_bar_bp, watch->instance, r_brk_clients); crisv32_bar_arbiter_irq()
611 r_addr = REG_RD(marb_bar_bp, watch->instance, r_brk_addr); crisv32_bar_arbiter_irq()
612 r_op = REG_RD(marb_bar_bp, watch->instance, r_brk_op); crisv32_bar_arbiter_irq()
613 r_first = REG_RD(marb_bar_bp, watch->instance, r_brk_first_client); crisv32_bar_arbiter_irq()
614 r_size = REG_RD(marb_bar_bp, watch->instance, r_brk_size); crisv32_bar_arbiter_irq()
H A Ddma.c47 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); crisv32_request_dma()
48 strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg); crisv32_request_dma()
H A Dpinmux.c98 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); crisv32_pinmux_alloc_fixed()
99 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); crisv32_pinmux_alloc_fixed()
275 hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); crisv32_pinmux_dealloc_fixed()
/linux-4.1.27/drivers/tty/serial/
H A Detraxfs-uart.c63 tr_dma_en = old = REG_RD(ser, up->regi_ser, rw_tr_dma_en); cris_console_write()
74 stat = REG_RD(ser, up->regi_ser, r_stat_din); cris_console_write()
80 stat = REG_RD(ser, up->regi_ser, r_stat_din); cris_console_write()
152 reg_ser_r_stat_din rstat = REG_RD(ser, regi_ser, r_stat_din); crisv32_serial_get_rts()
170 rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl); crisv32_serial_set_rts()
183 reg_ser_r_stat_din rstat = REG_RD(ser, regi_ser, r_stat_din); crisv32_serial_get_cts()
219 prev_tr_ctrl = tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl); etraxfs_uart_send_xchar()
220 rstat = REG_RD(ser, regi_ser, r_stat_din); etraxfs_uart_send_xchar()
243 rstat = REG_RD(ser, up->regi_ser, r_stat_din); etraxfs_uart_send_xchar()
254 tr_dma_en = REG_RD(ser, regi_ser, rw_tr_dma_en); etraxfs_uart_send_xchar()
300 tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl); etraxfs_uart_start_tx_bottom()
303 intr_mask = REG_RD(ser, regi_ser, rw_intr_mask); etraxfs_uart_start_tx_bottom()
333 intr_mask = REG_RD(ser, regi_ser, rw_intr_mask); etraxfs_uart_stop_tx()
337 tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl); etraxfs_uart_stop_tx()
370 reg_ser_rw_rec_ctrl rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl); etraxfs_uart_stop_rx()
393 rstat = REG_RD(ser, up->regi_ser, r_stat_din); etraxfs_uart_tx_empty()
449 tr_ctrl = REG_RD(ser, up->regi_ser, rw_tr_ctrl); etraxfs_uart_break_ctl()
450 tr_dma_en = REG_RD(ser, up->regi_ser, rw_tr_dma_en); etraxfs_uart_break_ctl()
451 intr_mask = REG_RD(ser, up->regi_ser, rw_intr_mask); etraxfs_uart_break_ctl()
497 intr_mask = REG_RD(ser, regi_ser, rw_intr_mask); transmit_chars_no_dma()
517 rstat = REG_RD(ser, regi_ser, r_stat_din); transmit_chars_no_dma()
534 rstat = REG_RD(ser, up->regi_ser, r_stat_din); receive_chars_no_dma()
539 stat_din = REG_RD(ser, up->regi_ser, rs_stat_din); receive_chars_no_dma()
570 rstat = REG_RD(ser, up->regi_ser, r_stat_din); receive_chars_no_dma()
591 masked_intr = REG_RD(ser, regi_ser, r_masked_intr); ser_interrupt()
620 stat = REG_RD(ser, up->regi_ser, rs_stat_din); etraxfs_uart_get_poll_char()
637 stat = REG_RD(ser, up->regi_ser, r_stat_din); etraxfs_uart_put_poll_char()
813 xoff = REG_RD(ser, up->regi_ser, rw_xoff); etraxfs_uart_set_termios()
/linux-4.1.27/arch/cris/arch-v32/kernel/
H A Ddebugport.c166 stat = REG_RD(ser, kgdb_port->instance, rs_stat_din); getDebugChar()
181 stat = REG_RD(ser, kgdb_port->instance, r_stat_din); putDebugChar()
192 stat = REG_RD(ser, port->instance, r_stat_din); early_putch()
H A Dtime.c64 data = REG_RD(timer, regi_timer0, r_tmr0_data); get_ns_in_jiffie()
152 REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); handle_watchdog_bite()
213 intr = REG_RD(timer, timer_base, r_masked_intr); crisv32_timer_interrupt()
248 return REG_RD(timer, timer_base, r_time); crisv32_timer_sched_clock()
261 timer_intr_mask = REG_RD(timer, timer_base, rw_intr_mask); crisv32_timer_init()
335 data = REG_RD(timer, timer_regs[freqs->cpu], cris_time_freq_notifier()
H A Dfasttimer.c139 r_time0 = REG_RD(timer, regi_timer0, r_time); start_timer_trig()
144 intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask); start_timer_trig()
165 r_time1 = REG_RD(timer, regi_timer0, r_time); start_timer_trig()
170 intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask); start_timer_trig()
312 masked_intr = REG_RD(timer, regi_timer0, r_masked_intr); timer_trig_interrupt()
337 intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask); timer_trig_handler()
H A Dtraps.c125 r = REG_RD(intr_vect, regi_irq, r_nmi); handle_nmi()
H A Dkgdb.c1549 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); kgdb_init()
1553 ser_intr_mask = REG_RD(ser, regi_ser0, rw_intr_mask); kgdb_init()
1561 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); kgdb_init()
1565 ser_intr_mask = REG_RD(ser, regi_ser1, rw_intr_mask); kgdb_init()
1573 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); kgdb_init()
1577 ser_intr_mask = REG_RD(ser, regi_ser2, rw_intr_mask); kgdb_init()
1585 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); kgdb_init()
1589 ser_intr_mask = REG_RD(ser, regi_ser3, rw_intr_mask); kgdb_init()
/linux-4.1.27/arch/cris/arch-v32/drivers/mach-fs/
H A Dnandflash.c60 dout = REG_RD(gio, regi_gio, rw_pa_dout); crisv32_hwcontrol()
93 reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din); crisv32_device_ready()
105 reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, crisv32_nand_flash_probe()
107 reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe); crisv32_nand_flash_probe()
H A Dgpio.c197 REG_RD(gio, regi_gio, r_pa_din)); gpio_poll()
201 intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg); gpio_poll()
309 masked_intr = REG_RD(gio, regi_gio, r_masked_intr); gpio_pa_interrupt()
333 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask); gpio_pa_interrupt()
891 intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg); virtual_gpio_init()
892 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask); virtual_gpio_init()
/linux-4.1.27/arch/cris/arch-v32/mach-fs/
H A Darbiter.c282 REG_RD(marb, regi_marb, rw_intr_mask); crisv32_arbiter_watch()
319 reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask); crisv32_arbiter_unwatch()
352 REG_RD(marb, regi_marb, r_masked_intr); crisv32_arbiter_irq()
381 r_clients = REG_RD(marb_bp, watch->instance, r_brk_clients); crisv32_arbiter_irq()
382 r_addr = REG_RD(marb_bp, watch->instance, r_brk_addr); crisv32_arbiter_irq()
383 r_op = REG_RD(marb_bp, watch->instance, r_brk_op); crisv32_arbiter_irq()
384 r_first = REG_RD(marb_bp, watch->instance, r_brk_first_client); crisv32_arbiter_irq()
385 r_size = REG_RD(marb_bp, watch->instance, r_brk_size); crisv32_arbiter_irq()
H A Ddma.c49 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl); crisv32_request_dma()
50 strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg); crisv32_request_dma()
H A Dpinmux.c56 reg_pinmux_rw_pa pa = REG_RD(pinmux, regi_pinmux, rw_pa); crisv32_pinmux_init()
104 reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); crisv32_pinmux_alloc_fixed()
238 reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); crisv32_pinmux_dealloc_fixed()
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/iop/
H A Diop_version_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_fifo_in_extra_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_fifo_out_extra_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_scrc_in_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_scrc_out_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_trigger_grp_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_crc_par_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_fifo_in_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_mpu_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_sap_in_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_timer_grp_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_dmc_in_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_dmc_out_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_fifo_out_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_sap_out_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_spu_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_sw_spu_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_sw_cfg_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_sw_cpu_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Diop_sw_mpu_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
H A Dstrmux_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Dclkgen_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Dl2cache_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Dmarb_bar_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
298 #ifndef REG_RD
299 #define REG_RD( scope, inst, reg ) \ macro
H A Dmarb_foo_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
424 #ifndef REG_RD
425 #define REG_RD( scope, inst, reg ) \ macro
H A Dddr2_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Dintr_vect_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Dpinmux_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Dpio_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Dtimer_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
H A Dgio_defs.h14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \ macro
/linux-4.1.27/arch/cris/arch-v32/drivers/
H A Diop_fw_load.c41 mpu_stat = REG_RD(iop_mpu, regi_iop_mpu, r_stat); wait_mpu_idle()
99 mc_stat = REG_RD(iop_sw_cpu, regi_iop_sw_cpu, r_mc_stat); iop_fw_load_spu()
122 (void) REG_RD(iop_sw_cpu, regi_iop_sw_cpu, rs_mc_data); iop_fw_load_spu()
H A Dsync_serial.c313 reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); sync_serial_start_port()
315 REG_RD(sser, port->regi_sser, rw_tr_cfg); sync_serial_start_port()
317 REG_RD(sser, port->regi_sser, rw_rec_cfg); sync_serial_start_port()
760 tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); sync_serial_ioctl_unlocked()
761 rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg); sync_serial_ioctl_unlocked()
762 frm_cfg = REG_RD(sser, port->regi_sser, rw_frm_cfg); sync_serial_ioctl_unlocked()
763 gen_cfg = REG_RD(sser, port->regi_sser, rw_cfg); sync_serial_ioctl_unlocked()
764 intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); sync_serial_ioctl_unlocked()
1143 reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); sync_serial_write()
1145 REG_RD(sser, port->regi_sser, rw_rec_cfg); sync_serial_write()
1168 intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); sync_serial_write()
1205 reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); send_word()
1276 reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, start_dma_out()
1344 masked = REG_RD(dma, port->regi_dmaout, r_masked_intr); tr_interrupt()
1351 stat = REG_RD(dma, port->regi_dmaout, rw_stat); tr_interrupt()
1421 tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); tr_interrupt()
1502 masked = REG_RD(dma, port->regi_dmain, r_masked_intr); rx_interrupt()
1509 while (REG_RD(dma, port->regi_dmain, rw_data) != rx_interrupt()
1531 masked = REG_RD(sser, port->regi_sser, r_masked_intr); manual_interrupt()
1535 REG_RD(sser, port->regi_sser, rw_rec_cfg); manual_interrupt()
1536 reg_sser_r_rec_data data = REG_RD(sser, manual_interrupt()
1590 intr_mask = REG_RD(sser, port->regi_sser, manual_interrupt()
H A Dcryptocop.c2081 dma_out_cfg = REG_RD(dma, OUT_DMA_INST, rw_cfg); cryptocop_job_queue_close()
2085 dma_in_cfg = REG_RD(dma, IN_DMA_INST, rw_cfg); cryptocop_job_queue_close()
2090 rw_cfg = REG_RD(strcop, regi_strcop, rw_cfg); cryptocop_job_queue_close()
/linux-4.1.27/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
H A Dconfig_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dstrmux_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dbif_slave_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dintr_vect_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dmarb_bp_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dmarb_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
276 #ifndef REG_RD
277 #define REG_RD( scope, inst, reg ) \ macro
H A Dbif_core_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dgio_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dpinmux_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dtimer_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
H A Dbif_dma_defs.h17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \ macro
/linux-4.1.27/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_main.c614 data[i] = REG_RD(bp, src_addr + i*4); bnx2x_read_dmae()
722 regs[j] = REG_RD(bp, bar_storm_intmem[storm] + bnx2x_mc_assert()
771 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); bnx2x_fw_dump_lvl()
772 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) bnx2x_fw_dump_lvl()
792 mark = REG_RD(bp, addr); bnx2x_fw_dump_lvl()
800 mark = REG_RD(bp, addr); bnx2x_fw_dump_lvl()
813 data[word] = htonl(REG_RD(bp, offset + 4*word)); bnx2x_fw_dump_lvl()
821 data[word] = htonl(REG_RD(bp, offset + 4*word)); bnx2x_fw_dump_lvl()
837 u32 val = REG_RD(bp, addr); bnx2x_hc_int_disable()
867 if (REG_RD(bp, addr) != val) bnx2x_hc_int_disable()
873 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); bnx2x_igu_int_disable()
885 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) bnx2x_igu_int_disable()
941 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset + bnx2x_panic_dump()
1038 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1210 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); bnx2x_pbf_pN_buf_flushed()
1211 crd = crd_start = REG_RD(bp, regs->crd); bnx2x_pbf_pN_buf_flushed()
1212 init_crd = REG_RD(bp, regs->init_crd); bnx2x_pbf_pN_buf_flushed()
1222 crd = REG_RD(bp, regs->crd); bnx2x_pbf_pN_buf_flushed()
1223 crd_freed = REG_RD(bp, regs->crd_freed); bnx2x_pbf_pN_buf_flushed()
1245 occup = to_free = REG_RD(bp, regs->lines_occup); bnx2x_pbf_pN_cmd_flushed()
1246 freed = freed_start = REG_RD(bp, regs->lines_freed); bnx2x_pbf_pN_cmd_flushed()
1254 occup = REG_RD(bp, regs->lines_occup); bnx2x_pbf_pN_cmd_flushed()
1255 freed = REG_RD(bp, regs->lines_freed); bnx2x_pbf_pN_cmd_flushed()
1276 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) bnx2x_flr_clnup_reg_poll()
1386 if (REG_RD(bp, comp_addr)) { bnx2x_send_final_clnup()
1402 (REG_RD(bp, comp_addr))); bnx2x_send_final_clnup()
1471 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); bnx2x_hw_enable_status()
1474 val = REG_RD(bp, PBF_REG_DISABLE_PF); bnx2x_hw_enable_status()
1477 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); bnx2x_hw_enable_status()
1480 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); bnx2x_hw_enable_status()
1483 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); bnx2x_hw_enable_status()
1486 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); bnx2x_hw_enable_status()
1489 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); bnx2x_hw_enable_status()
1492 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); bnx2x_hw_enable_status()
1545 u32 val = REG_RD(bp, addr); bnx2x_hc_int_enable()
1617 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); bnx2x_igu_int_enable()
1740 lock_status = REG_RD(bp, hw_lock_control_reg); bnx2x_trylock_hw_lock()
2004 lock_status = REG_RD(bp, hw_lock_control_reg); bnx2x_acquire_hw_lock()
2015 lock_status = REG_RD(bp, hw_lock_control_reg); bnx2x_acquire_hw_lock()
2052 lock_status = REG_RD(bp, hw_lock_control_reg); bnx2x_release_hw_lock()
2066 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && bnx2x_get_gpio()
2067 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; bnx2x_get_gpio()
2080 gpio_reg = REG_RD(bp, MISC_REG_GPIO); bnx2x_get_gpio()
2094 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && bnx2x_set_gpio()
2095 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; bnx2x_set_gpio()
2108 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); bnx2x_set_gpio()
2156 gpio_reg = REG_RD(bp, MISC_REG_GPIO); bnx2x_set_mult_gpio()
2197 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && bnx2x_set_gpio_int()
2198 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; bnx2x_set_gpio_int()
2211 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); bnx2x_set_gpio_int()
2254 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); bnx2x_set_spio()
3920 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); bnx2x_acquire_alr()
3983 aeu_mask = REG_RD(bp, aeu_addr); bnx2x_attn_int_asserted()
4003 nig_mask = REG_RD(bp, nig_int_mask_addr); bnx2x_attn_int_asserted()
4076 igu_acked = REG_RD(bp, bnx2x_attn_int_asserted()
4126 val = REG_RD(bp, reg_offset); bnx2x_attn_int_deasserted0()
4145 val = REG_RD(bp, reg_offset); bnx2x_attn_int_deasserted0()
4161 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); bnx2x_attn_int_deasserted1()
4176 val = REG_RD(bp, reg_offset); bnx2x_attn_int_deasserted1()
4192 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); bnx2x_attn_int_deasserted2()
4200 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); bnx2x_attn_int_deasserted2()
4207 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); bnx2x_attn_int_deasserted2()
4220 val = REG_RD(bp, reg_offset); bnx2x_attn_int_deasserted2()
4319 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); bnx2x_attn_int_deasserted3()
4324 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); bnx2x_attn_int_deasserted3()
4364 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); bnx2x_set_reset_global()
4378 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); bnx2x_clear_reset_global()
4390 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); bnx2x_reset_is_global()
4407 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); bnx2x_set_reset_done()
4427 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); bnx2x_set_reset_in_progress()
4441 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); bnx2x_reset_is_done()
4463 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); bnx2x_set_pf_load()
4501 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); bnx2x_clear_pf_load()
4532 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); bnx2x_get_load_status()
4546 pr_cont(" [0x%08x] ", REG_RD(bp, reg)); _print_parity()
4974 attn.sig[0] = REG_RD(bp, bnx2x_chk_parity_attn()
4977 attn.sig[1] = REG_RD(bp, bnx2x_chk_parity_attn()
4980 attn.sig[2] = REG_RD(bp, bnx2x_chk_parity_attn()
4983 attn.sig[3] = REG_RD(bp, bnx2x_chk_parity_attn()
4989 attn.sig[3] &= ((REG_RD(bp, bnx2x_chk_parity_attn()
4996 attn.sig[4] = REG_RD(bp, bnx2x_chk_parity_attn()
5008 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); bnx2x_attn_int_deasserted4()
5032 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); bnx2x_attn_int_deasserted4()
5086 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); bnx2x_attn_int_deasserted()
5087 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); bnx2x_attn_int_deasserted()
5088 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); bnx2x_attn_int_deasserted()
5089 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); bnx2x_attn_int_deasserted()
5092 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); bnx2x_attn_int_deasserted()
5142 aeu_mask = REG_RD(bp, reg_addr); bnx2x_attn_int_deasserted()
6015 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); bnx2x_init_def_sb()
6023 bp->attn_group[index].sig[4] = REG_RD(bp, bnx2x_init_def_sb()
6502 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & bnx2x_post_irq_nic_init()
6673 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); bnx2x_int_mem_test()
6727 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); bnx2x_int_mem_test()
6737 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); bnx2x_int_mem_test()
6743 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); bnx2x_int_mem_test()
6744 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); bnx2x_int_mem_test()
6912 val = REG_RD(bp, MISC_REG_SPIO_INT); bnx2x_setup_fan_failure_detection()
6917 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); bnx2x_setup_fan_failure_detection()
6924 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); bnx2x_pf_disable()
7059 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); bnx2x_init_hw_common()
7064 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); bnx2x_init_hw_common()
7181 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); bnx2x_init_hw_common()
7413 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); bnx2x_init_hw_common()
7599 REG_RD(bp, reg) & bnx2x_init_hw_port()
7604 REG_RD(bp, reg) & bnx2x_init_hw_port()
7659 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); bnx2x_init_hw_port()
7663 val = REG_RD(bp, reg_addr); bnx2x_init_hw_port()
7721 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) bnx2x_igu_clear_sb_gen()
7724 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { bnx2x_igu_clear_sb_gen()
7786 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : bnx2x_reset_nic_mode()
7791 mac_en[i] = REG_RD(bp, port ? bnx2x_reset_nic_mode()
7908 val = REG_RD(bp, addr); bnx2x_init_hw_func()
8165 val = REG_RD(bp, main_mem_prty_clr); bnx2x_init_hw_func()
8180 REG_RD(bp, main_mem_prty_clr); bnx2x_init_hw_func()
8903 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8952 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); bnx2x_reset_port()
9359 val = REG_RD(bp, addr); bnx2x_disable_close_the_gate()
9363 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); bnx2x_disable_close_the_gate()
9386 val = REG_RD(bp, HC_REG_CONFIG_1); bnx2x_set_234_gates()
9391 val = REG_RD(bp, HC_REG_CONFIG_0); bnx2x_set_234_gates()
9397 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); bnx2x_set_234_gates()
9454 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); bnx2x_reset_mcp_prep()
9490 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); bnx2x_init_shmem()
9649 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); bnx2x_er_poll_igu_vq()
9675 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); bnx2x_process_kill()
9676 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); bnx2x_process_kill()
9677 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); bnx2x_process_kill()
9678 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); bnx2x_process_kill()
9679 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); bnx2x_process_kill()
9681 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); bnx2x_process_kill()
10171 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]); bnx2x_prev_unload_close_umac()
10187 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); bnx2x_prev_unload_close_mac()
10190 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); bnx2x_prev_unload_close_mac()
10206 wb_data[0] = REG_RD(bp, base_addr + offset); bnx2x_prev_unload_close_mac()
10207 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); bnx2x_prev_unload_close_mac()
10217 vals->emac_val = REG_RD(bp, vals->emac_addr); bnx2x_prev_unload_close_mac()
10224 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); bnx2x_prev_unload_close_mac()
10230 vals->xmac_val = REG_RD(bp, vals->xmac_addr); bnx2x_prev_unload_close_mac()
10261 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) & bnx2x_prev_is_after_undi()
10265 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) { bnx2x_prev_is_after_undi()
10283 tmp_reg = REG_RD(bp, addr); bnx2x_prev_unload_undi_inc()
10525 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); bnx2x_prev_unload_common()
10546 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); bnx2x_prev_unload_common()
10553 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); bnx2x_prev_unload_common()
10557 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); bnx2x_prev_unload_common()
10621 hw_lock_val = REG_RD(bp, hw_lock_reg); bnx2x_prev_unload()
10634 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { bnx2x_prev_unload()
10695 val = REG_RD(bp, MISC_REG_CHIP_NUM); bnx2x_get_common_hwinfo()
10697 val = REG_RD(bp, MISC_REG_CHIP_REV); bnx2x_get_common_hwinfo()
10703 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); bnx2x_get_common_hwinfo()
10705 val = REG_RD(bp, MISC_REG_BOND_ID); bnx2x_get_common_hwinfo()
10710 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { bnx2x_get_common_hwinfo()
10724 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); bnx2x_get_common_hwinfo()
10726 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); bnx2x_get_common_hwinfo()
10748 val = (REG_RD(bp, 0x2874) & 0x55); bnx2x_get_common_hwinfo()
10755 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); bnx2x_get_common_hwinfo()
10763 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? bnx2x_get_common_hwinfo()
10772 REG_RD(bp, bp->common.shmem2_base + bnx2x_get_common_hwinfo()
10900 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); bnx2x_get_igu_cam_info()
10979 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); bnx2x_link_settings_supported()
10983 bp->port.phy_addr = REG_RD( bnx2x_link_settings_supported()
10987 bp->port.phy_addr = REG_RD( bnx2x_link_settings_supported()
11665 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) { bnx2x_get_hwinfo()
11687 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); bnx2x_get_hwinfo()
11698 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { bnx2x_get_hwinfo()
11703 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { bnx2x_get_hwinfo()
14553 REG_RD(bp, pretend_reg); bnx2x_pretend_func()
14566 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : bnx2x_ptp_task()
14570 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB : bnx2x_ptp_task()
14573 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB : bnx2x_ptp_task()
14600 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB : bnx2x_set_rx_ts()
14603 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB : bnx2x_set_rx_ts()
H A Dbnx2x_link.c226 u32 val = REG_RD(bp, reg); bnx2x_bits_en()
235 u32 val = REG_RD(bp, reg); bnx2x_bits_dis()
258 REG_RD(bp, params->lfa_base + bnx2x_check_lfa()
273 link_status = REG_RD(bp, params->shmem_base + bnx2x_check_lfa()
302 saved_val = REG_RD(bp, params->lfa_base + bnx2x_check_lfa()
311 saved_val = REG_RD(bp, params->lfa_base + bnx2x_check_lfa()
320 saved_val = REG_RD(bp, params->lfa_base + bnx2x_check_lfa()
330 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + bnx2x_check_lfa()
343 REG_RD(bp, params->lfa_base + bnx2x_check_lfa()
353 eee_status = REG_RD(bp, params->shmem2_base + bnx2x_check_lfa()
384 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); bnx2x_get_epio()
387 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; bnx2x_get_epio()
401 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); bnx2x_set_epio()
410 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); bnx2x_set_epio()
1429 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); bnx2x_set_mdio_clk()
1466 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); bnx2x_is_4_port_mode()
1472 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); bnx2x_is_4_port_mode()
1493 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); bnx2x_emac_init()
1498 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); bnx2x_emac_init()
1539 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & bnx2x_set_umac_rxtx()
1542 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); bnx2x_set_umac_rxtx()
1667 (REG_RD(bp, MISC_REG_RESET_REG_2) & bnx2x_xmac_init()
1721 if (REG_RD(bp, MISC_REG_RESET_REG_2) & bnx2x_set_xmac_rxtx()
1727 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); bnx2x_set_xmac_rxtx()
1733 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); bnx2x_set_xmac_rxtx()
1876 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); bnx2x_emac_enable()
1905 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); bnx2x_emac_enable()
2144 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : bnx2x_update_pfc_nig()
2253 val = REG_RD(bp, MISC_REG_RESET_REG_2); bnx2x_update_pfc()
2455 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); bnx2x_set_bmac_rx()
2462 if (REG_RD(bp, MISC_REG_RESET_REG_2) & bnx2x_set_bmac_rx()
2488 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); bnx2x_pbf_update()
2489 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); bnx2x_pbf_update()
2494 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); bnx2x_pbf_update()
2497 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); bnx2x_pbf_update()
2569 if (REG_RD(bp, NIG_REG_PORT_SWAP)) bnx2x_get_emac_base()
2575 if (REG_RD(bp, NIG_REG_PORT_SWAP)) bnx2x_get_emac_base()
2604 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); bnx2x_cl22_write()
2617 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); bnx2x_cl22_write()
2640 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); bnx2x_cl22_read()
2653 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); bnx2x_cl22_read()
2681 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | bnx2x_cl45_read()
2682 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); bnx2x_cl45_read()
2698 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); bnx2x_cl45_read()
2719 val = REG_RD(bp, phy->mdio_ctrl + bnx2x_cl45_read()
2756 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | bnx2x_cl45_write()
2757 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); bnx2x_cl45_write()
2774 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); bnx2x_cl45_write()
2794 tmp = REG_RD(bp, phy->mdio_ctrl + bnx2x_cl45_write()
2828 if (REG_RD(bp, params->shmem2_base) <= bnx2x_eee_has_cap()
2893 eee_mode = ((REG_RD(bp, params->shmem_base + bnx2x_eee_calc_timer()
3070 board_cfg = REG_RD(bp, params->shmem_base + bnx2x_bsc_module_sel()
3078 sfp_ctrl = REG_RD(bp, params->shmem_base + bnx2x_bsc_module_sel()
3109 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); bnx2x_bsc_read()
3126 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); bnx2x_bsc_read()
3129 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); bnx2x_bsc_read()
3150 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); bnx2x_bsc_read()
3153 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); bnx2x_bsc_read()
3164 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); bnx2x_bsc_read()
3240 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); bnx2x_get_warpcore_lane()
3244 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); bnx2x_get_warpcore_lane()
3250 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); bnx2x_get_warpcore_lane()
3254 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); bnx2x_get_warpcore_lane()
3264 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); bnx2x_get_warpcore_lane()
3269 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); bnx2x_get_warpcore_lane()
3797 if (REG_RD(bp, params->shmem_base + bnx2x_warpcore_enable_AN_KR()
3837 wc_lane_config = REG_RD(bp, params->shmem_base + bnx2x_warpcore_enable_AN_KR()
3989 cfg_tap_val = REG_RD(bp, params->shmem_base + bnx2x_warpcore_set_10G_XFI()
4322 cfg_pin = (REG_RD(bp, shmem_base + bnx2x_get_mod_abs_int_cfg()
4399 serdes_net_if = (REG_RD(bp, params->shmem_base + bnx2x_warpcore_config_runtime()
4462 cfg_pin = REG_RD(bp, params->shmem_base + bnx2x_sfp_e3_set_transmitter()
4483 serdes_net_if = (REG_RD(bp, params->shmem_base + bnx2x_warpcore_config_init()
4798 vars->link_status = REG_RD(bp, params->shmem_base + bnx2x_link_status_update()
4808 vars->eee_status = REG_RD(bp, params->shmem2_base + bnx2x_link_status_update()
4818 media_types = REG_RD(bp, sync_offset); bnx2x_link_status_update()
4836 vars->aeu_int_mask = REG_RD(bp, sync_offset); bnx2x_link_status_update()
6065 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); bnx2x_link_int_enable()
6067 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), bnx2x_link_int_enable()
6068 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), bnx2x_link_int_enable()
6069 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); bnx2x_link_int_enable()
6071 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), bnx2x_link_int_enable()
6072 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); bnx2x_link_int_enable()
6085 latch_status = REG_RD(bp, bnx2x_rearm_latch_signal()
6209 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); bnx2x_get_ext_phy_fw_version()
6219 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); bnx2x_get_ext_phy_fw_version()
6248 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + bnx2x_set_xgxs_loopback()
6776 val = REG_RD(bp, addr) + 1; bnx2x_chng_link_count()
6824 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); bnx2x_link_update()
6826 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + bnx2x_link_update()
6829 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), bnx2x_link_update()
6831 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); bnx2x_link_update()
6834 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), bnx2x_link_update()
6835 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); bnx2x_link_update()
7411 if (REG_RD(bp, params->shmem_base + bnx2x_8073_config_init()
7771 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); bnx2x_get_gpio_port()
7772 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); bnx2x_get_gpio_port()
7786 tx_en_mode = REG_RD(bp, params->shmem_base + bnx2x_sfp_e1e2_set_transmitter()
7918 pin_cfg = (REG_RD(bp, params->shmem_base + bnx2x_warpcore_power_module()
8217 media_types = REG_RD(bp, sync_offset); bnx2x_get_edc_mode()
8262 val = REG_RD(bp, params->shmem_base + bnx2x_verify_sfp_module()
8527 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + bnx2x_set_e1e2_module_fault_led()
8560 pin_cfg = (REG_RD(bp, params->shmem_base + bnx2x_set_e3_module_fault_led()
8682 u32 val = REG_RD(bp, params->shmem_base + bnx2x_sfp_module_detection()
8976 tx_en_mode = REG_RD(bp, params->shmem_base + bnx2x_8706_config_init()
9224 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); bnx2x_8727_hw_reset()
9225 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); bnx2x_8727_hw_reset()
9349 tx_en_mode = REG_RD(bp, params->shmem_base + bnx2x_8727_config_init()
9379 u32 val = REG_RD(bp, params->shmem_base + bnx2x_8727_handle_mod_abs()
10001 pair_swap = REG_RD(bp, params->shmem_base + bnx2x_84833_pair_swap_cfg()
10031 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + bnx2x_84833_get_reset_gpios()
10044 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + bnx2x_84833_get_reset_gpios()
10063 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + bnx2x_84833_hw_reset_phy()
10242 u32 cms_enable = REG_RD(bp, params->shmem_base + bnx2x_848x3_config_init()
10568 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + bnx2x_848xx_set_link_led()
10636 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + bnx2x_848xx_set_link_led()
10803 cfg_pin = (REG_RD(bp, params->shmem_base + bnx2x_54618se_config_init()
11044 cfg_pin = (REG_RD(bp, params->shmem_base + bnx2x_54618se_link_reset()
11875 rx = REG_RD(bp, shmem_base + bnx2x_populate_preemphasis()
11879 tx = REG_RD(bp, shmem_base + bnx2x_populate_preemphasis()
11883 rx = REG_RD(bp, shmem_base + bnx2x_populate_preemphasis()
11887 tx = REG_RD(bp, shmem_base + bnx2x_populate_preemphasis()
11906 ext_phy_config = REG_RD(bp, shmem_base + bnx2x_get_ext_phy_config()
11911 ext_phy_config = REG_RD(bp, shmem_base + bnx2x_get_ext_phy_config()
11927 u32 switch_cfg = (REG_RD(bp, shmem_base + bnx2x_populate_int_phy()
11931 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | bnx2x_populate_int_phy()
11932 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); bnx2x_populate_int_phy()
11937 phy_addr = REG_RD(bp, bnx2x_populate_int_phy()
11940 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) bnx2x_populate_int_phy()
11945 serdes_net_if = (REG_RD(bp, shmem_base + bnx2x_populate_int_phy()
12027 phy_addr = REG_RD(bp, bnx2x_populate_int_phy()
12033 phy_addr = REG_RD(bp, bnx2x_populate_int_phy()
12138 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, bnx2x_populate_ext_phy()
12149 u32 size = REG_RD(bp, shmem2_base); bnx2x_populate_ext_phy()
12172 u32 raw_ver = REG_RD(bp, phy->ver_addr); bnx2x_populate_ext_phy()
12206 link_config = REG_RD(bp, params->shmem_base + bnx2x_phy_def_cfg()
12209 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + bnx2x_phy_def_cfg()
12214 link_config = REG_RD(bp, params->shmem_base + bnx2x_phy_def_cfg()
12217 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + bnx2x_phy_def_cfg()
12353 media_types = REG_RD(bp, sync_offset); bnx2x_phy_probe()
12554 lfa_sts = REG_RD(bp, params->lfa_base + bnx2x_avoid_link_flap()
12633 tmp_val = REG_RD(bp, params->lfa_base + bnx2x_cannot_avoid_link_flap()
12641 lfa_sts = REG_RD(bp, params->lfa_base + bnx2x_cannot_avoid_link_flap()
12833 if (REG_RD(bp, MISC_REG_RESET_REG_2) & bnx2x_link_reset()
12908 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); bnx2x_8073_common_init_phy()
12909 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); bnx2x_8073_common_init_phy()
13033 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); bnx2x_8726_common_init_phy()
13076 u32 phy_gpio_reset = REG_RD(bp, shmem_base + bnx2x_get_ext_phy_reset_gpio()
13128 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); bnx2x_8727_common_init_phy()
13129 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); bnx2x_8727_common_init_phy()
13300 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); bnx2x_common_init_phy()
13304 phy_ver = REG_RD(bp, shmem_base_path[0] + bnx2x_common_init_phy()
13336 cfg_pin = (REG_RD(bp, params->shmem_base + bnx2x_check_over_curr()
13452 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) bnx2x_check_half_open_conn()
13456 (REG_RD(bp, MISC_REG_RESET_REG_2) & bnx2x_check_half_open_conn()
13470 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) bnx2x_check_half_open_conn()
13476 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & bnx2x_check_half_open_conn()
13507 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, bnx2x_sfp_tx_fault_detection()
13648 if ((REG_RD(bp, params->shmem_base + bnx2x_period_func()
13748 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); bnx2x_init_mod_abs_int()
13749 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); bnx2x_init_mod_abs_int()
13769 aeu_mask = REG_RD(bp, offset); bnx2x_init_mod_abs_int()
13774 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); bnx2x_init_mod_abs_int()
H A Dbnx2x_init.h208 u32 curr_cos = REG_RD(bp, QM_REG_QVOQIDX_0 + q_num * 4); bnx2x_map_q_cos()
235 reg_bit_map = REG_RD(bp, reg_addr); bnx2x_map_q_cos()
240 reg_bit_map = REG_RD(bp, reg_addr); bnx2x_map_q_cos()
248 reg_bit_map = REG_RD(bp, reg_addr); bnx2x_map_q_cos()
680 reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr); bnx2x_set_mcp_parity()
743 reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i]. bnx2x_clear_blocks_parity()
754 reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP); bnx2x_clear_blocks_parity()
H A Dbnx2x_init_ops.h260 REG_RD(bp, addr); bnx2x_init_block()
516 val = REG_RD(bp, write_arb_addr[i].l); bnx2x_init_pxp_arb()
520 val = REG_RD(bp, write_arb_addr[i].add); bnx2x_init_pxp_arb()
524 val = REG_RD(bp, write_arb_addr[i].ubound); bnx2x_init_pxp_arb()
585 val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST); bnx2x_init_pxp_arb()
H A Dbnx2x_ethtool.c831 *p++ = REG_RD(bp, addr); bnx2x_read_pages_regs()
860 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); __bnx2x_get_preset_regs()
869 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); __bnx2x_get_preset_regs()
877 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); __bnx2x_get_preset_regs()
884 *p++ = REG_RD(bp, addr + j*4); __bnx2x_get_preset_regs()
1197 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); bnx2x_acquire_nvram_lock()
1229 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); bnx2x_release_nvram_lock()
1251 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); bnx2x_enable_nvram_access()
1263 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); bnx2x_disable_nvram_access()
1300 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); bnx2x_nvram_read_dword()
1303 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); bnx2x_nvram_read_dword()
1574 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); bnx2x_nvram_write_dword()
2254 save_val = REG_RD(bp, offset); bnx2x_test_registers()
2258 val = REG_RD(bp, offset); bnx2x_test_registers()
2336 val = REG_RD(bp, prty_tbl[i].offset); bnx2x_test_memory()
2347 REG_RD(bp, mem_tbl[i].offset + j*4); bnx2x_test_memory()
2351 val = REG_RD(bp, prty_tbl[i].offset); bnx2x_test_memory()
2949 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); bnx2x_self_test()
H A Dbnx2x.h163 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) macro
198 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
203 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
210 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
213 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
219 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
2138 val = REG_RD(bp, reg); reg_poll()
H A Dbnx2x_stats.c858 estats->eee_tx_lpi += REG_RD(bp, lpi_reg); bnx2x_hw_stats_update()
1628 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38); bnx2x_stats_init()
1630 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38); bnx2x_stats_init()
H A Dbnx2x_cmn.h697 u32 result = REG_RD(bp, hc_addr); bnx2x_hc_ack_int()
706 u32 result = REG_RD(bp, igu_addr); bnx2x_igu_ack_int()
H A Dbnx2x_sriov.c766 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); bnx2x_vf_igu_reset()
1138 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4); bnx2x_get_vf_igu_cam_info()
1207 val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF); bnx2x_sriov_info()
2015 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); bnx2x_vf_igu_disable()
H A Dbnx2x_dcb.c52 /* helpers: read/write len bytes from addr into buff by REG_RD/REG_WR */ bnx2x_read_data()
58 *buff = REG_RD(bp, addr + i); bnx2x_read_data()
H A Dbnx2x_cmn.c2359 u32 loaded_fw = REG_RD(bp, XSEM_REG_PRAM); bnx2x_compare_fw_ver()
/linux-4.1.27/drivers/media/radio/wl128x/
H A Dfmdrv_rx.c83 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL); fm_rx_set_freq()
115 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2, &curr_frq, &resp_len); fm_rx_set_freq()
187 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, fm_rx_seek()
227 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL); fm_rx_seek()
283 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2, fm_rx_seek()
529 ret = fmc_send_cmd(fmdev, RSSI_LVL_GET, REG_RD, NULL, 2, fm_rx_get_rssi_level()
620 ret = fmc_send_cmd(fmdev, MOST_MODE_SET, REG_RD, NULL, 2, fm_rx_get_stereo_mono()
700 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, fm_rx_set_rds_mode()
H A Dfmdrv_common.c580 if (!fm_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, sizeof(flag), NULL)) fm_irq_send_flag_getcmd()
630 if (!fm_send_cmd(fmdev, RDS_DATA_GET, REG_RD, NULL, fm_irq_send_rdsdata_getcmd()
976 if (!fm_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, sizeof(payload), NULL)) fm_irq_afjump_rd_freq()
1348 if (fmc_send_cmd(fmdev, ASIC_ID_GET, REG_RD, NULL, fm_power_up()
1352 if (fmc_send_cmd(fmdev, ASIC_VER_GET, REG_RD, NULL, fm_power_up()
H A Dfmdrv_common.h28 #define REG_RD 0x1 macro
H A Dfmdrv_tx.c372 ret = fmc_send_cmd(fmdev, READ_FMANT_TUNE_VALUE, REG_RD, fm_tx_get_tune_cap_val()
/linux-4.1.27/arch/cris/arch-v32/drivers/mach-a3/
H A Dnandflash.c61 dout = REG_RD(pio, regi_pio, rw_dout); crisv32_hwcontrol()
98 reg_pio_r_din din = REG_RD(pio, regi_pio, r_din); crisv32_device_ready()
H A Dgpio.c269 masked_intr = REG_RD(gio, regi_gio, r_masked_intr); gpio_interrupt()
293 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask); gpio_interrupt()
913 intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg); virtual_gpio_init()
914 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask); virtual_gpio_init()
/linux-4.1.27/arch/x86/crypto/
H A Dsha1_avx2_x86_64_asm.S88 #define REG_RD %rax define
111 .set RD, REG_RD
/linux-4.1.27/drivers/scsi/bnx2i/
H A Dbnx2i.h128 #define REG_RD(__hba, offset) \ macro
H A Dbnx2i_hwi.c2750 config2 = REG_RD(ep->hba, BNX2_MQ_CONFIG2); bnx2i_map_ep_dbell_regs()

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