614 				data[i] = REG_RD(bp, src_addr + i*4);  in bnx2x_read_dmae()
722 				regs[j] = REG_RD(bp, bar_storm_intmem[storm] +  in bnx2x_mc_assert()
771 	val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);  in bnx2x_fw_dump_lvl()
772 	if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))  in bnx2x_fw_dump_lvl()
792 	mark = REG_RD(bp, addr);  in bnx2x_fw_dump_lvl()
800 	mark = REG_RD(bp, addr);  in bnx2x_fw_dump_lvl()
813 			data[word] = htonl(REG_RD(bp, offset + 4*word));  in bnx2x_fw_dump_lvl()
821 			data[word] = htonl(REG_RD(bp, offset + 4*word));  in bnx2x_fw_dump_lvl()
837 	u32 val = REG_RD(bp, addr);  in bnx2x_hc_int_disable()
867 	if (REG_RD(bp, addr) != val)  in bnx2x_hc_int_disable()
873 	u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);  in bnx2x_igu_int_disable()
885 	if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)  in bnx2x_igu_int_disable()
941 				REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +  in bnx2x_panic_dump()
1038 			*(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +  in bnx2x_panic_dump()
1210 	crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);  in bnx2x_pbf_pN_buf_flushed()
1211 	crd = crd_start = REG_RD(bp, regs->crd);  in bnx2x_pbf_pN_buf_flushed()
1212 	init_crd = REG_RD(bp, regs->init_crd);  in bnx2x_pbf_pN_buf_flushed()
1222 			crd = REG_RD(bp, regs->crd);  in bnx2x_pbf_pN_buf_flushed()
1223 			crd_freed = REG_RD(bp, regs->crd_freed);  in bnx2x_pbf_pN_buf_flushed()
1245 	occup = to_free = REG_RD(bp, regs->lines_occup);  in bnx2x_pbf_pN_cmd_flushed()
1246 	freed = freed_start = REG_RD(bp, regs->lines_freed);  in bnx2x_pbf_pN_cmd_flushed()
1254 			occup = REG_RD(bp, regs->lines_occup);  in bnx2x_pbf_pN_cmd_flushed()
1255 			freed = REG_RD(bp, regs->lines_freed);  in bnx2x_pbf_pN_cmd_flushed()
1276 	while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)  in bnx2x_flr_clnup_reg_poll()
1386 	if (REG_RD(bp, comp_addr)) {  in bnx2x_send_final_clnup()
1402 		   (REG_RD(bp, comp_addr)));  in bnx2x_send_final_clnup()
1471 	val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);  in bnx2x_hw_enable_status()
1474 	val = REG_RD(bp, PBF_REG_DISABLE_PF);  in bnx2x_hw_enable_status()
1477 	val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);  in bnx2x_hw_enable_status()
1480 	val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);  in bnx2x_hw_enable_status()
1483 	val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);  in bnx2x_hw_enable_status()
1486 	val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);  in bnx2x_hw_enable_status()
1489 	val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);  in bnx2x_hw_enable_status()
1492 	val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);  in bnx2x_hw_enable_status()
1545 	u32 val = REG_RD(bp, addr);  in bnx2x_hc_int_enable()
1617 	val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);  in bnx2x_igu_int_enable()
1740 	lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_trylock_hw_lock()
2004 	lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_acquire_hw_lock()
2015 		lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_acquire_hw_lock()
2052 	lock_status = REG_RD(bp, hw_lock_control_reg);  in bnx2x_release_hw_lock()
2066 	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&  in bnx2x_get_gpio()
2067 			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;  in bnx2x_get_gpio()
2080 	gpio_reg = REG_RD(bp, MISC_REG_GPIO);  in bnx2x_get_gpio()
2094 	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&  in bnx2x_set_gpio()
2095 			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;  in bnx2x_set_gpio()
2108 	gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);  in bnx2x_set_gpio()
2156 	gpio_reg = REG_RD(bp, MISC_REG_GPIO);  in bnx2x_set_mult_gpio()
2197 	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&  in bnx2x_set_gpio_int()
2198 			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;  in bnx2x_set_gpio_int()
2211 	gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);  in bnx2x_set_gpio_int()
2254 	spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);  in bnx2x_set_spio()
3920 		val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);  in bnx2x_acquire_alr()
3983 	aeu_mask = REG_RD(bp, aeu_addr);  in bnx2x_attn_int_asserted()
4003 			nig_mask = REG_RD(bp, nig_int_mask_addr);  in bnx2x_attn_int_asserted()
4076 				igu_acked = REG_RD(bp,  in bnx2x_attn_int_asserted()
4126 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted0()
4145 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted0()
4161 		val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);  in bnx2x_attn_int_deasserted1()
4176 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted1()
4192 		val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);  in bnx2x_attn_int_deasserted2()
4200 		val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);  in bnx2x_attn_int_deasserted2()
4207 			val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);  in bnx2x_attn_int_deasserted2()
4220 		val = REG_RD(bp, reg_offset);  in bnx2x_attn_int_deasserted2()
4319 					REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);  in bnx2x_attn_int_deasserted3()
4324 					REG_RD(bp, MISC_REG_GRC_RSV_ATTN);  in bnx2x_attn_int_deasserted3()
4364 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_set_reset_global()
4378 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_clear_reset_global()
4390 	u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_reset_is_global()
4407 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_set_reset_done()
4427 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_set_reset_in_progress()
4441 	u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_reset_is_done()
4463 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_set_pf_load()
4501 	val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_clear_pf_load()
4532 	u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);  in bnx2x_get_load_status()
4546 	pr_cont(" [0x%08x] ", REG_RD(bp, reg));  in _print_parity()
4974 	attn.sig[0] = REG_RD(bp,  in bnx2x_chk_parity_attn()
4977 	attn.sig[1] = REG_RD(bp,  in bnx2x_chk_parity_attn()
4980 	attn.sig[2] = REG_RD(bp,  in bnx2x_chk_parity_attn()
4983 	attn.sig[3] = REG_RD(bp,  in bnx2x_chk_parity_attn()
4989 	attn.sig[3] &= ((REG_RD(bp,  in bnx2x_chk_parity_attn()
4996 		attn.sig[4] = REG_RD(bp,  in bnx2x_chk_parity_attn()
5008 		val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);  in bnx2x_attn_int_deasserted4()
5032 		val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);  in bnx2x_attn_int_deasserted4()
5086 	attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5087 	attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5088 	attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5089 	attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5092 		      REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);  in bnx2x_attn_int_deasserted()
5142 	aeu_mask = REG_RD(bp, reg_addr);  in bnx2x_attn_int_deasserted()
6015 			   REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);  in bnx2x_init_def_sb()
6023 			bp->attn_group[index].sig[4] = REG_RD(bp,  in bnx2x_init_def_sb()
6502 		REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &  in bnx2x_post_irq_nic_init()
6673 		val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);  in bnx2x_int_mem_test()
6727 	val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);  in bnx2x_int_mem_test()
6737 	val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);  in bnx2x_int_mem_test()
6743 		REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);  in bnx2x_int_mem_test()
6744 	val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);  in bnx2x_int_mem_test()
6912 	val = REG_RD(bp, MISC_REG_SPIO_INT);  in bnx2x_setup_fan_failure_detection()
6917 	val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);  in bnx2x_setup_fan_failure_detection()
6924 	u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);  in bnx2x_pf_disable()
7059 	val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);  in bnx2x_init_hw_common()
7064 	val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);  in bnx2x_init_hw_common()
7181 			val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);  in bnx2x_init_hw_common()
7413 	REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);  in bnx2x_init_hw_common()
7599 	       REG_RD(bp, reg) &  in bnx2x_init_hw_port()
7604 	       REG_RD(bp, reg) &  in bnx2x_init_hw_port()
7659 	val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);  in bnx2x_init_hw_port()
7663 		val = REG_RD(bp, reg_addr);  in bnx2x_init_hw_port()
7721 	while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)  in bnx2x_igu_clear_sb_gen()
7724 	if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {  in bnx2x_igu_clear_sb_gen()
7786 		vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :  in bnx2x_reset_nic_mode()
7791 			mac_en[i] = REG_RD(bp, port ?  in bnx2x_reset_nic_mode()
7908 		val = REG_RD(bp, addr);  in bnx2x_init_hw_func()
8165 		val = REG_RD(bp, main_mem_prty_clr);  in bnx2x_init_hw_func()
8180 		REG_RD(bp, main_mem_prty_clr);  in bnx2x_init_hw_func()
8903 			if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))  in bnx2x_reset_func()
8952 	val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);  in bnx2x_reset_port()
9359 		val = REG_RD(bp, addr);  in bnx2x_disable_close_the_gate()
9363 		val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);  in bnx2x_disable_close_the_gate()
9386 		val = REG_RD(bp, HC_REG_CONFIG_1);  in bnx2x_set_234_gates()
9391 		val = REG_RD(bp, HC_REG_CONFIG_0);  in bnx2x_set_234_gates()
9397 		val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);  in bnx2x_set_234_gates()
9454 	shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);  in bnx2x_reset_mcp_prep()
9490 		bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);  in bnx2x_init_shmem()
9649 		pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);  in bnx2x_er_poll_igu_vq()
9675 		sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);  in bnx2x_process_kill()
9676 		blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);  in bnx2x_process_kill()
9677 		port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);  in bnx2x_process_kill()
9678 		port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);  in bnx2x_process_kill()
9679 		pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);  in bnx2x_process_kill()
9681 			tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);  in bnx2x_process_kill()
10171 	vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);  in bnx2x_prev_unload_close_umac()
10187 	reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);  in bnx2x_prev_unload_close_mac()
10190 		val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);  in bnx2x_prev_unload_close_mac()
10206 			wb_data[0] = REG_RD(bp, base_addr + offset);  in bnx2x_prev_unload_close_mac()
10207 			wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);  in bnx2x_prev_unload_close_mac()
10217 		vals->emac_val = REG_RD(bp, vals->emac_addr);  in bnx2x_prev_unload_close_mac()
10224 			val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);  in bnx2x_prev_unload_close_mac()
10230 			vals->xmac_val = REG_RD(bp, vals->xmac_addr);  in bnx2x_prev_unload_close_mac()
10261 	if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &  in bnx2x_prev_is_after_undi()
10265 	if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {  in bnx2x_prev_is_after_undi()
10283 	tmp_reg = REG_RD(bp, addr);  in bnx2x_prev_unload_undi_inc()
10525 	reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);  in bnx2x_prev_unload_common()
10546 			REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);  in bnx2x_prev_unload_common()
10553 		tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);  in bnx2x_prev_unload_common()
10557 			tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);  in bnx2x_prev_unload_common()
10621 	hw_lock_val = REG_RD(bp, hw_lock_reg);  in bnx2x_prev_unload()
10634 	if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {  in bnx2x_prev_unload()
10695 	val = REG_RD(bp, MISC_REG_CHIP_NUM);  in bnx2x_get_common_hwinfo()
10697 	val = REG_RD(bp, MISC_REG_CHIP_REV);  in bnx2x_get_common_hwinfo()
10703 	val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);  in bnx2x_get_common_hwinfo()
10705 	val = REG_RD(bp, MISC_REG_BOND_ID);  in bnx2x_get_common_hwinfo()
10710 	if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {  in bnx2x_get_common_hwinfo()
10724 		val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);  in bnx2x_get_common_hwinfo()
10726 			val = REG_RD(bp, MISC_REG_PORT4MODE_EN);  in bnx2x_get_common_hwinfo()
10748 	val = (REG_RD(bp, 0x2874) & 0x55);  in bnx2x_get_common_hwinfo()
10755 	val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);  in bnx2x_get_common_hwinfo()
10763 	bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?  in bnx2x_get_common_hwinfo()
10772 		REG_RD(bp, bp->common.shmem2_base +  in bnx2x_get_common_hwinfo()
10900 		val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);  in bnx2x_get_igu_cam_info()
10979 		bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);  in bnx2x_link_settings_supported()
10983 			bp->port.phy_addr = REG_RD(  in bnx2x_link_settings_supported()
10987 			bp->port.phy_addr = REG_RD(  in bnx2x_link_settings_supported()
11665 	if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {  in bnx2x_get_hwinfo()
11687 		val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);  in bnx2x_get_hwinfo()
11698 			while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {  in bnx2x_get_hwinfo()
11703 			if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {  in bnx2x_get_hwinfo()
14553 	REG_RD(bp, pretend_reg);  in bnx2x_pretend_func()
14566 	val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :  in bnx2x_ptp_task()
14570 		timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :  in bnx2x_ptp_task()
14573 		timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :  in bnx2x_ptp_task()
14600 	timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :  in bnx2x_set_rx_ts()
14603 	timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :  in bnx2x_set_rx_ts()