226 	u32 val = REG_RD(bp, reg);  in bnx2x_bits_en()
235 	u32 val = REG_RD(bp, reg);  in bnx2x_bits_dis()
258 		REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
273 	link_status = REG_RD(bp, params->shmem_base +  in bnx2x_check_lfa()
302 	saved_val = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
311 	saved_val = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
320 	saved_val = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
330 		cur_speed_cap_mask = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
343 		REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
353 	eee_status = REG_RD(bp, params->shmem2_base +  in bnx2x_check_lfa()
384 	gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);  in bnx2x_get_epio()
387 	*en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;  in bnx2x_get_epio()
401 	gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);  in bnx2x_set_epio()
410 	gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);  in bnx2x_set_epio()
1429 	cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_set_mdio_clk()
1466 	port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);  in bnx2x_is_4_port_mode()
1472 	return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);  in bnx2x_is_4_port_mode()
1493 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_init()
1498 		val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_init()
1539 	if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_set_umac_rxtx()
1542 	val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);  in bnx2x_set_umac_rxtx()
1667 	    (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_xmac_init()
1721 	if (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_set_xmac_rxtx()
1727 		pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);  in bnx2x_set_xmac_rxtx()
1733 		val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);  in bnx2x_set_xmac_rxtx()
1876 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);  in bnx2x_emac_enable()
1905 	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);  in bnx2x_emac_enable()
2144 	xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :  in bnx2x_update_pfc_nig()
2253 		val = REG_RD(bp, MISC_REG_RESET_REG_2);  in bnx2x_update_pfc()
2455 	u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);  in bnx2x_set_bmac_rx()
2462 	if (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_set_bmac_rx()
2488 	init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);  in bnx2x_pbf_update()
2489 	crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);  in bnx2x_pbf_update()
2494 		crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);  in bnx2x_pbf_update()
2497 	crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);  in bnx2x_pbf_update()
2569 		if (REG_RD(bp, NIG_REG_PORT_SWAP))  in bnx2x_get_emac_base()
2575 		if (REG_RD(bp, NIG_REG_PORT_SWAP))  in bnx2x_get_emac_base()
2604 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_write()
2617 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_write()
2640 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_read()
2653 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_read()
2681 		chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |  in bnx2x_cl45_read()
2682 			  ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);  in bnx2x_cl45_read()
2698 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_read()
2719 			val = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_read()
2756 		chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |  in bnx2x_cl45_write()
2757 			  ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);  in bnx2x_cl45_write()
2774 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_write()
2794 			tmp = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_write()
2828 	if (REG_RD(bp, params->shmem2_base) <=  in bnx2x_eee_has_cap()
2893 		eee_mode = ((REG_RD(bp, params->shmem_base +  in bnx2x_eee_calc_timer()
3070 	board_cfg = REG_RD(bp, params->shmem_base +  in bnx2x_bsc_module_sel()
3078 	sfp_ctrl = REG_RD(bp, params->shmem_base +  in bnx2x_bsc_module_sel()
3109 	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3126 	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3129 		val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3150 	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3153 		val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);  in bnx2x_bsc_read()
3164 		data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));  in bnx2x_bsc_read()
3240 		path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);  in bnx2x_get_warpcore_lane()
3244 			path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);  in bnx2x_get_warpcore_lane()
3250 		port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);  in bnx2x_get_warpcore_lane()
3254 			port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);  in bnx2x_get_warpcore_lane()
3264 			REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);  in bnx2x_get_warpcore_lane()
3269 				REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);  in bnx2x_get_warpcore_lane()
3797 	if (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_enable_AN_KR()
3837 		wc_lane_config = REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_enable_AN_KR()
3989 		cfg_tap_val = REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_set_10G_XFI()
4322 		cfg_pin = (REG_RD(bp, shmem_base +  in bnx2x_get_mod_abs_int_cfg()
4399 		serdes_net_if = (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_config_runtime()
4462 	cfg_pin = REG_RD(bp, params->shmem_base +  in bnx2x_sfp_e3_set_transmitter()
4483 	serdes_net_if = (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_config_init()
4798 	vars->link_status = REG_RD(bp, params->shmem_base +  in bnx2x_link_status_update()
4808 		vars->eee_status = REG_RD(bp, params->shmem2_base +  in bnx2x_link_status_update()
4818 	media_types = REG_RD(bp, sync_offset);  in bnx2x_link_status_update()
4836 	vars->aeu_int_mask = REG_RD(bp, sync_offset);  in bnx2x_link_status_update()
6065 		 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));  in bnx2x_link_int_enable()
6067 		 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),  in bnx2x_link_int_enable()
6068 		 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),  in bnx2x_link_int_enable()
6069 		 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));  in bnx2x_link_int_enable()
6071 	   REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),  in bnx2x_link_int_enable()
6072 	   REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));  in bnx2x_link_int_enable()
6085 	latch_status = REG_RD(bp,  in bnx2x_rearm_latch_signal()
6209 	spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);  in bnx2x_get_ext_phy_fw_version()
6219 		spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);  in bnx2x_get_ext_phy_fw_version()
6248 			md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +  in bnx2x_set_xgxs_loopback()
6776 		val = REG_RD(bp, addr) + 1;  in bnx2x_chng_link_count()
6824 		 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));  in bnx2x_link_update()
6826 	is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +  in bnx2x_link_update()
6829 		 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),  in bnx2x_link_update()
6831 		 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));  in bnx2x_link_update()
6834 	  REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),  in bnx2x_link_update()
6835 	  REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));  in bnx2x_link_update()
7411 	if (REG_RD(bp, params->shmem_base +  in bnx2x_8073_config_init()
7771 	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);  in bnx2x_get_gpio_port()
7772 	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);  in bnx2x_get_gpio_port()
7786 	tx_en_mode = REG_RD(bp, params->shmem_base +  in bnx2x_sfp_e1e2_set_transmitter()
7918 	pin_cfg = (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_power_module()
8217 	media_types = REG_RD(bp, sync_offset);  in bnx2x_get_edc_mode()
8262 	val = REG_RD(bp, params->shmem_base +  in bnx2x_verify_sfp_module()
8527 	u32 fault_led_gpio = REG_RD(bp, params->shmem_base +  in bnx2x_set_e1e2_module_fault_led()
8560 	pin_cfg = (REG_RD(bp, params->shmem_base +  in bnx2x_set_e3_module_fault_led()
8682 	u32 val = REG_RD(bp, params->shmem_base +  in bnx2x_sfp_module_detection()
8976 	tx_en_mode = REG_RD(bp, params->shmem_base +  in bnx2x_8706_config_init()
9224 	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);  in bnx2x_8727_hw_reset()
9225 	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);  in bnx2x_8727_hw_reset()
9349 	tx_en_mode = REG_RD(bp, params->shmem_base +  in bnx2x_8727_config_init()
9379 	u32 val = REG_RD(bp, params->shmem_base +  in bnx2x_8727_handle_mod_abs()
10001 	pair_swap = REG_RD(bp, params->shmem_base +  in bnx2x_84833_pair_swap_cfg()
10031 			reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +  in bnx2x_84833_get_reset_gpios()
10044 			reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +  in bnx2x_84833_get_reset_gpios()
10063 	u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +  in bnx2x_84833_hw_reset_phy()
10242 		u32 cms_enable = REG_RD(bp, params->shmem_base +  in bnx2x_848x3_config_init()
10568 				if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +  in bnx2x_848xx_set_link_led()
10636 				if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +  in bnx2x_848xx_set_link_led()
10803 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_54618se_config_init()
11044 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_54618se_link_reset()
11875 			rx = REG_RD(bp, shmem_base +  in bnx2x_populate_preemphasis()
11879 			tx = REG_RD(bp, shmem_base +  in bnx2x_populate_preemphasis()
11883 			rx = REG_RD(bp, shmem_base +  in bnx2x_populate_preemphasis()
11887 			tx = REG_RD(bp, shmem_base +  in bnx2x_populate_preemphasis()
11906 		ext_phy_config = REG_RD(bp, shmem_base +  in bnx2x_get_ext_phy_config()
11911 		ext_phy_config = REG_RD(bp, shmem_base +  in bnx2x_get_ext_phy_config()
11927 	u32 switch_cfg = (REG_RD(bp, shmem_base +  in bnx2x_populate_int_phy()
11931 	chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |  in bnx2x_populate_int_phy()
11932 		((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);  in bnx2x_populate_int_phy()
11937 		phy_addr = REG_RD(bp,  in bnx2x_populate_int_phy()
11940 		if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)  in bnx2x_populate_int_phy()
11945 		serdes_net_if = (REG_RD(bp, shmem_base +  in bnx2x_populate_int_phy()
12027 			phy_addr = REG_RD(bp,  in bnx2x_populate_int_phy()
12033 			phy_addr = REG_RD(bp,  in bnx2x_populate_int_phy()
12138 	config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,  in bnx2x_populate_ext_phy()
12149 		u32 size = REG_RD(bp, shmem2_base);  in bnx2x_populate_ext_phy()
12172 		u32 raw_ver = REG_RD(bp, phy->ver_addr);  in bnx2x_populate_ext_phy()
12206 		link_config = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12209 		phy->speed_cap_mask = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12214 		link_config = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12217 		phy->speed_cap_mask = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12353 		media_types = REG_RD(bp, sync_offset);  in bnx2x_phy_probe()
12554 	lfa_sts = REG_RD(bp, params->lfa_base +  in bnx2x_avoid_link_flap()
12633 	tmp_val = REG_RD(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
12641 	lfa_sts = REG_RD(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
12833 		if (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_link_reset()
12908 	swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);  in bnx2x_8073_common_init_phy()
12909 	swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);  in bnx2x_8073_common_init_phy()
13033 	val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);  in bnx2x_8726_common_init_phy()
13076 	u32 phy_gpio_reset = REG_RD(bp, shmem_base +  in bnx2x_get_ext_phy_reset_gpio()
13128 	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);  in bnx2x_8727_common_init_phy()
13129 	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);  in bnx2x_8727_common_init_phy()
13300 		val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);  in bnx2x_common_init_phy()
13304 	phy_ver = REG_RD(bp, shmem_base_path[0] +  in bnx2x_common_init_phy()
13336 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_check_over_curr()
13452 	    (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))  in bnx2x_check_half_open_conn()
13456 	    (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_check_half_open_conn()
13470 		if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))  in bnx2x_check_half_open_conn()
13476 	} else if (REG_RD(bp, MISC_REG_RESET_REG_2) &  in bnx2x_check_half_open_conn()
13507 	cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,  in bnx2x_sfp_tx_fault_detection()
13648 		if ((REG_RD(bp, params->shmem_base +  in bnx2x_period_func()
13748 	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);  in bnx2x_init_mod_abs_int()
13749 	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);  in bnx2x_init_mod_abs_int()
13769 	aeu_mask = REG_RD(bp, offset);  in bnx2x_init_mod_abs_int()
13774 	val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);  in bnx2x_init_mod_abs_int()