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Searched refs:R5 (Results 1 – 50 of 50) sorted by relevance

/linux-4.1.27/lib/
Dtest_bpf.c47 #define R5 BPF_REG_5 macro
773 BPF_ALU64_IMM(BPF_MOV, R5, 5),
783 BPF_ALU64_IMM(BPF_ADD, R5, 20),
793 BPF_ALU64_IMM(BPF_SUB, R5, 10),
803 BPF_ALU64_REG(BPF_ADD, R0, R5),
815 BPF_ALU64_REG(BPF_ADD, R1, R5),
827 BPF_ALU64_REG(BPF_ADD, R2, R5),
839 BPF_ALU64_REG(BPF_ADD, R3, R5),
851 BPF_ALU64_REG(BPF_ADD, R4, R5),
858 BPF_ALU64_REG(BPF_ADD, R5, R0),
[all …]
/linux-4.1.27/arch/x86/crypto/
Daes-x86_64-asm_64.S41 #define R5 %rsi macro
134 prologue(FUNC,KEY,B128,B192,R2,R8,R7,R9,R1,R3,R4,R6,R10,R5,R11)
136 #define return(FUNC) epilogue(FUNC,R8,R2,R9,R7,R5,R6,R3,R4,R11)
139 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4) \
140 move_regs(R1,R2,R5,R6)
143 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4)
146 round(TAB,OFFSET,R2,R1,R4,R3,R6,R5,R7,R10,R5,R6,R3,R4) \
147 move_regs(R1,R2,R5,R6)
150 round(TAB,OFFSET,R2,R1,R4,R3,R6,R5,R7,R10,R5,R6,R3,R4)
/linux-4.1.27/arch/blackfin/lib/
Ddivsi3.S116 R5 = R6 >> 31; /* Shift sign to LSB */ define
119 R2 = R2 | R5; /* Shift quotient bit */
125 R0 = R0 << 1 || R5 = [SP];
129 IF CC R5 = R1; /* or we might be adding divisor (AQ==1)*/
130 R0 = R0 + R5; /* do add or subtract, as indicated by AQ */
132 R5 = R6 >> 31; define
134 BITTGL(R5,0); /* tweak AQ to be what we want to shift in */
135 .Llend: R2 = R2 + R5; /* and then set shifted-in value to
Dudivsi3.S152 R3 = R3 << 1 || R5 = [SP];
156 IF CC R5 = R1; /* and if AQ==1, we'll add it. */
157 R3 = R3 + R5; /* Add/sub divsor to partial remainder */
160 R5 = R7 >> 31; /* Get AQ */ define
161 BITTGL(R5, 0); /* Invert it, to get what we'll shift */
162 .Lulend: R2 = R2 + R5; /* and "shift" it in. */
173 R5 = R0 - R3; /* Z = (dividend - Q * divisor) */ define
174 CC = R1 <= R5 (IU); /* Check if divisor <= Z? */
/linux-4.1.27/drivers/tty/serial/
Dpmac_zilog.c159 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); in pmz_load_zsregs()
191 write_zsreg(uap, R5, regs[R5]); in pmz_load_zsregs()
582 uap->curregs[R5] |= set_bits; in pmz_set_mctrl()
583 uap->curregs[R5] &= ~clear_bits; in pmz_set_mctrl()
585 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_set_mctrl()
587 set_bits, clear_bits, uap->curregs[R5]); in pmz_set_mctrl()
728 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; in pmz_break_ctl()
729 if (new_reg != uap->curregs[R5]) { in pmz_break_ctl()
730 uap->curregs[R5] = new_reg; in pmz_break_ctl()
731 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_break_ctl()
[all …]
Dip22zilog.c191 write_zsreg(channel, R5, regs[R5] & ~TxENAB); in __load_zsregs()
224 write_zsreg(channel, R5, regs[R5]); in __load_zsregs()
564 up->curregs[R5] |= set_bits; in ip22zilog_set_mctrl()
565 up->curregs[R5] &= ~clear_bits; in ip22zilog_set_mctrl()
566 write_zsreg(channel, R5, up->curregs[R5]); in ip22zilog_set_mctrl()
674 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; in ip22zilog_break_ctl()
675 if (new_reg != up->curregs[R5]) { in ip22zilog_break_ctl()
676 up->curregs[R5] = new_reg; in ip22zilog_break_ctl()
679 write_zsreg(channel, R5, up->curregs[R5]); in ip22zilog_break_ctl()
729 up->curregs[R5] |= TxENAB; in __ip22zilog_startup()
[all …]
Dsunzilog.c210 write_zsreg(channel, R5, regs[R5] & ~TxENAB); in __load_zsregs()
257 write_zsreg(channel, R5, regs[R5]); in __load_zsregs()
664 up->curregs[R5] |= set_bits; in sunzilog_set_mctrl()
665 up->curregs[R5] &= ~clear_bits; in sunzilog_set_mctrl()
666 write_zsreg(channel, R5, up->curregs[R5]); in sunzilog_set_mctrl()
774 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; in sunzilog_break_ctl()
775 if (new_reg != up->curregs[R5]) { in sunzilog_break_ctl()
776 up->curregs[R5] = new_reg; in sunzilog_break_ctl()
779 write_zsreg(channel, R5, up->curregs[R5]); in sunzilog_break_ctl()
794 up->curregs[R5] |= TxENAB; in __sunzilog_startup()
[all …]
Dzs.c273 write_zsreg(zport, R5, regs[5] & ~TxENAB); in load_zsregs()
288 write_zsreg(zport, R5, regs[5]); in load_zsregs()
405 write_zsreg(zport_a, R5, zport_a->regs[5]); in zs_set_mctrl()
529 write_zsreg(zport, R5, zport->regs[5]); in zs_break_ctl()
794 write_zsreg(zport, R5, zport->regs[5]); in zs_startup()
818 write_zsreg(zport, R5, zport->regs[5]); in zs_shutdown()
975 write_zsreg(zport, R5, zport->regs[5]); in zs_pm()
1167 write_zsreg(zport, R5, zport->regs[5]); in zs_console_write()
1179 write_zsreg(zport, R5, zport->regs[5]); in zs_console_write()
Dzs.h64 #define R5 5 macro
Dip22zilog.h43 #define R5 5 macro
Dsunzilog.h35 #define R5 5 macro
Dpmac_zilog.h131 #define R5 5 macro
/linux-4.1.27/tools/perf/arch/arm/tests/
Dregs_load.S8 #define R5 0x28 macro
45 str r5, [r0, #R5]
/linux-4.1.27/arch/powerpc/platforms/pseries/
DhvCall.S39 std r5,STK_PARAM(R5)(r1); \
51 ld r5,STACK_FRAME_OVERHEAD+STK_PARAM(R5)(r1); \
162 HCALL_INST_PRECALL(R5)
265 HCALL_INST_PRECALL(R5)
/linux-4.1.27/arch/blackfin/mach-common/
Dentry.S370 R5 = [P4]; /* Control Register*/ define
371 BITCLR(R5,ENICPLB_P);
373 [P4] = R5;
378 R5 = [P4]; define
379 BITCLR(R5,ENDCPLB_P);
381 [P4] = R5;
1197 R5 = [P4]; /* Control Register*/ define
1198 BITCLR(R5,ENICPLB_P);
1200 [P4] = R5;
1205 R5 = [P4]; define
[all …]
Ddpmc_modes.S114 R5 = W[P0](z); define
177 w[p0] = R5; /* Restore VCO multiplier */
/linux-4.1.27/arch/hexagon/kernel/
Dvm_entry.S70 { memd(R0 + #_PT_R0504) = R5:4; \
113 memd(R0 + #_PT_R0504) = R5:4; \
149 { R5:4 = memd(R0 + #_PT_R0504); \
181 { R5:4 = memd(R0 + #_PT_R0504); \
/linux-4.1.27/drivers/net/hamradio/
Dscc.c802 wr(scc,R5,Tx8|DTR|TxCRC_ENAB); /* TX 8 bits/char, disabled, DTR */ in init_channel()
934 or(scc,R5, TxENAB); in scc_key_trx()
935 scc->wreg[R5] |= RTS; in scc_key_trx()
937 or(scc,R5,RTS|TxENAB); /* set the RTS line and enable TX */ in scc_key_trx()
940 cl(scc,R5,RTS|TxENAB); in scc_key_trx()
968 or(scc,R5, TxENAB); in scc_key_trx()
969 scc->wreg[R5] |= RTS; in scc_key_trx()
971 or(scc,R5,RTS|TxENAB); /* enable tx */ in scc_key_trx()
974 cl(scc,R5,RTS|TxENAB); /* disable tx */ in scc_key_trx()
1106 if ( (grp1 & TXGROUP) && (scc2->wreg[R5] & RTS) ) in is_grouped()
[all …]
Dz8530.h11 #define R5 5 macro
Ddmascc.c763 write_scc(priv, R5, Tx8); in scc_open()
952 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8); in scc_send_packet()
1411 write_scc(priv, R5, TxCRC_ENAB | Tx8); in tm_isr()
1433 write_scc(priv, R5, in tm_isr()
/linux-4.1.27/drivers/media/i2c/
Dwm8739.c49 R5 = 5, R6, R7, R8, R9, R15 = 15, enumerator
242 wm8739_write(sd, R5, 0x000); in wm8739_probe()
/linux-4.1.27/tools/perf/arch/arm/util/
Dunwind-libdw.c22 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
/linux-4.1.27/arch/hexagon/lib/
Dmemcpy.S178 #define ptr_in_p_128 R5 /* pointer for prefetch of input data */
181 #define shift2 R5 /* in epilog to workshifter to extract bytes */
191 #define ptr_in_p_128kernel R5:4 /* packed fetch pointer & kernel cnt */
/linux-4.1.27/arch/m32r/kernel/
Dentry.S85 #define R5(reg) @(0x04,reg) macro
/linux-4.1.27/Documentation/networking/
Dfilter.txt619 * R1 - R5 - arguments from eBPF program to in-kernel function
630 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
665 place function arguments into R1 to R5 registers to satisfy calling
667 to in-kernel function. If R1 - R5 registers are mapped to CPU registers
674 After an in-kernel function call, R1 - R5 are reset to unreadable and R0 has
721 R5 - r8
737 bpf_mov R5, 5
744 bpf_mov R5, 9
786 interpreter. R0-R5 are scratch registers, so eBPF program needs to preserve
796 After the call the registers R1-R5 contain junk values and cannot be read.
[all …]
/linux-4.1.27/arch/powerpc/kvm/
Dbookehv_interrupts.S187 PPC_STL r5, VCPU_GPR(R5)(r4)
294 PPC_STL r5, VCPU_GPR(R5)(r11)
321 PPC_STL r5, VCPU_GPR(R5)(r11)
681 PPC_LL r5, VCPU_GPR(R5)(r4)
Dbooke_interrupts.S62 stw r5, VCPU_GPR(R5)(r4)
487 lwz r5, VCPU_GPR(R5)(r4)
Dbook3s_hv_rmhandlers.S958 ld r5, VCPU_GPR(R5)(r4)
1039 std r5, VCPU_GPR(R5)(r9)
1087 ld r5, VCPU_GPR(R5)(r9)
1663 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1737 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
/linux-4.1.27/arch/ia64/kernel/
Dentry.h54 .spillsp r4,SW(R4)+16+(off); .spillsp r5,SW(R5)+16+(off); \
Dentry.S263 adds r15=SW(R5)+16,sp
277 adds r15=SW(R5)+16,sp
280 st8.spill [r15]=r5,SW(R7)-SW(R5) // spill r5
/linux-4.1.27/drivers/net/wan/
Dz85230.h30 #define R5 5 macro
Dz85230.c308 write_zsreg(c, R5, c->regs[5]); in z8530_rtsdtr()
1494 write_zsreg(c, R5, c->regs[R5]|TxENAB); in z8530_tx_begin()
/linux-4.1.27/arch/powerpc/kernel/
Dfpu.S153 SAVE_32FPVSRS(0, R5, R10)
Dtm.S183 TRECLAIM(R5) /* Cause in r5 */
/linux-4.1.27/arch/m32r/platforms/oaks32r/
Ddot.gdbinit.nommu79 printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
/linux-4.1.27/arch/cris/arch-v10/kernel/
Dkgdb.c303 R4, R5, R6, R7, enumerator
/linux-4.1.27/arch/m32r/platforms/mappi3/
Ddot.gdbinit137 printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
/linux-4.1.27/arch/cris/arch-v32/kernel/
Dkgdb_asm.S481 move.d [$acr], $r5 ; Restore R5
Dkgdb.c312 R4, R5, R6, R7, enumerator
/linux-4.1.27/arch/m32r/platforms/mappi2/
Ddot.gdbinit.vdec2148 printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
/linux-4.1.27/arch/m32r/platforms/m32700ut/
Ddot.gdbinit_200MHz_16MB149 printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
Ddot.gdbinit_400MHz_32MB149 printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
Ddot.gdbinit_300MHz_32MB149 printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
/linux-4.1.27/arch/m32r/platforms/mappi/
Ddot.gdbinit165 printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
Ddot.gdbinit.nommu165 printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
Ddot.gdbinit.smp233 printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
/linux-4.1.27/arch/m32r/platforms/opsput/
Ddot.gdbinit174 printf " R4[%08lx] R5[%08lx] R6[%08lx] R7[%08lx]\n",$r4,$r5,$r6,$r7
/linux-4.1.27/arch/blackfin/include/asm/
Ddpmc.h15 #define PM_REG2 R5
/linux-4.1.27/drivers/platform/x86/
DKconfig277 R2, R3, R5, T2, W2 and Y2 series), say Y.
/linux-4.1.27/arch/arm/
DKconfig.debug1123 Cortex-R series tiles and SMMs, such as Cortex-R5 and Cortex-R7