Lines Matching refs:R5
159 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); in pmz_load_zsregs()
191 write_zsreg(uap, R5, regs[R5]); in pmz_load_zsregs()
582 uap->curregs[R5] |= set_bits; in pmz_set_mctrl()
583 uap->curregs[R5] &= ~clear_bits; in pmz_set_mctrl()
585 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_set_mctrl()
587 set_bits, clear_bits, uap->curregs[R5]); in pmz_set_mctrl()
728 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; in pmz_break_ctl()
729 if (new_reg != uap->curregs[R5]) { in pmz_break_ctl()
730 uap->curregs[R5] = new_reg; in pmz_break_ctl()
731 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_break_ctl()
877 uap->curregs[R5] = Tx8 | RTS; in __pmz_startup()
879 uap->curregs[R5] |= DTR; in __pmz_startup()
894 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); in __pmz_startup()
907 uap->curregs[R5] |= DTR; in pmz_irda_reset()
908 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_reset()
914 uap->curregs[R5] &= ~DTR; in pmz_irda_reset()
915 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_reset()
988 uap->curregs[R5] &= ~TxENABLE; in pmz_shutdown()
991 uap->curregs[R5] &= ~SND_BRK; in pmz_shutdown()
1188 uap->curregs[R5] |= DTR; in pmz_irda_setup()
1189 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_setup()
1238 uap->curregs[R5] &= ~DTR; in pmz_irda_setup()
1239 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_setup()
1980 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); in pmz_console_write()