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Searched refs:CLK (Results 1 – 48 of 48) sorted by relevance

/linux-4.1.27/arch/c6x/platforms/
Dplldata.c157 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
158 CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
159 CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
160 CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
161 CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
162 CLK(NULL, "core", &c6x_core_clk),
163 CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
164 CLK("watchdog", NULL, &c6x_watchdog_clk),
165 CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
166 CLK("", NULL, NULL)
[all …]
/linux-4.1.27/drivers/clk/ti/
Dclk-3xxx-legacy.c4249 CLK(NULL, "security_l4_ick2", &security_l4_ick2),
4250 CLK(NULL, "aes1_ick", &aes1_ick),
4251 CLK("omap_rng", "ick", &rng_ick),
4252 CLK("omap3-rom-rng", "ick", &rng_ick),
4253 CLK(NULL, "sha11_ick", &sha11_ick),
4254 CLK(NULL, "des1_ick", &des1_ick),
4255 CLK(NULL, "cam_mclk", &cam_mclk),
4256 CLK(NULL, "cam_ick", &cam_ick),
4257 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
4258 CLK(NULL, "security_l3_ick", &security_l3_ick),
[all …]
Dclock.h55 #define CLK(dev, con, ck) \ macro
/linux-4.1.27/arch/arm/mach-omap1/
Dclock_data.c675 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
676 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
678 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
679 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
680 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
681 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
682 CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
683 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
684 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
685 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
[all …]
Dclock.h29 #define CLK(dev, con, ck, cp) \ macro
/linux-4.1.27/arch/arm/mach-davinci/
Ddm646x.c323 CLK(NULL, "ref", &ref_clk),
324 CLK(NULL, "aux", &aux_clkin),
325 CLK(NULL, "pll1", &pll1_clk),
326 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
327 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
328 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
329 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
330 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
331 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
332 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
[all …]
Ddm644x.c288 CLK(NULL, "ref", &ref_clk),
289 CLK(NULL, "pll1", &pll1_clk),
290 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
291 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
292 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
293 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
294 CLK(NULL, "pll1_aux", &pll1_aux_clk),
295 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
296 CLK(NULL, "pll2", &pll2_clk),
297 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
[all …]
Ddm355.c340 CLK(NULL, "ref", &ref_clk),
341 CLK(NULL, "pll1", &pll1_clk),
342 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
343 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
344 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
345 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
346 CLK(NULL, "pll1_aux", &pll1_aux_clk),
347 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
348 CLK(NULL, "vpss_dac", &vpss_dac_clk),
349 CLK("vpss", "master", &vpss_master_clk),
[all …]
Ddm365.c428 CLK(NULL, "ref", &ref_clk),
429 CLK(NULL, "pll1", &pll1_clk),
430 CLK(NULL, "pll1_aux", &pll1_aux_clk),
431 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
432 CLK(NULL, "clkout0", &clkout0_clk),
433 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
434 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
435 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
436 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
437 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
[all …]
Dda850.c430 CLK(NULL, "ref", &ref_clk),
431 CLK(NULL, "pll0", &pll0_clk),
432 CLK(NULL, "pll0_aux", &pll0_aux_clk),
433 CLK(NULL, "pll0_sysclk1", &pll0_sysclk1),
434 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
435 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
436 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
437 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
438 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
439 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
[all …]
Dda830.c377 CLK(NULL, "ref", &ref_clk),
378 CLK(NULL, "pll0", &pll0_clk),
379 CLK(NULL, "pll0_aux", &pll0_aux_clk),
380 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
381 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
382 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
383 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
384 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
385 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
386 CLK("i2c_davinci.1", NULL, &i2c0_clk),
[all …]
Dclock.h120 #define CLK(dev, con, ck) \ macro
/linux-4.1.27/arch/blackfin/mach-bf609/
Dclock.c55 #define CLK(_clk, _devname, _conname) \ macro
379 CLK(sys_clkin, NULL, "SYS_CLKIN"),
380 CLK(pll_clk, NULL, "PLLCLK"),
381 CLK(cclk, NULL, "CCLK"),
382 CLK(cclk0, NULL, "CCLK0"),
383 CLK(cclk1, NULL, "CCLK1"),
384 CLK(sysclk, NULL, "SYSCLK"),
385 CLK(sclk0, NULL, "SCLK0"),
386 CLK(sclk1, NULL, "SCLK1"),
387 CLK(dclk, NULL, "DCLK"),
[all …]
/linux-4.1.27/drivers/staging/sm750fb/
Dddk750_mode.c42 dispControl &= FIELD_CLEAR(CRT_DISPLAY_CTRL, CLK); in displayControlAdjust_SM750LE()
47 dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL41); in displayControlAdjust_SM750LE()
49 dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL65); in displayControlAdjust_SM750LE()
51 dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL80); in displayControlAdjust_SM750LE()
53 dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL80); in displayControlAdjust_SM750LE()
55 dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL74); in displayControlAdjust_SM750LE()
57 dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL108); in displayControlAdjust_SM750LE()
59 dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL108); in displayControlAdjust_SM750LE()
61 dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL25); in displayControlAdjust_SM750LE()
Dddk750_power.c62 FIELD_SET( control_value, POWER_MODE_CTRL, 336CLK, OFF) | in setPowerMode()
70 FIELD_SET( control_value, POWER_MODE_CTRL, 336CLK, ON) | in setPowerMode()
/linux-4.1.27/Documentation/devicetree/bindings/video/
Dti,omap5-dss.txt73 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
95 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
Dti,omap4-dss.txt92 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
114 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
Dti,dra7-dss.txt68 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
Dti,omap3-dss.txt82 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
/linux-4.1.27/arch/arm/boot/dts/
Dste-href-family-pinctrl.dtsi236 "GPIO217_AH12"; /* CLK */
256 pins = "GPIO217_AH12"; /* CLK */
273 pins = "GPIO217_AH12"; /* CLK */
299 pins = "GPIO23_AA4"; /* CLK */
332 pins = "GPIO23_AA4"; /* CLK */
346 pins = "GPIO208_AH16"; /* CLK */
366 pins = "GPIO208_AH16"; /* CLK */
390 pins = "GPIO128_A5"; /* CLK */
414 pins = "GPIO128_A5"; /* CLK */
446 pins = "GPIO203_AE23"; /* CLK */
[all …]
Dda850.dtsi119 /* SIMO, SOMI, CLK */
Dste-snowball.dts466 "GPIO143_D12"; /* CLK */
Dam43x-epos-evm.dts283 /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
/linux-4.1.27/arch/arm/mach-pxa/
Dclock-pxa3xx.c40 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; in pxa3xx_get_clk_frequency_khz() local
57 CLK = (ro) ? RO_CLK : ((t) ? XN : XL); in pxa3xx_get_clk_frequency_khz()
73 return CLK / 1000; in pxa3xx_get_clk_frequency_khz()
/linux-4.1.27/drivers/gpu/drm/msm/dsi/
Dmmss_cc.xml.h49 CLK = 0, enumerator
58 case CLK: return 0x0000004c; in __offset_CLK()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dg84.c39 .base.handle = NV_SUBDEV(CLK, 0x84),
Dnv04.c96 .handle = NV_SUBDEV(CLK, 0x04),
Dnv40.c234 .handle = NV_SUBDEV(CLK, 0x40),
Dmcp77.c422 .handle = NV_SUBDEV(CLK, 0xaa),
Dgf100.c455 .handle = NV_SUBDEV(CLK, 0xc0),
Dgk104.c493 .handle = NV_SUBDEV(CLK, 0xe0),
Dgt215.c526 .handle = NV_SUBDEV(CLK, 0xa3),
Dnv50.c553 .base.handle = NV_SUBDEV(CLK, 0x50),
Dgk20a.c673 .handle = NV_SUBDEV(CLK, 0xea),
/linux-4.1.27/arch/c6x/include/asm/
Dclock.h124 #define CLK(dev, con, ck) \ macro
/linux-4.1.27/Documentation/devicetree/bindings/hwmon/
Dg762.txt8 on CLK pin of the chip.
/linux-4.1.27/drivers/net/ethernet/cadence/
Dmacb.c1536 config = GEM_BF(CLK, GEM_CLK_DIV8); in gem_mdc_clk_div()
1538 config = GEM_BF(CLK, GEM_CLK_DIV16); in gem_mdc_clk_div()
1540 config = GEM_BF(CLK, GEM_CLK_DIV32); in gem_mdc_clk_div()
1542 config = GEM_BF(CLK, GEM_CLK_DIV48); in gem_mdc_clk_div()
1544 config = GEM_BF(CLK, GEM_CLK_DIV64); in gem_mdc_clk_div()
1546 config = GEM_BF(CLK, GEM_CLK_DIV96); in gem_mdc_clk_div()
1561 config = MACB_BF(CLK, MACB_CLK_DIV8); in macb_mdc_clk_div()
1563 config = MACB_BF(CLK, MACB_CLK_DIV16); in macb_mdc_clk_div()
1565 config = MACB_BF(CLK, MACB_CLK_DIV32); in macb_mdc_clk_div()
1567 config = MACB_BF(CLK, MACB_CLK_DIV64); in macb_mdc_clk_div()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/regulator/
Dtps6586x.txt85 regulator-name = "PCIE CLK";
/linux-4.1.27/arch/arm/mach-omap2/
Dclock.h31 #define CLK(dev, con, ck) \ macro
/linux-4.1.27/drivers/media/dvb-frontends/
Dbcm3510_priv.h151 u8 CLK :1; member
/linux-4.1.27/drivers/video/fbdev/via/
Dhw.h644 void viafb_set_vclock(u32 CLK, int set_iga);
/linux-4.1.27/drivers/pinctrl/
Dpinctrl-tegra210.c1446 …PINGROUP(clk_32k_in, CLK, RSVD1, RSVD2, RSVD3, 0x3160, N, N, N, 0x…
Dpinctrl-tegra114.c1755 …PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N…
Dpinctrl-tegra124.c1952 …PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N…
/linux-4.1.27/drivers/mtd/nand/
Datmel_nand.c1050 pmecc_writel(host->ecc, CLK, 2); in atmel_pmecc_core_init()
/linux-4.1.27/Documentation/
Dpinctrl.txt437 (these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
Dkernel-parameters.txt57 CLK Common clock infrastructure is enabled.
608 [CLK]
/linux-4.1.27/
DMAINTAINERS2584 CLK API
2644 COMMON CLK FRAMEWORK