1/* 2 * TI DaVinci DM365 chip specific setup 3 * 4 * Copyright (C) 2009 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15#include <linux/init.h> 16#include <linux/clk.h> 17#include <linux/serial_8250.h> 18#include <linux/platform_device.h> 19#include <linux/dma-mapping.h> 20#include <linux/spi/spi.h> 21#include <linux/platform_data/edma.h> 22#include <linux/platform_data/gpio-davinci.h> 23#include <linux/platform_data/keyscan-davinci.h> 24#include <linux/platform_data/spi-davinci.h> 25 26#include <asm/mach/map.h> 27 28#include <mach/cputype.h> 29#include <mach/psc.h> 30#include <mach/mux.h> 31#include <mach/irqs.h> 32#include <mach/time.h> 33#include <mach/serial.h> 34#include <mach/common.h> 35 36#include "davinci.h" 37#include "clock.h" 38#include "mux.h" 39#include "asp.h" 40 41#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ 42#define DM365_RTC_BASE 0x01c69000 43#define DM365_KEYSCAN_BASE 0x01c69400 44#define DM365_OSD_BASE 0x01c71c00 45#define DM365_VENC_BASE 0x01c71e00 46#define DAVINCI_DM365_VC_BASE 0x01d0c000 47#define DAVINCI_DMA_VC_TX 2 48#define DAVINCI_DMA_VC_RX 3 49#define DM365_EMAC_BASE 0x01d07000 50#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000) 51#define DM365_EMAC_CNTRL_OFFSET 0x0000 52#define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000 53#define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000 54#define DM365_EMAC_CNTRL_RAM_SIZE 0x2000 55 56static struct pll_data pll1_data = { 57 .num = 1, 58 .phys_base = DAVINCI_PLL1_BASE, 59 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV, 60}; 61 62static struct pll_data pll2_data = { 63 .num = 2, 64 .phys_base = DAVINCI_PLL2_BASE, 65 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV, 66}; 67 68static struct clk ref_clk = { 69 .name = "ref_clk", 70 .rate = DM365_REF_FREQ, 71}; 72 73static struct clk pll1_clk = { 74 .name = "pll1", 75 .parent = &ref_clk, 76 .flags = CLK_PLL, 77 .pll_data = &pll1_data, 78}; 79 80static struct clk pll1_aux_clk = { 81 .name = "pll1_aux_clk", 82 .parent = &pll1_clk, 83 .flags = CLK_PLL | PRE_PLL, 84}; 85 86static struct clk pll1_sysclkbp = { 87 .name = "pll1_sysclkbp", 88 .parent = &pll1_clk, 89 .flags = CLK_PLL | PRE_PLL, 90 .div_reg = BPDIV 91}; 92 93static struct clk clkout0_clk = { 94 .name = "clkout0", 95 .parent = &pll1_clk, 96 .flags = CLK_PLL | PRE_PLL, 97}; 98 99static struct clk pll1_sysclk1 = { 100 .name = "pll1_sysclk1", 101 .parent = &pll1_clk, 102 .flags = CLK_PLL, 103 .div_reg = PLLDIV1, 104}; 105 106static struct clk pll1_sysclk2 = { 107 .name = "pll1_sysclk2", 108 .parent = &pll1_clk, 109 .flags = CLK_PLL, 110 .div_reg = PLLDIV2, 111}; 112 113static struct clk pll1_sysclk3 = { 114 .name = "pll1_sysclk3", 115 .parent = &pll1_clk, 116 .flags = CLK_PLL, 117 .div_reg = PLLDIV3, 118}; 119 120static struct clk pll1_sysclk4 = { 121 .name = "pll1_sysclk4", 122 .parent = &pll1_clk, 123 .flags = CLK_PLL, 124 .div_reg = PLLDIV4, 125}; 126 127static struct clk pll1_sysclk5 = { 128 .name = "pll1_sysclk5", 129 .parent = &pll1_clk, 130 .flags = CLK_PLL, 131 .div_reg = PLLDIV5, 132}; 133 134static struct clk pll1_sysclk6 = { 135 .name = "pll1_sysclk6", 136 .parent = &pll1_clk, 137 .flags = CLK_PLL, 138 .div_reg = PLLDIV6, 139}; 140 141static struct clk pll1_sysclk7 = { 142 .name = "pll1_sysclk7", 143 .parent = &pll1_clk, 144 .flags = CLK_PLL, 145 .div_reg = PLLDIV7, 146}; 147 148static struct clk pll1_sysclk8 = { 149 .name = "pll1_sysclk8", 150 .parent = &pll1_clk, 151 .flags = CLK_PLL, 152 .div_reg = PLLDIV8, 153}; 154 155static struct clk pll1_sysclk9 = { 156 .name = "pll1_sysclk9", 157 .parent = &pll1_clk, 158 .flags = CLK_PLL, 159 .div_reg = PLLDIV9, 160}; 161 162static struct clk pll2_clk = { 163 .name = "pll2", 164 .parent = &ref_clk, 165 .flags = CLK_PLL, 166 .pll_data = &pll2_data, 167}; 168 169static struct clk pll2_aux_clk = { 170 .name = "pll2_aux_clk", 171 .parent = &pll2_clk, 172 .flags = CLK_PLL | PRE_PLL, 173}; 174 175static struct clk clkout1_clk = { 176 .name = "clkout1", 177 .parent = &pll2_clk, 178 .flags = CLK_PLL | PRE_PLL, 179}; 180 181static struct clk pll2_sysclk1 = { 182 .name = "pll2_sysclk1", 183 .parent = &pll2_clk, 184 .flags = CLK_PLL, 185 .div_reg = PLLDIV1, 186}; 187 188static struct clk pll2_sysclk2 = { 189 .name = "pll2_sysclk2", 190 .parent = &pll2_clk, 191 .flags = CLK_PLL, 192 .div_reg = PLLDIV2, 193}; 194 195static struct clk pll2_sysclk3 = { 196 .name = "pll2_sysclk3", 197 .parent = &pll2_clk, 198 .flags = CLK_PLL, 199 .div_reg = PLLDIV3, 200}; 201 202static struct clk pll2_sysclk4 = { 203 .name = "pll2_sysclk4", 204 .parent = &pll2_clk, 205 .flags = CLK_PLL, 206 .div_reg = PLLDIV4, 207}; 208 209static struct clk pll2_sysclk5 = { 210 .name = "pll2_sysclk5", 211 .parent = &pll2_clk, 212 .flags = CLK_PLL, 213 .div_reg = PLLDIV5, 214}; 215 216static struct clk pll2_sysclk6 = { 217 .name = "pll2_sysclk6", 218 .parent = &pll2_clk, 219 .flags = CLK_PLL, 220 .div_reg = PLLDIV6, 221}; 222 223static struct clk pll2_sysclk7 = { 224 .name = "pll2_sysclk7", 225 .parent = &pll2_clk, 226 .flags = CLK_PLL, 227 .div_reg = PLLDIV7, 228}; 229 230static struct clk pll2_sysclk8 = { 231 .name = "pll2_sysclk8", 232 .parent = &pll2_clk, 233 .flags = CLK_PLL, 234 .div_reg = PLLDIV8, 235}; 236 237static struct clk pll2_sysclk9 = { 238 .name = "pll2_sysclk9", 239 .parent = &pll2_clk, 240 .flags = CLK_PLL, 241 .div_reg = PLLDIV9, 242}; 243 244static struct clk vpss_dac_clk = { 245 .name = "vpss_dac", 246 .parent = &pll1_sysclk3, 247 .lpsc = DM365_LPSC_DAC_CLK, 248}; 249 250static struct clk vpss_master_clk = { 251 .name = "vpss_master", 252 .parent = &pll1_sysclk5, 253 .lpsc = DM365_LPSC_VPSSMSTR, 254 .flags = CLK_PSC, 255}; 256 257static struct clk vpss_slave_clk = { 258 .name = "vpss_slave", 259 .parent = &pll1_sysclk5, 260 .lpsc = DAVINCI_LPSC_VPSSSLV, 261}; 262 263static struct clk arm_clk = { 264 .name = "arm_clk", 265 .parent = &pll2_sysclk2, 266 .lpsc = DAVINCI_LPSC_ARM, 267 .flags = ALWAYS_ENABLED, 268}; 269 270static struct clk uart0_clk = { 271 .name = "uart0", 272 .parent = &pll1_aux_clk, 273 .lpsc = DAVINCI_LPSC_UART0, 274}; 275 276static struct clk uart1_clk = { 277 .name = "uart1", 278 .parent = &pll1_sysclk4, 279 .lpsc = DAVINCI_LPSC_UART1, 280}; 281 282static struct clk i2c_clk = { 283 .name = "i2c", 284 .parent = &pll1_aux_clk, 285 .lpsc = DAVINCI_LPSC_I2C, 286}; 287 288static struct clk mmcsd0_clk = { 289 .name = "mmcsd0", 290 .parent = &pll1_sysclk8, 291 .lpsc = DAVINCI_LPSC_MMC_SD, 292}; 293 294static struct clk mmcsd1_clk = { 295 .name = "mmcsd1", 296 .parent = &pll1_sysclk4, 297 .lpsc = DM365_LPSC_MMC_SD1, 298}; 299 300static struct clk spi0_clk = { 301 .name = "spi0", 302 .parent = &pll1_sysclk4, 303 .lpsc = DAVINCI_LPSC_SPI, 304}; 305 306static struct clk spi1_clk = { 307 .name = "spi1", 308 .parent = &pll1_sysclk4, 309 .lpsc = DM365_LPSC_SPI1, 310}; 311 312static struct clk spi2_clk = { 313 .name = "spi2", 314 .parent = &pll1_sysclk4, 315 .lpsc = DM365_LPSC_SPI2, 316}; 317 318static struct clk spi3_clk = { 319 .name = "spi3", 320 .parent = &pll1_sysclk4, 321 .lpsc = DM365_LPSC_SPI3, 322}; 323 324static struct clk spi4_clk = { 325 .name = "spi4", 326 .parent = &pll1_aux_clk, 327 .lpsc = DM365_LPSC_SPI4, 328}; 329 330static struct clk gpio_clk = { 331 .name = "gpio", 332 .parent = &pll1_sysclk4, 333 .lpsc = DAVINCI_LPSC_GPIO, 334}; 335 336static struct clk aemif_clk = { 337 .name = "aemif", 338 .parent = &pll1_sysclk4, 339 .lpsc = DAVINCI_LPSC_AEMIF, 340}; 341 342static struct clk pwm0_clk = { 343 .name = "pwm0", 344 .parent = &pll1_aux_clk, 345 .lpsc = DAVINCI_LPSC_PWM0, 346}; 347 348static struct clk pwm1_clk = { 349 .name = "pwm1", 350 .parent = &pll1_aux_clk, 351 .lpsc = DAVINCI_LPSC_PWM1, 352}; 353 354static struct clk pwm2_clk = { 355 .name = "pwm2", 356 .parent = &pll1_aux_clk, 357 .lpsc = DAVINCI_LPSC_PWM2, 358}; 359 360static struct clk pwm3_clk = { 361 .name = "pwm3", 362 .parent = &ref_clk, 363 .lpsc = DM365_LPSC_PWM3, 364}; 365 366static struct clk timer0_clk = { 367 .name = "timer0", 368 .parent = &pll1_aux_clk, 369 .lpsc = DAVINCI_LPSC_TIMER0, 370}; 371 372static struct clk timer1_clk = { 373 .name = "timer1", 374 .parent = &pll1_aux_clk, 375 .lpsc = DAVINCI_LPSC_TIMER1, 376}; 377 378static struct clk timer2_clk = { 379 .name = "timer2", 380 .parent = &pll1_aux_clk, 381 .lpsc = DAVINCI_LPSC_TIMER2, 382 .usecount = 1, 383}; 384 385static struct clk timer3_clk = { 386 .name = "timer3", 387 .parent = &pll1_aux_clk, 388 .lpsc = DM365_LPSC_TIMER3, 389}; 390 391static struct clk usb_clk = { 392 .name = "usb", 393 .parent = &pll1_aux_clk, 394 .lpsc = DAVINCI_LPSC_USB, 395}; 396 397static struct clk emac_clk = { 398 .name = "emac", 399 .parent = &pll1_sysclk4, 400 .lpsc = DM365_LPSC_EMAC, 401}; 402 403static struct clk voicecodec_clk = { 404 .name = "voice_codec", 405 .parent = &pll2_sysclk4, 406 .lpsc = DM365_LPSC_VOICE_CODEC, 407}; 408 409static struct clk asp0_clk = { 410 .name = "asp0", 411 .parent = &pll1_sysclk4, 412 .lpsc = DM365_LPSC_McBSP1, 413}; 414 415static struct clk rto_clk = { 416 .name = "rto", 417 .parent = &pll1_sysclk4, 418 .lpsc = DM365_LPSC_RTO, 419}; 420 421static struct clk mjcp_clk = { 422 .name = "mjcp", 423 .parent = &pll1_sysclk3, 424 .lpsc = DM365_LPSC_MJCP, 425}; 426 427static struct clk_lookup dm365_clks[] = { 428 CLK(NULL, "ref", &ref_clk), 429 CLK(NULL, "pll1", &pll1_clk), 430 CLK(NULL, "pll1_aux", &pll1_aux_clk), 431 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), 432 CLK(NULL, "clkout0", &clkout0_clk), 433 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), 434 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), 435 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), 436 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), 437 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), 438 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), 439 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), 440 CLK(NULL, "pll1_sysclk8", &pll1_sysclk8), 441 CLK(NULL, "pll1_sysclk9", &pll1_sysclk9), 442 CLK(NULL, "pll2", &pll2_clk), 443 CLK(NULL, "pll2_aux", &pll2_aux_clk), 444 CLK(NULL, "clkout1", &clkout1_clk), 445 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), 446 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2), 447 CLK(NULL, "pll2_sysclk3", &pll2_sysclk3), 448 CLK(NULL, "pll2_sysclk4", &pll2_sysclk4), 449 CLK(NULL, "pll2_sysclk5", &pll2_sysclk5), 450 CLK(NULL, "pll2_sysclk6", &pll2_sysclk6), 451 CLK(NULL, "pll2_sysclk7", &pll2_sysclk7), 452 CLK(NULL, "pll2_sysclk8", &pll2_sysclk8), 453 CLK(NULL, "pll2_sysclk9", &pll2_sysclk9), 454 CLK(NULL, "vpss_dac", &vpss_dac_clk), 455 CLK("vpss", "master", &vpss_master_clk), 456 CLK("vpss", "slave", &vpss_slave_clk), 457 CLK(NULL, "arm", &arm_clk), 458 CLK("serial8250.0", NULL, &uart0_clk), 459 CLK("serial8250.1", NULL, &uart1_clk), 460 CLK("i2c_davinci.1", NULL, &i2c_clk), 461 CLK("da830-mmc.0", NULL, &mmcsd0_clk), 462 CLK("da830-mmc.1", NULL, &mmcsd1_clk), 463 CLK("spi_davinci.0", NULL, &spi0_clk), 464 CLK("spi_davinci.1", NULL, &spi1_clk), 465 CLK("spi_davinci.2", NULL, &spi2_clk), 466 CLK("spi_davinci.3", NULL, &spi3_clk), 467 CLK("spi_davinci.4", NULL, &spi4_clk), 468 CLK(NULL, "gpio", &gpio_clk), 469 CLK(NULL, "aemif", &aemif_clk), 470 CLK(NULL, "pwm0", &pwm0_clk), 471 CLK(NULL, "pwm1", &pwm1_clk), 472 CLK(NULL, "pwm2", &pwm2_clk), 473 CLK(NULL, "pwm3", &pwm3_clk), 474 CLK(NULL, "timer0", &timer0_clk), 475 CLK(NULL, "timer1", &timer1_clk), 476 CLK("davinci-wdt", NULL, &timer2_clk), 477 CLK(NULL, "timer3", &timer3_clk), 478 CLK(NULL, "usb", &usb_clk), 479 CLK("davinci_emac.1", NULL, &emac_clk), 480 CLK("davinci_mdio.0", "fck", &emac_clk), 481 CLK("davinci_voicecodec", NULL, &voicecodec_clk), 482 CLK("davinci-mcbsp", NULL, &asp0_clk), 483 CLK(NULL, "rto", &rto_clk), 484 CLK(NULL, "mjcp", &mjcp_clk), 485 CLK(NULL, NULL, NULL), 486}; 487 488/*----------------------------------------------------------------------*/ 489 490#define INTMUX 0x18 491#define EVTMUX 0x1c 492 493 494static const struct mux_config dm365_pins[] = { 495#ifdef CONFIG_DAVINCI_MUX 496MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false) 497 498MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false) 499MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false) 500MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false) 501MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false) 502MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false) 503MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false) 504 505MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false) 506MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false) 507 508MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false) 509MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false) 510MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false) 511MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false) 512MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false) 513MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false) 514MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false) 515MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false) 516 517MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false) 518MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false) 519MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false) 520MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false) 521MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false) 522MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false) 523 524MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false) 525MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false) 526MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false) 527MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false) 528MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false) 529 530MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false) 531MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false) 532MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false) 533MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false) 534MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false) 535MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false) 536 537MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false) 538MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false) 539MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false) 540MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false) 541MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false) 542MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false) 543MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false) 544MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false) 545MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false) 546MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false) 547MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false) 548MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false) 549MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false) 550MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false) 551MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false) 552MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false) 553MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false) 554 555MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false) 556 557MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false) 558MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false) 559MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false) 560MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false) 561MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false) 562MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false) 563MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false) 564MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false) 565MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false) 566MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false) 567MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false) 568MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false) 569 570MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false) 571MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false) 572MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false) 573MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false) 574MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false) 575 576MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false) 577MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false) 578MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false) 579MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false) 580MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false) 581 582MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false) 583MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false) 584MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false) 585MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false) 586MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false) 587 588MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false) 589MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false) 590MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false) 591MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false) 592MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false) 593 594MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false) 595MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false) 596MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false) 597 598MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false) 599MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false) 600MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false) 601MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false) 602MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false) 603MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false) 604MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false) 605 606MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false) 607MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false) 608MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false) 609MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) 610MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) 611MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false) 612MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false) 613MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false) 614MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false) 615MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false) 616 617INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false) 618INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false) 619INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false) 620INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false) 621INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false) 622INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false) 623INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false) 624INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false) 625INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false) 626INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false) 627INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false) 628INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false) 629INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false) 630INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false) 631INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false) 632INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false) 633INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false) 634INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false) 635 636EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false) 637EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false) 638EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false) 639EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false) 640#endif 641}; 642 643static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); 644 645static struct davinci_spi_platform_data dm365_spi0_pdata = { 646 .version = SPI_VERSION_1, 647 .num_chipselect = 2, 648 .dma_event_q = EVENTQ_3, 649}; 650 651static struct resource dm365_spi0_resources[] = { 652 { 653 .start = 0x01c66000, 654 .end = 0x01c667ff, 655 .flags = IORESOURCE_MEM, 656 }, 657 { 658 .start = IRQ_DM365_SPIINT0_0, 659 .flags = IORESOURCE_IRQ, 660 }, 661 { 662 .start = 17, 663 .flags = IORESOURCE_DMA, 664 }, 665 { 666 .start = 16, 667 .flags = IORESOURCE_DMA, 668 }, 669}; 670 671static struct platform_device dm365_spi0_device = { 672 .name = "spi_davinci", 673 .id = 0, 674 .dev = { 675 .dma_mask = &dm365_spi0_dma_mask, 676 .coherent_dma_mask = DMA_BIT_MASK(32), 677 .platform_data = &dm365_spi0_pdata, 678 }, 679 .num_resources = ARRAY_SIZE(dm365_spi0_resources), 680 .resource = dm365_spi0_resources, 681}; 682 683void __init dm365_init_spi0(unsigned chipselect_mask, 684 const struct spi_board_info *info, unsigned len) 685{ 686 davinci_cfg_reg(DM365_SPI0_SCLK); 687 davinci_cfg_reg(DM365_SPI0_SDI); 688 davinci_cfg_reg(DM365_SPI0_SDO); 689 690 /* not all slaves will be wired up */ 691 if (chipselect_mask & BIT(0)) 692 davinci_cfg_reg(DM365_SPI0_SDENA0); 693 if (chipselect_mask & BIT(1)) 694 davinci_cfg_reg(DM365_SPI0_SDENA1); 695 696 spi_register_board_info(info, len); 697 698 platform_device_register(&dm365_spi0_device); 699} 700 701static struct resource dm365_gpio_resources[] = { 702 { /* registers */ 703 .start = DAVINCI_GPIO_BASE, 704 .end = DAVINCI_GPIO_BASE + SZ_4K - 1, 705 .flags = IORESOURCE_MEM, 706 }, 707 { /* interrupt */ 708 .start = IRQ_DM365_GPIO0, 709 .end = IRQ_DM365_GPIO7, 710 .flags = IORESOURCE_IRQ, 711 }, 712}; 713 714static struct davinci_gpio_platform_data dm365_gpio_platform_data = { 715 .ngpio = 104, 716 .gpio_unbanked = 8, 717}; 718 719int __init dm365_gpio_register(void) 720{ 721 return davinci_gpio_register(dm365_gpio_resources, 722 ARRAY_SIZE(dm365_gpio_resources), 723 &dm365_gpio_platform_data); 724} 725 726static struct emac_platform_data dm365_emac_pdata = { 727 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET, 728 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET, 729 .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET, 730 .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE, 731 .version = EMAC_VERSION_2, 732}; 733 734static struct resource dm365_emac_resources[] = { 735 { 736 .start = DM365_EMAC_BASE, 737 .end = DM365_EMAC_BASE + SZ_16K - 1, 738 .flags = IORESOURCE_MEM, 739 }, 740 { 741 .start = IRQ_DM365_EMAC_RXTHRESH, 742 .end = IRQ_DM365_EMAC_RXTHRESH, 743 .flags = IORESOURCE_IRQ, 744 }, 745 { 746 .start = IRQ_DM365_EMAC_RXPULSE, 747 .end = IRQ_DM365_EMAC_RXPULSE, 748 .flags = IORESOURCE_IRQ, 749 }, 750 { 751 .start = IRQ_DM365_EMAC_TXPULSE, 752 .end = IRQ_DM365_EMAC_TXPULSE, 753 .flags = IORESOURCE_IRQ, 754 }, 755 { 756 .start = IRQ_DM365_EMAC_MISCPULSE, 757 .end = IRQ_DM365_EMAC_MISCPULSE, 758 .flags = IORESOURCE_IRQ, 759 }, 760}; 761 762static struct platform_device dm365_emac_device = { 763 .name = "davinci_emac", 764 .id = 1, 765 .dev = { 766 .platform_data = &dm365_emac_pdata, 767 }, 768 .num_resources = ARRAY_SIZE(dm365_emac_resources), 769 .resource = dm365_emac_resources, 770}; 771 772static struct resource dm365_mdio_resources[] = { 773 { 774 .start = DM365_EMAC_MDIO_BASE, 775 .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1, 776 .flags = IORESOURCE_MEM, 777 }, 778}; 779 780static struct platform_device dm365_mdio_device = { 781 .name = "davinci_mdio", 782 .id = 0, 783 .num_resources = ARRAY_SIZE(dm365_mdio_resources), 784 .resource = dm365_mdio_resources, 785}; 786 787static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { 788 [IRQ_VDINT0] = 2, 789 [IRQ_VDINT1] = 6, 790 [IRQ_VDINT2] = 6, 791 [IRQ_HISTINT] = 6, 792 [IRQ_H3AINT] = 6, 793 [IRQ_PRVUINT] = 6, 794 [IRQ_RSZINT] = 6, 795 [IRQ_DM365_INSFINT] = 7, 796 [IRQ_VENCINT] = 6, 797 [IRQ_ASQINT] = 6, 798 [IRQ_IMXINT] = 6, 799 [IRQ_DM365_IMCOPINT] = 4, 800 [IRQ_USBINT] = 4, 801 [IRQ_DM365_RTOINT] = 7, 802 [IRQ_DM365_TINT5] = 7, 803 [IRQ_DM365_TINT6] = 5, 804 [IRQ_CCINT0] = 5, 805 [IRQ_CCERRINT] = 5, 806 [IRQ_TCERRINT0] = 5, 807 [IRQ_TCERRINT] = 7, 808 [IRQ_PSCIN] = 4, 809 [IRQ_DM365_SPINT2_1] = 7, 810 [IRQ_DM365_TINT7] = 7, 811 [IRQ_DM365_SDIOINT0] = 7, 812 [IRQ_MBXINT] = 7, 813 [IRQ_MBRINT] = 7, 814 [IRQ_MMCINT] = 7, 815 [IRQ_DM365_MMCINT1] = 7, 816 [IRQ_DM365_PWMINT3] = 7, 817 [IRQ_AEMIFINT] = 2, 818 [IRQ_DM365_SDIOINT1] = 2, 819 [IRQ_TINT0_TINT12] = 7, 820 [IRQ_TINT0_TINT34] = 7, 821 [IRQ_TINT1_TINT12] = 7, 822 [IRQ_TINT1_TINT34] = 7, 823 [IRQ_PWMINT0] = 7, 824 [IRQ_PWMINT1] = 3, 825 [IRQ_PWMINT2] = 3, 826 [IRQ_I2C] = 3, 827 [IRQ_UARTINT0] = 3, 828 [IRQ_UARTINT1] = 3, 829 [IRQ_DM365_RTCINT] = 3, 830 [IRQ_DM365_SPIINT0_0] = 3, 831 [IRQ_DM365_SPIINT3_0] = 3, 832 [IRQ_DM365_GPIO0] = 3, 833 [IRQ_DM365_GPIO1] = 7, 834 [IRQ_DM365_GPIO2] = 4, 835 [IRQ_DM365_GPIO3] = 4, 836 [IRQ_DM365_GPIO4] = 7, 837 [IRQ_DM365_GPIO5] = 7, 838 [IRQ_DM365_GPIO6] = 7, 839 [IRQ_DM365_GPIO7] = 7, 840 [IRQ_DM365_EMAC_RXTHRESH] = 7, 841 [IRQ_DM365_EMAC_RXPULSE] = 7, 842 [IRQ_DM365_EMAC_TXPULSE] = 7, 843 [IRQ_DM365_EMAC_MISCPULSE] = 7, 844 [IRQ_DM365_GPIO12] = 7, 845 [IRQ_DM365_GPIO13] = 7, 846 [IRQ_DM365_GPIO14] = 7, 847 [IRQ_DM365_GPIO15] = 7, 848 [IRQ_DM365_KEYINT] = 7, 849 [IRQ_DM365_TCERRINT2] = 7, 850 [IRQ_DM365_TCERRINT3] = 7, 851 [IRQ_DM365_EMUINT] = 7, 852}; 853 854/* Four Transfer Controllers on DM365 */ 855static s8 856dm365_queue_priority_mapping[][2] = { 857 /* {event queue no, Priority} */ 858 {0, 7}, 859 {1, 7}, 860 {2, 7}, 861 {3, 0}, 862 {-1, -1}, 863}; 864 865static struct edma_soc_info edma_cc0_info = { 866 .queue_priority_mapping = dm365_queue_priority_mapping, 867 .default_queue = EVENTQ_3, 868}; 869 870static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = { 871 &edma_cc0_info, 872}; 873 874static struct resource edma_resources[] = { 875 { 876 .name = "edma_cc0", 877 .start = 0x01c00000, 878 .end = 0x01c00000 + SZ_64K - 1, 879 .flags = IORESOURCE_MEM, 880 }, 881 { 882 .name = "edma_tc0", 883 .start = 0x01c10000, 884 .end = 0x01c10000 + SZ_1K - 1, 885 .flags = IORESOURCE_MEM, 886 }, 887 { 888 .name = "edma_tc1", 889 .start = 0x01c10400, 890 .end = 0x01c10400 + SZ_1K - 1, 891 .flags = IORESOURCE_MEM, 892 }, 893 { 894 .name = "edma_tc2", 895 .start = 0x01c10800, 896 .end = 0x01c10800 + SZ_1K - 1, 897 .flags = IORESOURCE_MEM, 898 }, 899 { 900 .name = "edma_tc3", 901 .start = 0x01c10c00, 902 .end = 0x01c10c00 + SZ_1K - 1, 903 .flags = IORESOURCE_MEM, 904 }, 905 { 906 .name = "edma0", 907 .start = IRQ_CCINT0, 908 .flags = IORESOURCE_IRQ, 909 }, 910 { 911 .name = "edma0_err", 912 .start = IRQ_CCERRINT, 913 .flags = IORESOURCE_IRQ, 914 }, 915 /* not using TC*_ERR */ 916}; 917 918static struct platform_device dm365_edma_device = { 919 .name = "edma", 920 .id = 0, 921 .dev.platform_data = dm365_edma_info, 922 .num_resources = ARRAY_SIZE(edma_resources), 923 .resource = edma_resources, 924}; 925 926static struct resource dm365_asp_resources[] = { 927 { 928 .name = "mpu", 929 .start = DAVINCI_DM365_ASP0_BASE, 930 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1, 931 .flags = IORESOURCE_MEM, 932 }, 933 { 934 .start = DAVINCI_DMA_ASP0_TX, 935 .end = DAVINCI_DMA_ASP0_TX, 936 .flags = IORESOURCE_DMA, 937 }, 938 { 939 .start = DAVINCI_DMA_ASP0_RX, 940 .end = DAVINCI_DMA_ASP0_RX, 941 .flags = IORESOURCE_DMA, 942 }, 943}; 944 945static struct platform_device dm365_asp_device = { 946 .name = "davinci-mcbsp", 947 .id = -1, 948 .num_resources = ARRAY_SIZE(dm365_asp_resources), 949 .resource = dm365_asp_resources, 950}; 951 952static struct resource dm365_vc_resources[] = { 953 { 954 .start = DAVINCI_DM365_VC_BASE, 955 .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1, 956 .flags = IORESOURCE_MEM, 957 }, 958 { 959 .start = DAVINCI_DMA_VC_TX, 960 .end = DAVINCI_DMA_VC_TX, 961 .flags = IORESOURCE_DMA, 962 }, 963 { 964 .start = DAVINCI_DMA_VC_RX, 965 .end = DAVINCI_DMA_VC_RX, 966 .flags = IORESOURCE_DMA, 967 }, 968}; 969 970static struct platform_device dm365_vc_device = { 971 .name = "davinci_voicecodec", 972 .id = -1, 973 .num_resources = ARRAY_SIZE(dm365_vc_resources), 974 .resource = dm365_vc_resources, 975}; 976 977static struct resource dm365_rtc_resources[] = { 978 { 979 .start = DM365_RTC_BASE, 980 .end = DM365_RTC_BASE + SZ_1K - 1, 981 .flags = IORESOURCE_MEM, 982 }, 983 { 984 .start = IRQ_DM365_RTCINT, 985 .flags = IORESOURCE_IRQ, 986 }, 987}; 988 989static struct platform_device dm365_rtc_device = { 990 .name = "rtc_davinci", 991 .id = 0, 992 .num_resources = ARRAY_SIZE(dm365_rtc_resources), 993 .resource = dm365_rtc_resources, 994}; 995 996static struct map_desc dm365_io_desc[] = { 997 { 998 .virtual = IO_VIRT, 999 .pfn = __phys_to_pfn(IO_PHYS), 1000 .length = IO_SIZE, 1001 .type = MT_DEVICE 1002 }, 1003}; 1004 1005static struct resource dm365_ks_resources[] = { 1006 { 1007 /* registers */ 1008 .start = DM365_KEYSCAN_BASE, 1009 .end = DM365_KEYSCAN_BASE + SZ_1K - 1, 1010 .flags = IORESOURCE_MEM, 1011 }, 1012 { 1013 /* interrupt */ 1014 .start = IRQ_DM365_KEYINT, 1015 .end = IRQ_DM365_KEYINT, 1016 .flags = IORESOURCE_IRQ, 1017 }, 1018}; 1019 1020static struct platform_device dm365_ks_device = { 1021 .name = "davinci_keyscan", 1022 .id = 0, 1023 .num_resources = ARRAY_SIZE(dm365_ks_resources), 1024 .resource = dm365_ks_resources, 1025}; 1026 1027/* Contents of JTAG ID register used to identify exact cpu type */ 1028static struct davinci_id dm365_ids[] = { 1029 { 1030 .variant = 0x0, 1031 .part_no = 0xb83e, 1032 .manufacturer = 0x017, 1033 .cpu_id = DAVINCI_CPU_ID_DM365, 1034 .name = "dm365_rev1.1", 1035 }, 1036 { 1037 .variant = 0x8, 1038 .part_no = 0xb83e, 1039 .manufacturer = 0x017, 1040 .cpu_id = DAVINCI_CPU_ID_DM365, 1041 .name = "dm365_rev1.2", 1042 }, 1043}; 1044 1045static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; 1046 1047static struct davinci_timer_info dm365_timer_info = { 1048 .timers = davinci_timer_instance, 1049 .clockevent_id = T0_BOT, 1050 .clocksource_id = T0_TOP, 1051}; 1052 1053#define DM365_UART1_BASE (IO_PHYS + 0x106000) 1054 1055static struct plat_serial8250_port dm365_serial0_platform_data[] = { 1056 { 1057 .mapbase = DAVINCI_UART0_BASE, 1058 .irq = IRQ_UARTINT0, 1059 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 1060 UPF_IOREMAP, 1061 .iotype = UPIO_MEM, 1062 .regshift = 2, 1063 }, 1064 { 1065 .flags = 0, 1066 } 1067}; 1068static struct plat_serial8250_port dm365_serial1_platform_data[] = { 1069 { 1070 .mapbase = DM365_UART1_BASE, 1071 .irq = IRQ_UARTINT1, 1072 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 1073 UPF_IOREMAP, 1074 .iotype = UPIO_MEM, 1075 .regshift = 2, 1076 }, 1077 { 1078 .flags = 0, 1079 } 1080}; 1081 1082struct platform_device dm365_serial_device[] = { 1083 { 1084 .name = "serial8250", 1085 .id = PLAT8250_DEV_PLATFORM, 1086 .dev = { 1087 .platform_data = dm365_serial0_platform_data, 1088 } 1089 }, 1090 { 1091 .name = "serial8250", 1092 .id = PLAT8250_DEV_PLATFORM1, 1093 .dev = { 1094 .platform_data = dm365_serial1_platform_data, 1095 } 1096 }, 1097 { 1098 } 1099}; 1100 1101static struct davinci_soc_info davinci_soc_info_dm365 = { 1102 .io_desc = dm365_io_desc, 1103 .io_desc_num = ARRAY_SIZE(dm365_io_desc), 1104 .jtag_id_reg = 0x01c40028, 1105 .ids = dm365_ids, 1106 .ids_num = ARRAY_SIZE(dm365_ids), 1107 .cpu_clks = dm365_clks, 1108 .psc_bases = dm365_psc_bases, 1109 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases), 1110 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, 1111 .pinmux_pins = dm365_pins, 1112 .pinmux_pins_num = ARRAY_SIZE(dm365_pins), 1113 .intc_base = DAVINCI_ARM_INTC_BASE, 1114 .intc_type = DAVINCI_INTC_TYPE_AINTC, 1115 .intc_irq_prios = dm365_default_priorities, 1116 .intc_irq_num = DAVINCI_N_AINTC_IRQ, 1117 .timer_info = &dm365_timer_info, 1118 .emac_pdata = &dm365_emac_pdata, 1119 .sram_dma = 0x00010000, 1120 .sram_len = SZ_32K, 1121}; 1122 1123void __init dm365_init_asp(struct snd_platform_data *pdata) 1124{ 1125 davinci_cfg_reg(DM365_MCBSP0_BDX); 1126 davinci_cfg_reg(DM365_MCBSP0_X); 1127 davinci_cfg_reg(DM365_MCBSP0_BFSX); 1128 davinci_cfg_reg(DM365_MCBSP0_BDR); 1129 davinci_cfg_reg(DM365_MCBSP0_R); 1130 davinci_cfg_reg(DM365_MCBSP0_BFSR); 1131 davinci_cfg_reg(DM365_EVT2_ASP_TX); 1132 davinci_cfg_reg(DM365_EVT3_ASP_RX); 1133 dm365_asp_device.dev.platform_data = pdata; 1134 platform_device_register(&dm365_asp_device); 1135} 1136 1137void __init dm365_init_vc(struct snd_platform_data *pdata) 1138{ 1139 davinci_cfg_reg(DM365_EVT2_VC_TX); 1140 davinci_cfg_reg(DM365_EVT3_VC_RX); 1141 dm365_vc_device.dev.platform_data = pdata; 1142 platform_device_register(&dm365_vc_device); 1143} 1144 1145void __init dm365_init_ks(struct davinci_ks_platform_data *pdata) 1146{ 1147 dm365_ks_device.dev.platform_data = pdata; 1148 platform_device_register(&dm365_ks_device); 1149} 1150 1151void __init dm365_init_rtc(void) 1152{ 1153 davinci_cfg_reg(DM365_INT_PRTCSS); 1154 platform_device_register(&dm365_rtc_device); 1155} 1156 1157void __init dm365_init(void) 1158{ 1159 davinci_common_init(&davinci_soc_info_dm365); 1160 davinci_map_sysmod(); 1161} 1162 1163static struct resource dm365_vpss_resources[] = { 1164 { 1165 /* VPSS ISP5 Base address */ 1166 .name = "isp5", 1167 .start = 0x01c70000, 1168 .end = 0x01c70000 + 0xff, 1169 .flags = IORESOURCE_MEM, 1170 }, 1171 { 1172 /* VPSS CLK Base address */ 1173 .name = "vpss", 1174 .start = 0x01c70200, 1175 .end = 0x01c70200 + 0xff, 1176 .flags = IORESOURCE_MEM, 1177 }, 1178}; 1179 1180static struct platform_device dm365_vpss_device = { 1181 .name = "vpss", 1182 .id = -1, 1183 .dev.platform_data = "dm365_vpss", 1184 .num_resources = ARRAY_SIZE(dm365_vpss_resources), 1185 .resource = dm365_vpss_resources, 1186}; 1187 1188static struct resource vpfe_resources[] = { 1189 { 1190 .start = IRQ_VDINT0, 1191 .end = IRQ_VDINT0, 1192 .flags = IORESOURCE_IRQ, 1193 }, 1194 { 1195 .start = IRQ_VDINT1, 1196 .end = IRQ_VDINT1, 1197 .flags = IORESOURCE_IRQ, 1198 }, 1199}; 1200 1201static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); 1202static struct platform_device vpfe_capture_dev = { 1203 .name = CAPTURE_DRV_NAME, 1204 .id = -1, 1205 .num_resources = ARRAY_SIZE(vpfe_resources), 1206 .resource = vpfe_resources, 1207 .dev = { 1208 .dma_mask = &vpfe_capture_dma_mask, 1209 .coherent_dma_mask = DMA_BIT_MASK(32), 1210 }, 1211}; 1212 1213static void dm365_isif_setup_pinmux(void) 1214{ 1215 davinci_cfg_reg(DM365_VIN_CAM_WEN); 1216 davinci_cfg_reg(DM365_VIN_CAM_VD); 1217 davinci_cfg_reg(DM365_VIN_CAM_HD); 1218 davinci_cfg_reg(DM365_VIN_YIN4_7_EN); 1219 davinci_cfg_reg(DM365_VIN_YIN0_3_EN); 1220} 1221 1222static struct resource isif_resource[] = { 1223 /* ISIF Base address */ 1224 { 1225 .start = 0x01c71000, 1226 .end = 0x01c71000 + 0x1ff, 1227 .flags = IORESOURCE_MEM, 1228 }, 1229 /* ISIF Linearization table 0 */ 1230 { 1231 .start = 0x1C7C000, 1232 .end = 0x1C7C000 + 0x2ff, 1233 .flags = IORESOURCE_MEM, 1234 }, 1235 /* ISIF Linearization table 1 */ 1236 { 1237 .start = 0x1C7C400, 1238 .end = 0x1C7C400 + 0x2ff, 1239 .flags = IORESOURCE_MEM, 1240 }, 1241}; 1242static struct platform_device dm365_isif_dev = { 1243 .name = "isif", 1244 .id = -1, 1245 .num_resources = ARRAY_SIZE(isif_resource), 1246 .resource = isif_resource, 1247 .dev = { 1248 .dma_mask = &vpfe_capture_dma_mask, 1249 .coherent_dma_mask = DMA_BIT_MASK(32), 1250 .platform_data = dm365_isif_setup_pinmux, 1251 }, 1252}; 1253 1254static struct resource dm365_osd_resources[] = { 1255 { 1256 .start = DM365_OSD_BASE, 1257 .end = DM365_OSD_BASE + 0xff, 1258 .flags = IORESOURCE_MEM, 1259 }, 1260}; 1261 1262static u64 dm365_video_dma_mask = DMA_BIT_MASK(32); 1263 1264static struct platform_device dm365_osd_dev = { 1265 .name = DM365_VPBE_OSD_SUBDEV_NAME, 1266 .id = -1, 1267 .num_resources = ARRAY_SIZE(dm365_osd_resources), 1268 .resource = dm365_osd_resources, 1269 .dev = { 1270 .dma_mask = &dm365_video_dma_mask, 1271 .coherent_dma_mask = DMA_BIT_MASK(32), 1272 }, 1273}; 1274 1275static struct resource dm365_venc_resources[] = { 1276 { 1277 .start = IRQ_VENCINT, 1278 .end = IRQ_VENCINT, 1279 .flags = IORESOURCE_IRQ, 1280 }, 1281 /* venc registers io space */ 1282 { 1283 .start = DM365_VENC_BASE, 1284 .end = DM365_VENC_BASE + 0x177, 1285 .flags = IORESOURCE_MEM, 1286 }, 1287 /* vdaccfg registers io space */ 1288 { 1289 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG, 1290 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3, 1291 .flags = IORESOURCE_MEM, 1292 }, 1293}; 1294 1295static struct resource dm365_v4l2_disp_resources[] = { 1296 { 1297 .start = IRQ_VENCINT, 1298 .end = IRQ_VENCINT, 1299 .flags = IORESOURCE_IRQ, 1300 }, 1301 /* venc registers io space */ 1302 { 1303 .start = DM365_VENC_BASE, 1304 .end = DM365_VENC_BASE + 0x177, 1305 .flags = IORESOURCE_MEM, 1306 }, 1307}; 1308 1309static int dm365_vpbe_setup_pinmux(u32 if_type, int field) 1310{ 1311 switch (if_type) { 1312 case MEDIA_BUS_FMT_SGRBG8_1X8: 1313 davinci_cfg_reg(DM365_VOUT_FIELD_G81); 1314 davinci_cfg_reg(DM365_VOUT_COUTL_EN); 1315 davinci_cfg_reg(DM365_VOUT_COUTH_EN); 1316 break; 1317 case MEDIA_BUS_FMT_YUYV10_1X20: 1318 if (field) 1319 davinci_cfg_reg(DM365_VOUT_FIELD); 1320 else 1321 davinci_cfg_reg(DM365_VOUT_FIELD_G81); 1322 davinci_cfg_reg(DM365_VOUT_COUTL_EN); 1323 davinci_cfg_reg(DM365_VOUT_COUTH_EN); 1324 break; 1325 default: 1326 return -EINVAL; 1327 } 1328 1329 return 0; 1330} 1331 1332static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type, 1333 unsigned int pclock) 1334{ 1335 void __iomem *vpss_clkctl_reg; 1336 u32 val; 1337 1338 vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL); 1339 1340 switch (type) { 1341 case VPBE_ENC_STD: 1342 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE; 1343 break; 1344 case VPBE_ENC_DV_TIMINGS: 1345 if (pclock <= 27000000) { 1346 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE; 1347 } else { 1348 /* set sysclk4 to output 74.25 MHz from pll1 */ 1349 val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE | 1350 VPSS_VENCCLKEN_ENABLE; 1351 } 1352 break; 1353 default: 1354 return -EINVAL; 1355 } 1356 writel(val, vpss_clkctl_reg); 1357 1358 return 0; 1359} 1360 1361static struct platform_device dm365_vpbe_display = { 1362 .name = "vpbe-v4l2", 1363 .id = -1, 1364 .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources), 1365 .resource = dm365_v4l2_disp_resources, 1366 .dev = { 1367 .dma_mask = &dm365_video_dma_mask, 1368 .coherent_dma_mask = DMA_BIT_MASK(32), 1369 }, 1370}; 1371 1372static struct venc_platform_data dm365_venc_pdata = { 1373 .setup_pinmux = dm365_vpbe_setup_pinmux, 1374 .setup_clock = dm365_venc_setup_clock, 1375}; 1376 1377static struct platform_device dm365_venc_dev = { 1378 .name = DM365_VPBE_VENC_SUBDEV_NAME, 1379 .id = -1, 1380 .num_resources = ARRAY_SIZE(dm365_venc_resources), 1381 .resource = dm365_venc_resources, 1382 .dev = { 1383 .dma_mask = &dm365_video_dma_mask, 1384 .coherent_dma_mask = DMA_BIT_MASK(32), 1385 .platform_data = (void *)&dm365_venc_pdata, 1386 }, 1387}; 1388 1389static struct platform_device dm365_vpbe_dev = { 1390 .name = "vpbe_controller", 1391 .id = -1, 1392 .dev = { 1393 .dma_mask = &dm365_video_dma_mask, 1394 .coherent_dma_mask = DMA_BIT_MASK(32), 1395 }, 1396}; 1397 1398int __init dm365_init_video(struct vpfe_config *vpfe_cfg, 1399 struct vpbe_config *vpbe_cfg) 1400{ 1401 if (vpfe_cfg || vpbe_cfg) 1402 platform_device_register(&dm365_vpss_device); 1403 1404 if (vpfe_cfg) { 1405 vpfe_capture_dev.dev.platform_data = vpfe_cfg; 1406 platform_device_register(&dm365_isif_dev); 1407 platform_device_register(&vpfe_capture_dev); 1408 } 1409 if (vpbe_cfg) { 1410 dm365_vpbe_dev.dev.platform_data = vpbe_cfg; 1411 platform_device_register(&dm365_osd_dev); 1412 platform_device_register(&dm365_venc_dev); 1413 platform_device_register(&dm365_vpbe_dev); 1414 platform_device_register(&dm365_vpbe_display); 1415 } 1416 1417 return 0; 1418} 1419 1420static int __init dm365_init_devices(void) 1421{ 1422 int ret = 0; 1423 1424 if (!cpu_is_davinci_dm365()) 1425 return 0; 1426 1427 davinci_cfg_reg(DM365_INT_EDMA_CC); 1428 platform_device_register(&dm365_edma_device); 1429 1430 platform_device_register(&dm365_mdio_device); 1431 platform_device_register(&dm365_emac_device); 1432 1433 ret = davinci_init_wdt(); 1434 if (ret) 1435 pr_warn("%s: watchdog init failed: %d\n", __func__, ret); 1436 1437 return ret; 1438} 1439postcore_initcall(dm365_init_devices); 1440