Searched refs:CFG (Results 1 - 108 of 108) sorted by relevance

/linux-4.1.27/scripts/kconfig/
H A Dmerge_config.sh105 for CFG in $CFG_LIST ; do
106 grep -q -w $CFG $TMP_FILE || continue
107 PREV_VAL=$(grep -w $CFG $TMP_FILE)
108 NEW_VAL=$(grep -w $CFG $MERGE_FILE)
110 echo Value of $CFG is redefined by fragment $MERGE_FILE:
115 echo Value of $CFG is redundant by fragment $MERGE_FILE:
117 sed -i "/$CFG[ =]/d" $TMP_FILE
146 for CFG in $(sed -n "$SED_CONFIG_EXP" $TMP_FILE); do
148 REQUESTED_VAL=$(grep -w -e "$CFG" $TMP_FILE)
149 ACTUAL_VAL=$(grep -w -e "$CFG" $OUTPUT/.config)
151 echo "Value requested for $CFG not in final .config"
/linux-4.1.27/arch/mips/include/asm/mips-boards/
H A Dbonito64.h413 #define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
416 #define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
417 #define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
419 #define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \
420 (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \
421 (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \
/linux-4.1.27/drivers/crypto/
H A Dmv_cesa.h110 * | ACCEL CFG | 4 * 8
126 * | ACCEL CFG | 4 * 8
/linux-4.1.27/arch/tile/include/arch/
H A Dtrio.h65 * Tile PIO Region Configuration - CFG Address Format.
67 * associated region is setup with TYPE=CFG.
/linux-4.1.27/include/linux/platform_data/
H A Ddma-atmel.h29 * @cfg: Platform-specific initializer for the CFG register
37 /* Platform-configurable bits in CFG */
/linux-4.1.27/sound/pci/vx222/
H A Dvx222.h35 unsigned int regCFG; /* current CFG register */
68 /* Constants used to access the CFG register (0x24). */
H A Dvx222_ops.c785 vx_outl(chip, CFG, chip->regCFG); vx2_change_audio_source()
800 vx_outl(chip, CFG, chip->regCFG); vx2_set_clock_source()
/linux-4.1.27/drivers/net/ethernet/intel/i40e/
H A Di40e_dcb.c54 * @tlv: IEEE 802.1Qaz ETS CFG TLV
55 * @dcbcfg: Local store to update ETS CFG data
57 * Parses IEEE 802.1Qaz ETS CFG TLV
180 * @tlv: IEEE 802.1Qaz PFC CFG TLV
181 * @dcbcfg: Local store to update PFC CFG data
183 * Parses IEEE 802.1Qaz PFC CFG TLV
/linux-4.1.27/arch/powerpc/platforms/pasemi/
H A Ddma_lib.c54 * @reg: Register to read (offset into PCI CFG space)
63 * @reg: Register to write to (offset into PCI CFG space)
74 * @reg: Register to read (offset into PCI CFG space)
84 * @reg: Register to write to (offset into PCI CFG space)
94 * @reg: Register to read (offset into PCI CFG space)
103 * @reg: Register to write to (offset into PCI CFG space)
/linux-4.1.27/drivers/net/ethernet/pasemi/
H A Dpasemi_mac.h124 /* MAC CFG register offsets */
135 /* MAC CFG register fields */
/linux-4.1.27/drivers/net/ethernet/cisco/enic/
H A Dvnic_resource.h28 /* The MAC address assigned to the CFG vNIC is fixed. */
/linux-4.1.27/sound/soc/codecs/
H A Dcs35l32.h28 /* Data CFG for DUAL device */
H A Dtas2552.h101 /* PDM CFG Register */
/linux-4.1.27/sound/soc/samsung/
H A Dsmdk_wm9713.c20 * Default CFG switch settings to use this driver:
H A Dsmdk_wm8580.c23 * Default CFG switch settings to use this driver:
H A Dsmdk_wm8994.c18 * Default CFG switch settings to use this driver:
/linux-4.1.27/drivers/ide/
H A Dcs5536.c46 CFG = 0, enumerator in enum:__anon4736
118 cs5536_read(pdev, CFG, &cfg); cs5536_cable_detect()
274 cs5536_read(dev, CFG, &cfg); cs5536_init_one()
/linux-4.1.27/drivers/ata/
H A Dpata_cs5536.c62 CFG = 0, enumerator in enum:__anon3312
146 cs5536_read(pdev, CFG, &cfg); cs5536_cable_detect()
280 cs5536_read(dev, CFG, &cfg); cs5536_init_one()
/linux-4.1.27/drivers/staging/sm750fb/
H A Dddk750_sii164.h152 * User Configuration Data registers (CFG 7:0)
/linux-4.1.27/arch/arm/mach-cns3xxx/
H A Dcns3xxx.h173 #define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */
176 #define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */
191 #define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */
194 #define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */
/linux-4.1.27/arch/alpha/kernel/
H A Dcore_t2.c189 /* If Type1 access, must set T2 CFG. */ conf_read()
224 /* If Type1 access, must reset T2 CFG so normal IO space ops work. */ conf_read()
241 /* If Type1 access, must set T2 CFG. */ conf_write()
275 /* If Type1 access, must reset T2 CFG so normal IO space ops work. */ conf_write()
H A Dcore_cia.c120 /* If Type1 access, must set CIA CFG. */ conf_read()
146 /* If Type1 access, must reset IOC CFG so normal IO space ops work. */ conf_read()
174 /* If Type1 access, must set CIA CFG. */ conf_write()
196 /* If Type1 access, must reset IOC CFG so normal IO space ops work. */ conf_write()
660 /* Clear the CFG register, which gets used for PCI config space do_init_arch()
/linux-4.1.27/drivers/net/ethernet/ibm/emac/
H A Dmal.h50 /* MAL V1 CFG bits */
59 /* MAL V2 CFG bits */
H A Ddebug.c129 "CFG = 0x%08x ESR = 0x%08x IER = 0x%08x\n" emac_mal_dump()
/linux-4.1.27/drivers/dma/dw/
H A Dregs.h82 DW_REG(CFG);
213 /* Bitfields in CFG */
H A Dcore.c1107 dma_writel(dw, CFG, 0); dw_dma_off()
1115 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) dw_dma_off()
1124 dma_writel(dw, CFG, DW_CFG_DMA_EN); dw_dma_on()
/linux-4.1.27/arch/tile/kernel/
H A Dpci_gx.c51 pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \
54 pr_info("CFG RD %d-byte VAL %#x from bus %d dev %d func %d addr %u\n", \
176 pr_err("PCI: CFG PIO alloc failure on TRIO %d, give up\n", tile_pcie_open()
184 * For PIO CFG, the bus_address_hi parameter is 0. The mac parameter tile_pcie_open()
190 pr_err("PCI: CFG PIO init failure on TRIO %d, give up\n", tile_pcie_open()
826 pr_err("PCI: PCI CFG PIO alloc failure for mac %d on TRIO %d, give up\n", pcibios_init()
834 /* For PIO CFG, the bus_address_hi parameter is 0. */ pcibios_init()
839 pr_err("PCI: PCI CFG PIO init failure for mac %d on TRIO %d, give up\n", pcibios_init()
853 * bit 29 in the PIO CFG address format is reserved 0. With pcibios_init()
/linux-4.1.27/drivers/clk/shmobile/
H A Dclk-sh73a0.c115 /* handle CFG bit for PLL1 and PLL2 */ sh73a0_cpg_register_clock()
/linux-4.1.27/arch/mips/include/asm/sn/
H A Dkldir.h42 * | IP27 CFG |
/linux-4.1.27/arch/arm/mach-pxa/
H A Dam300epd.c97 static char *gpio_names[] = { "PWR", "CFG", "RDY", "DC", "RST", "RD", "WR",
/linux-4.1.27/drivers/net/ethernet/natsemi/
H A Dns83820.c323 #define CFG 0x04 macro
620 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; phy_intr()
692 writel(new_cfg, dev->base + CFG); phy_intr()
1241 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; ns83820_get_settings()
1292 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; ns83820_set_settings()
1373 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; ns83820_get_link()
2048 dev->CFG_cache = readl(dev->base + CFG); ns83820_init_one()
2100 writel(dev->CFG_cache, dev->base + CFG); ns83820_init_one()
2101 dprintk("CFG: %08x\n", dev->CFG_cache); ns83820_init_one()
2105 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG); ns83820_init_one()
2107 writel(dev->CFG_cache, dev->base + CFG); ns83820_init_one()
H A Dnatsemi.c27 * big endian support with CFG:BEM instead of cpu_to_le32
1374 /* CFG bits [13:16] [18:23] */
1400 /* CFG */ natsemi_reset()
1432 /* restore CFG */ natsemi_reset()
/linux-4.1.27/drivers/pci/host/
H A Dpci-dra7xx.c263 dev_dbg(dra7xx->dev, "CFG 'Bus Master Enable' change\n"); dra7xx_pcie_irq_handler()
266 dev_dbg(dra7xx->dev, "CFG 'Memory Space Enable' change\n"); dra7xx_pcie_irq_handler()
/linux-4.1.27/drivers/gpio/
H A Dgpio-adp5588.c295 adp5588_gpio_write(client, CFG, ADP5588_AUTO_INC); adp5588_irq_setup()
331 adp5588_gpio_write(client, CFG, adp5588_irq_setup()
/linux-4.1.27/arch/powerpc/sysdev/
H A Dtsi108_pci.c76 printk("PCI CFG write : "); tsi108_direct_write_config()
179 printk("PCI CFG read : "); tsi108_direct_read_config()
H A Dppc4xx_pci.c1510 * CFG and REG regions based on resources in the device tree ppc4xx_pciex_port_init()
/linux-4.1.27/drivers/atm/
H A Dnicstar.c213 writel(0x00000000, card->membase + CFG); nicstar_remove_one()
434 writel(NS_CFG_SWRST, card->membase + CFG); ns_init_card()
436 writel(0x00000000, card->membase + CFG); ns_init_card()
806 NS_CFG_PHYIE, card->membase + CFG); ns_init_card()
816 writel(0x00000000, card->membase + CFG); ns_init_card_error()
1046 writel((readl(card->membase + CFG) | NS_CFG_EFBIE), push_rxbufs()
1047 card->membase + CFG); push_rxbufs()
1175 writel(readl(card->membase + CFG) & ns_irq_handler()
1176 ~NS_CFG_EFBIE, card->membase + CFG); ns_irq_handler()
1200 writel(readl(card->membase + CFG) & ns_irq_handler()
1201 ~NS_CFG_EFBIE, card->membase + CFG); ns_irq_handler()
1550 cfg = readl(card->membase + CFG); ns_close()
1551 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg); ns_close()
H A Dnicstar.h432 CFG = 0x14, /* Configuration R/W */ enumerator in enum:ns_regs
/linux-4.1.27/drivers/mtd/nand/
H A Datmel_nand.c906 val = pmecc_readl_relaxed(host->ecc, CFG); pmecc_enable()
909 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP) pmecc_enable()
912 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP) pmecc_enable()
1042 pmecc_writel(host->ecc, CFG, val); atmel_pmecc_core_init()
1985 cfg = nfc_readl(host->nfc->hsmc_regs, CFG); nfc_sram_write_page()
1989 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE); nfc_sram_write_page()
1991 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE); nfc_sram_write_page()
2031 /* Initialize the NFC CFG register */ nfc_sram_init()
2065 nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc); nfc_sram_init()
/linux-4.1.27/drivers/iio/adc/
H A Dvf610_adc.c401 /* CFG: Feature set */ vf610_adc_hw_init()
408 /* CFG: power and speed set */ vf610_adc_hw_init()
/linux-4.1.27/drivers/input/keyboard/
H A Dadp5588-keys.c381 ret |= adp5588_write(client, CFG, ADP5588_INT_CFG | adp5588_setup()
605 adp5588_write(client, CFG, 0); adp5588_remove()
/linux-4.1.27/drivers/dma/
H A Dat_hdmac_regs.h153 /* Bitfields in CFG */
368 channel_readl(atchan, CFG), vdbg_dump_regs()
H A Dste_dma40_ll.h22 /* Most bits of the CFG register are the same in log as in phy mode */
H A Dat_hdmac.c1411 channel_writel(atchan, CFG, cfg); atc_alloc_chan_resources()
1875 atchan->save_cfg = channel_readl(atchan, CFG); at_dma_suspend_noirq()
1924 channel_writel(atchan, CFG, atchan->save_cfg); at_dma_resume_noirq()
H A Dfsl_raid.c736 /* Program the CFG reg */ fsl_re_chan_probe()
H A Dste_dma40.c1389 /* Set default config for CFG reg */ d40_config_write()
/linux-4.1.27/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-sgmii.c233 /* Read GMX CFG again to make sure the disable completed */ __cvmx_helper_sgmii_hardware_init_link_speed()
291 /* Read GMX CFG again to make sure the config completed */ __cvmx_helper_sgmii_hardware_init_link_speed()
/linux-4.1.27/drivers/usb/gadget/udc/
H A Datmel_usba_udc.c608 usba_ep_writel(ep, CFG, ept_cfg); usba_ep_enable()
627 (unsigned long)usba_ep_readl(ep, CFG)); usba_ep_enable()
1157 usba_ep_writel(ep, CFG, do_test_mode()
1162 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) { do_test_mode()
1173 usba_ep_writel(ep, CFG, do_test_mode()
1178 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) { do_test_mode()
1719 usba_ep_writel(ep0, CFG, usba_udc_irq()
1732 if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED)) usba_udc_irq()
H A Domap_udc.c2361 (tmp & UDC_CFG) ? " CFG" : "", proc_udc_show()
/linux-4.1.27/drivers/phy/
H A Dphy-spear1340-miphy.c38 /* PCIE CFG MASks */
/linux-4.1.27/include/linux/
H A Dparport_pc.h87 static const char *const ecr_modes[] = {"SPP", "PS2", "PPFIFO", "ECP", "xXx", "yYy", "TST", "CFG"}; dump_parport_state()
/linux-4.1.27/arch/powerpc/platforms/embedded6xx/
H A Dholly.c82 /* Map PCI CFG space */ holly_remap_bridge()
/linux-4.1.27/arch/arm/mm/
H A Dproc-fa526.S140 /* On return of this routine, r0 must carry correct flags for CFG register */
/linux-4.1.27/include/linux/i2c/
H A Dadp5588.h13 #define CFG 0x01 /* Configuration Register1 */ macro
/linux-4.1.27/drivers/net/wireless/mwifiex/
H A Dsdio.c562 dev_err(adapter->dev, "write CFG reg failed\n"); mwifiex_write_data_to_card()
985 dev_err(adapter->dev, "write CFG reg failed\n"); mwifiex_prog_fw_w_helper()
1576 dev_err(adapter->dev, "read CFG reg failed\n"); mwifiex_process_int_status()
1578 dev_dbg(adapter->dev, "info: CFG reg val = %d\n", cr); mwifiex_process_int_status()
1581 dev_err(adapter->dev, "write CFG reg failed\n"); mwifiex_process_int_status()
1586 dev_err(adapter->dev, "read CFG reg failed\n"); mwifiex_process_int_status()
1588 dev_dbg(adapter->dev, "info: CFG reg val =%x\n", cr); mwifiex_process_int_status()
/linux-4.1.27/drivers/misc/
H A Dspear13xx_pcie_gadget.c808 * Ideally CFG Clock should have been also enabled here. But spear_pcie_gadget_probe()
823 * Ideally CFG Clock should have been also enabled here. But spear_pcie_gadget_probe()
H A Dpch_phub.c110 * @clkcfg_reg: CLK CFG register val
/linux-4.1.27/drivers/net/wireless/iwlwifi/mvm/
H A Dfw.c307 IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n", iwl_send_phy_cfg_cmd()
474 IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n"); iwl_mvm_get_shared_mem_conf()
/linux-4.1.27/drivers/video/fbdev/msm/
H A Dmdp_ppp.c58 PPP_ARRAY1(CFG, SRC)
62 PPP_ARRAY1(CFG, DST)
/linux-4.1.27/arch/arm/mach-ixp4xx/include/mach/
H A Dixp4xx-regs.h35 * 0xC0000000 0x00001000 0xFEF13000 PCI CFG
37 * 0xC4000000 0x00001000 0xFEF14000 EXP CFG
/linux-4.1.27/drivers/net/ethernet/emulex/benet/
H A Dbe_hw.h36 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
/linux-4.1.27/drivers/net/wireless/iwlwifi/
H A Diwl-phy-db.c417 /* Send PHY DB CFG section */ iwl_send_phy_db_data()
/linux-4.1.27/drivers/staging/skein/
H A Dskein_base.h187 #define SKEIN_T1_BLK_TYPE_CFG SKEIN_T1_BLK_TYPE(CFG) /* config block */
H A Dskein_base.c52 /* set tweaks: T0=0; T1=CFG | FINAL */ skein_256_init()
274 /* set tweaks: T0=0; T1=CFG | FINAL */ skein_512_init()
496 /* set tweaks: T0=0; T1=CFG | FINAL */ skein_1024_init()
/linux-4.1.27/drivers/staging/vt6656/
H A Dmac.h205 /* Bits in the CFG register */
/linux-4.1.27/drivers/clk/spear/
H A Dspear6xx_clock.c30 /* CORE CLK CFG register masks */
H A Dspear3xx_clock.c32 /* CORE CLK CFG register masks */
/linux-4.1.27/drivers/dma/sh/
H A Dsudmac.c31 u32 offset; /* for CFG, BA, BBC, CA, CBC, DEN */
/linux-4.1.27/arch/parisc/include/asm/
H A Dropes.h261 #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
/linux-4.1.27/drivers/iommu/
H A Dmsm_iommu_hw-8xxx.h231 #define SET_CFG(b, v) SET_GLOBAL_FIELD(b, ESR, CFG, v)
348 #define GET_CFG(b) GET_GLOBAL_FIELD(b, ESR, CFG)
890 #define CFG (CFG_MASK << CFG_SHIFT) macro
/linux-4.1.27/arch/x86/pci/
H A Dacpi.c353 * So explicitly filter out PCI CFG IO ports[0xCF8-0xCFF].
/linux-4.1.27/drivers/scsi/esas2r/
H A Desas2r_flash.c491 /* The CFG image is written next */ fw_download_proc()
506 /* The CFG image has been written - read and verify */ fw_download_proc()
H A Desas2r_init.c1232 esas2r_hdebug("CFG init"); esas2r_format_init_msg()
1271 esas2r_hdebug("CFG get init"); esas2r_format_init_msg()
/linux-4.1.27/drivers/parisc/
H A Ddino.c186 /* tell HW which CFG address */ dino_cfg_read()
225 /* tell HW which CFG address */ dino_cfg_write()
/linux-4.1.27/arch/sparc/kernel/
H A Dleon_pci_grpci2.c263 /* Wait until GRPCI2 signals that CFG access is done, it should be grpci2_cfg_r32()
333 /* Wait until GRPCI2 signals that CFG access is done, it should be grpci2_cfg_w32()
/linux-4.1.27/arch/powerpc/kernel/
H A Deeh_pe.c664 * the PCI-CFG registers have been restored for the parent
667 * Don't use normal PCI-CFG accessors, which probably has been
/linux-4.1.27/drivers/mfd/
H A Dwm5110-tables.c664 { 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
665 { 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
666 { 0x0000000A, 0x0001 }, /* R10 - Ctrl IF I2C2 CFG 1 */
667 { 0x0000000B, 0x0036 }, /* R11 - Ctrl IF I2C1 CFG 2 */
668 { 0x0000000C, 0x0036 }, /* R12 - Ctrl IF I2C2 CFG 2 */
H A Dwm5102-tables.c247 { 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
248 { 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
H A Dwm8997-tables.c159 { 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
/linux-4.1.27/drivers/media/dvb-frontends/drx39xyj/
H A Ddrx_driver.h907 /*== CTRL CFG related data structures ========================================*/
1320 /* CTRL CFG MPEG ouput */
2249 /* Macros with device-specific handling are converted to CFG functions */
H A Ddrxj.h84 /*== CTRL CFG related data structures ========================================*/
/linux-4.1.27/drivers/isdn/hardware/eicon/
H A Dos_pri.c93 ** BAR4 - CONFIG (CFG), 0x1000
/linux-4.1.27/drivers/staging/vt6655/
H A Dmac.h296 /* Bits in the CFG register */
/linux-4.1.27/arch/arm/mach-shmobile/
H A Dclock-sh73a0.c100 /* handle CFG bit for PLL1 and PLL2 */ pll_recalc()
/linux-4.1.27/drivers/net/ethernet/qlogic/qlge/
H A Dqlge.h222 * Configuration Register (CFG) bit definitions.
808 CFG = 0x28, enumerator in enum:__anon7236
H A Dqlge_main.c191 /* The CFG register is used to download TX and RX control blocks
200 temp = ql_read32(qdev, CFG); ql_wait_cfg()
241 "Timed out waiting for CFG to come ready.\n"); ql_write_cfg()
250 ql_write32(qdev, CFG, (mask | value)); ql_write_cfg()
H A Dqlge_dbg.c1493 DUMP_REG(qdev, CFG); ql_dump_regs()
/linux-4.1.27/drivers/net/wan/
H A Ddscc4.c1509 netdev_err(dev, "CFG failed\n"); dscc4_irq()
1813 * ORed with TxSccRes, one sees the CFG ack (for dscc4_rx_irq()
/linux-4.1.27/drivers/net/ethernet/octeon/
H A Docteon_mgmt.c885 /* Read GMX CFG again to make sure the config is completed. */ octeon_mgmt_update_link()
/linux-4.1.27/drivers/net/wireless/ath/ath9k/
H A Ddebug.c611 PR("DESC CFG Error: ", desc_cfg_err); read_file_xmit()
H A Dhw.c1703 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", ath9k_hw_init_desc()
1708 ath_dbg(common, RESET, "Setting CFG 0x%x\n", ath9k_hw_init_desc()
/linux-4.1.27/arch/x86/kernel/
H A Dhpet.c147 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); _hpet_print_config()
/linux-4.1.27/drivers/bluetooth/
H A Dbtmrvl_sdio.c570 BT_ERR("writeb failed (CFG)"); btmrvl_sdio_download_fw_w_helper()
/linux-4.1.27/drivers/pinctrl/spear/
H A Dpinctrl-spear1340.c150 /* PCIE CFG MASks */
/linux-4.1.27/drivers/mmc/host/
H A Datmel-mci.c138 * @cfg_reg: Value of the CFG register.
448 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", atmci_regs_show()
/linux-4.1.27/drivers/gpu/drm/i915/
H A Di915_drv.c1112 * PCI CFG vlv_save_gunit_s0ix_state()
/linux-4.1.27/drivers/parport/
H A Dparport_ip32.c341 "TST", "CFG"}; parport_ip32_dump_state()
/linux-4.1.27/virt/kvm/arm/
H A Dvgic.c616 * The distributor uses 2 bits per IRQ for the CFG register, but the
/linux-4.1.27/drivers/media/platform/omap3isp/
H A Dispccdc.c94 CCDC_PRINT_REGISTER(isp, CFG); ccdc_print_status()
/linux-4.1.27/drivers/net/wireless/ath/ath6kl/
H A Dcfg80211.c1919 * parameter from CFG layer. So it's always passed as ZERO ath6kl_wow_usr()
/linux-4.1.27/drivers/net/ethernet/sun/
H A Dsungem.c1670 /* Revert MIF CFG setting done on stop_phy */ gem_init_phy()
/linux-4.1.27/include/linux/mfd/arizona/
H A Dregisters.h1192 * R8 (0x08) - Ctrl IF SPI CFG 1
1207 * R9 (0x09) - Ctrl IF I2C1 CFG 1
/linux-4.1.27/drivers/net/wireless/ath/wcn36xx/
H A Dhal.h775 /* Config format required by HAL for each CFG item*/
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Datombios.h2913 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
/linux-4.1.27/drivers/net/wireless/
H A Dairo.c4656 mode & 1 ? "CFG ": "", proc_status_open()
/linux-4.1.27/drivers/message/fusion/
H A Dmptbase.c7560 "IR2: Foreign CFG Detected: " mpt_display_event_info()
/linux-4.1.27/drivers/net/wireless/ipw2x00/
H A Dipw2200.c6070 "[CFG 0x%08X]\n", priv->config); ipw_debug_config()
/linux-4.1.27/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_main.c7061 BNX2X_ERR("PXP2 CFG failed\n"); bnx2x_init_hw_common()

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