1/* 2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. 3 All rights reserved. 4 5 Redistribution and use in source and binary forms, with or without 6 modification, are permitted provided that the following conditions are met: 7 8 * Redistributions of source code must retain the above copyright notice, 9 this list of conditions and the following disclaimer. 10 * Redistributions in binary form must reproduce the above copyright notice, 11 this list of conditions and the following disclaimer in the documentation 12 and/or other materials provided with the distribution. 13 * Neither the name of Trident Microsystems nor Hauppauge Computer Works 14 nor the names of its contributors may be used to endorse or promote 15 products derived from this software without specific prior written 16 permission. 17 18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 POSSIBILITY OF SUCH DAMAGE. 29*/ 30 31#ifndef __DRXDRIVER_H__ 32#define __DRXDRIVER_H__ 33 34#include <linux/kernel.h> 35#include <linux/errno.h> 36#include <linux/firmware.h> 37#include <linux/i2c.h> 38 39/* 40 * This structure contains the I2C address, the device ID and a user_data pointer. 41 * The user_data pointer can be used for application specific purposes. 42 */ 43struct i2c_device_addr { 44 u16 i2c_addr; /* The I2C address of the device. */ 45 u16 i2c_dev_id; /* The device identifier. */ 46 void *user_data; /* User data pointer */ 47}; 48 49/** 50* \def IS_I2C_10BIT( addr ) 51* \brief Determine if I2C address 'addr' is a 10 bits address or not. 52* \param addr The I2C address. 53* \return int. 54* \retval 0 if address is not a 10 bits I2C address. 55* \retval 1 if address is a 10 bits I2C address. 56*/ 57#define IS_I2C_10BIT(addr) \ 58 (((addr) & 0xF8) == 0xF0) 59 60/*------------------------------------------------------------------------------ 61Exported FUNCTIONS 62------------------------------------------------------------------------------*/ 63 64/** 65* \fn drxbsp_i2c_init() 66* \brief Initialize I2C communication module. 67* \return int Return status. 68* \retval 0 Initialization successful. 69* \retval -EIO Initialization failed. 70*/ 71int drxbsp_i2c_init(void); 72 73/** 74* \fn drxbsp_i2c_term() 75* \brief Terminate I2C communication module. 76* \return int Return status. 77* \retval 0 Termination successful. 78* \retval -EIO Termination failed. 79*/ 80int drxbsp_i2c_term(void); 81 82/** 83* \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, 84* u16 w_count, 85* u8 * wData, 86* struct i2c_device_addr *r_dev_addr, 87* u16 r_count, 88* u8 * r_data) 89* \brief Read and/or write count bytes from I2C bus, store them in data[]. 90* \param w_dev_addr The device i2c address and the device ID to write to 91* \param w_count The number of bytes to write 92* \param wData The array to write the data to 93* \param r_dev_addr The device i2c address and the device ID to read from 94* \param r_count The number of bytes to read 95* \param r_data The array to read the data from 96* \return int Return status. 97* \retval 0 Succes. 98* \retval -EIO Failure. 99* \retval -EINVAL Parameter 'wcount' is not zero but parameter 100* 'wdata' contains NULL. 101* Idem for 'rcount' and 'rdata'. 102* Both w_dev_addr and r_dev_addr are NULL. 103* 104* This function must implement an atomic write and/or read action on the I2C bus 105* No other process may use the I2C bus when this function is executing. 106* The critical section of this function runs from and including the I2C 107* write, up to and including the I2C read action. 108* 109* The device ID can be useful if several devices share an I2C address. 110* It can be used to control a "switch" on the I2C bus to the correct device. 111*/ 112int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, 113 u16 w_count, 114 u8 *wData, 115 struct i2c_device_addr *r_dev_addr, 116 u16 r_count, u8 *r_data); 117 118/** 119* \fn drxbsp_i2c_error_text() 120* \brief Returns a human readable error. 121* Counter part of numerical drx_i2c_error_g. 122* 123* \return char* Pointer to human readable error text. 124*/ 125char *drxbsp_i2c_error_text(void); 126 127/** 128* \var drx_i2c_error_g; 129* \brief I2C specific error codes, platform dependent. 130*/ 131extern int drx_i2c_error_g; 132 133#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ 134#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ 135#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */ 136#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */ 137#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */ 138#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */ 139#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */ 140#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */ 141 142#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */ 143#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */ 144#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */ 145#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */ 146#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */ 147#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */ 148#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ 149 150#define TUNER_MODE_SUB_MAX 8 151#define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ 152 TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \ 153 TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ 154 TUNER_MODE_SUB6 | TUNER_MODE_SUB7) 155 156 157enum tuner_lock_status { 158 TUNER_LOCKED, 159 TUNER_NOT_LOCKED 160}; 161 162struct tuner_common { 163 char *name; /* Tuner brand & type name */ 164 s32 min_freq_rf; /* Lowest RF input frequency, in kHz */ 165 s32 max_freq_rf; /* Highest RF input frequency, in kHz */ 166 167 u8 sub_mode; /* Index to sub-mode in use */ 168 char ***sub_mode_descriptions; /* Pointer to description of sub-modes */ 169 u8 sub_modes; /* Number of available sub-modes */ 170 171 /* The following fields will be either 0, NULL or false and do not need 172 initialisation */ 173 void *self_check; /* gives proof of initialization */ 174 bool programmed; /* only valid if self_check is OK */ 175 s32 r_ffrequency; /* only valid if programmed */ 176 s32 i_ffrequency; /* only valid if programmed */ 177 178 void *my_user_data; /* pointer to associated demod instance */ 179 u16 my_capabilities; /* value for storing application flags */ 180}; 181 182struct tuner_instance; 183 184typedef int(*tuner_open_func_t) (struct tuner_instance *tuner); 185typedef int(*tuner_close_func_t) (struct tuner_instance *tuner); 186 187typedef int(*tuner_set_frequency_func_t) (struct tuner_instance *tuner, 188 u32 mode, 189 s32 190 frequency); 191 192typedef int(*tuner_get_frequency_func_t) (struct tuner_instance *tuner, 193 u32 mode, 194 s32 * 195 r_ffrequency, 196 s32 * 197 i_ffrequency); 198 199typedef int(*tuner_lock_status_func_t) (struct tuner_instance *tuner, 200 enum tuner_lock_status * 201 lock_stat); 202 203typedef int(*tune_ri2c_write_read_func_t) (struct tuner_instance *tuner, 204 struct i2c_device_addr * 205 w_dev_addr, u16 w_count, 206 u8 *wData, 207 struct i2c_device_addr * 208 r_dev_addr, u16 r_count, 209 u8 *r_data); 210 211struct tuner_ops { 212 tuner_open_func_t open_func; 213 tuner_close_func_t close_func; 214 tuner_set_frequency_func_t set_frequency_func; 215 tuner_get_frequency_func_t get_frequency_func; 216 tuner_lock_status_func_t lock_status_func; 217 tune_ri2c_write_read_func_t i2c_write_read_func; 218 219}; 220 221struct tuner_instance { 222 struct i2c_device_addr my_i2c_dev_addr; 223 struct tuner_common *my_common_attr; 224 void *my_ext_attr; 225 struct tuner_ops *my_funct; 226}; 227 228int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, 229 u32 mode, 230 s32 frequency); 231 232int drxbsp_tuner_get_frequency(struct tuner_instance *tuner, 233 u32 mode, 234 s32 *r_ffrequency, 235 s32 *i_ffrequency); 236 237int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, 238 struct i2c_device_addr *w_dev_addr, 239 u16 w_count, 240 u8 *wData, 241 struct i2c_device_addr *r_dev_addr, 242 u16 r_count, u8 *r_data); 243 244/************** 245* 246* This section configures the DRX Data Access Protocols (DAPs). 247* 248**************/ 249 250/** 251* \def DRXDAP_SINGLE_MASTER 252* \brief Enable I2C single or I2C multimaster mode on host. 253* 254* Set to 1 to enable single master mode 255* Set to 0 to enable multi master mode 256* 257* The actual DAP implementation may be restricted to only one of the modes. 258* A compiler warning or error will be generated if the DAP implementation 259* overides or cannot handle the mode defined below. 260* 261*/ 262#ifndef DRXDAP_SINGLE_MASTER 263#define DRXDAP_SINGLE_MASTER 1 264#endif 265 266/** 267* \def DRXDAP_MAX_WCHUNKSIZE 268* \brief Defines maximum chunksize of an i2c write action by host. 269* 270* This indicates the maximum size of data the I2C device driver is able to 271* write at a time. This includes I2C device address and register addressing. 272* 273* This maximum size may be restricted by the actual DAP implementation. 274* A compiler warning or error will be generated if the DAP implementation 275* overides or cannot handle the chunksize defined below. 276* 277* Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data 278* buffer. Do not undefine or choose too large, unless your system is able to 279* handle a stack buffer of that size. 280* 281*/ 282#ifndef DRXDAP_MAX_WCHUNKSIZE 283#define DRXDAP_MAX_WCHUNKSIZE 60 284#endif 285 286/** 287* \def DRXDAP_MAX_RCHUNKSIZE 288* \brief Defines maximum chunksize of an i2c read action by host. 289* 290* This indicates the maximum size of data the I2C device driver is able to read 291* at a time. Minimum value is 2. Also, the read chunk size must be even. 292* 293* This maximum size may be restricted by the actual DAP implementation. 294* A compiler warning or error will be generated if the DAP implementation 295* overides or cannot handle the chunksize defined below. 296* 297*/ 298#ifndef DRXDAP_MAX_RCHUNKSIZE 299#define DRXDAP_MAX_RCHUNKSIZE 60 300#endif 301 302/************** 303* 304* This section describes drxdriver defines. 305* 306**************/ 307 308/** 309* \def DRX_UNKNOWN 310* \brief Generic UNKNOWN value for DRX enumerated types. 311* 312* Used to indicate that the parameter value is unknown or not yet initalized. 313*/ 314#ifndef DRX_UNKNOWN 315#define DRX_UNKNOWN (254) 316#endif 317 318/** 319* \def DRX_AUTO 320* \brief Generic AUTO value for DRX enumerated types. 321* 322* Used to instruct the driver to automatically determine the value of the 323* parameter. 324*/ 325#ifndef DRX_AUTO 326#define DRX_AUTO (255) 327#endif 328 329/************** 330* 331* This section describes flag definitions for the device capbilities. 332* 333**************/ 334 335/** 336* \brief LNA capability flag 337* 338* Device has a Low Noise Amplifier 339* 340*/ 341#define DRX_CAPABILITY_HAS_LNA (1UL << 0) 342/** 343* \brief OOB-RX capability flag 344* 345* Device has OOB-RX 346* 347*/ 348#define DRX_CAPABILITY_HAS_OOBRX (1UL << 1) 349/** 350* \brief ATV capability flag 351* 352* Device has ATV 353* 354*/ 355#define DRX_CAPABILITY_HAS_ATV (1UL << 2) 356/** 357* \brief DVB-T capability flag 358* 359* Device has DVB-T 360* 361*/ 362#define DRX_CAPABILITY_HAS_DVBT (1UL << 3) 363/** 364* \brief ITU-B capability flag 365* 366* Device has ITU-B 367* 368*/ 369#define DRX_CAPABILITY_HAS_ITUB (1UL << 4) 370/** 371* \brief Audio capability flag 372* 373* Device has Audio 374* 375*/ 376#define DRX_CAPABILITY_HAS_AUD (1UL << 5) 377/** 378* \brief SAW switch capability flag 379* 380* Device has SAW switch 381* 382*/ 383#define DRX_CAPABILITY_HAS_SAWSW (1UL << 6) 384/** 385* \brief GPIO1 capability flag 386* 387* Device has GPIO1 388* 389*/ 390#define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7) 391/** 392* \brief GPIO2 capability flag 393* 394* Device has GPIO2 395* 396*/ 397#define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8) 398/** 399* \brief IRQN capability flag 400* 401* Device has IRQN 402* 403*/ 404#define DRX_CAPABILITY_HAS_IRQN (1UL << 9) 405/** 406* \brief 8VSB capability flag 407* 408* Device has 8VSB 409* 410*/ 411#define DRX_CAPABILITY_HAS_8VSB (1UL << 10) 412/** 413* \brief SMA-TX capability flag 414* 415* Device has SMATX 416* 417*/ 418#define DRX_CAPABILITY_HAS_SMATX (1UL << 11) 419/** 420* \brief SMA-RX capability flag 421* 422* Device has SMARX 423* 424*/ 425#define DRX_CAPABILITY_HAS_SMARX (1UL << 12) 426/** 427* \brief ITU-A/C capability flag 428* 429* Device has ITU-A/C 430* 431*/ 432#define DRX_CAPABILITY_HAS_ITUAC (1UL << 13) 433 434/*------------------------------------------------------------------------- 435MACROS 436-------------------------------------------------------------------------*/ 437/* Macros to stringify the version number */ 438#define DRX_VERSIONSTRING(MAJOR, MINOR, PATCH) \ 439 DRX_VERSIONSTRING_HELP(MAJOR)"." \ 440 DRX_VERSIONSTRING_HELP(MINOR)"." \ 441 DRX_VERSIONSTRING_HELP(PATCH) 442#define DRX_VERSIONSTRING_HELP(NUM) #NUM 443 444/** 445* \brief Macro to create byte array elements from 16 bit integers. 446* This macro is used to create byte arrays for block writes. 447* Block writes speed up I2C traffic between host and demod. 448* The macro takes care of the required byte order in a 16 bits word. 449* x->lowbyte(x), highbyte(x) 450*/ 451#define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ 452 ((u8)((((u16)x)>>8)&0xFF)) 453 454/** 455* \brief Macro to sign extend signed 9 bit value to signed 16 bit value 456*/ 457#define DRX_S9TOS16(x) ((((u16)x)&0x100) ? ((s16)((u16)(x)|0xFF00)) : (x)) 458 459/** 460* \brief Macro to sign extend signed 9 bit value to signed 16 bit value 461*/ 462#define DRX_S24TODRXFREQ(x) ((((u32) x) & 0x00800000UL) ? \ 463 ((s32) \ 464 (((u32) x) | 0xFF000000)) : \ 465 ((s32) x)) 466 467/** 468* \brief Macro to convert 16 bit register value to a s32 469*/ 470#define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \ 471 ((s32) \ 472 (((u32) x) | 0xFFFF0000)) : \ 473 ((s32) x)) 474 475/*------------------------------------------------------------------------- 476ENUM 477-------------------------------------------------------------------------*/ 478 479/** 480* \enum enum drx_standard 481* \brief Modulation standards. 482*/ 483enum drx_standard { 484 DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */ 485 DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */ 486 DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */ 487 DRX_STANDARD_PAL_SECAM_BG, 488 /**< Terrestrial analog PAL/SECAM B/G */ 489 DRX_STANDARD_PAL_SECAM_DK, 490 /**< Terrestrial analog PAL/SECAM D/K */ 491 DRX_STANDARD_PAL_SECAM_I, 492 /**< Terrestrial analog PAL/SECAM I */ 493 DRX_STANDARD_PAL_SECAM_L, 494 /**< Terrestrial analog PAL/SECAM L 495 with negative modulation */ 496 DRX_STANDARD_PAL_SECAM_LP, 497 /**< Terrestrial analog PAL/SECAM L 498 with positive modulation */ 499 DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */ 500 DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */ 501 DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */ 502 DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */ 503 DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */ 504 DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/ 505 DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, 506 /**< Standard unknown. */ 507 DRX_STANDARD_AUTO = DRX_AUTO 508 /**< Autodetect standard. */ 509}; 510 511/** 512* \enum enum drx_standard 513* \brief Modulation sub-standards. 514*/ 515enum drx_substandard { 516 DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */ 517 DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, 518 DRX_SUBSTANDARD_ATV_DK_POLAND, 519 DRX_SUBSTANDARD_ATV_DK_CHINA, 520 DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, 521 /**< Sub-standard unknown. */ 522 DRX_SUBSTANDARD_AUTO = DRX_AUTO 523 /**< Auto (default) sub-standard */ 524}; 525 526/** 527* \enum enum drx_bandwidth 528* \brief Channel bandwidth or channel spacing. 529*/ 530enum drx_bandwidth { 531 DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */ 532 DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */ 533 DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */ 534 DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, 535 /**< Bandwidth unknown. */ 536 DRX_BANDWIDTH_AUTO = DRX_AUTO 537 /**< Auto Set Bandwidth */ 538}; 539 540/** 541* \enum enum drx_mirror 542* \brief Indicate if channel spectrum is mirrored or not. 543*/ 544enum drx_mirror { 545 DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */ 546 DRX_MIRROR_YES, /**< Spectrum is mirrored. */ 547 DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, 548 /**< Unknown if spectrum is mirrored. */ 549 DRX_MIRROR_AUTO = DRX_AUTO 550 /**< Autodetect if spectrum is mirrored. */ 551}; 552 553/** 554* \enum enum drx_modulation 555* \brief Constellation type of the channel. 556*/ 557enum drx_modulation { 558 DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */ 559 DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */ 560 DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */ 561 DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */ 562 DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */ 563 DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */ 564 DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */ 565 DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */ 566 DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */ 567 DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */ 568 DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */ 569 DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, 570 /**< Constellation unknown. */ 571 DRX_CONSTELLATION_AUTO = DRX_AUTO 572 /**< Autodetect constellation. */ 573}; 574 575/** 576* \enum enum drx_hierarchy 577* \brief Hierarchy of the channel. 578*/ 579enum drx_hierarchy { 580 DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */ 581 DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */ 582 DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */ 583 DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */ 584 DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, 585 /**< Hierarchy unknown. */ 586 DRX_HIERARCHY_AUTO = DRX_AUTO 587 /**< Autodetect hierarchy. */ 588}; 589 590/** 591* \enum enum drx_priority 592* \brief Channel priority in case of hierarchical transmission. 593*/ 594enum drx_priority { 595 DRX_PRIORITY_LOW = 0, /**< Low priority channel. */ 596 DRX_PRIORITY_HIGH, /**< High priority channel. */ 597 DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN 598 /**< Priority unknown. */ 599}; 600 601/** 602* \enum enum drx_coderate 603* \brief Channel priority in case of hierarchical transmission. 604*/ 605enum drx_coderate { 606 DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */ 607 DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */ 608 DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */ 609 DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */ 610 DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */ 611 DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, 612 /**< Code rate unknown. */ 613 DRX_CODERATE_AUTO = DRX_AUTO 614 /**< Autodetect code rate. */ 615}; 616 617/** 618* \enum enum drx_guard 619* \brief Guard interval of a channel. 620*/ 621enum drx_guard { 622 DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */ 623 DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */ 624 DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */ 625 DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */ 626 DRX_GUARD_UNKNOWN = DRX_UNKNOWN, 627 /**< Guard interval unknown. */ 628 DRX_GUARD_AUTO = DRX_AUTO 629 /**< Autodetect guard interval. */ 630}; 631 632/** 633* \enum enum drx_fft_mode 634* \brief FFT mode. 635*/ 636enum drx_fft_mode { 637 DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */ 638 DRX_FFTMODE_4K, /**< 4K FFT mode. */ 639 DRX_FFTMODE_8K, /**< 8K FFT mode. */ 640 DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, 641 /**< FFT mode unknown. */ 642 DRX_FFTMODE_AUTO = DRX_AUTO 643 /**< Autodetect FFT mode. */ 644}; 645 646/** 647* \enum enum drx_classification 648* \brief Channel classification. 649*/ 650enum drx_classification { 651 DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */ 652 DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */ 653 DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */ 654 DRX_CLASSIFICATION_STATIC, /**< Static echo. */ 655 DRX_CLASSIFICATION_MOVING, /**< Moving echo. */ 656 DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */ 657 DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, 658 /**< Unknown classification */ 659 DRX_CLASSIFICATION_AUTO = DRX_AUTO 660 /**< Autodetect classification. */ 661}; 662 663/** 664* /enum enum drx_interleave_mode 665* /brief Interleave modes 666*/ 667enum drx_interleave_mode { 668 DRX_INTERLEAVEMODE_I128_J1 = 0, 669 DRX_INTERLEAVEMODE_I128_J1_V2, 670 DRX_INTERLEAVEMODE_I128_J2, 671 DRX_INTERLEAVEMODE_I64_J2, 672 DRX_INTERLEAVEMODE_I128_J3, 673 DRX_INTERLEAVEMODE_I32_J4, 674 DRX_INTERLEAVEMODE_I128_J4, 675 DRX_INTERLEAVEMODE_I16_J8, 676 DRX_INTERLEAVEMODE_I128_J5, 677 DRX_INTERLEAVEMODE_I8_J16, 678 DRX_INTERLEAVEMODE_I128_J6, 679 DRX_INTERLEAVEMODE_RESERVED_11, 680 DRX_INTERLEAVEMODE_I128_J7, 681 DRX_INTERLEAVEMODE_RESERVED_13, 682 DRX_INTERLEAVEMODE_I128_J8, 683 DRX_INTERLEAVEMODE_RESERVED_15, 684 DRX_INTERLEAVEMODE_I12_J17, 685 DRX_INTERLEAVEMODE_I5_J4, 686 DRX_INTERLEAVEMODE_B52_M240, 687 DRX_INTERLEAVEMODE_B52_M720, 688 DRX_INTERLEAVEMODE_B52_M48, 689 DRX_INTERLEAVEMODE_B52_M0, 690 DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, 691 /**< Unknown interleave mode */ 692 DRX_INTERLEAVEMODE_AUTO = DRX_AUTO 693 /**< Autodetect interleave mode */ 694}; 695 696/** 697* \enum enum drx_carrier_mode 698* \brief Channel Carrier Mode. 699*/ 700enum drx_carrier_mode { 701 DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */ 702 DRX_CARRIER_SINGLE, /**< Single carrier mode */ 703 DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, 704 /**< Carrier mode unknown. */ 705 DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */ 706}; 707 708/** 709* \enum enum drx_frame_mode 710* \brief Channel Frame Mode. 711*/ 712enum drx_frame_mode { 713 DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */ 714 DRX_FRAMEMODE_595, /**< 595 */ 715 DRX_FRAMEMODE_945, /**< 945 with variable PN */ 716 DRX_FRAMEMODE_420_FIXED_PN, 717 /**< 420 with fixed PN */ 718 DRX_FRAMEMODE_945_FIXED_PN, 719 /**< 945 with fixed PN */ 720 DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, 721 /**< Frame mode unknown. */ 722 DRX_FRAMEMODE_AUTO = DRX_AUTO 723 /**< Autodetect frame mode */ 724}; 725 726/** 727* \enum enum drx_tps_frame 728* \brief Frame number in current super-frame. 729*/ 730enum drx_tps_frame { 731 DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */ 732 DRX_TPS_FRAME2, /**< TPS frame 2. */ 733 DRX_TPS_FRAME3, /**< TPS frame 3. */ 734 DRX_TPS_FRAME4, /**< TPS frame 4. */ 735 DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN 736 /**< TPS frame unknown. */ 737}; 738 739/** 740* \enum enum drx_ldpc 741* \brief TPS LDPC . 742*/ 743enum drx_ldpc { 744 DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */ 745 DRX_LDPC_0_6, /**< LDPC 0.6 */ 746 DRX_LDPC_0_8, /**< LDPC 0.8 */ 747 DRX_LDPC_UNKNOWN = DRX_UNKNOWN, 748 /**< LDPC unknown. */ 749 DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */ 750}; 751 752/** 753* \enum enum drx_pilot_mode 754* \brief Pilot modes in DTMB. 755*/ 756enum drx_pilot_mode { 757 DRX_PILOT_ON = 0, /**< Pilot On */ 758 DRX_PILOT_OFF, /**< Pilot Off */ 759 DRX_PILOT_UNKNOWN = DRX_UNKNOWN, 760 /**< Pilot unknown. */ 761 DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */ 762}; 763 764/** 765 * enum drxu_code_action - indicate if firmware has to be uploaded or verified. 766 * @UCODE_UPLOAD: Upload the microcode image to device 767 * @UCODE_VERIFY: Compare microcode image with code on device 768 */ 769enum drxu_code_action { 770 UCODE_UPLOAD, 771 UCODE_VERIFY 772}; 773 774/** 775* \enum enum drx_lock_status * \brief Used to reflect current lock status of demodulator. 776* 777* The generic lock states have device dependent semantics. 778 779 DRX_NEVER_LOCK = 0, 780 **< Device will never lock on this signal * 781 DRX_NOT_LOCKED, 782 **< Device has no lock at all * 783 DRX_LOCK_STATE_1, 784 **< Generic lock state * 785 DRX_LOCK_STATE_2, 786 **< Generic lock state * 787 DRX_LOCK_STATE_3, 788 **< Generic lock state * 789 DRX_LOCK_STATE_4, 790 **< Generic lock state * 791 DRX_LOCK_STATE_5, 792 **< Generic lock state * 793 DRX_LOCK_STATE_6, 794 **< Generic lock state * 795 DRX_LOCK_STATE_7, 796 **< Generic lock state * 797 DRX_LOCK_STATE_8, 798 **< Generic lock state * 799 DRX_LOCK_STATE_9, 800 **< Generic lock state * 801 DRX_LOCKED **< Device is in lock * 802*/ 803 804enum drx_lock_status { 805 DRX_NEVER_LOCK = 0, 806 DRX_NOT_LOCKED, 807 DRX_LOCK_STATE_1, 808 DRX_LOCK_STATE_2, 809 DRX_LOCK_STATE_3, 810 DRX_LOCK_STATE_4, 811 DRX_LOCK_STATE_5, 812 DRX_LOCK_STATE_6, 813 DRX_LOCK_STATE_7, 814 DRX_LOCK_STATE_8, 815 DRX_LOCK_STATE_9, 816 DRX_LOCKED 817}; 818 819/** 820* \enum enum drx_uio* \brief Used to address a User IO (UIO). 821*/ 822enum drx_uio { 823 DRX_UIO1, 824 DRX_UIO2, 825 DRX_UIO3, 826 DRX_UIO4, 827 DRX_UIO5, 828 DRX_UIO6, 829 DRX_UIO7, 830 DRX_UIO8, 831 DRX_UIO9, 832 DRX_UIO10, 833 DRX_UIO11, 834 DRX_UIO12, 835 DRX_UIO13, 836 DRX_UIO14, 837 DRX_UIO15, 838 DRX_UIO16, 839 DRX_UIO17, 840 DRX_UIO18, 841 DRX_UIO19, 842 DRX_UIO20, 843 DRX_UIO21, 844 DRX_UIO22, 845 DRX_UIO23, 846 DRX_UIO24, 847 DRX_UIO25, 848 DRX_UIO26, 849 DRX_UIO27, 850 DRX_UIO28, 851 DRX_UIO29, 852 DRX_UIO30, 853 DRX_UIO31, 854 DRX_UIO32, 855 DRX_UIO_MAX = DRX_UIO32 856}; 857 858/** 859* \enum enum drxuio_mode * \brief Used to configure the modus oprandi of a UIO. 860* 861* DRX_UIO_MODE_FIRMWARE is an old uio mode. 862* It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9. 863* To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to 864* DRX_UIO_MODE_FIRMWARE0. 865*/ 866enum drxuio_mode { 867 DRX_UIO_MODE_DISABLE = 0x01, 868 /**< not used, pin is configured as input */ 869 DRX_UIO_MODE_READWRITE = 0x02, 870 /**< used for read/write by application */ 871 DRX_UIO_MODE_FIRMWARE = 0x04, 872 /**< controlled by firmware, function 0 */ 873 DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE, 874 /**< same as above */ 875 DRX_UIO_MODE_FIRMWARE1 = 0x08, 876 /**< controlled by firmware, function 1 */ 877 DRX_UIO_MODE_FIRMWARE2 = 0x10, 878 /**< controlled by firmware, function 2 */ 879 DRX_UIO_MODE_FIRMWARE3 = 0x20, 880 /**< controlled by firmware, function 3 */ 881 DRX_UIO_MODE_FIRMWARE4 = 0x40, 882 /**< controlled by firmware, function 4 */ 883 DRX_UIO_MODE_FIRMWARE5 = 0x80 884 /**< controlled by firmware, function 5 */ 885}; 886 887/** 888* \enum enum drxoob_downstream_standard * \brief Used to select OOB standard. 889* 890* Based on ANSI 55-1 and 55-2 891*/ 892enum drxoob_downstream_standard { 893 DRX_OOB_MODE_A = 0, 894 /**< ANSI 55-1 */ 895 DRX_OOB_MODE_B_GRADE_A, 896 /**< ANSI 55-2 A */ 897 DRX_OOB_MODE_B_GRADE_B 898 /**< ANSI 55-2 B */ 899}; 900 901/*------------------------------------------------------------------------- 902STRUCTS 903-------------------------------------------------------------------------*/ 904 905/*============================================================================*/ 906/*============================================================================*/ 907/*== CTRL CFG related data structures ========================================*/ 908/*============================================================================*/ 909/*============================================================================*/ 910 911#ifndef DRX_CFG_BASE 912#define DRX_CFG_BASE 0 913#endif 914 915#define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */ 916#define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) /* Packet Error */ 917#define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) /* Symbol Clk Offset */ 918#define DRX_CFG_SMA (DRX_CFG_BASE + 3) /* Smart Antenna */ 919#define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) /* Pin safe mode */ 920#define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) /* substandard */ 921#define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) /* volume */ 922#define DRX_CFG_AUD_RDS (DRX_CFG_BASE + 7) /* rds */ 923#define DRX_CFG_AUD_AUTOSOUND (DRX_CFG_BASE + 8) /* ASS & ASC */ 924#define DRX_CFG_AUD_ASS_THRES (DRX_CFG_BASE + 9) /* ASS Thresholds */ 925#define DRX_CFG_AUD_DEVIATION (DRX_CFG_BASE + 10) /* Deviation */ 926#define DRX_CFG_AUD_PRESCALE (DRX_CFG_BASE + 11) /* Prescale */ 927#define DRX_CFG_AUD_MIXER (DRX_CFG_BASE + 12) /* Mixer */ 928#define DRX_CFG_AUD_AVSYNC (DRX_CFG_BASE + 13) /* AVSync */ 929#define DRX_CFG_AUD_CARRIER (DRX_CFG_BASE + 14) /* Audio carriers */ 930#define DRX_CFG_I2S_OUTPUT (DRX_CFG_BASE + 15) /* I2S output */ 931#define DRX_CFG_ATV_STANDARD (DRX_CFG_BASE + 16) /* ATV standard */ 932#define DRX_CFG_SQI_SPEED (DRX_CFG_BASE + 17) /* SQI speed */ 933#define DRX_CTRL_CFG_MAX (DRX_CFG_BASE + 18) /* never to be used */ 934 935#define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE 936/*============================================================================*/ 937/*============================================================================*/ 938/*== CTRL related data structures ============================================*/ 939/*============================================================================*/ 940/*============================================================================*/ 941 942/** 943 * struct drxu_code_info Parameters for microcode upload and verfiy. 944 * 945 * @mc_file: microcode file name 946 * 947 * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE 948 */ 949struct drxu_code_info { 950 char *mc_file; 951}; 952 953/** 954* \struct drx_mc_version_rec_t 955* \brief Microcode version record 956* Version numbers are stored in BCD format, as usual: 957* o major number = bits 31-20 (first three nibbles of MSW) 958* o minor number = bits 19-16 (fourth nibble of MSW) 959* o patch number = bits 15-0 (remaining nibbles in LSW) 960* 961* The device type indicates for which the device is meant. It is based on the 962* JTAG ID, using everything except the bond ID and the metal fix. 963* 964* Special values: 965* - mc_dev_type == 0 => any device allowed 966* - mc_base_version == 0.0.0 => full microcode (mc_version is the version) 967* - mc_base_version != 0.0.0 => patch microcode, the base microcode version 968* (mc_version is the version) 969*/ 970#define AUX_VER_RECORD 0x8000 971 972struct drx_mc_version_rec { 973 u16 aux_type; /* type of aux data - 0x8000 for version record */ 974 u32 mc_dev_type; /* device type, based on JTAG ID */ 975 u32 mc_version; /* version of microcode */ 976 u32 mc_base_version; /* in case of patch: the original microcode version */ 977}; 978 979/*========================================*/ 980 981/** 982* \struct drx_filter_info_t 983* \brief Parameters for loading filter coefficients 984* 985* Used by DRX_CTRL_LOAD_FILTER 986*/ 987struct drx_filter_info { 988 u8 *data_re; 989 /**< pointer to coefficients for RE */ 990 u8 *data_im; 991 /**< pointer to coefficients for IM */ 992 u16 size_re; 993 /**< size of coefficients for RE */ 994 u16 size_im; 995 /**< size of coefficients for IM */ 996}; 997 998/*========================================*/ 999 1000/** 1001* \struct struct drx_channel * \brief The set of parameters describing a single channel. 1002* 1003* Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL. 1004* Only certain fields need to be used for a specfic standard. 1005* 1006*/ 1007struct drx_channel { 1008 s32 frequency; 1009 /**< frequency in kHz */ 1010 enum drx_bandwidth bandwidth; 1011 /**< bandwidth */ 1012 enum drx_mirror mirror; /**< mirrored or not on RF */ 1013 enum drx_modulation constellation; 1014 /**< constellation */ 1015 enum drx_hierarchy hierarchy; 1016 /**< hierarchy */ 1017 enum drx_priority priority; /**< priority */ 1018 enum drx_coderate coderate; /**< coderate */ 1019 enum drx_guard guard; /**< guard interval */ 1020 enum drx_fft_mode fftmode; /**< fftmode */ 1021 enum drx_classification classification; 1022 /**< classification */ 1023 u32 symbolrate; 1024 /**< symbolrate in symbols/sec */ 1025 enum drx_interleave_mode interleavemode; 1026 /**< interleaveMode QAM */ 1027 enum drx_ldpc ldpc; /**< ldpc */ 1028 enum drx_carrier_mode carrier; /**< carrier */ 1029 enum drx_frame_mode framemode; 1030 /**< frame mode */ 1031 enum drx_pilot_mode pilot; /**< pilot mode */ 1032}; 1033 1034/*========================================*/ 1035 1036enum drx_cfg_sqi_speed { 1037 DRX_SQI_SPEED_FAST = 0, 1038 DRX_SQI_SPEED_MEDIUM, 1039 DRX_SQI_SPEED_SLOW, 1040 DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN 1041}; 1042 1043/*========================================*/ 1044 1045/** 1046* \struct struct drx_complex * A complex number. 1047* 1048* Used by DRX_CTRL_CONSTEL. 1049*/ 1050struct drx_complex { 1051 s16 im; 1052 /**< Imaginary part. */ 1053 s16 re; 1054 /**< Real part. */ 1055}; 1056 1057/*========================================*/ 1058 1059/** 1060* \struct struct drx_frequency_plan * Array element of a frequency plan. 1061* 1062* Used by DRX_CTRL_SCAN_INIT. 1063*/ 1064struct drx_frequency_plan { 1065 s32 first; 1066 /**< First centre frequency in this band */ 1067 s32 last; 1068 /**< Last centre frequency in this band */ 1069 s32 step; 1070 /**< Stepping frequency in this band */ 1071 enum drx_bandwidth bandwidth; 1072 /**< Bandwidth within this frequency band */ 1073 u16 ch_number; 1074 /**< First channel number in this band, or first 1075 index in ch_names */ 1076 char **ch_names; 1077 /**< Optional list of channel names in this 1078 band */ 1079}; 1080 1081/*========================================*/ 1082 1083/** 1084* \struct struct drx_scan_param * Parameters for channel scan. 1085* 1086* Used by DRX_CTRL_SCAN_INIT. 1087*/ 1088struct drx_scan_param { 1089 struct drx_frequency_plan *frequency_plan; 1090 /**< Frequency plan (array)*/ 1091 u16 frequency_plan_size; /**< Number of bands */ 1092 u32 num_tries; /**< Max channels tried */ 1093 s32 skip; /**< Minimum frequency step to take 1094 after a channel is found */ 1095 void *ext_params; /**< Standard specific params */ 1096}; 1097 1098/*========================================*/ 1099 1100/** 1101* \brief Scan commands. 1102* Used by scanning algorithms. 1103*/ 1104enum drx_scan_command { 1105 DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */ 1106 DRX_SCAN_COMMAND_NEXT, /**< Next scan */ 1107 DRX_SCAN_COMMAND_STOP /**< Stop scanning */ 1108}; 1109 1110/*========================================*/ 1111 1112/** 1113* \brief Inner scan function prototype. 1114*/ 1115typedef int(*drx_scan_func_t) (void *scan_context, 1116 enum drx_scan_command scan_command, 1117 struct drx_channel *scan_channel, 1118 bool *get_next_channel); 1119 1120/*========================================*/ 1121 1122/** 1123* \struct struct drxtps_info * TPS information, DVB-T specific. 1124* 1125* Used by DRX_CTRL_TPS_INFO. 1126*/ 1127 struct drxtps_info { 1128 enum drx_fft_mode fftmode; /**< Fft mode */ 1129 enum drx_guard guard; /**< Guard interval */ 1130 enum drx_modulation constellation; 1131 /**< Constellation */ 1132 enum drx_hierarchy hierarchy; 1133 /**< Hierarchy */ 1134 enum drx_coderate high_coderate; 1135 /**< High code rate */ 1136 enum drx_coderate low_coderate; 1137 /**< Low cod rate */ 1138 enum drx_tps_frame frame; /**< Tps frame */ 1139 u8 length; /**< Length */ 1140 u16 cell_id; /**< Cell id */ 1141 }; 1142 1143/*========================================*/ 1144 1145/** 1146* \brief Power mode of device. 1147* 1148* Used by DRX_CTRL_SET_POWER_MODE. 1149*/ 1150 enum drx_power_mode { 1151 DRX_POWER_UP = 0, 1152 /**< Generic , Power Up Mode */ 1153 DRX_POWER_MODE_1, 1154 /**< Device specific , Power Up Mode */ 1155 DRX_POWER_MODE_2, 1156 /**< Device specific , Power Up Mode */ 1157 DRX_POWER_MODE_3, 1158 /**< Device specific , Power Up Mode */ 1159 DRX_POWER_MODE_4, 1160 /**< Device specific , Power Up Mode */ 1161 DRX_POWER_MODE_5, 1162 /**< Device specific , Power Up Mode */ 1163 DRX_POWER_MODE_6, 1164 /**< Device specific , Power Up Mode */ 1165 DRX_POWER_MODE_7, 1166 /**< Device specific , Power Up Mode */ 1167 DRX_POWER_MODE_8, 1168 /**< Device specific , Power Up Mode */ 1169 1170 DRX_POWER_MODE_9, 1171 /**< Device specific , Power Down Mode */ 1172 DRX_POWER_MODE_10, 1173 /**< Device specific , Power Down Mode */ 1174 DRX_POWER_MODE_11, 1175 /**< Device specific , Power Down Mode */ 1176 DRX_POWER_MODE_12, 1177 /**< Device specific , Power Down Mode */ 1178 DRX_POWER_MODE_13, 1179 /**< Device specific , Power Down Mode */ 1180 DRX_POWER_MODE_14, 1181 /**< Device specific , Power Down Mode */ 1182 DRX_POWER_MODE_15, 1183 /**< Device specific , Power Down Mode */ 1184 DRX_POWER_MODE_16, 1185 /**< Device specific , Power Down Mode */ 1186 DRX_POWER_DOWN = 255 1187 /**< Generic , Power Down Mode */ 1188 }; 1189 1190/*========================================*/ 1191 1192/** 1193* \enum enum drx_module * \brief Software module identification. 1194* 1195* Used by DRX_CTRL_VERSION. 1196*/ 1197 enum drx_module { 1198 DRX_MODULE_DEVICE, 1199 DRX_MODULE_MICROCODE, 1200 DRX_MODULE_DRIVERCORE, 1201 DRX_MODULE_DEVICEDRIVER, 1202 DRX_MODULE_DAP, 1203 DRX_MODULE_BSP_I2C, 1204 DRX_MODULE_BSP_TUNER, 1205 DRX_MODULE_BSP_HOST, 1206 DRX_MODULE_UNKNOWN 1207 }; 1208 1209/** 1210* \enum struct drx_version * \brief Version information of one software module. 1211* 1212* Used by DRX_CTRL_VERSION. 1213*/ 1214 struct drx_version { 1215 enum drx_module module_type; 1216 /**< Type identifier of the module */ 1217 char *module_name; 1218 /**< Name or description of module */ 1219 u16 v_major; /**< Major version number */ 1220 u16 v_minor; /**< Minor version number */ 1221 u16 v_patch; /**< Patch version number */ 1222 char *v_string; /**< Version as text string */ 1223 }; 1224 1225/** 1226* \enum struct drx_version_list * \brief List element of NULL terminated, linked list for version information. 1227* 1228* Used by DRX_CTRL_VERSION. 1229*/ 1230struct drx_version_list { 1231 struct drx_version *version;/**< Version information */ 1232 struct drx_version_list *next; 1233 /**< Next list element */ 1234}; 1235 1236/*========================================*/ 1237 1238/** 1239* \brief Parameters needed to confiugure a UIO. 1240* 1241* Used by DRX_CTRL_UIO_CFG. 1242*/ 1243 struct drxuio_cfg { 1244 enum drx_uio uio; 1245 /**< UIO identifier */ 1246 enum drxuio_mode mode; 1247 /**< UIO operational mode */ 1248 }; 1249 1250/*========================================*/ 1251 1252/** 1253* \brief Parameters needed to read from or write to a UIO. 1254* 1255* Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE. 1256*/ 1257 struct drxuio_data { 1258 enum drx_uio uio; 1259 /**< UIO identifier */ 1260 bool value; 1261 /**< UIO value (true=1, false=0) */ 1262 }; 1263 1264/*========================================*/ 1265 1266/** 1267* \brief Parameters needed to configure OOB. 1268* 1269* Used by DRX_CTRL_SET_OOB. 1270*/ 1271 struct drxoob { 1272 s32 frequency; /**< Frequency in kHz */ 1273 enum drxoob_downstream_standard standard; 1274 /**< OOB standard */ 1275 bool spectrum_inverted; /**< If true, then spectrum 1276 is inverted */ 1277 }; 1278 1279/*========================================*/ 1280 1281/** 1282* \brief Metrics from OOB. 1283* 1284* Used by DRX_CTRL_GET_OOB. 1285*/ 1286 struct drxoob_status { 1287 s32 frequency; /**< Frequency in Khz */ 1288 enum drx_lock_status lock; /**< Lock status */ 1289 u32 mer; /**< MER */ 1290 s32 symbol_rate_offset; /**< Symbolrate offset in ppm */ 1291 }; 1292 1293/*========================================*/ 1294 1295/** 1296* \brief Device dependent configuration data. 1297* 1298* Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. 1299* A sort of nested drx_ctrl() functionality for device specific controls. 1300*/ 1301 struct drx_cfg { 1302 u32 cfg_type; 1303 /**< Function identifier */ 1304 void *cfg_data; 1305 /**< Function data */ 1306 }; 1307 1308/*========================================*/ 1309 1310/** 1311* /struct DRXMpegStartWidth_t 1312* MStart width [nr MCLK cycles] for serial MPEG output. 1313*/ 1314 1315 enum drxmpeg_str_width { 1316 DRX_MPEG_STR_WIDTH_1, 1317 DRX_MPEG_STR_WIDTH_8 1318 }; 1319 1320/* CTRL CFG MPEG ouput */ 1321/** 1322* \struct struct drx_cfg_mpeg_output * \brief Configuartion parameters for MPEG output control. 1323* 1324* Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and 1325* DRX_CTRL_GET_CFG. 1326*/ 1327 1328 struct drx_cfg_mpeg_output { 1329 bool enable_mpeg_output;/**< If true, enable MPEG output */ 1330 bool insert_rs_byte; /**< If true, insert RS byte */ 1331 bool enable_parallel; /**< If true, parallel out otherwise 1332 serial */ 1333 bool invert_data; /**< If true, invert DATA signals */ 1334 bool invert_err; /**< If true, invert ERR signal */ 1335 bool invert_str; /**< If true, invert STR signals */ 1336 bool invert_val; /**< If true, invert VAL signals */ 1337 bool invert_clk; /**< If true, invert CLK signals */ 1338 bool static_clk; /**< If true, static MPEG clockrate 1339 will be used, otherwise clockrate 1340 will adapt to the bitrate of the 1341 TS */ 1342 u32 bitrate; /**< Maximum bitrate in b/s in case 1343 static clockrate is selected */ 1344 enum drxmpeg_str_width width_str; 1345 /**< MPEG start width */ 1346 }; 1347 1348 1349/*========================================*/ 1350 1351/** 1352* \struct struct drxi2c_data * \brief Data for I2C via 2nd or 3rd or etc I2C port. 1353* 1354* Used by DRX_CTRL_I2C_READWRITE. 1355* If port_nr is equal to primairy port_nr BSPI2C will be used. 1356* 1357*/ 1358 struct drxi2c_data { 1359 u16 port_nr; /**< I2C port number */ 1360 struct i2c_device_addr *w_dev_addr; 1361 /**< Write device address */ 1362 u16 w_count; /**< Size of write data in bytes */ 1363 u8 *wData; /**< Pointer to write data */ 1364 struct i2c_device_addr *r_dev_addr; 1365 /**< Read device address */ 1366 u16 r_count; /**< Size of data to read in bytes */ 1367 u8 *r_data; /**< Pointer to read buffer */ 1368 }; 1369 1370/*========================================*/ 1371 1372/** 1373* \enum enum drx_aud_standard * \brief Audio standard identifier. 1374* 1375* Used by DRX_CTRL_SET_AUD. 1376*/ 1377 enum drx_aud_standard { 1378 DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */ 1379 DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */ 1380 DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */ 1381 DRX_AUD_STANDARD_FM_STEREO,/**< set to FM-Stereo Radio */ 1382 DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */ 1383 DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */ 1384 DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */ 1385 DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */ 1386 DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */ 1387 DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */ 1388 DRX_AUD_STANDARD_BG_NICAM_FM, 1389 /**< set BG_NICAM_FM standard */ 1390 DRX_AUD_STANDARD_L_NICAM_AM, 1391 /**< set L_NICAM_AM standard */ 1392 DRX_AUD_STANDARD_I_NICAM_FM, 1393 /**< set I_NICAM_FM standard */ 1394 DRX_AUD_STANDARD_D_K_NICAM_FM, 1395 /**< set D_K_NICAM_FM standard */ 1396 DRX_AUD_STANDARD_NOT_READY,/**< used to detect audio standard */ 1397 DRX_AUD_STANDARD_AUTO = DRX_AUTO, 1398 /**< Automatic Standard Detection */ 1399 DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN 1400 /**< used as auto and for readback */ 1401 }; 1402 1403/* CTRL_AUD_GET_STATUS - struct drx_aud_status */ 1404/** 1405* \enum enum drx_aud_nicam_status * \brief Status of NICAM carrier. 1406*/ 1407 enum drx_aud_nicam_status { 1408 DRX_AUD_NICAM_DETECTED = 0, 1409 /**< NICAM carrier detected */ 1410 DRX_AUD_NICAM_NOT_DETECTED, 1411 /**< NICAM carrier not detected */ 1412 DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */ 1413 }; 1414 1415/** 1416* \struct struct drx_aud_status * \brief Audio status characteristics. 1417*/ 1418 struct drx_aud_status { 1419 bool stereo; /**< stereo detection */ 1420 bool carrier_a; /**< carrier A detected */ 1421 bool carrier_b; /**< carrier B detected */ 1422 bool sap; /**< sap / bilingual detection */ 1423 bool rds; /**< RDS data array present */ 1424 enum drx_aud_nicam_status nicam_status; 1425 /**< status of NICAM carrier */ 1426 s8 fm_ident; /**< FM Identification value */ 1427 }; 1428 1429/* CTRL_AUD_READ_RDS - DRXRDSdata_t */ 1430 1431/** 1432* \struct DRXRDSdata_t 1433* \brief Raw RDS data array. 1434*/ 1435 struct drx_cfg_aud_rds { 1436 bool valid; /**< RDS data validation */ 1437 u16 data[18]; /**< data from one RDS data array */ 1438 }; 1439 1440/* DRX_CFG_AUD_VOLUME - struct drx_cfg_aud_volume - set/get */ 1441/** 1442* \enum DRXAudAVCDecayTime_t 1443* \brief Automatic volume control configuration. 1444*/ 1445 enum drx_aud_avc_mode { 1446 DRX_AUD_AVC_OFF, /**< Automatic volume control off */ 1447 DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */ 1448 DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */ 1449 DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */ 1450 DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */ 1451 }; 1452 1453/** 1454* /enum DRXAudMaxAVCGain_t 1455* /brief Automatic volume control max gain in audio baseband. 1456*/ 1457 enum drx_aud_avc_max_gain { 1458 DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */ 1459 DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */ 1460 DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */ 1461 }; 1462 1463/** 1464* /enum DRXAudMaxAVCAtten_t 1465* /brief Automatic volume control max attenuation in audio baseband. 1466*/ 1467 enum drx_aud_avc_max_atten { 1468 DRX_AUD_AVC_MAX_ATTEN_12DB, 1469 /**< maximum AVC attenuation 12 dB */ 1470 DRX_AUD_AVC_MAX_ATTEN_18DB, 1471 /**< maximum AVC attenuation 18 dB */ 1472 DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */ 1473 }; 1474/** 1475* \struct struct drx_cfg_aud_volume * \brief Audio volume configuration. 1476*/ 1477 struct drx_cfg_aud_volume { 1478 bool mute; /**< mute overrides volume setting */ 1479 s16 volume; /**< volume, range -114 to 12 dB */ 1480 enum drx_aud_avc_mode avc_mode; /**< AVC auto volume control mode */ 1481 u16 avc_ref_level; /**< AVC reference level */ 1482 enum drx_aud_avc_max_gain avc_max_gain; 1483 /**< AVC max gain selection */ 1484 enum drx_aud_avc_max_atten avc_max_atten; 1485 /**< AVC max attenuation selection */ 1486 s16 strength_left; /**< quasi-peak, left speaker */ 1487 s16 strength_right; /**< quasi-peak, right speaker */ 1488 }; 1489 1490/* DRX_CFG_I2S_OUTPUT - struct drx_cfg_i2s_output - set/get */ 1491/** 1492* \enum enum drxi2s_mode * \brief I2S output mode. 1493*/ 1494 enum drxi2s_mode { 1495 DRX_I2S_MODE_MASTER, /**< I2S is in master mode */ 1496 DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */ 1497 }; 1498 1499/** 1500* \enum enum drxi2s_word_length * \brief Width of I2S data. 1501*/ 1502 enum drxi2s_word_length { 1503 DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */ 1504 DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */ 1505 }; 1506 1507/** 1508* \enum enum drxi2s_format * \brief Data wordstrobe alignment for I2S. 1509*/ 1510 enum drxi2s_format { 1511 DRX_I2S_FORMAT_WS_WITH_DATA, 1512 /**< I2S data and wordstrobe are aligned */ 1513 DRX_I2S_FORMAT_WS_ADVANCED 1514 /**< I2S data one cycle after wordstrobe */ 1515 }; 1516 1517/** 1518* \enum enum drxi2s_polarity * \brief Polarity of I2S data. 1519*/ 1520 enum drxi2s_polarity { 1521 DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */ 1522 DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */ 1523 }; 1524 1525/** 1526* \struct struct drx_cfg_i2s_output * \brief I2S output configuration. 1527*/ 1528 struct drx_cfg_i2s_output { 1529 bool output_enable; /**< I2S output enable */ 1530 u32 frequency; /**< range from 8000-48000 Hz */ 1531 enum drxi2s_mode mode; /**< I2S mode, master or slave */ 1532 enum drxi2s_word_length word_length; 1533 /**< I2S wordlength, 16 or 32 bits */ 1534 enum drxi2s_polarity polarity;/**< I2S wordstrobe polarity */ 1535 enum drxi2s_format format; /**< I2S wordstrobe delay to data */ 1536 }; 1537 1538/* ------------------------------expert interface-----------------------------*/ 1539/** 1540* /enum enum drx_aud_fm_deemphasis * setting for FM-Deemphasis in audio demodulator. 1541* 1542*/ 1543 enum drx_aud_fm_deemphasis { 1544 DRX_AUD_FM_DEEMPH_50US, 1545 DRX_AUD_FM_DEEMPH_75US, 1546 DRX_AUD_FM_DEEMPH_OFF 1547 }; 1548 1549/** 1550* /enum DRXAudDeviation_t 1551* setting for deviation mode in audio demodulator. 1552* 1553*/ 1554 enum drx_cfg_aud_deviation { 1555 DRX_AUD_DEVIATION_NORMAL, 1556 DRX_AUD_DEVIATION_HIGH 1557 }; 1558 1559/** 1560* /enum enum drx_no_carrier_option * setting for carrier, mute/noise. 1561* 1562*/ 1563 enum drx_no_carrier_option { 1564 DRX_NO_CARRIER_MUTE, 1565 DRX_NO_CARRIER_NOISE 1566 }; 1567 1568/** 1569* \enum DRXAudAutoSound_t 1570* \brief Automatic Sound 1571*/ 1572 enum drx_cfg_aud_auto_sound { 1573 DRX_AUD_AUTO_SOUND_OFF = 0, 1574 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, 1575 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF 1576 }; 1577 1578/** 1579* \enum DRXAudASSThres_t 1580* \brief Automatic Sound Select Thresholds 1581*/ 1582 struct drx_cfg_aud_ass_thres { 1583 u16 a2; /* A2 Threshold for ASS configuration */ 1584 u16 btsc; /* BTSC Threshold for ASS configuration */ 1585 u16 nicam; /* Nicam Threshold for ASS configuration */ 1586 }; 1587 1588/** 1589* \struct struct drx_aud_carrier * \brief Carrier detection related parameters 1590*/ 1591 struct drx_aud_carrier { 1592 u16 thres; /* carrier detetcion threshold for primary carrier (A) */ 1593 enum drx_no_carrier_option opt; /* Mute or noise at no carrier detection (A) */ 1594 s32 shift; /* DC level of incoming signal (A) */ 1595 s32 dco; /* frequency adjustment (A) */ 1596 }; 1597 1598/** 1599* \struct struct drx_cfg_aud_carriers * \brief combining carrier A & B to one struct 1600*/ 1601 struct drx_cfg_aud_carriers { 1602 struct drx_aud_carrier a; 1603 struct drx_aud_carrier b; 1604 }; 1605 1606/** 1607* /enum enum drx_aud_i2s_src * Selection of audio source 1608*/ 1609 enum drx_aud_i2s_src { 1610 DRX_AUD_SRC_MONO, 1611 DRX_AUD_SRC_STEREO_OR_AB, 1612 DRX_AUD_SRC_STEREO_OR_A, 1613 DRX_AUD_SRC_STEREO_OR_B}; 1614 1615/** 1616* \enum enum drx_aud_i2s_matrix * \brief Used for selecting I2S output. 1617*/ 1618 enum drx_aud_i2s_matrix { 1619 DRX_AUD_I2S_MATRIX_A_MONO, 1620 /**< A sound only, stereo or mono */ 1621 DRX_AUD_I2S_MATRIX_B_MONO, 1622 /**< B sound only, stereo or mono */ 1623 DRX_AUD_I2S_MATRIX_STEREO, 1624 /**< A+B sound, transparant */ 1625 DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */}; 1626 1627/** 1628* /enum enum drx_aud_fm_matrix * setting for FM-Matrix in audio demodulator. 1629* 1630*/ 1631 enum drx_aud_fm_matrix { 1632 DRX_AUD_FM_MATRIX_NO_MATRIX, 1633 DRX_AUD_FM_MATRIX_GERMAN, 1634 DRX_AUD_FM_MATRIX_KOREAN, 1635 DRX_AUD_FM_MATRIX_SOUND_A, 1636 DRX_AUD_FM_MATRIX_SOUND_B}; 1637 1638/** 1639* \struct DRXAudMatrices_t 1640* \brief Mixer settings 1641*/ 1642struct drx_cfg_aud_mixer { 1643 enum drx_aud_i2s_src source_i2s; 1644 enum drx_aud_i2s_matrix matrix_i2s; 1645 enum drx_aud_fm_matrix matrix_fm; 1646}; 1647 1648/** 1649* \enum DRXI2SVidSync_t 1650* \brief Audio/video synchronization, interacts with I2S mode. 1651* AUTO_1 and AUTO_2 are for automatic video standard detection with preference 1652* for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz) 1653*/ 1654 enum drx_cfg_aud_av_sync { 1655 DRX_AUD_AVSYNC_OFF,/**< audio/video synchronization is off */ 1656 DRX_AUD_AVSYNC_NTSC, 1657 /**< it is an NTSC system */ 1658 DRX_AUD_AVSYNC_MONOCHROME, 1659 /**< it is a MONOCHROME system */ 1660 DRX_AUD_AVSYNC_PAL_SECAM 1661 /**< it is a PAL/SECAM system */}; 1662 1663/** 1664* \struct struct drx_cfg_aud_prescale * \brief Prescalers 1665*/ 1666struct drx_cfg_aud_prescale { 1667 u16 fm_deviation; 1668 s16 nicam_gain; 1669}; 1670 1671/** 1672* \struct struct drx_aud_beep * \brief Beep 1673*/ 1674struct drx_aud_beep { 1675 s16 volume; /* dB */ 1676 u16 frequency; /* Hz */ 1677 bool mute; 1678}; 1679 1680/** 1681* \enum enum drx_aud_btsc_detect * \brief BTSC detetcion mode 1682*/ 1683 enum drx_aud_btsc_detect { 1684 DRX_BTSC_STEREO, 1685 DRX_BTSC_MONO_AND_SAP}; 1686 1687/** 1688* \struct struct drx_aud_data * \brief Audio data structure 1689*/ 1690struct drx_aud_data { 1691 /* audio storage */ 1692 bool audio_is_active; 1693 enum drx_aud_standard audio_standard; 1694 struct drx_cfg_i2s_output i2sdata; 1695 struct drx_cfg_aud_volume volume; 1696 enum drx_cfg_aud_auto_sound auto_sound; 1697 struct drx_cfg_aud_ass_thres ass_thresholds; 1698 struct drx_cfg_aud_carriers carriers; 1699 struct drx_cfg_aud_mixer mixer; 1700 enum drx_cfg_aud_deviation deviation; 1701 enum drx_cfg_aud_av_sync av_sync; 1702 struct drx_cfg_aud_prescale prescale; 1703 enum drx_aud_fm_deemphasis deemph; 1704 enum drx_aud_btsc_detect btsc_detect; 1705 /* rds */ 1706 u16 rds_data_counter; 1707 bool rds_data_present; 1708}; 1709 1710/** 1711* \enum enum drx_qam_lock_range * \brief QAM lock range mode 1712*/ 1713 enum drx_qam_lock_range { 1714 DRX_QAM_LOCKRANGE_NORMAL, 1715 DRX_QAM_LOCKRANGE_EXTENDED}; 1716 1717/*============================================================================*/ 1718/*============================================================================*/ 1719/*== Data access structures ==================================================*/ 1720/*============================================================================*/ 1721/*============================================================================*/ 1722 1723/* Address on device */ 1724 typedef u32 dr_xaddr_t, *pdr_xaddr_t; 1725 1726/* Protocol specific flags */ 1727 typedef u32 dr_xflags_t, *pdr_xflags_t; 1728 1729/* Write block of data to device */ 1730 typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1731 u32 addr, /* address of register/memory */ 1732 u16 datasize, /* size of data in bytes */ 1733 u8 *data, /* data to send */ 1734 u32 flags); 1735 1736/* Read block of data from device */ 1737 typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1738 u32 addr, /* address of register/memory */ 1739 u16 datasize, /* size of data in bytes */ 1740 u8 *data, /* receive buffer */ 1741 u32 flags); 1742 1743/* Write 8-bits value to device */ 1744 typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1745 u32 addr, /* address of register/memory */ 1746 u8 data, /* data to send */ 1747 u32 flags); 1748 1749/* Read 8-bits value to device */ 1750 typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1751 u32 addr, /* address of register/memory */ 1752 u8 *data, /* receive buffer */ 1753 u32 flags); 1754 1755/* Read modify write 8-bits value to device */ 1756 typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1757 u32 waddr, /* write address of register */ 1758 u32 raddr, /* read address of register */ 1759 u8 wdata, /* data to write */ 1760 u8 *rdata); /* data to read */ 1761 1762/* Write 16-bits value to device */ 1763 typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1764 u32 addr, /* address of register/memory */ 1765 u16 data, /* data to send */ 1766 u32 flags); 1767 1768/* Read 16-bits value to device */ 1769 typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1770 u32 addr, /* address of register/memory */ 1771 u16 *data, /* receive buffer */ 1772 u32 flags); 1773 1774/* Read modify write 16-bits value to device */ 1775 typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1776 u32 waddr, /* write address of register */ 1777 u32 raddr, /* read address of register */ 1778 u16 wdata, /* data to write */ 1779 u16 *rdata); /* data to read */ 1780 1781/* Write 32-bits value to device */ 1782 typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1783 u32 addr, /* address of register/memory */ 1784 u32 data, /* data to send */ 1785 u32 flags); 1786 1787/* Read 32-bits value to device */ 1788 typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1789 u32 addr, /* address of register/memory */ 1790 u32 *data, /* receive buffer */ 1791 u32 flags); 1792 1793/* Read modify write 32-bits value to device */ 1794 typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ 1795 u32 waddr, /* write address of register */ 1796 u32 raddr, /* read address of register */ 1797 u32 wdata, /* data to write */ 1798 u32 *rdata); /* data to read */ 1799 1800/** 1801* \struct struct drx_access_func * \brief Interface to an access protocol. 1802*/ 1803struct drx_access_func { 1804 drx_write_block_func_t write_block_func; 1805 drx_read_block_func_t read_block_func; 1806 drx_write_reg8func_t write_reg8func; 1807 drx_read_reg8func_t read_reg8func; 1808 drx_read_modify_write_reg8func_t read_modify_write_reg8func; 1809 drx_write_reg16func_t write_reg16func; 1810 drx_read_reg16func_t read_reg16func; 1811 drx_read_modify_write_reg16func_t read_modify_write_reg16func; 1812 drx_write_reg32func_t write_reg32func; 1813 drx_read_reg32func_t read_reg32func; 1814 drx_read_modify_write_reg32func_t read_modify_write_reg32func; 1815}; 1816 1817/* Register address and data for register dump function */ 1818struct drx_reg_dump { 1819 u32 address; 1820 u32 data; 1821}; 1822 1823/*============================================================================*/ 1824/*============================================================================*/ 1825/*== Demod instance data structures ==========================================*/ 1826/*============================================================================*/ 1827/*============================================================================*/ 1828 1829/** 1830* \struct struct drx_common_attr * \brief Set of common attributes, shared by all DRX devices. 1831*/ 1832 struct drx_common_attr { 1833 /* Microcode (firmware) attributes */ 1834 char *microcode_file; /**< microcode filename */ 1835 bool verify_microcode; 1836 /**< Use microcode verify or not. */ 1837 struct drx_mc_version_rec mcversion; 1838 /**< Version record of microcode from file */ 1839 1840 /* Clocks and tuner attributes */ 1841 s32 intermediate_freq; 1842 /**< IF,if tuner instance not used. (kHz)*/ 1843 s32 sys_clock_freq; 1844 /**< Systemclock frequency. (kHz) */ 1845 s32 osc_clock_freq; 1846 /**< Oscillator clock frequency. (kHz) */ 1847 s16 osc_clock_deviation; 1848 /**< Oscillator clock deviation. (ppm) */ 1849 bool mirror_freq_spect; 1850 /**< Mirror IF frequency spectrum or not.*/ 1851 1852 /* Initial MPEG output attributes */ 1853 struct drx_cfg_mpeg_output mpeg_cfg; 1854 /**< MPEG configuration */ 1855 1856 bool is_opened; /**< if true instance is already opened. */ 1857 1858 /* Channel scan */ 1859 struct drx_scan_param *scan_param; 1860 /**< scan parameters */ 1861 u16 scan_freq_plan_index; 1862 /**< next index in freq plan */ 1863 s32 scan_next_frequency; 1864 /**< next freq to scan */ 1865 bool scan_ready; /**< scan ready flag */ 1866 u32 scan_max_channels;/**< number of channels in freqplan */ 1867 u32 scan_channels_scanned; 1868 /**< number of channels scanned */ 1869 /* Channel scan - inner loop: demod related */ 1870 drx_scan_func_t scan_function; 1871 /**< function to check channel */ 1872 /* Channel scan - inner loop: SYSObj related */ 1873 void *scan_context; /**< Context Pointer of SYSObj */ 1874 /* Channel scan - parameters for default DTV scan function in core driver */ 1875 u16 scan_demod_lock_timeout; 1876 /**< millisecs to wait for lock */ 1877 enum drx_lock_status scan_desired_lock; 1878 /**< lock requirement for channel found */ 1879 /* scan_active can be used by SetChannel to decide how to program the tuner, 1880 fast or slow (but stable). Usually fast during scan. */ 1881 bool scan_active; /**< true when scan routines are active */ 1882 1883 /* Power management */ 1884 enum drx_power_mode current_power_mode; 1885 /**< current power management mode */ 1886 1887 /* Tuner */ 1888 u8 tuner_port_nr; /**< nr of I2C port to wich tuner is */ 1889 s32 tuner_min_freq_rf; 1890 /**< minimum RF input frequency, in kHz */ 1891 s32 tuner_max_freq_rf; 1892 /**< maximum RF input frequency, in kHz */ 1893 bool tuner_rf_agc_pol; /**< if true invert RF AGC polarity */ 1894 bool tuner_if_agc_pol; /**< if true invert IF AGC polarity */ 1895 bool tuner_slow_mode; /**< if true invert IF AGC polarity */ 1896 1897 struct drx_channel current_channel; 1898 /**< current channel parameters */ 1899 enum drx_standard current_standard; 1900 /**< current standard selection */ 1901 enum drx_standard prev_standard; 1902 /**< previous standard selection */ 1903 enum drx_standard di_cache_standard; 1904 /**< standard in DI cache if available */ 1905 bool use_bootloader; /**< use bootloader in open */ 1906 u32 capabilities; /**< capabilities flags */ 1907 u32 product_id; /**< product ID inc. metal fix number */}; 1908 1909/* 1910* Generic functions for DRX devices. 1911*/ 1912 1913struct drx_demod_instance; 1914 1915/** 1916* \struct struct drx_demod_instance * \brief Top structure of demodulator instance. 1917*/ 1918struct drx_demod_instance { 1919 /**< data access protocol functions */ 1920 struct i2c_device_addr *my_i2c_dev_addr; 1921 /**< i2c address and device identifier */ 1922 struct drx_common_attr *my_common_attr; 1923 /**< common DRX attributes */ 1924 void *my_ext_attr; /**< device specific attributes */ 1925 /* generic demodulator data */ 1926 1927 struct i2c_adapter *i2c; 1928 const struct firmware *firmware; 1929}; 1930 1931/*------------------------------------------------------------------------- 1932MACROS 1933Conversion from enum values to human readable form. 1934-------------------------------------------------------------------------*/ 1935 1936/* standard */ 1937 1938#define DRX_STR_STANDARD(x) ( \ 1939 (x == DRX_STANDARD_DVBT) ? "DVB-T" : \ 1940 (x == DRX_STANDARD_8VSB) ? "8VSB" : \ 1941 (x == DRX_STANDARD_NTSC) ? "NTSC" : \ 1942 (x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \ 1943 (x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \ 1944 (x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \ 1945 (x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \ 1946 (x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \ 1947 (x == DRX_STANDARD_ITU_A) ? "ITU-A" : \ 1948 (x == DRX_STANDARD_ITU_B) ? "ITU-B" : \ 1949 (x == DRX_STANDARD_ITU_C) ? "ITU-C" : \ 1950 (x == DRX_STANDARD_ITU_D) ? "ITU-D" : \ 1951 (x == DRX_STANDARD_FM) ? "FM" : \ 1952 (x == DRX_STANDARD_DTMB) ? "DTMB" : \ 1953 (x == DRX_STANDARD_AUTO) ? "Auto" : \ 1954 (x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \ 1955 "(Invalid)") 1956 1957/* channel */ 1958 1959#define DRX_STR_BANDWIDTH(x) ( \ 1960 (x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \ 1961 (x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \ 1962 (x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \ 1963 (x == DRX_BANDWIDTH_AUTO) ? "Auto" : \ 1964 (x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \ 1965 "(Invalid)") 1966#define DRX_STR_FFTMODE(x) ( \ 1967 (x == DRX_FFTMODE_2K) ? "2k" : \ 1968 (x == DRX_FFTMODE_4K) ? "4k" : \ 1969 (x == DRX_FFTMODE_8K) ? "8k" : \ 1970 (x == DRX_FFTMODE_AUTO) ? "Auto" : \ 1971 (x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \ 1972 "(Invalid)") 1973#define DRX_STR_GUARD(x) ( \ 1974 (x == DRX_GUARD_1DIV32) ? "1/32nd" : \ 1975 (x == DRX_GUARD_1DIV16) ? "1/16th" : \ 1976 (x == DRX_GUARD_1DIV8) ? "1/8th" : \ 1977 (x == DRX_GUARD_1DIV4) ? "1/4th" : \ 1978 (x == DRX_GUARD_AUTO) ? "Auto" : \ 1979 (x == DRX_GUARD_UNKNOWN) ? "Unknown" : \ 1980 "(Invalid)") 1981#define DRX_STR_CONSTELLATION(x) ( \ 1982 (x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \ 1983 (x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \ 1984 (x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \ 1985 (x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \ 1986 (x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \ 1987 (x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \ 1988 (x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \ 1989 (x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \ 1990 (x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \ 1991 (x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \ 1992 (x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \ 1993 (x == DRX_CONSTELLATION_AUTO) ? "Auto" : \ 1994 (x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \ 1995 "(Invalid)") 1996#define DRX_STR_CODERATE(x) ( \ 1997 (x == DRX_CODERATE_1DIV2) ? "1/2nd" : \ 1998 (x == DRX_CODERATE_2DIV3) ? "2/3rd" : \ 1999 (x == DRX_CODERATE_3DIV4) ? "3/4th" : \ 2000 (x == DRX_CODERATE_5DIV6) ? "5/6th" : \ 2001 (x == DRX_CODERATE_7DIV8) ? "7/8th" : \ 2002 (x == DRX_CODERATE_AUTO) ? "Auto" : \ 2003 (x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \ 2004 "(Invalid)") 2005#define DRX_STR_HIERARCHY(x) ( \ 2006 (x == DRX_HIERARCHY_NONE) ? "None" : \ 2007 (x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \ 2008 (x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \ 2009 (x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \ 2010 (x == DRX_HIERARCHY_AUTO) ? "Auto" : \ 2011 (x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \ 2012 "(Invalid)") 2013#define DRX_STR_PRIORITY(x) ( \ 2014 (x == DRX_PRIORITY_LOW) ? "Low" : \ 2015 (x == DRX_PRIORITY_HIGH) ? "High" : \ 2016 (x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \ 2017 "(Invalid)") 2018#define DRX_STR_MIRROR(x) ( \ 2019 (x == DRX_MIRROR_NO) ? "Normal" : \ 2020 (x == DRX_MIRROR_YES) ? "Mirrored" : \ 2021 (x == DRX_MIRROR_AUTO) ? "Auto" : \ 2022 (x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \ 2023 "(Invalid)") 2024#define DRX_STR_CLASSIFICATION(x) ( \ 2025 (x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \ 2026 (x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \ 2027 (x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \ 2028 (x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \ 2029 (x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \ 2030 (x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \ 2031 (x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \ 2032 (x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \ 2033 "(Invalid)") 2034 2035#define DRX_STR_INTERLEAVEMODE(x) ( \ 2036 (x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \ 2037 (x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \ 2038 (x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \ 2039 (x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \ 2040 (x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \ 2041 (x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \ 2042 (x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \ 2043 (x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \ 2044 (x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \ 2045 (x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \ 2046 (x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \ 2047 (x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \ 2048 (x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \ 2049 (x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \ 2050 (x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \ 2051 (x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \ 2052 (x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \ 2053 (x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \ 2054 (x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \ 2055 (x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \ 2056 (x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \ 2057 (x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \ 2058 (x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \ 2059 (x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \ 2060 "(Invalid)") 2061 2062#define DRX_STR_LDPC(x) ( \ 2063 (x == DRX_LDPC_0_4) ? "0.4" : \ 2064 (x == DRX_LDPC_0_6) ? "0.6" : \ 2065 (x == DRX_LDPC_0_8) ? "0.8" : \ 2066 (x == DRX_LDPC_AUTO) ? "Auto" : \ 2067 (x == DRX_LDPC_UNKNOWN) ? "Unknown" : \ 2068 "(Invalid)") 2069 2070#define DRX_STR_CARRIER(x) ( \ 2071 (x == DRX_CARRIER_MULTI) ? "Multi" : \ 2072 (x == DRX_CARRIER_SINGLE) ? "Single" : \ 2073 (x == DRX_CARRIER_AUTO) ? "Auto" : \ 2074 (x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \ 2075 "(Invalid)") 2076 2077#define DRX_STR_FRAMEMODE(x) ( \ 2078 (x == DRX_FRAMEMODE_420) ? "420" : \ 2079 (x == DRX_FRAMEMODE_595) ? "595" : \ 2080 (x == DRX_FRAMEMODE_945) ? "945" : \ 2081 (x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \ 2082 (x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \ 2083 (x == DRX_FRAMEMODE_AUTO) ? "Auto" : \ 2084 (x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \ 2085 "(Invalid)") 2086 2087#define DRX_STR_PILOT(x) ( \ 2088 (x == DRX_PILOT_ON) ? "On" : \ 2089 (x == DRX_PILOT_OFF) ? "Off" : \ 2090 (x == DRX_PILOT_AUTO) ? "Auto" : \ 2091 (x == DRX_PILOT_UNKNOWN) ? "Unknown" : \ 2092 "(Invalid)") 2093/* TPS */ 2094 2095#define DRX_STR_TPS_FRAME(x) ( \ 2096 (x == DRX_TPS_FRAME1) ? "Frame1" : \ 2097 (x == DRX_TPS_FRAME2) ? "Frame2" : \ 2098 (x == DRX_TPS_FRAME3) ? "Frame3" : \ 2099 (x == DRX_TPS_FRAME4) ? "Frame4" : \ 2100 (x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \ 2101 "(Invalid)") 2102 2103/* lock status */ 2104 2105#define DRX_STR_LOCKSTATUS(x) ( \ 2106 (x == DRX_NEVER_LOCK) ? "Never" : \ 2107 (x == DRX_NOT_LOCKED) ? "No" : \ 2108 (x == DRX_LOCKED) ? "Locked" : \ 2109 (x == DRX_LOCK_STATE_1) ? "Lock state 1" : \ 2110 (x == DRX_LOCK_STATE_2) ? "Lock state 2" : \ 2111 (x == DRX_LOCK_STATE_3) ? "Lock state 3" : \ 2112 (x == DRX_LOCK_STATE_4) ? "Lock state 4" : \ 2113 (x == DRX_LOCK_STATE_5) ? "Lock state 5" : \ 2114 (x == DRX_LOCK_STATE_6) ? "Lock state 6" : \ 2115 (x == DRX_LOCK_STATE_7) ? "Lock state 7" : \ 2116 (x == DRX_LOCK_STATE_8) ? "Lock state 8" : \ 2117 (x == DRX_LOCK_STATE_9) ? "Lock state 9" : \ 2118 "(Invalid)") 2119 2120/* version information , modules */ 2121#define DRX_STR_MODULE(x) ( \ 2122 (x == DRX_MODULE_DEVICE) ? "Device" : \ 2123 (x == DRX_MODULE_MICROCODE) ? "Microcode" : \ 2124 (x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \ 2125 (x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \ 2126 (x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \ 2127 (x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \ 2128 (x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \ 2129 (x == DRX_MODULE_DAP) ? "Data Access Protocol" : \ 2130 (x == DRX_MODULE_UNKNOWN) ? "Unknown" : \ 2131 "(Invalid)") 2132 2133#define DRX_STR_POWER_MODE(x) ( \ 2134 (x == DRX_POWER_UP) ? "DRX_POWER_UP " : \ 2135 (x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \ 2136 (x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \ 2137 (x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \ 2138 (x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \ 2139 (x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \ 2140 (x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \ 2141 (x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \ 2142 (x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \ 2143 (x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \ 2144 (x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \ 2145 (x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \ 2146 (x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \ 2147 (x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \ 2148 (x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \ 2149 (x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \ 2150 (x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \ 2151 (x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \ 2152 "(Invalid)") 2153 2154#define DRX_STR_OOB_STANDARD(x) ( \ 2155 (x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \ 2156 (x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \ 2157 (x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \ 2158 "(Invalid)") 2159 2160#define DRX_STR_AUD_STANDARD(x) ( \ 2161 (x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \ 2162 (x == DRX_AUD_STANDARD_A2) ? "A2" : \ 2163 (x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \ 2164 (x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \ 2165 (x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \ 2166 (x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \ 2167 (x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \ 2168 (x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \ 2169 (x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \ 2170 (x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \ 2171 (x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \ 2172 (x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \ 2173 (x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \ 2174 (x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \ 2175 (x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \ 2176 (x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \ 2177 "(Invalid)") 2178#define DRX_STR_AUD_STEREO(x) ( \ 2179 (x == true) ? "Stereo" : \ 2180 (x == false) ? "Mono" : \ 2181 "(Invalid)") 2182 2183#define DRX_STR_AUD_SAP(x) ( \ 2184 (x == true) ? "Present" : \ 2185 (x == false) ? "Not present" : \ 2186 "(Invalid)") 2187 2188#define DRX_STR_AUD_CARRIER(x) ( \ 2189 (x == true) ? "Present" : \ 2190 (x == false) ? "Not present" : \ 2191 "(Invalid)") 2192 2193#define DRX_STR_AUD_RDS(x) ( \ 2194 (x == true) ? "Available" : \ 2195 (x == false) ? "Not Available" : \ 2196 "(Invalid)") 2197 2198#define DRX_STR_AUD_NICAM_STATUS(x) ( \ 2199 (x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \ 2200 (x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \ 2201 (x == DRX_AUD_NICAM_BAD) ? "Bad" : \ 2202 "(Invalid)") 2203 2204#define DRX_STR_RDS_VALID(x) ( \ 2205 (x == true) ? "Valid" : \ 2206 (x == false) ? "Not Valid" : \ 2207 "(Invalid)") 2208 2209/*------------------------------------------------------------------------- 2210Access macros 2211-------------------------------------------------------------------------*/ 2212 2213/** 2214* \brief Create a compilable reference to the microcode attribute 2215* \param d pointer to demod instance 2216* 2217* Used as main reference to an attribute field. 2218* Used by both macro implementation and function implementation. 2219* These macros are defined to avoid duplication of code in macro and function 2220* definitions that handle access of demod common or extended attributes. 2221* 2222*/ 2223 2224#define DRX_ATTR_MCRECORD(d) ((d)->my_common_attr->mcversion) 2225#define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->my_common_attr->mirror_freq_spect) 2226#define DRX_ATTR_CURRENTPOWERMODE(d)((d)->my_common_attr->current_power_mode) 2227#define DRX_ATTR_ISOPENED(d) ((d)->my_common_attr->is_opened) 2228#define DRX_ATTR_USEBOOTLOADER(d) ((d)->my_common_attr->use_bootloader) 2229#define DRX_ATTR_CURRENTSTANDARD(d) ((d)->my_common_attr->current_standard) 2230#define DRX_ATTR_PREVSTANDARD(d) ((d)->my_common_attr->prev_standard) 2231#define DRX_ATTR_CACHESTANDARD(d) ((d)->my_common_attr->di_cache_standard) 2232#define DRX_ATTR_CURRENTCHANNEL(d) ((d)->my_common_attr->current_channel) 2233#define DRX_ATTR_MICROCODE(d) ((d)->my_common_attr->microcode) 2234#define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode) 2235#define DRX_ATTR_CAPABILITIES(d) ((d)->my_common_attr->capabilities) 2236#define DRX_ATTR_PRODUCTID(d) ((d)->my_common_attr->product_id) 2237#define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->my_common_attr->intermediate_freq) 2238#define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->my_common_attr->sys_clock_freq) 2239#define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->my_common_attr->tuner_rf_agc_pol) 2240#define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->my_common_attr->tuner_if_agc_pol) 2241#define DRX_ATTR_TUNERSLOWMODE(d) ((d)->my_common_attr->tuner_slow_mode) 2242#define DRX_ATTR_TUNERSPORTNR(d) ((d)->my_common_attr->tuner_port_nr) 2243#define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr) 2244#define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id) 2245#define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD) 2246 2247/**************************/ 2248 2249/* Macros with device-specific handling are converted to CFG functions */ 2250 2251#define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \ 2252 do { \ 2253 struct drx_cfg config; \ 2254 data_type cfg_data; \ 2255 config.cfg_type = cfg_name; \ 2256 config.cfg_data = &cfg_data; \ 2257 cfg_data = value; \ 2258 drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \ 2259 } while (0) 2260 2261#define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \ 2262 do { \ 2263 int cfg_status; \ 2264 struct drx_cfg config; \ 2265 data_type cfg_data; \ 2266 config.cfg_type = cfg_name; \ 2267 config.cfg_data = &cfg_data; \ 2268 cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \ 2269 if (cfg_status == 0) { \ 2270 value = cfg_data; \ 2271 } else { \ 2272 value = (data_type)error_value; \ 2273 } \ 2274 } while (0) 2275 2276/* Configuration functions for usage by Access (XS) Macros */ 2277 2278#ifndef DRX_XS_CFG_BASE 2279#define DRX_XS_CFG_BASE (500) 2280#endif 2281 2282#define DRX_XS_CFG_PRESET (DRX_XS_CFG_BASE + 0) 2283#define DRX_XS_CFG_AUD_BTSC_DETECT (DRX_XS_CFG_BASE + 1) 2284#define DRX_XS_CFG_QAM_LOCKRANGE (DRX_XS_CFG_BASE + 2) 2285 2286/* Access Macros with device-specific handling */ 2287 2288#define DRX_SET_PRESET(d, x) \ 2289 DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*) 2290#define DRX_GET_PRESET(d, x) \ 2291 DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR") 2292 2293#define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \ 2294 DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect) 2295#define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \ 2296 DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect, DRX_UNKNOWN) 2297 2298#define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \ 2299 DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range) 2300#define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \ 2301 DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range, DRX_UNKNOWN) 2302 2303/** 2304* \brief Macro to check if std is an ATV standard 2305* \retval true std is an ATV standard 2306* \retval false std is an ATV standard 2307*/ 2308#define DRX_ISATVSTD(std) (((std) == DRX_STANDARD_PAL_SECAM_BG) || \ 2309 ((std) == DRX_STANDARD_PAL_SECAM_DK) || \ 2310 ((std) == DRX_STANDARD_PAL_SECAM_I) || \ 2311 ((std) == DRX_STANDARD_PAL_SECAM_L) || \ 2312 ((std) == DRX_STANDARD_PAL_SECAM_LP) || \ 2313 ((std) == DRX_STANDARD_NTSC) || \ 2314 ((std) == DRX_STANDARD_FM)) 2315 2316/** 2317* \brief Macro to check if std is an QAM standard 2318* \retval true std is an QAM standards 2319* \retval false std is an QAM standards 2320*/ 2321#define DRX_ISQAMSTD(std) (((std) == DRX_STANDARD_ITU_A) || \ 2322 ((std) == DRX_STANDARD_ITU_B) || \ 2323 ((std) == DRX_STANDARD_ITU_C) || \ 2324 ((std) == DRX_STANDARD_ITU_D)) 2325 2326/** 2327* \brief Macro to check if std is VSB standard 2328* \retval true std is VSB standard 2329* \retval false std is not VSB standard 2330*/ 2331#define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB) 2332 2333/** 2334* \brief Macro to check if std is DVBT standard 2335* \retval true std is DVBT standard 2336* \retval false std is not DVBT standard 2337*/ 2338#define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT) 2339 2340/*------------------------------------------------------------------------- 2341THE END 2342-------------------------------------------------------------------------*/ 2343#endif /* __DRXDRIVER_H__ */ 2344