1#ifndef DDK750_SII164_H__ 2#define DDK750_SII164_H__ 3 4#define USE_DVICHIP 5 6/* Hot Plug detection mode structure */ 7typedef enum _sii164_hot_plug_mode_t 8{ 9 SII164_HOTPLUG_DISABLE = 0, /* Disable Hot Plug output bit (always high). */ 10 SII164_HOTPLUG_USE_MDI, /* Use Monitor Detect Interrupt bit. */ 11 SII164_HOTPLUG_USE_RSEN, /* Use Receiver Sense detect bit. */ 12 SII164_HOTPLUG_USE_HTPLG /* Use Hot Plug detect bit. */ 13} sii164_hot_plug_mode_t; 14 15 16/* Silicon Image SiI164 chip prototype */ 17long sii164InitChip( 18 unsigned char edgeSelect, 19 unsigned char busSelect, 20 unsigned char dualEdgeClkSelect, 21 unsigned char hsyncEnable, 22 unsigned char vsyncEnable, 23 unsigned char deskewEnable, 24 unsigned char deskewSetting, 25 unsigned char continuousSyncEnable, 26 unsigned char pllFilterEnable, 27 unsigned char pllFilterValue 28); 29 30unsigned short sii164GetVendorID(void); 31unsigned short sii164GetDeviceID(void); 32 33 34#ifdef SII164_FULL_FUNCTIONS 35void sii164ResetChip(void); 36char *sii164GetChipString(void); 37void sii164SetPower(unsigned char powerUp); 38void sii164EnableHotPlugDetection(unsigned char enableHotPlug); 39unsigned char sii164IsConnected(void); 40unsigned char sii164CheckInterrupt(void); 41void sii164ClearInterrupt(void); 42#endif 43/* below register definination is used for Silicon Image SiI164 DVI controller chip */ 44/* 45 * Vendor ID registers 46 */ 47#define SII164_VENDOR_ID_LOW 0x00 48#define SII164_VENDOR_ID_HIGH 0x01 49 50/* 51 * Device ID registers 52 */ 53#define SII164_DEVICE_ID_LOW 0x02 54#define SII164_DEVICE_ID_HIGH 0x03 55 56/* 57 * Device Revision 58 */ 59#define SII164_DEVICE_REVISION 0x04 60 61/* 62 * Frequency Limitation registers 63 */ 64#define SII164_FREQUENCY_LIMIT_LOW 0x06 65#define SII164_FREQUENCY_LIMIT_HIGH 0x07 66 67/* 68 * Power Down and Input Signal Configuration registers 69 */ 70#define SII164_CONFIGURATION 0x08 71 72/* Power down (PD) */ 73#define SII164_CONFIGURATION_POWER_DOWN 0x00 74#define SII164_CONFIGURATION_POWER_NORMAL 0x01 75#define SII164_CONFIGURATION_POWER_MASK 0x01 76 77/* Input Edge Latch Select (EDGE) */ 78#define SII164_CONFIGURATION_LATCH_FALLING 0x00 79#define SII164_CONFIGURATION_LATCH_RISING 0x02 80 81/* Bus Select (BSEL) */ 82#define SII164_CONFIGURATION_BUS_12BITS 0x00 83#define SII164_CONFIGURATION_BUS_24BITS 0x04 84 85/* Dual Edge Clock Select (DSEL) */ 86#define SII164_CONFIGURATION_CLOCK_SINGLE 0x00 87#define SII164_CONFIGURATION_CLOCK_DUAL 0x08 88 89/* Horizontal Sync Enable (HEN) */ 90#define SII164_CONFIGURATION_HSYNC_FORCE_LOW 0x00 91#define SII164_CONFIGURATION_HSYNC_AS_IS 0x10 92 93/* Vertical Sync Enable (VEN) */ 94#define SII164_CONFIGURATION_VSYNC_FORCE_LOW 0x00 95#define SII164_CONFIGURATION_VSYNC_AS_IS 0x20 96 97/* 98 * Detection registers 99 */ 100#define SII164_DETECT 0x09 101 102/* Monitor Detect Interrupt (MDI) */ 103#define SII164_DETECT_MONITOR_STATE_CHANGE 0x00 104#define SII164_DETECT_MONITOR_STATE_NO_CHANGE 0x01 105#define SII164_DETECT_MONITOR_STATE_CLEAR 0x01 106#define SII164_DETECT_MONITOR_STATE_MASK 0x01 107 108/* Hot Plug detect Input (HTPLG) */ 109#define SII164_DETECT_HOT_PLUG_STATUS_OFF 0x00 110#define SII164_DETECT_HOT_PLUG_STATUS_ON 0x02 111#define SII164_DETECT_HOT_PLUG_STATUS_MASK 0x02 112 113/* Receiver Sense (RSEN) */ 114#define SII164_DETECT_RECEIVER_SENSE_NOT_DETECTED 0x00 115#define SII164_DETECT_RECEIVER_SENSE_DETECTED 0x04 116 117/* Interrupt Generation Method (TSEL) */ 118#define SII164_DETECT_INTERRUPT_BY_RSEN_PIN 0x00 119#define SII164_DETECT_INTERRUPT_BY_HTPLG_PIN 0x08 120#define SII164_DETECT_INTERRUPT_MASK 0x08 121 122/* Monitor Sense Output (MSEN) */ 123#define SII164_DETECT_MONITOR_SENSE_OUTPUT_HIGH 0x00 124#define SII164_DETECT_MONITOR_SENSE_OUTPUT_MDI 0x10 125#define SII164_DETECT_MONITOR_SENSE_OUTPUT_RSEN 0x20 126#define SII164_DETECT_MONITOR_SENSE_OUTPUT_HTPLG 0x30 127#define SII164_DETECT_MONITOR_SENSE_OUTPUT_FLAG 0x30 128 129/* 130 * Skewing registers 131 */ 132#define SII164_DESKEW 0x0A 133 134/* General Purpose Input (CTL[3:1]) */ 135#define SII164_DESKEW_GENERAL_PURPOSE_INPUT_MASK 0x0E 136 137/* De-skewing Enable bit (DKEN) */ 138#define SII164_DESKEW_DISABLE 0x00 139#define SII164_DESKEW_ENABLE 0x10 140 141/* De-skewing Setting (DK[3:1])*/ 142#define SII164_DESKEW_1_STEP 0x00 143#define SII164_DESKEW_2_STEP 0x20 144#define SII164_DESKEW_3_STEP 0x40 145#define SII164_DESKEW_4_STEP 0x60 146#define SII164_DESKEW_5_STEP 0x80 147#define SII164_DESKEW_6_STEP 0xA0 148#define SII164_DESKEW_7_STEP 0xC0 149#define SII164_DESKEW_8_STEP 0xE0 150 151/* 152 * User Configuration Data registers (CFG 7:0) 153 */ 154#define SII164_USER_CONFIGURATION 0x0B 155 156/* 157 * PLL registers 158 */ 159#define SII164_PLL 0x0C 160 161/* PLL Filter Value (PLLF) */ 162#define SII164_PLL_FILTER_VALUE_MASK 0x0E 163 164/* PLL Filter Enable (PFEN) */ 165#define SII164_PLL_FILTER_DISABLE 0x00 166#define SII164_PLL_FILTER_ENABLE 0x01 167 168/* Sync Continuous (SCNT) */ 169#define SII164_PLL_FILTER_SYNC_CONTINUOUS_DISABLE 0x00 170#define SII164_PLL_FILTER_SYNC_CONTINUOUS_ENABLE 0x80 171 172#endif 173