1#ifndef __MV_CRYPTO_H__
2#define __MV_CRYPTO_H__
3
4#define DIGEST_INITIAL_VAL_A	0xdd00
5#define DIGEST_INITIAL_VAL_B	0xdd04
6#define DIGEST_INITIAL_VAL_C	0xdd08
7#define DIGEST_INITIAL_VAL_D	0xdd0c
8#define DIGEST_INITIAL_VAL_E	0xdd10
9#define DES_CMD_REG		0xdd58
10
11#define SEC_ACCEL_CMD		0xde00
12#define SEC_CMD_EN_SEC_ACCL0	(1 << 0)
13#define SEC_CMD_EN_SEC_ACCL1	(1 << 1)
14#define SEC_CMD_DISABLE_SEC	(1 << 2)
15
16#define SEC_ACCEL_DESC_P0	0xde04
17#define SEC_DESC_P0_PTR(x)	(x)
18
19#define SEC_ACCEL_DESC_P1	0xde14
20#define SEC_DESC_P1_PTR(x)	(x)
21
22#define SEC_ACCEL_CFG		0xde08
23#define SEC_CFG_STOP_DIG_ERR	(1 << 0)
24#define SEC_CFG_CH0_W_IDMA	(1 << 7)
25#define SEC_CFG_CH1_W_IDMA	(1 << 8)
26#define SEC_CFG_ACT_CH0_IDMA	(1 << 9)
27#define SEC_CFG_ACT_CH1_IDMA	(1 << 10)
28
29#define SEC_ACCEL_STATUS	0xde0c
30#define SEC_ST_ACT_0		(1 << 0)
31#define SEC_ST_ACT_1		(1 << 1)
32
33/*
34 * FPGA_INT_STATUS looks like a FPGA leftover and is documented only in Errata
35 * 4.12. It looks like that it was part of an IRQ-controller in FPGA and
36 * someone forgot to remove  it while switching to the core and moving to
37 * SEC_ACCEL_INT_STATUS.
38 */
39#define FPGA_INT_STATUS		0xdd68
40#define SEC_ACCEL_INT_STATUS	0xde20
41#define SEC_INT_AUTH_DONE	(1 << 0)
42#define SEC_INT_DES_E_DONE	(1 << 1)
43#define SEC_INT_AES_E_DONE	(1 << 2)
44#define SEC_INT_AES_D_DONE	(1 << 3)
45#define SEC_INT_ENC_DONE	(1 << 4)
46#define SEC_INT_ACCEL0_DONE	(1 << 5)
47#define SEC_INT_ACCEL1_DONE	(1 << 6)
48#define SEC_INT_ACC0_IDMA_DONE	(1 << 7)
49#define SEC_INT_ACC1_IDMA_DONE	(1 << 8)
50
51#define SEC_ACCEL_INT_MASK	0xde24
52
53#define AES_KEY_LEN	(8 * 4)
54
55struct sec_accel_config {
56
57	u32 config;
58#define CFG_OP_MAC_ONLY		0
59#define CFG_OP_CRYPT_ONLY	1
60#define CFG_OP_MAC_CRYPT	2
61#define CFG_OP_CRYPT_MAC	3
62#define CFG_MACM_MD5		(4 << 4)
63#define CFG_MACM_SHA1		(5 << 4)
64#define CFG_MACM_HMAC_MD5	(6 << 4)
65#define CFG_MACM_HMAC_SHA1	(7 << 4)
66#define CFG_ENCM_DES		(1 << 8)
67#define CFG_ENCM_3DES		(2 << 8)
68#define CFG_ENCM_AES		(3 << 8)
69#define CFG_DIR_ENC		(0 << 12)
70#define CFG_DIR_DEC		(1 << 12)
71#define CFG_ENC_MODE_ECB	(0 << 16)
72#define CFG_ENC_MODE_CBC	(1 << 16)
73#define CFG_3DES_EEE		(0 << 20)
74#define CFG_3DES_EDE		(1 << 20)
75#define CFG_AES_LEN_128		(0 << 24)
76#define CFG_AES_LEN_192		(1 << 24)
77#define CFG_AES_LEN_256		(2 << 24)
78#define CFG_NOT_FRAG		(0 << 30)
79#define CFG_FIRST_FRAG		(1 << 30)
80#define CFG_LAST_FRAG		(2 << 30)
81#define CFG_MID_FRAG		(3 << 30)
82
83	u32 enc_p;
84#define ENC_P_SRC(x)		(x)
85#define ENC_P_DST(x)		((x) << 16)
86
87	u32 enc_len;
88#define ENC_LEN(x)		(x)
89
90	u32 enc_key_p;
91#define ENC_KEY_P(x)		(x)
92
93	u32 enc_iv;
94#define ENC_IV_POINT(x)		((x) << 0)
95#define ENC_IV_BUF_POINT(x)	((x) << 16)
96
97	u32 mac_src_p;
98#define MAC_SRC_DATA_P(x)	(x)
99#define MAC_SRC_TOTAL_LEN(x)	((x) << 16)
100
101	u32 mac_digest;
102#define MAC_DIGEST_P(x)	(x)
103#define MAC_FRAG_LEN(x)	((x) << 16)
104	u32 mac_iv;
105#define MAC_INNER_IV_P(x)	(x)
106#define MAC_OUTER_IV_P(x)	((x) << 16)
107}__attribute__ ((packed));
108	/*
109	 * /-----------\ 0
110	 * | ACCEL CFG |	4 * 8
111	 * |-----------| 0x20
112	 * | CRYPT KEY |	8 * 4
113	 * |-----------| 0x40
114	 * |  IV   IN  |	4 * 4
115	 * |-----------| 0x40 (inplace)
116	 * |  IV BUF   |	4 * 4
117	 * |-----------| 0x80
118	 * |  DATA IN  |	16 * x (max ->max_req_size)
119	 * |-----------| 0x80 (inplace operation)
120	 * |  DATA OUT |	16 * x (max ->max_req_size)
121	 * \-----------/ SRAM size
122	 */
123
124	/* Hashing memory map:
125	 * /-----------\ 0
126	 * | ACCEL CFG |        4 * 8
127	 * |-----------| 0x20
128	 * | Inner IV  |        5 * 4
129	 * |-----------| 0x34
130	 * | Outer IV  |        5 * 4
131	 * |-----------| 0x48
132	 * | Output BUF|        5 * 4
133	 * |-----------| 0x80
134	 * |  DATA IN  |        64 * x (max ->max_req_size)
135	 * \-----------/ SRAM size
136	 */
137#define SRAM_CONFIG		0x00
138#define SRAM_DATA_KEY_P		0x20
139#define SRAM_DATA_IV		0x40
140#define SRAM_DATA_IV_BUF	0x40
141#define SRAM_DATA_IN_START	0x80
142#define SRAM_DATA_OUT_START	0x80
143
144#define SRAM_HMAC_IV_IN		0x20
145#define SRAM_HMAC_IV_OUT	0x34
146#define SRAM_DIGEST_BUF		0x48
147
148#define SRAM_CFG_SPACE		0x80
149
150#endif
151