| /linux-4.4.14/drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll.c | 16 static int dsi_pll_enable(struct msm_dsi_pll *pll) in dsi_pll_enable() argument
24 if (unlikely(pll->pll_on)) in dsi_pll_enable()
28 for (i = 0; i < pll->en_seq_cnt; i++) { in dsi_pll_enable()
29 ret = pll->enable_seqs[i](pll); in dsi_pll_enable()
41 pll->pll_on = true; in dsi_pll_enable()
46 static void dsi_pll_disable(struct msm_dsi_pll *pll) in dsi_pll_disable() argument
48 if (unlikely(!pll->pll_on)) in dsi_pll_disable()
51 pll->disable_seq(pll); in dsi_pll_disable()
53 pll->pll_on = false; in dsi_pll_disable()
62 struct msm_dsi_pll *pll = hw_clk_to_pll(hw); in msm_dsi_pll_helper_clk_round_rate() local
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| D | dsi_pll_28nm.c | 138 struct msm_dsi_pll *pll = hw_clk_to_pll(hw); in dsi_pll_28nm_clk_set_rate() local
139 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_clk_set_rate()
253 struct msm_dsi_pll *pll = hw_clk_to_pll(hw); in dsi_pll_28nm_clk_is_enabled() local
254 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_clk_is_enabled()
263 struct msm_dsi_pll *pll = hw_clk_to_pll(hw); in dsi_pll_28nm_clk_recalc_rate() local
264 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_clk_recalc_rate()
321 static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll) in dsi_pll_28nm_enable_seq_hpm() argument
323 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_enable_seq_hpm()
396 static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll) in dsi_pll_28nm_enable_seq_lp() argument
398 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_enable_seq_lp()
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| D | dsi_pll.h | 36 int (*enable_seqs[MAX_DSI_PLL_EN_SEQS])(struct msm_dsi_pll *pll);
37 void (*disable_seq)(struct msm_dsi_pll *pll);
38 int (*get_provider)(struct msm_dsi_pll *pll,
41 void (*destroy)(struct msm_dsi_pll *pll);
42 void (*save_state)(struct msm_dsi_pll *pll);
43 int (*restore_state)(struct msm_dsi_pll *pll);
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| /linux-4.4.14/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 17 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
18 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
19 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
20 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
119 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) in aty_dsp_gt() argument
126 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; in aty_dsp_gt()
127 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; in aty_dsp_gt()
129 ras_multiplier = pll->xclkmaxrasdelay; in aty_dsp_gt()
135 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ in aty_dsp_gt()
141 if (pll->xres != 0) { in aty_dsp_gt()
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| D | mach64_gx.c | 80 const union aty_pll *pll, u32 bpp, u32 accel) in aty_set_dac_514() argument
123 u32 bpp, union aty_pll *pll) in aty_var_to_pll_514() argument
153 pll->ibm514.m = RGB514_clocks[i].m; in aty_var_to_pll_514()
154 pll->ibm514.n = RGB514_clocks[i].n; in aty_var_to_pll_514()
161 const union aty_pll *pll) in aty_pll_514_to_var() argument
166 df = pll->ibm514.m >> 6; in aty_pll_514_to_var()
167 vco_div_count = pll->ibm514.m & 0x3f; in aty_pll_514_to_var()
168 ref_div_count = pll->ibm514.n; in aty_pll_514_to_var()
175 const union aty_pll *pll) in aty_set_pll_514() argument
185 aty_st_514(0x20, pll->ibm514.m, par); /* F0 / M0 */ in aty_set_pll_514()
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| D | radeon_base.c | 562 rinfo->pll.ref_clk = (*val) / 10; in radeon_read_xtal_OF()
566 rinfo->pll.sclk = (*val) / 10; in radeon_read_xtal_OF()
570 rinfo->pll.mclk = (*val) / 10; in radeon_read_xtal_OF()
706 rinfo->pll.ref_clk = xtal; in radeon_probe_pll_params()
707 rinfo->pll.ref_div = ref_div; in radeon_probe_pll_params()
708 rinfo->pll.sclk = sclk; in radeon_probe_pll_params()
709 rinfo->pll.mclk = mclk; in radeon_probe_pll_params()
727 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
728 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
729 rinfo->pll.mclk = 23000; in radeon_get_pllinfo()
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| D | atyfb.h | 136 union aty_pll pll; member
300 const union aty_pll * pll, u32 bpp, u32 accel);
315 int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll);
316 u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll);
317 void (*set_pll) (const struct fb_info * info, const union aty_pll * pll);
318 void (*get_pll) (const struct fb_info *info, union aty_pll * pll);
319 int (*init_pll) (const struct fb_info * info, union aty_pll * pll);
320 void (*resume_pll)(const struct fb_info *info, union aty_pll *pll);
332 extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll);
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| D | atyfb_base.c | 305 static int pll; variable
368 int pll, mclk, xclk, ecp_max; member
455 par->pll_limits.pll_max = aty_chips[i].pll; in correct_chipset()
583 par->pll.ct.xres = 0; in atyfb_get_pixclock()
587 par->pll.ct.xres = var->xres; in atyfb_get_pixclock()
1330 var->bits_per_pixel, &par->pll); in atyfb_set_par()
1349 par->dac_ops->set_dac(info, &par->pll, in atyfb_set_par()
1351 par->pll_ops->set_pll(info, &par->pll); in atyfb_set_par()
1355 pixclock_in_ps = par->pll_ops->pll_to_var(info, &par->pll); in atyfb_set_par()
1543 union aty_pll pll; in atyfb_check_var() local
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| D | aty128fb.c | 444 struct aty128_pll pll; member
1331 static void aty128_set_pll(struct aty128_pll *pll, in aty128_set_pll() argument
1353 div3 |= pll->feedback_divider; in aty128_set_pll()
1355 div3 |= post_conv[pll->post_divider] << 16; in aty128_set_pll()
1371 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, in aty128_var_to_pll() argument
1393 pll->post_divider = post_dividers[i]; in aty128_var_to_pll()
1405 pll->feedback_divider = round_div(n, d); in aty128_var_to_pll()
1406 pll->vclk = vclk; in aty128_var_to_pll()
1409 "vclk_per: %d\n", pll->post_divider, in aty128_var_to_pll()
1410 pll->feedback_divider, vclk, output_freq, in aty128_var_to_pll()
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| /linux-4.4.14/drivers/clk/tegra/ |
| D | clk-pll.c | 223 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) in clk_pll_enable_lock() argument
227 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) in clk_pll_enable_lock()
230 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) in clk_pll_enable_lock()
233 val = pll_readl_misc(pll); in clk_pll_enable_lock()
234 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
235 pll_writel_misc(val, pll); in clk_pll_enable_lock()
238 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) in clk_pll_wait_for_lock() argument
244 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { in clk_pll_wait_for_lock()
245 udelay(pll->params->lock_delay); in clk_pll_wait_for_lock()
249 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
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| D | Makefile | 7 obj-y += clk-pll.o
8 obj-y += clk-pll-out.o
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| /linux-4.4.14/drivers/clk/mediatek/ |
| D | clk-pll.c | 61 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
63 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; in mtk_pll_is_prepared()
66 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
69 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
90 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, in mtk_pll_set_rate_regs() argument
96 pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; in mtk_pll_set_rate_regs()
99 val = readl(pll->pd_addr); in mtk_pll_set_rate_regs()
100 val &= ~(POSTDIV_MASK << pll->data->pd_shift); in mtk_pll_set_rate_regs()
101 val |= (ffs(postdiv) - 1) << pll->data->pd_shift; in mtk_pll_set_rate_regs()
104 if (pll->pd_addr != pll->pcw_addr) { in mtk_pll_set_rate_regs()
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| D | Makefile | 1 obj-y += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
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| /linux-4.4.14/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 71 struct iproc_pll *pll; member
96 static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate) in pll_get_rate_index() argument
100 for (i = 0; i < pll->num_vco_entries; i++) in pll_get_rate_index()
101 if (target_rate == pll->vco_param[i].rate) in pll_get_rate_index()
104 if (i >= pll->num_vco_entries) in pll_get_rate_index()
125 static int pll_wait_for_lock(struct iproc_pll *pll) in pll_wait_for_lock() argument
128 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in pll_wait_for_lock()
131 u32 val = readl(pll->status_base + ctrl->status.offset); in pll_wait_for_lock()
141 static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, in iproc_pll_write() argument
144 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in iproc_pll_write()
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| D | clk-iproc-armpll.c | 74 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
79 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
88 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
92 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
114 static int __get_mdiv(struct iproc_arm_pll *pll) in __get_mdiv() argument
120 fid = __get_fid(pll); in __get_mdiv()
129 val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); in __get_mdiv()
136 val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET); in __get_mdiv()
149 static unsigned int __get_ndiv(struct iproc_arm_pll *pll) in __get_ndiv() argument
154 val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET); in __get_ndiv()
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| D | clk-bcm2835.c | 818 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); in bcm2835_pll_is_on() local
819 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_is_on()
820 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_is_on()
865 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); in bcm2835_pll_get_rate() local
866 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_get_rate()
867 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_get_rate()
889 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); in bcm2835_pll_off() local
890 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_off()
891 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_off()
905 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); in bcm2835_pll_on() local
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| /linux-4.4.14/drivers/clk/qcom/ |
| D | clk-pll.c | 39 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
44 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
53 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
65 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
74 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
80 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable() local
84 regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_disable()
89 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); in clk_pll_disable()
95 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate() local
100 regmap_read(pll->clkr.regmap, pll->l_reg, &l); in clk_pll_recalc_rate()
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| D | clk-pll.h | 84 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
86 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
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| /linux-4.4.14/drivers/media/i2c/ |
| D | smiapp-pll.c | 61 static void print_pll(struct device *dev, struct smiapp_pll *pll) in print_pll() argument
63 dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div); in print_pll()
64 dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier); in print_pll()
65 if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { in print_pll()
66 dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div); in print_pll()
67 dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div); in print_pll()
69 dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div); in print_pll()
70 dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div); in print_pll()
72 dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz); in print_pll()
73 dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz); in print_pll()
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| D | aptina-pll.c | 31 struct aptina_pll *pll) in aptina_pll_calculate() argument
41 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
43 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
44 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
49 if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { in aptina_pll_calculate()
55 div = gcd(pll->pix_clock, pll->ext_clock); in aptina_pll_calculate()
56 pll->m = pll->pix_clock / div; in aptina_pll_calculate()
57 div = pll->ext_clock / div; in aptina_pll_calculate()
69 mf_min = DIV_ROUND_UP(limits->m_min, pll->m); in aptina_pll_calculate()
71 (pll->ext_clock / limits->n_min * pll->m)); in aptina_pll_calculate()
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| D | mt9m032.c | 282 struct aptina_pll pll; in mt9m032_setup_pll() local
286 pll.ext_clock = pdata->ext_clock; in mt9m032_setup_pll()
287 pll.pix_clock = pdata->pix_clock; in mt9m032_setup_pll()
289 ret = aptina_pll_calculate(&client->dev, &limits, &pll); in mt9m032_setup_pll()
296 (pll.m << MT9M032_PLL_CONFIG1_MUL_SHIFT) | in mt9m032_setup_pll()
297 ((pll.n - 1) & MT9M032_PLL_CONFIG1_PREDIV_MASK)); in mt9m032_setup_pll()
307 reg_val = (pll.p1 == 6 ? MT9M032_FORMATTER1_PLL_P1_6 : 0) in mt9m032_setup_pll()
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| D | aptina-pll.h | 54 struct aptina_pll *pll);
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| /linux-4.4.14/drivers/clk/imx/ |
| D | clk-pllv3.c | 51 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) in clk_pllv3_wait_lock() argument
54 u32 val = readl_relaxed(pll->base) & pll->powerdown; in clk_pllv3_wait_lock()
57 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) in clk_pllv3_wait_lock()
62 if (readl_relaxed(pll->base) & BM_PLL_LOCK) in clk_pllv3_wait_lock()
69 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; in clk_pllv3_wait_lock()
74 struct clk_pllv3 *pll = to_clk_pllv3(hw); in clk_pllv3_prepare() local
77 val = readl_relaxed(pll->base); in clk_pllv3_prepare()
78 if (pll->powerup_set) in clk_pllv3_prepare()
82 writel_relaxed(val, pll->base); in clk_pllv3_prepare()
84 return clk_pllv3_wait_lock(pll); in clk_pllv3_prepare()
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| D | clk-pllv1.c | 31 static inline bool is_imx1_pllv1(struct clk_pllv1 *pll) in is_imx1_pllv1() argument
33 return pll->type == IMX_PLLV1_IMX1; in is_imx1_pllv1()
36 static inline bool is_imx21_pllv1(struct clk_pllv1 *pll) in is_imx21_pllv1() argument
38 return pll->type == IMX_PLLV1_IMX21; in is_imx21_pllv1()
41 static inline bool is_imx27_pllv1(struct clk_pllv1 *pll) in is_imx27_pllv1() argument
43 return pll->type == IMX_PLLV1_IMX27; in is_imx27_pllv1()
46 static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn) in mfn_is_negative() argument
48 return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN); in mfn_is_negative()
54 struct clk_pllv1 *pll = to_clk_pllv1(hw); in clk_pllv1_recalc_rate() local
61 reg = readl(pll->base); in clk_pllv1_recalc_rate()
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| D | clk-pllv2.c | 113 struct clk_pllv2 *pll = to_clk_pllv2(hw); in clk_pllv2_recalc_rate() local
115 pllbase = pll->base; in clk_pllv2_recalc_rate()
157 struct clk_pllv2 *pll = to_clk_pllv2(hw); in clk_pllv2_set_rate() local
162 pllbase = pll->base; in clk_pllv2_set_rate()
192 struct clk_pllv2 *pll = to_clk_pllv2(hw); in clk_pllv2_prepare() local
197 pllbase = pll->base; in clk_pllv2_prepare()
220 struct clk_pllv2 *pll = to_clk_pllv2(hw); in clk_pllv2_unprepare() local
224 pllbase = pll->base; in clk_pllv2_unprepare()
240 struct clk_pllv2 *pll; in imx_clk_pllv2() local
244 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in imx_clk_pllv2()
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| D | clk-cpu.c | 21 struct clk *pll; member
43 return clk_round_rate(cpu->pll, rate); in clk_cpu_round_rate()
58 ret = clk_set_rate(cpu->pll, rate); in clk_cpu_set_rate()
60 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
64 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
79 struct clk *div, struct clk *mux, struct clk *pll, in imx_clk_cpu() argument
92 cpu->pll = pll; in imx_clk_cpu()
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| /linux-4.4.14/drivers/clk/pistachio/ |
| D | clk-pll.c | 81 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg) in pll_readl() argument
83 return readl(pll->base + reg); in pll_readl()
86 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) in pll_writel() argument
88 writel(val, pll->base + reg); in pll_writel()
91 static inline void pll_lock(struct pistachio_clk_pll *pll) in pll_lock() argument
93 while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) in pll_lock()
110 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); in pll_frac_get_mode() local
113 val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD; in pll_frac_get_mode()
119 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); in pll_frac_set_mode() local
122 val = pll_readl(pll, PLL_CTRL3); in pll_frac_set_mode()
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| D | Makefile | 2 obj-y += clk-pll.o
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| /linux-4.4.14/drivers/clk/rockchip/ |
| D | clk-pll.c | 52 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
54 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
57 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
68 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_round_rate() local
69 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
73 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_round_rate()
87 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_pll_wait_lock() argument
94 ret = regmap_read(grf, pll->lock_offset, &val); in rockchip_pll_wait_lock()
101 if (val & BIT(pll->lock_shift)) in rockchip_pll_wait_lock()
129 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, in rockchip_rk3066_pll_get_params() argument
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| D | Makefile | 7 obj-y += clk-pll.o
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| /linux-4.4.14/drivers/clk/mxs/ |
| D | clk-pll.c | 40 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
42 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
51 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare() local
53 writel_relaxed(1 << pll->power, pll->base + CLR); in clk_pll_unprepare()
58 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
60 writel_relaxed(1 << 31, pll->base + CLR); in clk_pll_enable()
67 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable() local
69 writel_relaxed(1 << 31, pll->base + SET); in clk_pll_disable()
75 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate() local
77 return pll->rate; in clk_pll_recalc_rate()
[all …]
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| D | Makefile | 5 obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o clk-ssp.o
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| /linux-4.4.14/drivers/video/fbdev/omap2/dss/ |
| D | hdmi_pll.c | 25 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) in hdmi_pll_dump() argument
28 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
41 void hdmi_pll_compute(struct hdmi_pll_data *pll, in hdmi_pll_compute() argument
49 const struct dss_pll_hw *hw = pll->pll.hw; in hdmi_pll_compute()
51 clkin = clk_get_rate(pll->pll.clkin); in hdmi_pll_compute()
103 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); in hdmi_pll_enable() local
104 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable()
118 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); in hdmi_pll_disable() local
119 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable()
181 struct dss_pll *pll = &hpll->pll; in dsi_init_pll_data() local
[all …]
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| D | video-pll.c | 26 struct dss_pll pll; member
62 static int dss_video_pll_enable(struct dss_pll *pll) in dss_video_pll_enable() argument
64 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_enable()
71 dss_ctrl_pll_enable(pll->id, true); in dss_video_pll_enable()
75 r = dss_pll_wait_reset_done(pll); in dss_video_pll_enable()
85 dss_ctrl_pll_enable(pll->id, false); in dss_video_pll_enable()
91 static void dss_video_pll_disable(struct dss_pll *pll) in dss_video_pll_disable() argument
93 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_disable()
99 dss_ctrl_pll_enable(pll->id, false); in dss_video_pll_disable()
142 struct dss_pll *pll; in dss_video_pll_init() local
[all …]
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| D | pll.c | 41 int dss_pll_register(struct dss_pll *pll) in dss_pll_register() argument
47 dss_plls[i] = pll; in dss_pll_register()
55 void dss_pll_unregister(struct dss_pll *pll) in dss_pll_unregister() argument
60 if (dss_plls[i] == pll) { in dss_pll_unregister()
79 int dss_pll_enable(struct dss_pll *pll) in dss_pll_enable() argument
83 r = clk_prepare_enable(pll->clkin); in dss_pll_enable()
87 if (pll->regulator) { in dss_pll_enable()
88 r = regulator_enable(pll->regulator); in dss_pll_enable()
93 r = pll->ops->enable(pll); in dss_pll_enable()
100 if (pll->regulator) in dss_pll_enable()
[all …]
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| D | dpi.c | 48 struct dss_pll *pll; member
143 struct dss_pll *pll; member
215 return dss_pll_hsdiv_calc(ctx->pll, clkdco, in dpi_calc_pll_cb()
237 ctx->pll = dpi->pll; in dpi_dsi_clk_calc()
244 clkin = clk_get_rate(ctx->pll->clkin); in dpi_dsi_clk_calc()
246 return dss_pll_calc(ctx->pll, clkin, in dpi_dsi_clk_calc()
294 r = dss_pll_set_config(dpi->pll, &ctx.dsi_cinfo); in dpi_set_dsi_clk()
344 if (dpi->pll) in dpi_set_mode()
418 if (dpi->pll) { in dpi_display_enable()
419 r = dss_pll_enable(dpi->pll); in dpi_display_enable()
[all …]
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| D | dss.h | 134 int (*enable)(struct dss_pll *pll);
135 void (*disable)(struct dss_pll *pll);
136 int (*set_config)(struct dss_pll *pll,
275 void dss_video_pll_uninit(struct dss_pll *pll);
452 int dss_pll_register(struct dss_pll *pll);
453 void dss_pll_unregister(struct dss_pll *pll);
455 int dss_pll_enable(struct dss_pll *pll);
456 void dss_pll_disable(struct dss_pll *pll);
457 int dss_pll_set_config(struct dss_pll *pll,
460 bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
[all …]
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| D | hdmi5.c | 196 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
203 r = dss_pll_enable(&hdmi.pll.pll); in hdmi_power_on_full()
209 r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo); in hdmi_power_on_full()
254 dss_pll_disable(&hdmi.pll.pll); in hdmi_power_on_full()
272 dss_pll_disable(&hdmi.pll.pll); in hdmi_power_off_full()
320 hdmi_pll_dump(&hdmi.pll, s); in hdmi_dump_regs()
751 r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp); in hdmi5_bind()
794 hdmi_pll_uninit(&hdmi.pll); in hdmi5_bind()
807 hdmi_pll_uninit(&hdmi.pll); in hdmi5_unbind()
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| D | hdmi4.c | 184 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
186 r = dss_pll_enable(&hdmi.pll.pll); in hdmi_power_on_full()
192 r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo); in hdmi_power_on_full()
237 dss_pll_disable(&hdmi.pll.pll); in hdmi_power_on_full()
255 dss_pll_disable(&hdmi.pll.pll); in hdmi_power_off_full()
299 hdmi_pll_dump(&hdmi.pll, s); in hdmi_dump_regs()
715 r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp); in hdmi4_bind()
758 hdmi_pll_uninit(&hdmi.pll); in hdmi4_bind()
771 hdmi_pll_uninit(&hdmi.pll); in hdmi4_unbind()
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| D | hdmi.h | 239 struct dss_pll pll; member
308 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
309 void hdmi_pll_compute(struct hdmi_pll_data *pll,
311 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
345 struct hdmi_pll_data pll; member
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| D | Makefile | 5 output.o dss-of.o pll.o video-pll.o
|
| D | dsi.c | 279 struct dss_pll *pll; member
321 struct dss_pll pll; member
1252 return dsi->pll.cinfo.clkout[HSDIV_DISPC]; in dsi_get_pll_hsdiv_dispc_rate()
1259 return dsi->pll.cinfo.clkout[HSDIV_DSI]; in dsi_get_pll_hsdiv_dsi_rate()
1266 return dsi->pll.cinfo.clkdco / 16; in dsi_get_txbyteclkhs()
1396 static int dsi_pll_enable(struct dss_pll *pll) in dsi_pll_enable() argument
1398 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); in dsi_pll_enable()
1474 static void dsi_pll_disable(struct dss_pll *pll) in dsi_pll_disable() argument
1476 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); in dsi_pll_disable()
1486 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; in dsi_dump_dsidev_clocks()
[all …]
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| /linux-4.4.14/drivers/clk/samsung/ |
| D | clk-pll.c | 34 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
36 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
39 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
50 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
51 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_round_rate()
55 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_round_rate()
78 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2126_recalc_rate() local
82 pll_con = __raw_readl(pll->con_reg); in samsung_pll2126_recalc_rate()
111 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3000_recalc_rate() local
115 pll_con = __raw_readl(pll->con_reg); in samsung_pll3000_recalc_rate()
[all …]
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| /linux-4.4.14/arch/mips/ath79/ |
| D | clock.c | 61 u32 pll; in ar71xx_clocks_init() local
67 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
69 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; in ar71xx_clocks_init()
72 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
75 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; in ar71xx_clocks_init()
78 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; in ar71xx_clocks_init()
96 u32 pll; in ar724x_clocks_init() local
101 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init()
103 div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); in ar724x_clocks_init()
106 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); in ar724x_clocks_init()
[all …]
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| /linux-4.4.14/drivers/clk/at91/ |
| D | clk-pll.c | 74 struct clk_pll *pll = (struct clk_pll *)dev_id; in clk_pll_irq_handler() local
76 wake_up(&pll->wait); in clk_pll_irq_handler()
77 disable_irq_nosync(pll->irq); in clk_pll_irq_handler()
84 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
85 struct at91_pmc *pmc = pll->pmc; in clk_pll_prepare()
86 const struct clk_pll_layout *layout = pll->layout; in clk_pll_prepare()
88 pll->characteristics; in clk_pll_prepare()
89 u8 id = pll->id; in clk_pll_prepare()
102 (div == pll->div && mul == pll->mul)) in clk_pll_prepare()
106 out = characteristics->out[pll->range]; in clk_pll_prepare()
[all …]
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| /linux-4.4.14/drivers/clk/meson/ |
| D | clk-pll.c | 59 struct meson_clk_pll *pll = to_meson_clk_pll(hw); in meson_clk_pll_recalc_rate() local
66 p = &pll->conf->n; in meson_clk_pll_recalc_rate()
67 reg = readl(pll->base + p->reg_off); in meson_clk_pll_recalc_rate()
70 p = &pll->conf->m; in meson_clk_pll_recalc_rate()
71 reg = readl(pll->base + p->reg_off); in meson_clk_pll_recalc_rate()
74 p = &pll->conf->od; in meson_clk_pll_recalc_rate()
75 reg = readl(pll->base + p->reg_off); in meson_clk_pll_recalc_rate()
86 struct meson_clk_pll *pll = to_meson_clk_pll(hw); in meson_clk_pll_round_rate() local
87 const struct pll_rate_table *rate_table = pll->conf->rate_table; in meson_clk_pll_round_rate()
90 for (i = 0; i < pll->rate_count; i++) { in meson_clk_pll_round_rate()
[all …]
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| D | Makefile | 5 obj-y += clkc.o clk-pll.o clk-cpu.o
|
| D | clkc.h | 110 struct pll_conf *pll; member
143 .conf.pll = (_c), \
|
| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_pll.c | 113 void amdgpu_pll_compute(struct amdgpu_pll *pll, in amdgpu_pll_compute() argument
121 unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ? in amdgpu_pll_compute()
131 fb_div_min = pll->min_feedback_div; in amdgpu_pll_compute()
132 fb_div_max = pll->max_feedback_div; in amdgpu_pll_compute()
134 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { in amdgpu_pll_compute()
140 if (pll->flags & AMDGPU_PLL_USE_REF_DIV) in amdgpu_pll_compute()
141 ref_div_min = pll->reference_div; in amdgpu_pll_compute()
143 ref_div_min = pll->min_ref_div; in amdgpu_pll_compute()
145 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && in amdgpu_pll_compute()
146 pll->flags & AMDGPU_PLL_USE_REF_DIV) in amdgpu_pll_compute()
[all …]
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| D | atombios_crtc.c | 748 struct amdgpu_pll *pll; in amdgpu_atombios_crtc_set_pll() local
758 pll = &adev->clock.ppll[0]; in amdgpu_atombios_crtc_set_pll()
761 pll = &adev->clock.ppll[1]; in amdgpu_atombios_crtc_set_pll()
766 pll = &adev->clock.ppll[2]; in amdgpu_atombios_crtc_set_pll()
771 pll->flags = amdgpu_crtc->pll_flags; in amdgpu_atombios_crtc_set_pll()
772 pll->reference_div = amdgpu_crtc->pll_reference_div; in amdgpu_atombios_crtc_set_pll()
773 pll->post_div = amdgpu_crtc->pll_post_div; in amdgpu_atombios_crtc_set_pll()
775 amdgpu_pll_compute(pll, amdgpu_crtc->adjusted_clock, &pll_clock, in amdgpu_atombios_crtc_set_pll()
797 (125 * 25 * pll->reference_freq / 100); in amdgpu_atombios_crtc_set_pll()
800 (125 * 25 * pll->reference_freq / 100); in amdgpu_atombios_crtc_set_pll()
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| D | amdgpu_pll.h | 27 void amdgpu_pll_compute(struct amdgpu_pll *pll,
|
| /linux-4.4.14/drivers/clk/st/ |
| D | clkgen-pll.c | 328 struct clkgen_pll *pll = to_clkgen_pll(hw); in clkgen_pll_is_locked() local
329 u32 locked = CLKGEN_READ(pll, locked_status); in clkgen_pll_is_locked()
336 struct clkgen_pll *pll = to_clkgen_pll(hw); in clkgen_pll_is_enabled() local
337 u32 poweroff = CLKGEN_READ(pll, pdn_status); in clkgen_pll_is_enabled()
343 struct clkgen_pll *pll = to_clkgen_pll(hw); in __clkgen_pll_enable() local
344 void __iomem *base = pll->regs_base; in __clkgen_pll_enable()
345 struct clkgen_field *field = &pll->data->locked_status; in __clkgen_pll_enable()
352 CLKGEN_WRITE(pll, pdn_ctrl, 0); in __clkgen_pll_enable()
358 if (pll->data->switch2pll_en) in __clkgen_pll_enable()
359 CLKGEN_WRITE(pll, switch2pll, 0); in __clkgen_pll_enable()
[all …]
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| D | clkgen-fsyn.c | 428 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); in quadfs_pll_enable() local
431 if (pll->lock) in quadfs_pll_enable()
432 spin_lock_irqsave(pll->lock, flags); in quadfs_pll_enable()
437 if (pll->data->reset_present) in quadfs_pll_enable()
438 CLKGEN_WRITE(pll, nreset, 1); in quadfs_pll_enable()
443 if (pll->data->bwfilter_present) in quadfs_pll_enable()
444 CLKGEN_WRITE(pll, ref_bw, PLL_BW_GOODREF); in quadfs_pll_enable()
447 CLKGEN_WRITE(pll, ndiv, pll->ndiv); in quadfs_pll_enable()
452 CLKGEN_WRITE(pll, npda, !pll->data->powerup_polarity); in quadfs_pll_enable()
454 if (pll->lock) in quadfs_pll_enable()
[all …]
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| D | clkgen.h | 43 #define CLKGEN_READ(pll, field) clkgen_read(pll->regs_base, \ argument
44 &pll->data->field)
46 #define CLKGEN_WRITE(pll, field, val) clkgen_write(pll->regs_base, \ argument
47 &pll->data->field, val)
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| D | Makefile | 1 obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o clk-flexgen.o
|
| /linux-4.4.14/arch/arm/mach-davinci/ |
| D | clock.c | 292 struct pll_data *pll; in clk_sysclk_recalc() local
308 pll = clk->parent->pll_data; in clk_sysclk_recalc()
312 rate = pll->input_rate; in clk_sysclk_recalc()
317 v = __raw_readl(pll->base + clk->div_reg); in clk_sysclk_recalc()
319 plldiv = (v & pll->div_ratio_mask) + 1; in clk_sysclk_recalc()
330 struct pll_data *pll; in davinci_set_sysclk_rate() local
350 pll = clk->parent->pll_data; in davinci_set_sysclk_rate()
356 input = pll->input_rate; in davinci_set_sysclk_rate()
376 if (ratio > pll->div_ratio_mask) in davinci_set_sysclk_rate()
380 v = __raw_readl(pll->base + PLLSTAT); in davinci_set_sysclk_rate()
[all …]
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| /linux-4.4.14/Documentation/devicetree/bindings/c6x/ |
| D | clocks.txt | 10 - compatible: "ti,c64x+pll"
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
33 compatible = "ti,c6472-pll", "ti,c64x+pll";
37 ti,c64x+pll-bypass-delay = <200>;
[all …]
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| /linux-4.4.14/drivers/clk/berlin/ |
| D | berlin2-pll.c | 55 struct berlin2_pll *pll = to_berlin2_pll(hw); in berlin2_pll_recalc_rate() local
56 struct berlin2_pll_map *map = &pll->map; in berlin2_pll_recalc_rate()
60 val = readl_relaxed(pll->base + SPLL_CTRL0); in berlin2_pll_recalc_rate()
68 val = readl_relaxed(pll->base + SPLL_CTRL1); in berlin2_pll_recalc_rate()
93 struct berlin2_pll *pll; in berlin2_pll_register() local
95 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in berlin2_pll_register()
96 if (!pll) in berlin2_pll_register()
100 memcpy(&pll->map, map, sizeof(*map)); in berlin2_pll_register()
101 pll->base = base; in berlin2_pll_register()
102 pll->hw.init = &init; in berlin2_pll_register()
[all …]
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| D | Makefile | 1 obj-y += berlin2-avpll.o berlin2-pll.o berlin2-div.o
|
| /linux-4.4.14/drivers/clk/spear/ |
| D | clk-vco-pll.c | 87 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_round_rate_index() local
97 for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) { in clk_pll_round_rate_index()
100 *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index, in clk_pll_round_rate_index()
127 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate() local
131 if (pll->vco->lock) in clk_pll_recalc_rate()
132 spin_lock_irqsave(pll->vco->lock, flags); in clk_pll_recalc_rate()
134 p = readl_relaxed(pll->vco->cfg_reg); in clk_pll_recalc_rate()
136 if (pll->vco->lock) in clk_pll_recalc_rate()
137 spin_unlock_irqrestore(pll->vco->lock, flags); in clk_pll_recalc_rate()
147 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate() local
[all …]
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| D | Makefile | 5 obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
|
| /linux-4.4.14/drivers/clk/zynq/ |
| D | pll.c | 200 struct zynq_pll *pll; in clk_register_zynq_pll() local
213 pll = kmalloc(sizeof(*pll), GFP_KERNEL); in clk_register_zynq_pll()
214 if (!pll) in clk_register_zynq_pll()
218 pll->hw.init = &initd; in clk_register_zynq_pll()
219 pll->pll_ctrl = pll_ctrl; in clk_register_zynq_pll()
220 pll->pll_status = pll_status; in clk_register_zynq_pll()
221 pll->lockbit = lock_index; in clk_register_zynq_pll()
222 pll->lock = lock; in clk_register_zynq_pll()
224 spin_lock_irqsave(pll->lock, flags); in clk_register_zynq_pll()
226 reg = clk_readl(pll->pll_ctrl); in clk_register_zynq_pll()
[all …]
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| D | Makefile | 3 obj-y += clkc.o pll.o
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| /linux-4.4.14/drivers/video/fbdev/matrox/ |
| D | g450_pll.c | 35 return (minfo->features.pll.ref_freq * n + (m >> 1)) / m; in g450_mnp2vco()
99 n = ((tvco * (m+1) + minfo->features.pll.ref_freq) / (minfo->features.pll.ref_freq * 2)) - 2; in g450_nextpll()
137 unsigned int mnp, unsigned int pll) in g450_setpll() argument
139 switch (pll) { in g450_setpll()
174 unsigned int mnp, unsigned int pll) in g450_cmppll() argument
180 switch (pll) { in g450_cmppll()
230 unsigned int pll) in g450_testpll() argument
232 return g450_isplllocked(minfo, g450_setpll(minfo, mnp, pll)); in g450_testpll()
235 static void updatehwstate_clk(struct matrox_hw_state* hw, unsigned int mnp, unsigned int pll) { in updatehwstate_clk() argument
236 switch (pll) { in updatehwstate_clk()
[all …]
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| D | matroxfb_misc.c | 128 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int f… in matroxfb_PLL_calcclock() argument
132 unsigned int fxtal = pll->ref_freq; in matroxfb_PLL_calcclock()
141 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max); in matroxfb_PLL_calcclock()
142 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq); in matroxfb_PLL_calcclock()
144 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min); in matroxfb_PLL_calcclock()
145 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min); in matroxfb_PLL_calcclock()
146 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max); in matroxfb_PLL_calcclock()
147 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min); in matroxfb_PLL_calcclock()
148 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max); in matroxfb_PLL_calcclock()
151 for (p = 1; p <= pll->post_shift_max; p++) { in matroxfb_PLL_calcclock()
[all …]
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| D | g450_pll.h | 7 unsigned int pll);
10 unsigned int pll);
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| D | matroxfb_misc.h | 7 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int f…
14 return matroxfb_PLL_calcclock(&minfo->features.pll, freq, fmax, in, feed, post); in PLL_calcclock()
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| D | matroxfb_DAC1064.c | 180 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) { in g450_set_plls()
588 minfo->features.pll.vco_freq_min = 62000; in MGA1064_ramdac_init()
589 minfo->features.pll.ref_freq = 14318; in MGA1064_ramdac_init()
590 minfo->features.pll.feed_div_min = 100; in MGA1064_ramdac_init()
591 minfo->features.pll.feed_div_max = 127; in MGA1064_ramdac_init()
592 minfo->features.pll.in_div_min = 1; in MGA1064_ramdac_init()
593 minfo->features.pll.in_div_max = 31; in MGA1064_ramdac_init()
594 minfo->features.pll.post_shift_max = 3; in MGA1064_ramdac_init()
726 matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL); in g450_mclk_init()
736 matroxfb_g450_setclk(minfo, minfo->values.pll.system, M_SYSTEM_PLL); in g450_mclk_init()
[all …]
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| D | matroxfb_Ti3026.c | 545 minfo->features.pll.vco_freq_min = 110000; in ti3026_ramdac_init()
546 minfo->features.pll.ref_freq = 114545; in ti3026_ramdac_init()
547 minfo->features.pll.feed_div_min = 2; in ti3026_ramdac_init()
548 minfo->features.pll.feed_div_max = 24; in ti3026_ramdac_init()
549 minfo->features.pll.in_div_min = 2; in ti3026_ramdac_init()
550 minfo->features.pll.in_div_max = 63; in ti3026_ramdac_init()
551 minfo->features.pll.post_shift_max = 3; in ti3026_ramdac_init()
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| D | matroxfb_maven.c | 223 static int matroxfb_PLL_mavenclock(const struct matrox_pll_features2* pll, in matroxfb_PLL_mavenclock() argument
230 unsigned int fmin = pll->vco_freq_min / ctl->den; in matroxfb_PLL_mavenclock()
240 fmax = pll->vco_freq_max / ctl->den; in matroxfb_PLL_mavenclock()
244 for (p = 1; p <= pll->post_shift_max; p++) { in matroxfb_PLL_mavenclock()
255 for (m = pll->in_div_min; m <= pll->in_div_max; m++) { in matroxfb_PLL_mavenclock()
261 if (n < pll->feed_div_min) in matroxfb_PLL_mavenclock()
263 if (n > pll->feed_div_max) in matroxfb_PLL_mavenclock()
|
| /linux-4.4.14/drivers/media/pci/bt8xx/ |
| D | bttv-cards.c | 99 static unsigned int pll[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET }; variable
121 module_param_array(pll, int, NULL, 0444);
134 MODULE_PARM_DESC(pll, "specify installed crystal (0=none, 28=28 MHz, 35=35 MHz, 14=14 MHz)");
401 .pll = PLL_28,
465 .pll = PLL_28,
477 .pll = PLL_28,
490 .pll = PLL_28,
528 .pll = PLL_28,
543 .pll = PLL_28,
571 .pll = PLL_28,
[all …]
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| /linux-4.4.14/arch/m68k/q40/ |
| D | config.c | 47 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
48 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
302 static int q40_get_rtc_pll(struct rtc_pll_info *pll) in q40_get_rtc_pll() argument
306 pll->pll_value = tmp & Q40_RTC_PLL_MASK; in q40_get_rtc_pll()
308 pll->pll_value = -pll->pll_value; in q40_get_rtc_pll()
309 pll->pll_max = 31; in q40_get_rtc_pll()
310 pll->pll_min = -31; in q40_get_rtc_pll()
311 pll->pll_posmult = 512; in q40_get_rtc_pll()
312 pll->pll_negmult = 256; in q40_get_rtc_pll()
313 pll->pll_clock = 125829120; in q40_get_rtc_pll()
[all …]
|
| /linux-4.4.14/Documentation/devicetree/bindings/clock/ |
| D | keystone-pll.txt | 15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
17 - reg - pll control0 and pll multipler registers
19 post-divider registers are applicable only for main pll clock
26 compatible = "ti,keystone,main-pll-clock";
35 compatible = "ti,keystone,pll-clock";
37 clock-output-names = "pa-pll-clk";
44 - compatible : shall be "ti,keystone,pll-mux-clock"
46 - reg - pll mux register
56 compatible = "ti,keystone,pll-mux-clock";
66 - compatible : shall be "ti,keystone,pll-divider-clock"
[all …]
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| D | qca,ath79-pll.txt | 8 - "qca,ar7100-pll"
9 - "qca,ar7240-pll"
10 - "qca,ar9130-pll"
11 - "qca,ar9330-pll"
12 - "qca,ar9340-pll"
13 - "qca,qca9550-pll"
25 compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
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| D | qoriq-clock.txt | 70 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
97 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
98 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
105 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
106 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
109 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
110 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
143 compatible = "fsl,qoriq-core-pll-1.0";
151 compatible = "fsl,qoriq-core-pll-1.0";
174 platform-pll: platform-pll@c00 {
[all …]
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| D | vt8500.txt | 9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
16 - reg : shall be the control register offset from PMC base for the pll clock.
23 be a pll output.
61 compatible = "wm,wm8650-pll-clock";
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| D | ti-keystone-pllctrl.txt | 1 * Device tree bindings for Texas Instruments keystone pll controller
3 The main pll controller used to drive theC66x CorePacs, the switch fabric,
12 - reg: contains offset/length value for pll controller
17 pllctrl: pll-controller@0x02310000 {
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| D | silabs,si5351.txt | 26 - silabs,pll-source: pair of (number, source) for each pll. Allows
27 to overwrite clock source of pll A (number=0) or B (number=1).
45 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
47 - silabs,pll-master: boolean, multisynth can change pll frequency.
78 silabs,pll-source = <0 0>, <1 0>;
93 silabs,pll-master;
109 pll-master;
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| D | clock-bindings.txt | 104 pll: pll@4c000 {
105 compatible = "vendor,some-pll-interface"
110 clock-output-names = "pll", "pll-switched";
120 clocks = <&osc 0>, <&pll 1>;
131 ("pll" and "pll-switched").
133 register clock connected to the PLL clock (the "pll-switched" signal)
153 clocks = <&osc 0>, <&pll 1>;
156 assigned-clocks = <&clkcon 0>, <&pll 2>;
157 assigned-clock-parents = <&pll 2>;
161 In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
[all …]
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| D | renesas,h8s2678-pll-clock.txt | 7 - compatible: Must be "renesas,h8s2678-pll-clock"
19 compatible = "renesas,h8s2678-pll-clock";
|
| D | at91-clock.txt | 49 "atmel,at91rm9200-clk-pll" or
50 "atmel,at91sam9g45-clk-pll" or
52 "atmel,sama5d3-clk-pll":
53 at91 pll clocks
283 Required properties for pll clocks:
288 - reg : pll id.
294 - #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
302 - atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
303 depending on #atmel,pll-output-range-cells
308 compatible = "atmel,at91sam9g45-clk-pll";
[all …]
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| D | rockchip,rk3368-cru.txt | 18 If missing, pll rates are not changeable, due to the missing pll lock status.
39 - "usbotg_out" - output clock of the pll in the otg phy
|
| D | calxeda.txt | 9 "calxeda,hb-pll-clock" - for a PLL clock
16 either an oscillator or a pll output.
|
| D | moxa,moxart-clock.txt | 14 - compatible : Must be "moxa,moxart-pll-clock"
38 compatible = "moxa,moxart-pll-clock";
|
| D | altr_socfpga.txt | 9 "altr,socfpga-pll-clock" - for a PLL clock
17 either an oscillator or a pll output.
|
| D | renesas,rz-cpg-clocks.txt | 17 - clock-output-names: The names of the clocks. Supported clocks are "pll",
38 clock-output-names = "pll", "i", "g";
|
| D | rockchip,rk3288-cru.txt | 18 If missing pll rates are not changable, due to the missing pll lock status.
|
| D | rockchip,rk3188-cru.txt | 19 If missing pll rates are not changable, due to the missing pll lock status.
|
| /linux-4.4.14/Documentation/devicetree/bindings/sound/ |
| D | pcm512x.txt | 20 is absent the device will be configured to clock from BCLK. If pll-in
21 and pll-out are specified in addition to a clock, the device is
24 - pll-in, pll-out : gpio pins used to connect the pll using <1>
26 given pll-in pin and PLL output on the given pll-out pin. An
27 external connection from the pll-out pin to the SCLK pin is assumed.
50 pll-in = <3>;
51 pll-out = <6>;
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| D | adi,adau1701.txt | 14 - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs
35 adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>;
|
| /linux-4.4.14/drivers/clk/ |
| D | clk-qoriq.c | 51 int pll; /* CGx_PLLn */ member
91 struct clockgen_pll pll[6]; member
355 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
357 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p2041_init_periph()
367 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
369 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
372 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
374 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
387 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; in p5020_init_periph()
389 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5020_init_periph()
[all …]
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| D | clk-nomadik.c | 166 struct clk_pll *pll = to_pll(hw); in pll_clk_enable() local
171 if (pll->id == 1) { in pll_clk_enable()
176 } else if (pll->id == 2) { in pll_clk_enable()
186 struct clk_pll *pll = to_pll(hw); in pll_clk_disable() local
191 if (pll->id == 1) { in pll_clk_disable()
196 } else if (pll->id == 2) { in pll_clk_disable()
205 struct clk_pll *pll = to_pll(hw); in pll_clk_is_enabled() local
209 if (pll->id == 1) { in pll_clk_is_enabled()
212 } else if (pll->id == 2) { in pll_clk_is_enabled()
221 struct clk_pll *pll = to_pll(hw); in pll_clk_recalc_rate() local
[all …]
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| D | clk-cdce706.c | 27 #define CDCE706_PLL_M_LOW(pll) (1 + 3 * (pll)) argument
28 #define CDCE706_PLL_N_LOW(pll) (2 + 3 * (pll)) argument
29 #define CDCE706_PLL_HI(pll) (3 + 3 * (pll)) argument
40 #define CDCE706_PLL_MUX_MASK(pll) (0x80 >> (pll)) argument
48 #define CDCE706_PLL_FVCO_MASK(pll) (0x80 >> (pll)) argument
89 struct cdce706_hw_data pll[3]; member
530 for (i = 0; i < ARRAY_SIZE(cdce->pll); ++i) { in cdce706_register_plls()
542 cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8); in cdce706_register_plls()
543 cdce->pll[i].mul = n | ((v & CDCE706_PLL_HI_N_MASK) << in cdce706_register_plls()
545 cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i); in cdce706_register_plls()
[all …]
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| D | clk-cdce925.c | 63 struct clk_cdce925_pll pll[NUMBER_OF_PLLS]; member
205 u8 pll[4]; /* Bits are spread out over 4 byte registers */ in cdce925_pll_prepare() local
233 pll[0] = n >> 4; in cdce925_pll_prepare()
234 pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F); in cdce925_pll_prepare()
235 pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07); in cdce925_pll_prepare()
236 pll[3] = ((q & 0x07) << 5) | (p << 2) | in cdce925_pll_prepare()
239 for (i = 0; i < ARRAY_SIZE(pll); ++i) in cdce925_pll_prepare()
241 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); in cdce925_pll_prepare()
357 struct clk *pll = clk_get_parent(hw->clk); in cdce925_clk_best_parent_rate() local
358 struct clk *root = clk_get_parent(pll); in cdce925_clk_best_parent_rate()
[all …]
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| D | clk-ls1x.c | 35 u32 pll, rate; in ls1x_pll_recalc_rate() local
37 pll = __raw_readl(LS1X_CLK_PLL_FREQ); in ls1x_pll_recalc_rate()
38 rate = 12 + (pll & 0x3f) + (((pll >> 8) & 0x3ff) >> 10); in ls1x_pll_recalc_rate()
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| D | clk-vt8500.c | 542 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_set_rate() local
549 switch (pll->type) { in vtwm_pll_set_rate()
571 spin_lock_irqsave(pll->lock, flags); in vtwm_pll_set_rate()
574 writel(pll_val, pll->reg); in vtwm_pll_set_rate()
577 spin_unlock_irqrestore(pll->lock, flags); in vtwm_pll_set_rate()
585 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_round_rate() local
589 switch (pll->type) { in vtwm_pll_round_rate()
616 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_recalc_rate() local
617 u32 pll_val = readl(pll->reg); in vtwm_pll_recalc_rate()
620 switch (pll->type) { in vtwm_pll_recalc_rate()
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| D | clk-xgene.c | 88 u32 pll; in xgene_clk_pll_recalc_rate() local
93 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
101 fvco = parent_rate * (N_DIV_RD(pll) + 4); in xgene_clk_pll_recalc_rate()
108 nref = CLKR_RD(pll) + 1; in xgene_clk_pll_recalc_rate()
109 nout = CLKOD_RD(pll) + 1; in xgene_clk_pll_recalc_rate()
110 nfb = CLKF_RD(pll); in xgene_clk_pll_recalc_rate()
|
| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | radeon_display.c | 981 void radeon_compute_pll_avivo(struct radeon_pll *pll, in radeon_compute_pll_avivo() argument
989 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? in radeon_compute_pll_avivo()
999 fb_div_min = pll->min_feedback_div; in radeon_compute_pll_avivo()
1000 fb_div_max = pll->max_feedback_div; in radeon_compute_pll_avivo()
1002 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
1008 if (pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
1009 ref_div_min = pll->reference_div; in radeon_compute_pll_avivo()
1011 ref_div_min = pll->min_ref_div; in radeon_compute_pll_avivo()
1013 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && in radeon_compute_pll_avivo()
1014 pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
[all …]
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| D | atombios_crtc.c | 1064 struct radeon_pll *pll; in atombios_crtc_set_pll() local
1075 pll = &rdev->clock.p1pll; in atombios_crtc_set_pll()
1078 pll = &rdev->clock.p2pll; in atombios_crtc_set_pll()
1083 pll = &rdev->clock.dcpll; in atombios_crtc_set_pll()
1088 pll->flags = radeon_crtc->pll_flags; in atombios_crtc_set_pll()
1089 pll->reference_div = radeon_crtc->pll_reference_div; in atombios_crtc_set_pll()
1090 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()
1094 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1097 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1100 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
[all …]
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| D | radeon_legacy_crtc.c | 751 struct radeon_pll *pll; in radeon_set_pll() local
774 pll = &rdev->clock.p2pll; in radeon_set_pll()
776 pll = &rdev->clock.p1pll; in radeon_set_pll()
778 pll->flags = RADEON_PLL_LEGACY; in radeon_set_pll()
781 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in radeon_set_pll()
783 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in radeon_set_pll()
795 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; in radeon_set_pll()
810 pll->flags |= RADEON_PLL_USE_REF_DIV; in radeon_set_pll()
818 radeon_compute_pll_legacy(pll, mode->clock, in radeon_set_pll()
849 pll_gain = radeon_compute_pll_gain(pll->reference_freq, in radeon_set_pll()
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| D | radeon_legacy_tv.c | 242 struct radeon_pll *pll; in radeon_legacy_tv_get_std_mode() local
246 pll = &rdev->clock.p2pll; in radeon_legacy_tv_get_std_mode()
248 pll = &rdev->clock.p1pll; in radeon_legacy_tv_get_std_mode()
251 *pll_ref_freq = pll->reference_freq; in radeon_legacy_tv_get_std_mode()
256 if (pll->reference_freq == 2700) in radeon_legacy_tv_get_std_mode()
261 if (pll->reference_freq == 2700) in radeon_legacy_tv_get_std_mode()
434 struct radeon_pll *pll; in radeon_legacy_tv_init_restarts() local
438 pll = &rdev->clock.p2pll; in radeon_legacy_tv_init_restarts()
440 pll = &rdev->clock.p1pll; in radeon_legacy_tv_init_restarts()
|
| /linux-4.4.14/arch/c6x/platforms/ |
| D | plldata.c | 172 struct pll_data *pll = &c6x_soc_pll1; in c6455_setup_clocks() local
173 struct clk *sysclks = pll->sysclks; in c6455_setup_clocks()
175 pll->flags = PLL_HAS_PRE | PLL_HAS_MUL; in c6455_setup_clocks()
210 struct pll_data *pll = &c6x_soc_pll1; in c6457_setup_clocks() local
211 struct clk *sysclks = pll->sysclks; in c6457_setup_clocks()
213 pll->flags = PLL_HAS_MUL | PLL_HAS_POST; in c6457_setup_clocks()
260 struct pll_data *pll = &c6x_soc_pll1; in c6472_setup_clocks() local
261 struct clk *sysclks = pll->sysclks; in c6472_setup_clocks()
264 pll->flags = PLL_HAS_MUL; in c6472_setup_clocks()
309 struct pll_data *pll = &c6x_soc_pll1; in c6474_setup_clocks() local
[all …]
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| D | pll.c | 204 static u32 pll_read(struct pll_data *pll, int reg) in pll_read() argument
206 return soc_readl(pll->base + reg); in pll_read()
212 struct pll_data *pll; in clk_sysclk_recalc() local
224 pll = clk->parent->pll_data; in clk_sysclk_recalc()
228 rate = pll->input_rate; in clk_sysclk_recalc()
243 v = pll_read(pll, clk->div); in clk_sysclk_recalc()
273 struct pll_data *pll = clk->pll_data; in clk_pllclk_recalc() local
279 ctrl = pll_read(pll, PLLCTL); in clk_pllclk_recalc()
280 rate = pll->input_rate = clk->parent->rate; in clk_pllclk_recalc()
287 if (pll->flags & PLL_HAS_MUL) { in clk_pllclk_recalc()
[all …]
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| D | Makefile | 7 obj-y = platform.o cache.o megamod-pic.o pll.o plldata.o timer64.o
|
| /linux-4.4.14/drivers/staging/sm750fb/ |
| D | ddk750_chip.c | 54 pll_value_t pll; in setChipClock() local
65 pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ in setChipClock()
66 pll.clockType = MXCLK_PLL; in setChipClock()
73 ulActualMxClk = calcPllValue(frequency, &pll); in setChipClock()
76 POKE32(MXCLK_PLL_CTRL, formatPllReg(&pll)); in setChipClock()
297 unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) in calcPllValue() argument
317 input = pll->inputFreq / 1000; in calcPllValue()
320 if (pll->clockType == MXCLK_PLL) in calcPllValue()
339 tmpClock = pll->inputFreq * M / N / X; in calcPllValue()
342 pll->M = M; in calcPllValue()
[all …]
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| D | ddk750_mode.c | 78 static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) in programModeRegisters() argument
84 if (pll->clockType == SECONDARY_PLL) { in programModeRegisters()
86 POKE32(CRT_PLL_CTRL, formatPllReg(pll)); in programModeRegisters()
122 } else if (pll->clockType == PRIMARY_PLL) { in programModeRegisters()
125 POKE32(PANEL_PLL_CTRL, formatPllReg(pll)); in programModeRegisters()
186 pll_value_t pll; in ddk750_setModeTiming() local
189 pll.inputFreq = DEFAULT_INPUT_CLOCK; in ddk750_setModeTiming()
190 pll.clockType = clock; in ddk750_setModeTiming()
192 uiActualPixelClk = calcPllValue(parm->pixel_clock, &pll); in ddk750_setModeTiming()
198 programModeRegisters(parm, &pll); in ddk750_setModeTiming()
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| /linux-4.4.14/drivers/video/fbdev/via/ |
| D | via_clock.h | 63 struct via_pll_config pll) in get_pll_internal_frequency() argument
65 return ref_freq / pll.divisor * pll.multiplier; in get_pll_internal_frequency()
69 struct via_pll_config pll) in get_pll_output_frequency() argument
71 return get_pll_internal_frequency(ref_freq, pll) >> pll.rshift; in get_pll_output_frequency()
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| D | via_clock.c | 36 static inline u32 cle266_encode_pll(struct via_pll_config pll) in cle266_encode_pll() argument
38 return (pll.multiplier << 8) in cle266_encode_pll()
39 | (pll.rshift << 6) in cle266_encode_pll()
40 | pll.divisor; in cle266_encode_pll()
43 static inline u32 k800_encode_pll(struct via_pll_config pll) in k800_encode_pll() argument
45 return ((pll.divisor - 2) << 16) in k800_encode_pll()
46 | (pll.rshift << 10) in k800_encode_pll()
47 | (pll.multiplier - 2); in k800_encode_pll()
50 static inline u32 vx855_encode_pll(struct via_pll_config pll) in vx855_encode_pll() argument
52 return (pll.divisor << 16) in vx855_encode_pll()
[all …]
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| /linux-4.4.14/drivers/char/ |
| D | genrtc.c | 270 struct rtc_pll_info pll; in gen_rtc_ioctl() local
276 if (get_rtc_pll(&pll)) in gen_rtc_ioctl()
279 return copy_to_user(argp, &pll, sizeof pll) ? -EFAULT : 0; in gen_rtc_ioctl()
284 if (copy_from_user(&pll, argp, sizeof(pll))) in gen_rtc_ioctl()
286 return set_rtc_pll(&pll); in gen_rtc_ioctl()
394 struct rtc_pll_info pll; in gen_rtc_proc_show() local
442 if (!get_rtc_pll(&pll)) in gen_rtc_proc_show()
450 pll.pll_value, in gen_rtc_proc_show()
451 pll.pll_max, in gen_rtc_proc_show()
452 pll.pll_min, in gen_rtc_proc_show()
[all …]
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| /linux-4.4.14/drivers/cpufreq/ |
| D | cpufreq-nforce2.c | 67 static int nforce2_calc_fsb(int pll) in nforce2_calc_fsb() argument
71 mul = (pll >> 8) & 0xff; in nforce2_calc_fsb()
72 div = pll & 0xff; in nforce2_calc_fsb()
116 static void nforce2_write_pll(int pll) in nforce2_write_pll() argument
125 pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll); in nforce2_write_pll()
174 int pll = 0; in nforce2_set_fsb() local
190 pll = nforce2_calc_pll(tfsb); in nforce2_set_fsb()
192 if (pll < 0) in nforce2_set_fsb()
195 nforce2_write_pll(pll); in nforce2_set_fsb()
214 pll = nforce2_calc_pll(tfsb); in nforce2_set_fsb()
[all …]
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| D | s3c24xx-cpufreq.c | 72 cfg->pll.driver_data = __raw_readl(S3C2410_MPLLCON); in s3c_cpufreq_getcur()
73 cfg->pll.frequency = fclk; in s3c_cpufreq_getcur()
83 unsigned long pll = cfg->pll.frequency; in s3c_cpufreq_calc() local
85 cfg->freq.fclk = pll; in s3c_cpufreq_calc()
86 cfg->freq.hclk = pll / cfg->divs.h_divisor; in s3c_cpufreq_calc()
87 cfg->freq.pclk = pll / cfg->divs.p_divisor; in s3c_cpufreq_calc()
105 pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, in s3c_cpufreq_show()
155 struct cpufreq_frequency_table *pll) in s3c_cpufreq_settarget() argument
167 cpu_new.pll = pll ? *pll : cpu_cur.pll; in s3c_cpufreq_settarget()
169 if (pll) in s3c_cpufreq_settarget()
[all …]
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| D | cris-artpec3-cpufreq.c | 27 return clk_ctrl.pll ? 200000 : 6000; in cris_freq_get_cpu_frequency()
40 clk_ctrl.pll = 1; in cris_freq_target()
42 clk_ctrl.pll = 0; in cris_freq_target()
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| D | cris-etraxfs-cpufreq.c | 27 return clk_ctrl.pll ? 200000 : 6000; in cris_freq_get_cpu_frequency()
40 clk_ctrl.pll = 1; in cris_freq_target()
42 clk_ctrl.pll = 0; in cris_freq_target()
|
| /linux-4.4.14/drivers/video/fbdev/nvidia/ |
| D | nv_hw.c | 144 unsigned int pll, N, M, MB, NB, P; in nvGetClocks() local
147 pll = NV_RD32(par->PMC, 0x4020); in nvGetClocks()
148 P = (pll >> 16) & 0x07; in nvGetClocks()
149 pll = NV_RD32(par->PMC, 0x4024); in nvGetClocks()
150 M = pll & 0xFF; in nvGetClocks()
151 N = (pll >> 8) & 0xFF; in nvGetClocks()
157 MB = (pll >> 16) & 0xFF; in nvGetClocks()
158 NB = (pll >> 24) & 0xFF; in nvGetClocks()
162 pll = NV_RD32(par->PMC, 0x4000); in nvGetClocks()
163 P = (pll >> 16) & 0x07; in nvGetClocks()
[all …]
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| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gt215.c | 108 read_pll(struct gt215_clk *clk, int idx, u32 pll) in read_pll() argument
111 u32 ctrl = nvkm_rd32(device, pll + 0); in read_pll()
116 u32 coef = nvkm_rd32(device, pll + 4); in read_pll()
124 if ((pll & 0x00ff00) == 0x00e800) in read_pll()
232 gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz, in gt215_pll_info() argument
241 info->pll = 0; in gt215_pll_info()
247 if (!pll || (diff >= -2000 && diff < 3000)) { in gt215_pll_info()
252 ret = nvbios_pll_parse(subdev->device->bios, pll, &limits); in gt215_pll_info()
262 info->pll = (P << 16) | (N << 8) | M; in gt215_pll_info()
272 int idx, u32 pll, int dom) in calc_clk() argument
[all …]
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| D | nv40.c | 128 struct nvbios_pll pll; in nv40_clk_calc_pll() local
131 ret = nvbios_pll_parse(subdev->device->bios, reg, &pll); in nv40_clk_calc_pll()
135 if (khz < pll.vco1.max_freq) in nv40_clk_calc_pll()
136 pll.vco2.max_freq = 0; in nv40_clk_calc_pll()
138 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P); in nv40_clk_calc_pll()
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| D | mcp77.c | 169 struct nvbios_pll pll; in calc_pll() local
172 ret = nvbios_pll_parse(subdev->device->bios, reg, &pll); in calc_pll()
176 pll.vco2.max_freq = 0; in calc_pll()
177 pll.refclk = nvkm_clk_read(&clk->base, nv_clk_src_href); in calc_pll()
178 if (!pll.refclk) in calc_pll()
181 return nv04_pll_calc(subdev, &pll, clock, N, M, NULL, NULL, P); in calc_pll()
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| D | gk104.c | 60 read_pll(struct gk104_clk *clk, u32 pll) in read_pll() argument
63 u32 ctrl = nvkm_rd32(device, pll + 0x00); in read_pll()
64 u32 coef = nvkm_rd32(device, pll + 0x04); in read_pll()
74 switch (pll) { in read_pll()
86 fN = nvkm_rd32(device, pll + 0x10) >> 16; in read_pll()
92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
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| D | nv50.c | 328 struct nvbios_pll pll; in calc_pll() local
331 ret = nvbios_pll_parse(subdev->device->bios, reg, &pll); in calc_pll()
335 pll.vco2.max_freq = 0; in calc_pll()
336 pll.refclk = read_pll_ref(clk, reg); in calc_pll()
337 if (!pll.refclk) in calc_pll()
340 return nv04_pll_calc(subdev, &pll, idx, N, M, NULL, NULL, P); in calc_pll()
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| D | gf100.c | 59 read_pll(struct gf100_clk *clk, u32 pll) in read_pll() argument
62 u32 ctrl = nvkm_rd32(device, pll + 0x00); in read_pll()
63 u32 coef = nvkm_rd32(device, pll + 0x04); in read_pll()
72 switch (pll) { in read_pll()
88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
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| D | gt215.h | 7 u32 pll; member
|
| /linux-4.4.14/drivers/gpu/drm/msm/dsi/ |
| D | dsi.h | 109 void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);
110 int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
112 void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);
113 int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
119 static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) in msm_dsi_pll_destroy() argument
122 static inline int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, in msm_dsi_pll_get_clk_provider() argument
127 static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll) in msm_dsi_pll_save_state() argument
130 static inline int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll) in msm_dsi_pll_restore_state() argument
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| /linux-4.4.14/sound/soc/codecs/ |
| D | ak4671.c | 477 u8 pll; in ak4671_set_dai_sysclk() local
479 pll = snd_soc_read(codec, AK4671_PLL_MODE_SELECT0); in ak4671_set_dai_sysclk()
480 pll &= ~AK4671_PLL; in ak4671_set_dai_sysclk()
484 pll |= AK4671_PLL_11_2896MHZ; in ak4671_set_dai_sysclk()
487 pll |= AK4671_PLL_12MHZ; in ak4671_set_dai_sysclk()
490 pll |= AK4671_PLL_12_288MHZ; in ak4671_set_dai_sysclk()
493 pll |= AK4671_PLL_13MHZ; in ak4671_set_dai_sysclk()
496 pll |= AK4671_PLL_13_5MHZ; in ak4671_set_dai_sysclk()
499 pll |= AK4671_PLL_19_2MHZ; in ak4671_set_dai_sysclk()
502 pll |= AK4671_PLL_24MHZ; in ak4671_set_dai_sysclk()
[all …]
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| D | adav80x.c | 47 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00 argument
48 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll)) argument
49 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll)) argument
57 #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll)) argument
60 #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4)) argument
62 #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00) argument
63 #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08) argument
64 #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c) argument
66 #define ADAV80X_PLL_CTRL2_SEL(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x02) argument
67 #define ADAV80X_PLL_CTRL2_DOUB(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x01) argument
[all …]
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| D | wm8955.c | 147 int Fref, int Fout, struct pll_factors *pll) in wm8995_pll_factors() argument
160 pll->outdiv = 1; in wm8995_pll_factors()
163 pll->outdiv = 0; in wm8995_pll_factors()
173 pll->n = Ndiv; in wm8995_pll_factors()
188 pll->k = K / 10; in wm8995_pll_factors()
190 dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv); in wm8995_pll_factors()
252 struct pll_factors pll; in wm8955_configure_clocking() local
286 clock_cfgs[sr].mclk, &pll); in wm8955_configure_clocking()
296 (pll.n << WM8955_N_SHIFT) | in wm8955_configure_clocking()
297 pll.k >> 18); in wm8955_configure_clocking()
[all …]
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| D | ak4642.c | 344 u8 pll; in ak4642_dai_set_sysclk() local
349 pll = PLL2; in ak4642_dai_set_sysclk()
352 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
355 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
358 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
361 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
364 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
375 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
[all …]
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| /linux-4.4.14/arch/avr32/boards/atstk1000/ |
| D | atstk1003.c | 84 struct clk *pll; in atstk1003_setup_extdac() local
89 pll = clk_get(NULL, "pll0"); in atstk1003_setup_extdac()
90 if (IS_ERR(pll)) in atstk1003_setup_extdac()
93 if (clk_set_parent(gclk, pll)) { in atstk1003_setup_extdac()
102 clk_put(pll); in atstk1003_setup_extdac()
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| D | atstk1004.c | 89 struct clk *pll; in atstk1004_setup_extdac() local
94 pll = clk_get(NULL, "pll0"); in atstk1004_setup_extdac()
95 if (IS_ERR(pll)) in atstk1004_setup_extdac()
98 if (clk_set_parent(gclk, pll)) { in atstk1004_setup_extdac()
107 clk_put(pll); in atstk1004_setup_extdac()
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| D | atstk1002.c | 217 struct clk *pll; in atstk1002_setup_extdac() local
222 pll = clk_get(NULL, "pll0"); in atstk1002_setup_extdac()
223 if (IS_ERR(pll)) in atstk1002_setup_extdac()
226 if (clk_set_parent(gclk, pll)) { in atstk1002_setup_extdac()
235 clk_put(pll); in atstk1002_setup_extdac()
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| /linux-4.4.14/drivers/clk/keystone/ |
| D | pll.c | 82 struct clk_pll *pll = to_clk_pll(hw); in clk_pllclk_recalc() local
83 struct clk_pll_data *pll_data = pll->pll_data; in clk_pllclk_recalc()
130 struct clk_pll *pll; in clk_register_pll() local
133 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in clk_register_pll()
134 if (!pll) in clk_register_pll()
143 pll->pll_data = pll_data; in clk_register_pll()
144 pll->hw.init = &init; in clk_register_pll()
146 clk = clk_register(NULL, &pll->hw); in clk_register_pll()
152 kfree(pll); in clk_register_pll()
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| D | Makefile | 1 obj-y += pll.o gate.o
|
| /linux-4.4.14/arch/m68k/include/asm/ |
| D | rtc.h | 63 static inline int get_rtc_pll(struct rtc_pll_info *pll) in get_rtc_pll() argument
66 return mach_get_rtc_pll(pll); in get_rtc_pll()
70 static inline int set_rtc_pll(struct rtc_pll_info *pll) in set_rtc_pll() argument
73 return mach_set_rtc_pll(pll); in set_rtc_pll()
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| /linux-4.4.14/arch/c6x/boot/dts/ |
| D | tms320c6457.dtsi | 61 compatible = "ti,c6457-pll", "ti,c64x+pll";
63 ti,c64x+pll-bypass-delay = <300>;
64 ti,c64x+pll-reset-delay = <24000>;
65 ti,c64x+pll-lock-delay = <50000>;
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| D | tms320c6474.dtsi | 82 compatible = "ti,c6474-pll", "ti,c64x+pll";
84 ti,c64x+pll-bypass-delay = <120>;
85 ti,c64x+pll-reset-delay = <30000>;
86 ti,c64x+pll-lock-delay = <60000>;
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| D | tms320c6455.dtsi | 71 compatible = "ti,c6455-pll", "ti,c64x+pll";
73 ti,c64x+pll-bypass-delay = <1440>;
74 ti,c64x+pll-reset-delay = <15360>;
75 ti,c64x+pll-lock-delay = <24000>;
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| D | tms320c6472.dtsi | 105 compatible = "ti,c6472-pll", "ti,c64x+pll";
107 ti,c64x+pll-bypass-delay = <200>;
108 ti,c64x+pll-reset-delay = <12000>;
109 ti,c64x+pll-lock-delay = <80000>;
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| D | tms320c6678.dtsi | 127 compatible = "ti,c6678-pll", "ti,c64x+pll";
129 ti,c64x+pll-bypass-delay = <200>;
130 ti,c64x+pll-reset-delay = <12000>;
131 ti,c64x+pll-lock-delay = <80000>;
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| /linux-4.4.14/drivers/gpu/drm/i915/ |
| D | intel_ddi.c | 1109 u32 val, pll; in hsw_ddi_clock_get() local
1129 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; in hsw_ddi_clock_get()
1130 if (pll == SPLL_PLL_FREQ_810MHz) in hsw_ddi_clock_get()
1132 else if (pll == SPLL_PLL_FREQ_1350MHz) in hsw_ddi_clock_get()
1134 else if (pll == SPLL_PLL_FREQ_2700MHz) in hsw_ddi_clock_get()
1154 struct intel_shared_dpll *pll; in bxt_calc_pll_link() local
1162 pll = &dev_priv->shared_dplls[dpll]; in bxt_calc_pll_link()
1163 state = &pll->config.hw_state; in bxt_calc_pll_link()
1274 struct intel_shared_dpll *pll; in hsw_ddi_pll_select() local
1289 pll = intel_get_shared_dpll(intel_crtc, crtc_state); in hsw_ddi_pll_select()
[all …]
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| D | intel_display.c | 1202 struct intel_shared_dpll *pll, in assert_shared_dpll() argument
1208 if (WARN (!pll, in assert_shared_dpll()
1212 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); in assert_shared_dpll()
1215 pll->name, state_string(state), state_string(cur_state)); in assert_shared_dpll()
1870 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_prepare_shared_dpll() local
1872 if (WARN_ON(pll == NULL)) in intel_prepare_shared_dpll()
1875 WARN_ON(!pll->config.crtc_mask); in intel_prepare_shared_dpll()
1876 if (pll->active == 0) { in intel_prepare_shared_dpll()
1877 DRM_DEBUG_DRIVER("setting up %s\n", pll->name); in intel_prepare_shared_dpll()
1878 WARN_ON(pll->on); in intel_prepare_shared_dpll()
[all …]
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| D | intel_atomic.c | 270 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_atomic_duplicate_dpll_state() local
272 shared_dpll[i] = pll->config; in intel_atomic_duplicate_dpll_state()
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| /linux-4.4.14/drivers/clk/nxp/ |
| D | clk-lpc18xx-cgu.c | 267 struct lpc18xx_pll pll; member
352 struct lpc18xx_pll *pll = to_lpc_pll(hw); in lpc18xx_pll0_recalc_rate() local
355 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); in lpc18xx_pll0_recalc_rate()
356 mdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV); in lpc18xx_pll0_recalc_rate()
357 npdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); in lpc18xx_pll0_recalc_rate()
398 struct lpc18xx_pll *pll = to_lpc_pll(hw); in lpc18xx_pll0_set_rate() local
418 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); in lpc18xx_pll0_set_rate()
422 clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); in lpc18xx_pll0_set_rate()
425 clk_writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV); in lpc18xx_pll0_set_rate()
426 clk_writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); in lpc18xx_pll0_set_rate()
[all …]
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| /linux-4.4.14/Documentation/devicetree/bindings/clock/st/ |
| D | st,clkgen-pll.txt | 1 Binding for a ST pll clock driver.
28 "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
29 "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
42 clk_s_a0_pll: clk-s-a0-pll {
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| D | st,clkgen.txt | 4 A Clockgen node can contain pll, diviser or multiplexer nodes.
48 [4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
64 clk_s_a0_pll: clk-s-a0-pll {
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| /linux-4.4.14/arch/mips/boot/dts/qca/ |
| D | ar9132.dtsi | 60 clocks = <&pll 2>;
85 pll: pll-controller@18050000 { label
87 "qca,ar9130-pll";
103 clocks = <&pll 2>;
132 clocks = <&pll 2>;
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| /linux-4.4.14/Documentation/devicetree/bindings/display/ti/ |
| D | ti,omap5-dss.txt | 60 - reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
61 - reg-names: "proto", "phy", "pll"
65 - clocks: handles to fclk and pll clock
82 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
84 - reg-names: "wp", "pll", "phy", "core"
88 - clocks: handles to fclk and pll clock
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| D | ti,dra7-dss.txt | 25 - clocks: handle to video1 pll clock and video2 pll clock
55 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
57 - reg-names: "wp", "pll", "phy", "core"
61 - clocks: handles to fclk and pll clock
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| D | ti,omap4-dss.txt | 79 - reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
80 - reg-names: "proto", "phy", "pll"
84 - clocks: handles to fclk and pll clock
101 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
103 - reg-names: "wp", "pll", "phy", "core"
107 - clocks: handles to fclk and pll clock
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| D | ti,omap3-dss.txt | 73 - reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
74 - reg-names: "proto", "phy", "pll"
78 - clocks: handles to fclk and pll clock
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| /linux-4.4.14/arch/powerpc/boot/dts/fsl/ |
| D | qoriq-clockgen2.dtsi | 51 compatible = "fsl,qoriq-core-pll-2.0";
58 compatible = "fsl,qoriq-core-pll-2.0";
62 platform_pll: platform-pll@c00 {
65 compatible = "fsl,qoriq-platform-pll-2.0";
67 clock-output-names = "platform-pll", "platform-pll-div2";
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| D | qoriq-clockgen1.dtsi | 52 compatible = "fsl,qoriq-core-pll-1.0";
59 compatible = "fsl,qoriq-core-pll-1.0";
79 platform_pll: platform-pll@c00 {
82 compatible = "fsl,qoriq-platform-pll-1.0";
84 clock-output-names = "platform-pll", "platform-pll-div2";
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| /linux-4.4.14/Documentation/devicetree/bindings/ufs/ |
| D | ufs-qcom.txt | 17 - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply
26 - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
39 vdda-pll-supply = <&pma8084_l12>;
41 vdda-pll-max-microamp = <1000>;
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| /linux-4.4.14/arch/arm/boot/dts/ |
| D | k2e-clocks.dtsi | 14 compatible = "ti,keystone,main-pll-clock";
22 compatible = "ti,keystone,pll-clock";
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "ddr-3a-pll-clk";
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| D | wm8850.dtsi | 86 compatible = "wm,wm8850-pll-clock";
93 compatible = "wm,wm8850-pll-clock";
100 compatible = "wm,wm8850-pll-clock";
107 compatible = "wm,wm8850-pll-clock";
114 compatible = "wm,wm8850-pll-clock";
121 compatible = "wm,wm8850-pll-clock";
128 compatible = "wm,wm8850-pll-clock";
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| D | wm8650.dtsi | 83 compatible = "wm,wm8650-pll-clock";
90 compatible = "wm,wm8650-pll-clock";
97 compatible = "wm,wm8650-pll-clock";
104 compatible = "wm,wm8650-pll-clock";
111 compatible = "wm,wm8650-pll-clock";
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| D | dove-cubox.dts | 93 silabs,pll-source = <0 0>, <1 0>;
100 silabs,pll-master;
108 silabs,pll-master;
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| D | k2l-clocks.dtsi | 14 compatible = "ti,keystone,pll-clock";
16 clock-output-names = "arm-pll-clk";
23 compatible = "ti,keystone,main-pll-clock";
31 compatible = "ti,keystone,pll-clock";
40 compatible = "ti,keystone,pll-clock";
42 clock-output-names = "ddr-3a-pll-clk";
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| D | at91sam9g20.dtsi | 45 atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
58 atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
|
| D | k2hk-clocks.dtsi | 14 compatible = "ti,keystone,pll-clock";
16 clock-output-names = "arm-pll-clk";
23 compatible = "ti,keystone,main-pll-clock";
31 compatible = "ti,keystone,pll-clock";
40 compatible = "ti,keystone,pll-clock";
42 clock-output-names = "ddr-3a-pll-clk";
49 compatible = "ti,keystone,pll-clock";
51 clock-output-names = "ddr-3b-pll-clk";
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| D | wm8750.dtsi | 89 compatible = "wm,wm8750-pll-clock";
96 compatible = "wm,wm8750-pll-clock";
103 compatible = "wm,wm8750-pll-clock";
110 compatible = "wm,wm8750-pll-clock";
117 compatible = "wm,wm8750-pll-clock";
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| D | wm8505.dtsi | 86 compatible = "via,vt8500-pll-clock";
93 compatible = "via,vt8500-pll-clock";
100 compatible = "via,vt8500-pll-clock";
107 compatible = "via,vt8500-pll-clock";
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| D | stih416-clock.dtsi | 33 clk_s_a0_pll: clk-s-a0-pll {
91 clk_s_a1_pll: clk-s-a1-pll {
503 clockgen_a9_pll: clockgen-a9-pll {
508 clock-output-names = "clockgen-a9-pll-odf";
615 "clk-s-hdmi-reject-pll",
731 clockgen_ddr_pll: clockgen-ddr-pll {
747 clockgen_gpu_pll: clockgen-gpu-pll {
749 compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32";
752 clock-output-names = "clockgen-gpu-pll";
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| D | stih407-clock.dtsi | 43 clockgen_a9_pll: clockgen-a9-pll {
49 clock-output-names = "clockgen-a9-pll-odf";
97 clk_s_a0_pll: clk-s-a0-pll {
103 clock-output-names = "clk-s-a0-pll-ofd-0";
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| D | ecx-common.dtsi | 157 compatible = "calxeda,hb-pll-clock";
164 compatible = "calxeda,hb-pll-clock";
185 compatible = "calxeda,hb-pll-clock";
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramnv40.c | 39 struct nvbios_pll pll; in nv40_ram_calc() local
43 ret = nvbios_pll_parse(bios, 0x04, &pll); in nv40_ram_calc()
49 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P); in nv40_ram_calc()
54 ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20; in nv40_ram_calc()
|
| /linux-4.4.14/Documentation/devicetree/bindings/power/reset/ |
| D | keystone-reset.txt | 16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
17 access pll controller registers and the offset to use
40 pllctrl: pll-controller@02310000 {
52 ti,syscon-pll = <&pllctrl 0xe4>;
63 ti,syscon-pll = <&pllctrl 0xe4>;
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| /linux-4.4.14/arch/mips/ar7/ |
| D | clock.c | 62 u32 pll; member
178 u32 pll = readl(&clock->pll); in tnetd7300_get_clock() local
182 int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1; in tnetd7300_get_clock()
202 if ((pll & PLL_MODE_MASK) == 0) in tnetd7300_get_clock()
205 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { in tnetd7300_get_clock()
243 writel(4, &clock->pll); in tnetd7300_set_clock()
244 while (readl(&clock->pll) & PLL_STATUS) in tnetd7300_set_clock()
246 writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll); in tnetd7300_set_clock()
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| /linux-4.4.14/drivers/media/radio/ |
| D | tef6862.c | 108 u16 pll; in tef6862_s_frequency() local
116 pll = 1964 + ((freq - TEF6862_LO_FREQ) * 20) / FREQ_MUL; in tef6862_s_frequency()
118 i2cmsg[1] = (pll >> 8) & 0xff; in tef6862_s_frequency()
119 i2cmsg[2] = pll & 0xff; in tef6862_s_frequency()
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| /linux-4.4.14/drivers/clk/socfpga/ |
| D | Makefile | 3 obj-y += clk-pll.o
5 obj-y += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
|
| /linux-4.4.14/arch/powerpc/include/asm/ |
| D | rtc.h | 68 static inline int get_rtc_pll(struct rtc_pll_info *pll) in get_rtc_pll() argument
72 static inline int set_rtc_pll(struct rtc_pll_info *pll) in set_rtc_pll() argument
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| /linux-4.4.14/drivers/video/fbdev/core/ |
| D | svgalib.c | 381 int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node) in svga_compute_pll() argument
388 ar = pll->r_max; in svga_compute_pll()
398 while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) { in svga_compute_pll()
404 if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max)) in svga_compute_pll()
412 am = pll->m_min; in svga_compute_pll()
413 an = pll->n_min; in svga_compute_pll()
415 while ((am <= pll->m_max) && (an <= pll->n_max)) { in svga_compute_pll()
416 f_current = (pll->f_base * am) / an; in svga_compute_pll()
432 f_current = (pll->f_base * *m) / *n; in svga_compute_pll()
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| /linux-4.4.14/drivers/clk/ingenic/ |
| D | jz4740-cgu.c | 70 .pll = {
281 cppcr &= ~BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit); in jz4740_clock_suspend()
290 cppcr |= BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit); in jz4740_clock_resume()
293 stable = BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.stable_bit); in jz4740_clock_resume()
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| D | jz4780-cgu.c | 249 .pll = DEF_PLL(APLL),
255 .pll = DEF_PLL(MPLL),
261 .pll = DEF_PLL(EPLL),
267 .pll = DEF_PLL(VPLL),
|
| /linux-4.4.14/drivers/video/fbdev/intelfb/ |
| D | intelfbhw.c | 667 struct pll_min_max *pll = &plls[index]; in calc_vclock() local
672 vco = pll->ref_clk * m / n; in calc_vclock()
883 struct pll_min_max *pll = &plls[index]; in splitm() local
886 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) { in splitm()
887 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) { in splitm()
904 struct pll_min_max *pll = &plls[index]; in splitp() local
921 if (p % 4 == 0 && p1 < pll->min_p1) { in splitp()
925 if (p1 < pll->min_p1 || p1 > pll->max_p1 || in splitp()
943 struct pll_min_max *pll = &plls[index]; in calc_pll_params() local
951 div_max = pll->max_vco / clock; in calc_pll_params()
[all …]
|
| /linux-4.4.14/drivers/media/i2c/smiapp/ |
| D | smiapp-core.c | 200 struct smiapp_pll *pll = &sensor->pll; in smiapp_pll_configure() local
204 sensor, SMIAPP_REG_U16_VT_PIX_CLK_DIV, pll->vt.pix_clk_div); in smiapp_pll_configure()
209 sensor, SMIAPP_REG_U16_VT_SYS_CLK_DIV, pll->vt.sys_clk_div); in smiapp_pll_configure()
214 sensor, SMIAPP_REG_U16_PRE_PLL_CLK_DIV, pll->pre_pll_clk_div); in smiapp_pll_configure()
219 sensor, SMIAPP_REG_U16_PLL_MULTIPLIER, pll->pll_multiplier); in smiapp_pll_configure()
226 DIV_ROUND_UP(pll->op.sys_clk_freq_hz, 1000000 / 256 / 256)); in smiapp_pll_configure()
231 sensor, SMIAPP_REG_U16_OP_PIX_CLK_DIV, pll->op.pix_clk_div); in smiapp_pll_configure()
236 sensor, SMIAPP_REG_U16_OP_SYS_CLK_DIV, pll->op.sys_clk_div); in smiapp_pll_configure()
240 struct smiapp_pll *pll) in smiapp_pll_try() argument
275 return smiapp_pll_calculate(&client->dev, &lim, pll); in smiapp_pll_try()
[all …]
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| /linux-4.4.14/drivers/clk/h8300/ |
| D | clk-h8s2678.c | 60 int pll; in pll_set_rate() local
65 pll = ((rate / parent_rate) / 2) & 0x03; in pll_set_rate()
72 val |= pll; in pll_set_rate()
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| /linux-4.4.14/drivers/media/dvb-frontends/ |
| D | dib8000.c | 691 const struct dibx000_bandwidth_config *pll = state->cfg.pll; in dib8000_reset_pll() local
696 (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); in dib8000_reset_pll()
698 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) | in dib8000_reset_pll()
699 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | in dib8000_reset_pll()
700 (1 << 3) | (pll->pll_range << 1) | in dib8000_reset_pll()
701 (pll->pll_reset << 0); in dib8000_reset_pll()
704 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3); in dib8000_reset_pll()
710 if (state->cfg.pll->ADClkSrc == 0) in dib8000_reset_pll()
713 (pll->modulo << 8) | in dib8000_reset_pll()
714 (pll->ADClkSrc << 7) | (0 << 1)); in dib8000_reset_pll()
[all …]
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| D | mb86a20s.c | 1766 u64 pll; in mb86a20s_initfe() local
1813 pll = (((u64)1) << 34) * state->if_freq; in mb86a20s_initfe()
1814 do_div(pll, 63 * fclk); in mb86a20s_initfe()
1815 pll = (1 << 25) - pll; in mb86a20s_initfe()
1819 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); in mb86a20s_initfe()
1822 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); in mb86a20s_initfe()
1825 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); in mb86a20s_initfe()
1829 __func__, fclk, state->if_freq, (long long)pll); in mb86a20s_initfe()
1832 pll = state->if_freq * 1677721600L; in mb86a20s_initfe()
1833 do_div(pll, 1628571429L); in mb86a20s_initfe()
[all …]
|
| D | dib8000.h | 14 struct dibx000_bandwidth_config *pll; member
45 struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio);
|
| D | dib0090.c | 2235 const struct dib0090_pll *pll = state->current_pll_table_index; in dib0090_tune() local
2349 pll = dib0090_pll_table; in dib0090_tune()
2351 pll = dib0090_p1g_pll_table; in dib0090_tune()
2356 while (state->rf_request > pll->max_freq) in dib0090_tune()
2357 pll++; in dib0090_tune()
2360 state->current_pll_table_index = pll; in dib0090_tune()
2364 VCOF_kHz = (pll->hfdiv * state->rf_request) * 2; in dib0090_tune()
2370 FBDiv = (VCOF_kHz / pll->topresc / FREF); in dib0090_tune()
2371 Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF; in dib0090_tune()
2390 if (pll->vco_band) in dib0090_tune()
[all …]
|
| /linux-4.4.14/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_phy_8960.c | 30 struct clk *pll; member
495 phy_8960->pll = devm_clk_register(&hdmi->pdev->dev, &phy_8960->pll_hw); in hdmi_phy_8960_init()
496 if (IS_ERR(phy_8960->pll)) { in hdmi_phy_8960_init()
497 ret = PTR_ERR(phy_8960->pll); in hdmi_phy_8960_init()
498 phy_8960->pll = NULL; in hdmi_phy_8960_init()
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| /linux-4.4.14/drivers/video/fbdev/riva/ |
| D | riva_hw.c | 619 unsigned int M, N, P, pll, MClk; in nv3UpdateArbitrationSettings() local
621 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv3UpdateArbitrationSettings()
622 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv3UpdateArbitrationSettings()
808 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local
810 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv4UpdateArbitrationSettings()
811 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv4UpdateArbitrationSettings()
813 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nv4UpdateArbitrationSettings()
814 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv4UpdateArbitrationSettings()
1071 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv10UpdateArbitrationSettings() local
1073 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv10UpdateArbitrationSettings()
[all …]
|
| /linux-4.4.14/arch/arm/mach-s3c24xx/ |
| D | Makefile | 15 obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
28 obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
29 obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
|
| D | cpufreq-utils.c | 65 clk_set_rate(cfg->mpll, cfg->pll.frequency); in s3c2410_set_fvco()
|
| /linux-4.4.14/drivers/net/wireless/ath/ath9k/ |
| D | ar5008_phy.c | 901 u32 pll; in ar9160_hw_compute_pll_control() local
903 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); in ar9160_hw_compute_pll_control()
906 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
908 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
911 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
913 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
915 return pll; in ar9160_hw_compute_pll_control()
921 u32 pll; in ar5008_hw_compute_pll_control() local
923 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; in ar5008_hw_compute_pll_control()
926 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
[all …]
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| D | ar9002_phy.c | 308 u32 pll; in ar9002_hw_compute_pll_control() local
319 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); in ar9002_hw_compute_pll_control()
320 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); in ar9002_hw_compute_pll_control()
323 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
325 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
327 return pll; in ar9002_hw_compute_pll_control()
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| /linux-4.4.14/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy.c | 348 phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id); in dsi_phy_driver_probe()
349 if (!phy->pll) in dsi_phy_driver_probe()
368 if (phy && phy->pll) { in dsi_phy_driver_remove()
369 msm_dsi_pll_destroy(phy->pll); in dsi_phy_driver_remove()
370 phy->pll = NULL; in dsi_phy_driver_remove()
450 return phy->pll; in msm_dsi_phy_get_pll()
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| /linux-4.4.14/arch/parisc/include/asm/ |
| D | rtc.h | 121 static inline int get_rtc_pll(struct rtc_pll_info *pll) in get_rtc_pll() argument
125 static inline int set_rtc_pll(struct rtc_pll_info *pll) in set_rtc_pll() argument
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| /linux-4.4.14/arch/alpha/include/asm/ |
| D | core_marvel.h | 268 #define IO7_PLL_RNGA(pll) (((pll) >> 3) & 0x7) argument
269 #define IO7_PLL_RNGB(pll) (((pll) >> 6) & 0x7) argument
|
| /linux-4.4.14/Documentation/devicetree/bindings/media/i2c/ |
| D | adv7343.txt | 16 - adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows
39 adi,power-mode-pll-ctrl;
|
| /linux-4.4.14/Documentation/devicetree/bindings/soc/fsl/ |
| D | qman.txt | 145 platform_pll: platform-pll@c00 {
148 compatible = "fsl,qoriq-platform-pll-1.0";
150 clock-output-names = "platform-pll", "platform-pll-div2";
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| /linux-4.4.14/drivers/video/fbdev/ |
| D | w100fb.c | 1067 static int w100_pll_adjust(struct w100_pll_info *pll) in w100_pll_adjust() argument
1091 if (tf80 >= (pll->tfgoal)) { in w100_pll_adjust()
1097 if (tf20 <= (pll->tfgoal)) in w100_pll_adjust()
1125 static int w100_pll_calibration(struct w100_pll_info *pll) in w100_pll_calibration() argument
1129 status = w100_pll_adjust(pll); in w100_pll_calibration()
1154 static int w100_pll_set_clk(struct w100_pll_info *pll) in w100_pll_set_clk() argument
1169 w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = pll->M; in w100_pll_set_clk()
1170 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = pll->N_int; in w100_pll_set_clk()
1171 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = pll->N_fac; in w100_pll_set_clk()
1172 w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = pll->lock_time; in w100_pll_set_clk()
[all …]
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| /linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/ |
| D | config_defs.h | 92 unsigned int pll : 1; member
100 unsigned int pll : 1; member
|
| /linux-4.4.14/drivers/gpu/drm/msm/ |
| D | Makefile | 67 msm-y += dsi/pll/dsi_pll.o
68 msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o
|
| /linux-4.4.14/arch/cris/include/arch-v32/mach-fs/mach/hwregs/ |
| D | config_defs.h | 92 unsigned int pll : 1; member
100 unsigned int pll : 1; member
|
| /linux-4.4.14/Documentation/video4linux/bttv/ |
| D | README.WINVIEW | 26 To use the driver I use the following options, the tuner and pll settings might
32 insmod bttv pll=1 radio=1 card=17
|
| /linux-4.4.14/drivers/bcma/ |
| D | driver_chipcommon_pmu.c | 447 u32 pll; in bcma_pmu_get_cpu_clock() local
454 pll = BCMA_CC_PMU5356_MAINPLL_PLL0; in bcma_pmu_get_cpu_clock()
458 pll = BCMA_CC_PMU5357_MAINPLL_PLL0; in bcma_pmu_get_cpu_clock()
461 pll = BCMA_CC_PMU4716_MAINPLL_PLL0; in bcma_pmu_get_cpu_clock()
465 return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU); in bcma_pmu_get_cpu_clock()
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| /linux-4.4.14/drivers/mfd/ |
| D | twl6040.c | 319 twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL; in twl6040_power()
373 if (pll_id != twl6040->pll) { in twl6040_set_pll()
402 if (twl6040->pll == pll_id) in twl6040_set_pll()
490 twl6040->pll = pll_id; in twl6040_set_pll()
501 return twl6040->pll; in twl6040_get_pll()
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| /linux-4.4.14/arch/m68k/coldfire/ |
| D | m5407.c | 23 DEFINE_CLK(pll, "pll.0", MCF_CLK);
|
| D | m5206.c | 23 DEFINE_CLK(pll, "pll.0", MCF_CLK);
|
| /linux-4.4.14/include/asm-generic/ |
| D | rtc.h | 238 static inline int get_rtc_pll(struct rtc_pll_info *pll) in get_rtc_pll() argument
242 static inline int set_rtc_pll(struct rtc_pll_info *pll) in set_rtc_pll() argument
|