1/*
2 * PLL clock driver for Keystone devices
3 *
4 * Copyright (C) 2013 Texas Instruments Inc.
5 *	Murali Karicheri <m-karicheri2@ti.com>
6 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13#include <linux/clk-provider.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <linux/of_address.h>
18#include <linux/of.h>
19#include <linux/module.h>
20
21#define PLLM_LOW_MASK		0x3f
22#define PLLM_HIGH_MASK		0x7ffc0
23#define MAIN_PLLM_HIGH_MASK	0x7f000
24#define PLLM_HIGH_SHIFT		6
25#define PLLD_MASK		0x3f
26#define CLKOD_MASK		0x780000
27#define CLKOD_SHIFT		19
28
29/**
30 * struct clk_pll_data - pll data structure
31 * @has_pllctrl: If set to non zero, lower 6 bits of multiplier is in pllm
32 *	register of pll controller, else it is in the pll_ctrl0((bit 11-6)
33 * @phy_pllm: Physical address of PLLM in pll controller. Used when
34 *	has_pllctrl is non zero.
35 * @phy_pll_ctl0: Physical address of PLL ctrl0. This could be that of
36 *	Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
37 *	or PA PLL available on keystone2. These PLLs are controlled by
38 *	this register. Main PLL is controlled by a PLL controller.
39 * @pllm: PLL register map address for multiplier bits
40 * @pllod: PLL register map address for post divider bits
41 * @pll_ctl0: PLL controller map address
42 * @pllm_lower_mask: multiplier lower mask
43 * @pllm_upper_mask: multiplier upper mask
44 * @pllm_upper_shift: multiplier upper shift
45 * @plld_mask: divider mask
46 * @clkod_mask: output divider mask
47 * @clkod_shift: output divider shift
48 * @plld_mask: divider mask
49 * @postdiv: Fixed post divider
50 */
51struct clk_pll_data {
52	bool has_pllctrl;
53	u32 phy_pllm;
54	u32 phy_pll_ctl0;
55	void __iomem *pllm;
56	void __iomem *pllod;
57	void __iomem *pll_ctl0;
58	u32 pllm_lower_mask;
59	u32 pllm_upper_mask;
60	u32 pllm_upper_shift;
61	u32 plld_mask;
62	u32 clkod_mask;
63	u32 clkod_shift;
64	u32 postdiv;
65};
66
67/**
68 * struct clk_pll - Main pll clock
69 * @hw: clk_hw for the pll
70 * @pll_data: PLL driver specific data
71 */
72struct clk_pll {
73	struct clk_hw hw;
74	struct clk_pll_data *pll_data;
75};
76
77#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
78
79static unsigned long clk_pllclk_recalc(struct clk_hw *hw,
80					unsigned long parent_rate)
81{
82	struct clk_pll *pll = to_clk_pll(hw);
83	struct clk_pll_data *pll_data = pll->pll_data;
84	unsigned long rate = parent_rate;
85	u32  mult = 0, prediv, postdiv, val;
86
87	/*
88	 * get bits 0-5 of multiplier from pllctrl PLLM register
89	 * if has_pllctrl is non zero
90	 */
91	if (pll_data->has_pllctrl) {
92		val = readl(pll_data->pllm);
93		mult = (val & pll_data->pllm_lower_mask);
94	}
95
96	/* bit6-12 of PLLM is in Main PLL control register */
97	val = readl(pll_data->pll_ctl0);
98	mult |= ((val & pll_data->pllm_upper_mask)
99			>> pll_data->pllm_upper_shift);
100	prediv = (val & pll_data->plld_mask);
101
102	if (!pll_data->has_pllctrl)
103		/* read post divider from od bits*/
104		postdiv = ((val & pll_data->clkod_mask) >>
105				 pll_data->clkod_shift) + 1;
106	else if (pll_data->pllod) {
107		postdiv = readl(pll_data->pllod);
108		postdiv = ((postdiv & pll_data->clkod_mask) >>
109				pll_data->clkod_shift) + 1;
110	} else
111		postdiv = pll_data->postdiv;
112
113	rate /= (prediv + 1);
114	rate = (rate * (mult + 1));
115	rate /= postdiv;
116
117	return rate;
118}
119
120static const struct clk_ops clk_pll_ops = {
121	.recalc_rate = clk_pllclk_recalc,
122};
123
124static struct clk *clk_register_pll(struct device *dev,
125			const char *name,
126			const char *parent_name,
127			struct clk_pll_data *pll_data)
128{
129	struct clk_init_data init;
130	struct clk_pll *pll;
131	struct clk *clk;
132
133	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
134	if (!pll)
135		return ERR_PTR(-ENOMEM);
136
137	init.name = name;
138	init.ops = &clk_pll_ops;
139	init.flags = 0;
140	init.parent_names = (parent_name ? &parent_name : NULL);
141	init.num_parents = (parent_name ? 1 : 0);
142
143	pll->pll_data	= pll_data;
144	pll->hw.init = &init;
145
146	clk = clk_register(NULL, &pll->hw);
147	if (IS_ERR(clk))
148		goto out;
149
150	return clk;
151out:
152	kfree(pll);
153	return NULL;
154}
155
156/**
157 * _of_clk_init - PLL initialisation via DT
158 * @node: device tree node for this clock
159 * @pllctrl: If true, lower 6 bits of multiplier is in pllm register of
160 *		pll controller, else it is in the control register0(bit 11-6)
161 */
162static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
163{
164	struct clk_pll_data *pll_data;
165	const char *parent_name;
166	struct clk *clk;
167	int i;
168
169	pll_data = kzalloc(sizeof(*pll_data), GFP_KERNEL);
170	if (!pll_data) {
171		pr_err("%s: Out of memory\n", __func__);
172		return;
173	}
174
175	parent_name = of_clk_get_parent_name(node, 0);
176	if (of_property_read_u32(node, "fixed-postdiv",	&pll_data->postdiv)) {
177		/* assume the PLL has output divider register bits */
178		pll_data->clkod_mask = CLKOD_MASK;
179		pll_data->clkod_shift = CLKOD_SHIFT;
180
181		/*
182		 * Check if there is an post-divider register. If not
183		 * assume od bits are part of control register.
184		 */
185		i = of_property_match_string(node, "reg-names",
186					     "post-divider");
187		pll_data->pllod = of_iomap(node, i);
188	}
189
190	i = of_property_match_string(node, "reg-names", "control");
191	pll_data->pll_ctl0 = of_iomap(node, i);
192	if (!pll_data->pll_ctl0) {
193		pr_err("%s: ioremap failed\n", __func__);
194		iounmap(pll_data->pllod);
195		goto out;
196	}
197
198	pll_data->pllm_lower_mask = PLLM_LOW_MASK;
199	pll_data->pllm_upper_shift = PLLM_HIGH_SHIFT;
200	pll_data->plld_mask = PLLD_MASK;
201	pll_data->has_pllctrl = pllctrl;
202	if (!pll_data->has_pllctrl) {
203		pll_data->pllm_upper_mask = PLLM_HIGH_MASK;
204	} else {
205		pll_data->pllm_upper_mask = MAIN_PLLM_HIGH_MASK;
206		i = of_property_match_string(node, "reg-names", "multiplier");
207		pll_data->pllm = of_iomap(node, i);
208		if (!pll_data->pllm) {
209			iounmap(pll_data->pll_ctl0);
210			iounmap(pll_data->pllod);
211			goto out;
212		}
213	}
214
215	clk = clk_register_pll(NULL, node->name, parent_name, pll_data);
216	if (clk) {
217		of_clk_add_provider(node, of_clk_src_simple_get, clk);
218		return;
219	}
220
221out:
222	pr_err("%s: error initializing pll %s\n", __func__, node->name);
223	kfree(pll_data);
224}
225
226/**
227 * of_keystone_pll_clk_init - PLL initialisation DT wrapper
228 * @node: device tree node for this clock
229 */
230static void __init of_keystone_pll_clk_init(struct device_node *node)
231{
232	_of_pll_clk_init(node, false);
233}
234CLK_OF_DECLARE(keystone_pll_clock, "ti,keystone,pll-clock",
235					of_keystone_pll_clk_init);
236
237/**
238 * of_keystone_pll_main_clk_init - Main PLL initialisation DT wrapper
239 * @node: device tree node for this clock
240 */
241static void __init of_keystone_main_pll_clk_init(struct device_node *node)
242{
243	_of_pll_clk_init(node, true);
244}
245CLK_OF_DECLARE(keystone_main_pll_clock, "ti,keystone,main-pll-clock",
246						of_keystone_main_pll_clk_init);
247
248/**
249 * of_pll_div_clk_init - PLL divider setup function
250 * @node: device tree node for this clock
251 */
252static void __init of_pll_div_clk_init(struct device_node *node)
253{
254	const char *parent_name;
255	void __iomem *reg;
256	u32 shift, mask;
257	struct clk *clk;
258	const char *clk_name = node->name;
259
260	of_property_read_string(node, "clock-output-names", &clk_name);
261	reg = of_iomap(node, 0);
262	if (!reg) {
263		pr_err("%s: ioremap failed\n", __func__);
264		return;
265	}
266
267	parent_name = of_clk_get_parent_name(node, 0);
268	if (!parent_name) {
269		pr_err("%s: missing parent clock\n", __func__);
270		return;
271	}
272
273	if (of_property_read_u32(node, "bit-shift", &shift)) {
274		pr_err("%s: missing 'shift' property\n", __func__);
275		return;
276	}
277
278	if (of_property_read_u32(node, "bit-mask", &mask)) {
279		pr_err("%s: missing 'bit-mask' property\n", __func__);
280		return;
281	}
282
283	clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift,
284				 mask, 0, NULL);
285	if (clk)
286		of_clk_add_provider(node, of_clk_src_simple_get, clk);
287	else
288		pr_err("%s: error registering divider %s\n", __func__, clk_name);
289}
290CLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init);
291
292/**
293 * of_pll_mux_clk_init - PLL mux setup function
294 * @node: device tree node for this clock
295 */
296static void __init of_pll_mux_clk_init(struct device_node *node)
297{
298	void __iomem *reg;
299	u32 shift, mask;
300	struct clk *clk;
301	const char *parents[2];
302	const char *clk_name = node->name;
303
304	of_property_read_string(node, "clock-output-names", &clk_name);
305	reg = of_iomap(node, 0);
306	if (!reg) {
307		pr_err("%s: ioremap failed\n", __func__);
308		return;
309	}
310
311	of_clk_parent_fill(node, parents, 2);
312	if (!parents[0] || !parents[1]) {
313		pr_err("%s: missing parent clocks\n", __func__);
314		return;
315	}
316
317	if (of_property_read_u32(node, "bit-shift", &shift)) {
318		pr_err("%s: missing 'shift' property\n", __func__);
319		return;
320	}
321
322	if (of_property_read_u32(node, "bit-mask", &mask)) {
323		pr_err("%s: missing 'bit-mask' property\n", __func__);
324		return;
325	}
326
327	clk = clk_register_mux(NULL, clk_name, (const char **)&parents,
328				ARRAY_SIZE(parents) , 0, reg, shift, mask,
329				0, NULL);
330	if (clk)
331		of_clk_add_provider(node, of_clk_src_simple_get, clk);
332	else
333		pr_err("%s: error registering mux %s\n", __func__, clk_name);
334}
335CLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init);
336