1* Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
2
3UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
4Each UFS PHY node should have its own node.
5
6To bind UFS PHY with UFS host controller, the controller node should
7contain a phandle reference to UFS PHY node.
8
9Required properties:
10- compatible        : compatible list, contains "qcom,ufs-phy-qmp-20nm"
11		      or "qcom,ufs-phy-qmp-14nm" according to the relevant phy in use.
12- reg               : should contain PHY register address space (mandatory),
13- reg-names         : indicates various resources passed to driver (via reg proptery) by name.
14                      Required "reg-names" is "phy_mem".
15- #phy-cells        : This property shall be set to 0
16- vdda-phy-supply   : phandle to main PHY supply for analog domain
17- vdda-pll-supply   : phandle to PHY PLL and Power-Gen block power supply
18- clocks	    : List of phandle and clock specifier pairs
19- clock-names       : List of clock input name strings sorted in the same
20		      order as the clocks property. "ref_clk_src", "ref_clk",
21		      "tx_iface_clk" & "rx_iface_clk" are mandatory but
22		      "ref_clk_parent" is optional
23
24Optional properties:
25- vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply
26- vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
27- vddp-ref-clk-supply   : phandle to UFS device ref_clk pad power supply
28- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
29- vddp-ref-clk-always-on : specifies if this supply needs to be kept always on
30
31Example:
32
33	ufsphy1: ufsphy@0xfc597000 {
34		compatible = "qcom,ufs-phy-qmp-20nm";
35		reg = <0xfc597000 0x800>;
36		reg-names = "phy_mem";
37		#phy-cells = <0>;
38		vdda-phy-supply = <&pma8084_l4>;
39		vdda-pll-supply = <&pma8084_l12>;
40		vdda-phy-max-microamp = <50000>;
41		vdda-pll-max-microamp = <1000>;
42		clock-names = "ref_clk_src",
43			"ref_clk_parent",
44			"ref_clk",
45			"tx_iface_clk",
46			"rx_iface_clk";
47		clocks = <&clock_rpm clk_ln_bb_clk>,
48			<&clock_gcc clk_pcie_1_phy_ldo >,
49			<&clock_gcc clk_ufs_phy_ldo>,
50			<&clock_gcc clk_gcc_ufs_tx_cfg_clk>,
51			<&clock_gcc clk_gcc_ufs_rx_cfg_clk>;
52	};
53
54	ufshc@0xfc598000 {
55		...
56		phys = <&ufsphy1>;
57		phy-names = "ufsphy";
58	};
59