Searched refs:pin (Results 1 - 200 of 1886) sorted by relevance

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/linux-4.4.14/arch/mips/include/asm/mach-pnx833x/
H A Dgpio.h55 /* Select GPIO direction for a pin */ pnx833x_gpio_select_input()
56 static inline void pnx833x_gpio_select_input(unsigned int pin) pnx833x_gpio_select_input() argument
58 if (pin < 32) pnx833x_gpio_select_input()
59 CLEAR_REG_BIT(PNX833X_PIO_DIR, pin); pnx833x_gpio_select_input()
61 CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31); pnx833x_gpio_select_input()
63 static inline void pnx833x_gpio_select_output(unsigned int pin) pnx833x_gpio_select_output() argument
65 if (pin < 32) pnx833x_gpio_select_output()
66 SET_REG_BIT(PNX833X_PIO_DIR, pin); pnx833x_gpio_select_output()
68 SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31); pnx833x_gpio_select_output()
71 /* Select GPIO or alternate function for a pin */ pnx833x_gpio_select_function_io()
72 static inline void pnx833x_gpio_select_function_io(unsigned int pin) pnx833x_gpio_select_function_io() argument
74 if (pin < 32) pnx833x_gpio_select_function_io()
75 CLEAR_REG_BIT(PNX833X_PIO_SEL, pin); pnx833x_gpio_select_function_io()
77 CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31); pnx833x_gpio_select_function_io()
79 static inline void pnx833x_gpio_select_function_alt(unsigned int pin) pnx833x_gpio_select_function_alt() argument
81 if (pin < 32) pnx833x_gpio_select_function_alt()
82 SET_REG_BIT(PNX833X_PIO_SEL, pin); pnx833x_gpio_select_function_alt()
84 SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31); pnx833x_gpio_select_function_alt()
87 /* Read GPIO pin */ pnx833x_gpio_read()
88 static inline int pnx833x_gpio_read(unsigned int pin) pnx833x_gpio_read() argument
90 if (pin < 32) pnx833x_gpio_read()
91 return (PNX833X_PIO_IN >> pin) & 1; pnx833x_gpio_read()
93 return (PNX833X_PIO_IN2 >> (pin & 31)) & 1; pnx833x_gpio_read()
96 /* Write GPIO pin */ pnx833x_gpio_write()
97 static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin) pnx833x_gpio_write() argument
99 if (pin < 32) { pnx833x_gpio_write()
101 SET_REG_BIT(PNX833X_PIO_OUT, pin); pnx833x_gpio_write()
103 CLEAR_REG_BIT(PNX833X_PIO_OUT, pin); pnx833x_gpio_write()
106 SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31); pnx833x_gpio_write()
108 CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31); pnx833x_gpio_write()
119 static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin) pnx833x_gpio_setup_irq() argument
123 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); pnx833x_gpio_setup_irq()
124 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); pnx833x_gpio_setup_irq()
125 SET_REG_BIT(PNX833X_PIO_INT_LO, pin); pnx833x_gpio_setup_irq()
128 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); pnx833x_gpio_setup_irq()
129 SET_REG_BIT(PNX833X_PIO_INT_HI, pin); pnx833x_gpio_setup_irq()
130 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); pnx833x_gpio_setup_irq()
133 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); pnx833x_gpio_setup_irq()
134 SET_REG_BIT(PNX833X_PIO_INT_HI, pin); pnx833x_gpio_setup_irq()
135 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); pnx833x_gpio_setup_irq()
138 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); pnx833x_gpio_setup_irq()
139 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); pnx833x_gpio_setup_irq()
140 SET_REG_BIT(PNX833X_PIO_INT_LO, pin); pnx833x_gpio_setup_irq()
143 SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin); pnx833x_gpio_setup_irq()
144 SET_REG_BIT(PNX833X_PIO_INT_HI, pin); pnx833x_gpio_setup_irq()
145 SET_REG_BIT(PNX833X_PIO_INT_LO, pin); pnx833x_gpio_setup_irq()
148 CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin); pnx833x_gpio_setup_irq()
149 CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin); pnx833x_gpio_setup_irq()
150 CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin); pnx833x_gpio_setup_irq()
156 static inline void pnx833x_gpio_enable_irq(unsigned int pin) pnx833x_gpio_enable_irq() argument
158 SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); pnx833x_gpio_enable_irq()
160 static inline void pnx833x_gpio_disable_irq(unsigned int pin) pnx833x_gpio_disable_irq() argument
162 CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin); pnx833x_gpio_disable_irq()
166 static inline void pnx833x_gpio_clear_irq(unsigned int pin) pnx833x_gpio_clear_irq() argument
168 SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); pnx833x_gpio_clear_irq()
169 CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin); pnx833x_gpio_clear_irq()
/linux-4.4.14/arch/arm/mach-orion5x/
H A Dboard-rd88f5182.c42 int pin; rd88f5182_pci_preinit() local
47 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; rd88f5182_pci_preinit()
48 if (gpio_request(pin, "PCI IntA") == 0) { rd88f5182_pci_preinit()
49 if (gpio_direction_input(pin) == 0) { rd88f5182_pci_preinit()
50 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); rd88f5182_pci_preinit()
53 "set_irq_type pin %d\n", pin); rd88f5182_pci_preinit()
54 gpio_free(pin); rd88f5182_pci_preinit()
57 printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); rd88f5182_pci_preinit()
60 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; rd88f5182_pci_preinit()
61 if (gpio_request(pin, "PCI IntB") == 0) { rd88f5182_pci_preinit()
62 if (gpio_direction_input(pin) == 0) { rd88f5182_pci_preinit()
63 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); rd88f5182_pci_preinit()
66 "set_irq_type pin %d\n", pin); rd88f5182_pci_preinit()
67 gpio_free(pin); rd88f5182_pci_preinit()
70 printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin); rd88f5182_pci_preinit()
75 u8 pin) rd88f5182_pci_map_irq()
82 irq = orion5x_pci_map_irq(dev, slot, pin); rd88f5182_pci_map_irq()
91 if (pin == 1) rd88f5182_pci_map_irq()
74 rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) rd88f5182_pci_map_irq() argument
H A Drd88f5182-setup.c113 int pin; rd88f5182_pci_preinit() local
118 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; rd88f5182_pci_preinit()
119 if (gpio_request(pin, "PCI IntA") == 0) { rd88f5182_pci_preinit()
120 if (gpio_direction_input(pin) == 0) { rd88f5182_pci_preinit()
121 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); rd88f5182_pci_preinit()
124 "set_irq_type pin %d\n", pin); rd88f5182_pci_preinit()
125 gpio_free(pin); rd88f5182_pci_preinit()
128 printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); rd88f5182_pci_preinit()
131 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; rd88f5182_pci_preinit()
132 if (gpio_request(pin, "PCI IntB") == 0) { rd88f5182_pci_preinit()
133 if (gpio_direction_input(pin) == 0) { rd88f5182_pci_preinit()
134 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); rd88f5182_pci_preinit()
137 "set_irq_type pin %d\n", pin); rd88f5182_pci_preinit()
138 gpio_free(pin); rd88f5182_pci_preinit()
141 printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin); rd88f5182_pci_preinit()
146 u8 pin) rd88f5182_pci_map_irq()
153 irq = orion5x_pci_map_irq(dev, slot, pin); rd88f5182_pci_map_irq()
162 if (pin == 1) rd88f5182_pci_map_irq()
145 rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) rd88f5182_pci_map_irq() argument
H A Ddb88f5281-setup.c207 int pin; db88f5281_pci_preinit() local
212 pin = DB88F5281_PCI_SLOT0_IRQ_PIN; db88f5281_pci_preinit()
213 if (gpio_request(pin, "PCI Int1") == 0) { db88f5281_pci_preinit()
214 if (gpio_direction_input(pin) == 0) { db88f5281_pci_preinit()
215 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); db88f5281_pci_preinit()
218 "set_irq_type pin %d\n", pin); db88f5281_pci_preinit()
219 gpio_free(pin); db88f5281_pci_preinit()
222 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); db88f5281_pci_preinit()
225 pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; db88f5281_pci_preinit()
226 if (gpio_request(pin, "PCI Int2") == 0) { db88f5281_pci_preinit()
227 if (gpio_direction_input(pin) == 0) { db88f5281_pci_preinit()
228 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); db88f5281_pci_preinit()
231 "to set_irq_type pin %d\n", pin); db88f5281_pci_preinit()
232 gpio_free(pin); db88f5281_pci_preinit()
235 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); db88f5281_pci_preinit()
240 u8 pin) db88f5281_pci_map_irq()
247 irq = orion5x_pci_map_irq(dev, slot, pin); db88f5281_pci_map_irq()
239 db88f5281_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) db88f5281_pci_map_irq() argument
H A Dts209-setup.c111 int pin; qnap_ts209_pci_preinit() local
116 pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; qnap_ts209_pci_preinit()
117 if (gpio_request(pin, "PCI Int1") == 0) { qnap_ts209_pci_preinit()
118 if (gpio_direction_input(pin) == 0) { qnap_ts209_pci_preinit()
119 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); qnap_ts209_pci_preinit()
122 "set_irq_type pin %d\n", pin); qnap_ts209_pci_preinit()
123 gpio_free(pin); qnap_ts209_pci_preinit()
127 "%d\n", pin); qnap_ts209_pci_preinit()
130 pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; qnap_ts209_pci_preinit()
131 if (gpio_request(pin, "PCI Int2") == 0) { qnap_ts209_pci_preinit()
132 if (gpio_direction_input(pin) == 0) { qnap_ts209_pci_preinit()
133 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); qnap_ts209_pci_preinit()
136 "to set_irq_type pin %d\n", pin); qnap_ts209_pci_preinit()
137 gpio_free(pin); qnap_ts209_pci_preinit()
141 "%d\n", pin); qnap_ts209_pci_preinit()
146 u8 pin) qnap_ts209_pci_map_irq()
153 irq = orion5x_pci_map_irq(dev, slot, pin); qnap_ts209_pci_map_irq()
145 qnap_ts209_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) qnap_ts209_pci_map_irq() argument
H A Dterastation_pro2-setup.c82 int pin; tsp2_pci_preinit() local
87 pin = TSP2_PCI_SLOT0_IRQ_PIN; tsp2_pci_preinit()
88 if (gpio_request(pin, "PCI Int1") == 0) { tsp2_pci_preinit()
89 if (gpio_direction_input(pin) == 0) { tsp2_pci_preinit()
90 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); tsp2_pci_preinit()
93 "to set_irq_type pin %d\n", pin); tsp2_pci_preinit()
94 gpio_free(pin); tsp2_pci_preinit()
98 "gpio_request %d\n", pin); tsp2_pci_preinit()
102 static int __init tsp2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) tsp2_pci_map_irq() argument
109 irq = orion5x_pci_map_irq(dev, slot, pin); tsp2_pci_map_irq()
/linux-4.4.14/include/linux/input/
H A Dcy8ctmg110_pdata.h6 int reset_pin; /* Reset pin is wired to this GPIO (optional) */
7 int irq_pin; /* IRQ pin is wired to this GPIO */
H A Dbu21013.h14 * @cs_pin: chip select pin
15 * @touch_pin: touch gpio pin
H A Dgp2ap002a00f.h10 * @vout_gpio: The gpio connected to the object detected pin (VOUT)
/linux-4.4.14/sound/pci/ice1712/
H A Dprodigy192.h12 #define VT1724_PRODIGY192_CS (1 << 8) /* GPIO8, pin 75 */
13 #define VT1724_PRODIGY192_CCLK (1 << 9) /* GPIO9, pin 76 */
14 #define VT1724_PRODIGY192_CDOUT (1 << 10) /* GPIO10, pin 77 */
15 #define VT1724_PRODIGY192_CDIN (1 << 11) /* GPIO11, pin 86 */
/linux-4.4.14/drivers/pinctrl/qcom/
H A Dpinctrl-ssbi-mpp.c95 * struct pm8xxx_pin_data - dynamic configuration for a pin
98 * @mode: operating mode for the pin (digital, analog or current sink)
99 * @input: pin is input
100 * @output: pin is output
101 * @high_z: pin is floating
172 struct pm8xxx_pin_data *pin) pm8xxx_mpp_update()
180 switch (pin->mode) { pm8xxx_mpp_update()
182 if (pin->dtest) { pm8xxx_mpp_update()
184 ctrl = pin->dtest - 1; pm8xxx_mpp_update()
185 } else if (pin->input && pin->output) { pm8xxx_mpp_update()
187 if (pin->high_z) pm8xxx_mpp_update()
189 else if (pin->pullup == 600) pm8xxx_mpp_update()
191 else if (pin->pullup == 10000) pm8xxx_mpp_update()
195 } else if (pin->input) { pm8xxx_mpp_update()
197 if (pin->dtest) pm8xxx_mpp_update()
198 ctrl = pin->dtest; pm8xxx_mpp_update()
203 ctrl = !!pin->output_value; pm8xxx_mpp_update()
204 if (pin->paired) pm8xxx_mpp_update()
208 level = pin->power_source; pm8xxx_mpp_update()
211 if (pin->output) { pm8xxx_mpp_update()
213 level = pin->aout_level; pm8xxx_mpp_update()
214 ctrl = pin->output_value; pm8xxx_mpp_update()
215 if (pin->paired) pm8xxx_mpp_update()
219 level = pin->amux; pm8xxx_mpp_update()
224 level = (pin->drive_strength / 5) - 1; pm8xxx_mpp_update()
225 if (pin->dtest) { pm8xxx_mpp_update()
227 ctrl = pin->dtest - 1; pm8xxx_mpp_update()
230 ctrl = pin->output_value; pm8xxx_mpp_update()
231 if (pin->paired) pm8xxx_mpp_update()
240 ret = regmap_write(pctrl->regmap, pin->reg, val); pm8xxx_mpp_update()
310 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; pm8xxx_pinmux_set_mux() local
312 pin->mode = function; pm8xxx_pinmux_set_mux()
313 pm8xxx_mpp_update(pctrl, pin); pm8xxx_pinmux_set_mux()
330 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_pin_config_get() local
336 arg = pin->pullup; pm8xxx_pin_config_get()
339 arg = pin->high_z; pm8xxx_pin_config_get()
342 arg = pin->input; pm8xxx_pin_config_get()
345 arg = pin->output_value; pm8xxx_pin_config_get()
348 arg = pin->power_source; pm8xxx_pin_config_get()
351 arg = pin->drive_strength; pm8xxx_pin_config_get()
354 arg = pin->dtest; pm8xxx_pin_config_get()
357 arg = pin->amux; pm8xxx_pin_config_get()
360 arg = pin->aout_level; pm8xxx_pin_config_get()
363 arg = pin->paired; pm8xxx_pin_config_get()
380 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_pin_config_set() local
391 pin->pullup = arg; pm8xxx_pin_config_set()
394 pin->high_z = true; pm8xxx_pin_config_set()
397 pin->input = true; pm8xxx_pin_config_set()
400 pin->output = true; pm8xxx_pin_config_set()
401 pin->output_value = !!arg; pm8xxx_pin_config_set()
404 pin->power_source = arg; pm8xxx_pin_config_set()
407 pin->drive_strength = arg; pm8xxx_pin_config_set()
410 pin->dtest = arg; pm8xxx_pin_config_set()
413 pin->amux = arg; pm8xxx_pin_config_set()
416 pin->aout_level = arg; pm8xxx_pin_config_set()
419 pin->paired = !!arg; pm8xxx_pin_config_set()
429 pm8xxx_mpp_update(pctrl, pin); pm8xxx_pin_config_set()
452 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_mpp_direction_input() local
454 switch (pin->mode) { pm8xxx_mpp_direction_input()
456 pin->input = true; pm8xxx_mpp_direction_input()
459 pin->input = true; pm8xxx_mpp_direction_input()
460 pin->output = true; pm8xxx_mpp_direction_input()
466 pm8xxx_mpp_update(pctrl, pin); pm8xxx_mpp_direction_input()
476 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_mpp_direction_output() local
478 switch (pin->mode) { pm8xxx_mpp_direction_output()
480 pin->output = true; pm8xxx_mpp_direction_output()
483 pin->input = false; pm8xxx_mpp_direction_output()
484 pin->output = true; pm8xxx_mpp_direction_output()
487 pin->input = false; pm8xxx_mpp_direction_output()
488 pin->output = true; pm8xxx_mpp_direction_output()
492 pm8xxx_mpp_update(pctrl, pin); pm8xxx_mpp_direction_output()
500 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_mpp_get() local
504 if (!pin->input) pm8xxx_mpp_get()
505 return pin->output_value; pm8xxx_mpp_get()
507 ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state); pm8xxx_mpp_get()
517 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_mpp_set() local
519 pin->output_value = !!value; pm8xxx_mpp_set()
521 pm8xxx_mpp_update(pctrl, pin); pm8xxx_mpp_set()
541 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_mpp_to_irq() local
543 return pin->irq; pm8xxx_mpp_to_irq()
556 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_mpp_dbg_show_one() local
570 switch (pin->mode) { pm8xxx_mpp_dbg_show_one()
573 if (pin->dtest) { pm8xxx_mpp_dbg_show_one()
574 seq_printf(s, "dtest%d\n", pin->dtest); pm8xxx_mpp_dbg_show_one()
575 } else if (pin->input && pin->output) { pm8xxx_mpp_dbg_show_one()
576 if (pin->high_z) pm8xxx_mpp_dbg_show_one()
579 seq_printf(s, "bi-dir %dOhm", pin->pullup); pm8xxx_mpp_dbg_show_one()
580 } else if (pin->input) { pm8xxx_mpp_dbg_show_one()
581 if (pin->dtest) pm8xxx_mpp_dbg_show_one()
582 seq_printf(s, "in dtest%d", pin->dtest); pm8xxx_mpp_dbg_show_one()
585 } else if (pin->output) { pm8xxx_mpp_dbg_show_one()
588 if (!pin->paired) { pm8xxx_mpp_dbg_show_one()
589 seq_puts(s, pin->output_value ? pm8xxx_mpp_dbg_show_one()
592 seq_puts(s, pin->output_value ? pm8xxx_mpp_dbg_show_one()
599 if (pin->output) { pm8xxx_mpp_dbg_show_one()
600 seq_printf(s, "out %s ", aout_lvls[pin->aout_level]); pm8xxx_mpp_dbg_show_one()
601 if (!pin->paired) { pm8xxx_mpp_dbg_show_one()
602 seq_puts(s, pin->output_value ? pm8xxx_mpp_dbg_show_one()
605 seq_puts(s, pin->output_value ? pm8xxx_mpp_dbg_show_one()
609 seq_printf(s, "input mux %s", amuxs[pin->amux]); pm8xxx_mpp_dbg_show_one()
613 seq_printf(s, " sink %dmA ", pin->drive_strength); pm8xxx_mpp_dbg_show_one()
614 if (pin->dtest) { pm8xxx_mpp_dbg_show_one()
615 seq_printf(s, "dtest%d", pin->dtest); pm8xxx_mpp_dbg_show_one()
617 if (!pin->paired) { pm8xxx_mpp_dbg_show_one()
618 seq_puts(s, pin->output_value ? pm8xxx_mpp_dbg_show_one()
621 seq_puts(s, pin->output_value ? pm8xxx_mpp_dbg_show_one()
657 struct pm8xxx_pin_data *pin) pm8xxx_pin_populate()
665 ret = regmap_read(pctrl->regmap, pin->reg, &val); pm8xxx_pin_populate()
677 pin->mode = PM8XXX_MPP_DIGITAL; pm8xxx_pin_populate()
678 pin->input = true; pm8xxx_pin_populate()
679 pin->power_source = level; pm8xxx_pin_populate()
680 pin->dtest = ctrl; pm8xxx_pin_populate()
683 pin->mode = PM8XXX_MPP_DIGITAL; pm8xxx_pin_populate()
684 pin->output = true; pm8xxx_pin_populate()
685 pin->power_source = level; pm8xxx_pin_populate()
686 pin->output_value = !!(ctrl & BIT(0)); pm8xxx_pin_populate()
687 pin->paired = !!(ctrl & BIT(1)); pm8xxx_pin_populate()
690 pin->mode = PM8XXX_MPP_DIGITAL; pm8xxx_pin_populate()
691 pin->input = true; pm8xxx_pin_populate()
692 pin->output = true; pm8xxx_pin_populate()
693 pin->power_source = level; pm8xxx_pin_populate()
696 pin->pullup = 600; pm8xxx_pin_populate()
699 pin->high_z = true; pm8xxx_pin_populate()
702 pin->pullup = 10000; pm8xxx_pin_populate()
705 pin->pullup = 30000; pm8xxx_pin_populate()
710 pin->mode = PM8XXX_MPP_ANALOG; pm8xxx_pin_populate()
711 pin->input = true; pm8xxx_pin_populate()
712 pin->amux = level; pm8xxx_pin_populate()
715 pin->mode = PM8XXX_MPP_ANALOG; pm8xxx_pin_populate()
716 pin->output = true; pm8xxx_pin_populate()
717 pin->aout_level = level; pm8xxx_pin_populate()
718 pin->output_value = !!(ctrl & BIT(0)); pm8xxx_pin_populate()
719 pin->paired = !!(ctrl & BIT(1)); pm8xxx_pin_populate()
722 pin->mode = PM8XXX_MPP_SINK; pm8xxx_pin_populate()
723 pin->drive_strength = 5 * (level + 1); pm8xxx_pin_populate()
724 pin->output_value = !!(ctrl & BIT(0)); pm8xxx_pin_populate()
725 pin->paired = !!(ctrl & BIT(1)); pm8xxx_pin_populate()
728 pin->mode = PM8XXX_MPP_SINK; pm8xxx_pin_populate()
729 pin->dtest = ctrl + 1; pm8xxx_pin_populate()
730 pin->drive_strength = 5 * (level + 1); pm8xxx_pin_populate()
733 pin->mode = PM8XXX_MPP_DIGITAL; pm8xxx_pin_populate()
734 pin->power_source = level; pm8xxx_pin_populate()
736 pin->dtest = ctrl; pm8xxx_pin_populate()
796 "missing interrupts for pin %d\n", i); pm8xxx_mpp_probe()
839 dev_err(pctrl->dev, "failed to add pin range\n"); pm8xxx_mpp_probe()
171 pm8xxx_mpp_update(struct pm8xxx_mpp *pctrl, struct pm8xxx_pin_data *pin) pm8xxx_mpp_update() argument
656 pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl, struct pm8xxx_pin_data *pin) pm8xxx_pin_populate() argument
H A Dpinctrl-ssbi-gpio.c62 * struct pm8xxx_pin_data - dynamic configuration for a pin
67 * @mode: operating mode for the pin (input/output)
74 * @disable: pin disabled / configured as tristate
76 * @inverted: pin logic is inverted
133 struct pm8xxx_pin_data *pin, int bank) pm8xxx_read_bank()
138 ret = regmap_write(pctrl->regmap, pin->reg, val); pm8xxx_read_bank()
144 ret = regmap_read(pctrl->regmap, pin->reg, &val); pm8xxx_read_bank()
154 struct pm8xxx_pin_data *pin, pm8xxx_write_bank()
163 ret = regmap_write(pctrl->regmap, pin->reg, val); pm8xxx_write_bank()
233 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; pm8xxx_pinmux_set_mux() local
236 pin->function = function; pm8xxx_pinmux_set_mux()
237 val = pin->function << 1; pm8xxx_pinmux_set_mux()
239 pm8xxx_write_bank(pctrl, pin, 4, val); pm8xxx_pinmux_set_mux()
256 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_pin_config_get() local
262 arg = pin->bias == PM8XXX_GPIO_BIAS_NP; pm8xxx_pin_config_get()
265 arg = pin->bias == PM8XXX_GPIO_BIAS_PD; pm8xxx_pin_config_get()
268 arg = pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30; pm8xxx_pin_config_get()
271 arg = pin->pull_up_strength; pm8xxx_pin_config_get()
274 arg = pin->disable; pm8xxx_pin_config_get()
277 arg = pin->mode == PM8XXX_GPIO_MODE_INPUT; pm8xxx_pin_config_get()
280 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT) pm8xxx_pin_config_get()
281 arg = pin->output_value; pm8xxx_pin_config_get()
286 arg = pin->power_source; pm8xxx_pin_config_get()
289 arg = pin->output_strength; pm8xxx_pin_config_get()
292 arg = !pin->open_drain; pm8xxx_pin_config_get()
295 arg = pin->open_drain; pm8xxx_pin_config_get()
312 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_pin_config_set() local
325 pin->bias = PM8XXX_GPIO_BIAS_NP; pm8xxx_pin_config_set()
327 pin->disable = 0; pm8xxx_pin_config_set()
331 pin->bias = PM8XXX_GPIO_BIAS_PD; pm8xxx_pin_config_set()
333 pin->disable = 0; pm8xxx_pin_config_set()
341 pin->pull_up_strength = arg; pm8xxx_pin_config_set()
344 pin->bias = pin->pull_up_strength; pm8xxx_pin_config_set()
346 pin->disable = 0; pm8xxx_pin_config_set()
350 pin->disable = 1; pm8xxx_pin_config_set()
354 pin->mode = PM8XXX_GPIO_MODE_INPUT; pm8xxx_pin_config_set()
358 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; pm8xxx_pin_config_set()
359 pin->output_value = !!arg; pm8xxx_pin_config_set()
363 pin->power_source = arg; pm8xxx_pin_config_set()
371 pin->output_strength = arg; pm8xxx_pin_config_set()
375 pin->open_drain = 0; pm8xxx_pin_config_set()
379 pin->open_drain = 1; pm8xxx_pin_config_set()
391 val = pin->power_source << 1; pm8xxx_pin_config_set()
393 pm8xxx_write_bank(pctrl, pin, 0, val); pm8xxx_pin_config_set()
397 val = pin->mode << 2; pm8xxx_pin_config_set()
398 val |= pin->open_drain << 1; pm8xxx_pin_config_set()
399 val |= pin->output_value; pm8xxx_pin_config_set()
400 pm8xxx_write_bank(pctrl, pin, 1, val); pm8xxx_pin_config_set()
404 val = pin->bias << 1; pm8xxx_pin_config_set()
405 pm8xxx_write_bank(pctrl, pin, 2, val); pm8xxx_pin_config_set()
409 val = pin->output_strength << 2; pm8xxx_pin_config_set()
410 val |= pin->disable; pm8xxx_pin_config_set()
411 pm8xxx_write_bank(pctrl, pin, 3, val); pm8xxx_pin_config_set()
415 val = pin->function << 1; pm8xxx_pin_config_set()
416 pm8xxx_write_bank(pctrl, pin, 4, val); pm8xxx_pin_config_set()
421 if (!pin->inverted) pm8xxx_pin_config_set()
423 pm8xxx_write_bank(pctrl, pin, 5, val); pm8xxx_pin_config_set()
447 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_gpio_direction_input() local
450 pin->mode = PM8XXX_GPIO_MODE_INPUT; pm8xxx_gpio_direction_input()
451 val = pin->mode << 2; pm8xxx_gpio_direction_input()
453 pm8xxx_write_bank(pctrl, pin, 1, val); pm8xxx_gpio_direction_input()
463 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_gpio_direction_output() local
466 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; pm8xxx_gpio_direction_output()
467 pin->output_value = !!value; pm8xxx_gpio_direction_output()
469 val = pin->mode << 2; pm8xxx_gpio_direction_output()
470 val |= pin->open_drain << 1; pm8xxx_gpio_direction_output()
471 val |= pin->output_value; pm8xxx_gpio_direction_output()
473 pm8xxx_write_bank(pctrl, pin, 1, val); pm8xxx_gpio_direction_output()
481 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_gpio_get() local
485 if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) { pm8xxx_gpio_get()
486 ret = pin->output_value; pm8xxx_gpio_get()
488 ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state); pm8xxx_gpio_get()
499 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_gpio_set() local
502 pin->output_value = !!value; pm8xxx_gpio_set()
504 val = pin->mode << 2; pm8xxx_gpio_set()
505 val |= pin->open_drain << 1; pm8xxx_gpio_set()
506 val |= pin->output_value; pm8xxx_gpio_set()
508 pm8xxx_write_bank(pctrl, pin, 1, val); pm8xxx_gpio_set()
528 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_gpio_to_irq() local
530 return pin->irq; pm8xxx_gpio_to_irq()
543 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pm8xxx_gpio_dbg_show_one() local
560 if (pin->disable) { pm8xxx_gpio_dbg_show_one()
563 seq_printf(s, " %-4s", modes[pin->mode]); pm8xxx_gpio_dbg_show_one()
564 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]); pm8xxx_gpio_dbg_show_one()
565 seq_printf(s, " VIN%d", pin->power_source); pm8xxx_gpio_dbg_show_one()
566 seq_printf(s, " %-27s", biases[pin->bias]); pm8xxx_gpio_dbg_show_one()
567 seq_printf(s, " %-10s", buffer_types[pin->open_drain]); pm8xxx_gpio_dbg_show_one()
568 seq_printf(s, " %-4s", pin->output_value ? "high" : "low"); pm8xxx_gpio_dbg_show_one()
569 seq_printf(s, " %-7s", strengths[pin->output_strength]); pm8xxx_gpio_dbg_show_one()
570 if (pin->inverted) pm8xxx_gpio_dbg_show_one()
602 struct pm8xxx_pin_data *pin) pm8xxx_pin_populate()
606 val = pm8xxx_read_bank(pctrl, pin, 0); pm8xxx_pin_populate()
610 pin->power_source = (val >> 1) & 0x7; pm8xxx_pin_populate()
612 val = pm8xxx_read_bank(pctrl, pin, 1); pm8xxx_pin_populate()
616 pin->mode = (val >> 2) & 0x3; pm8xxx_pin_populate()
617 pin->open_drain = !!(val & BIT(1)); pm8xxx_pin_populate()
618 pin->output_value = val & BIT(0); pm8xxx_pin_populate()
620 val = pm8xxx_read_bank(pctrl, pin, 2); pm8xxx_pin_populate()
624 pin->bias = (val >> 1) & 0x7; pm8xxx_pin_populate()
625 if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30) pm8xxx_pin_populate()
626 pin->pull_up_strength = pin->bias; pm8xxx_pin_populate()
628 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30; pm8xxx_pin_populate()
630 val = pm8xxx_read_bank(pctrl, pin, 3); pm8xxx_pin_populate()
634 pin->output_strength = (val >> 2) & 0x3; pm8xxx_pin_populate()
635 pin->disable = val & BIT(0); pm8xxx_pin_populate()
637 val = pm8xxx_read_bank(pctrl, pin, 4); pm8xxx_pin_populate()
641 pin->function = (val >> 1) & 0x7; pm8xxx_pin_populate()
643 val = pm8xxx_read_bank(pctrl, pin, 5); pm8xxx_pin_populate()
647 pin->inverted = !(val & BIT(3)); pm8xxx_pin_populate()
705 "missing interrupts for pin %d\n", i); pm8xxx_gpio_probe()
748 dev_err(pctrl->dev, "failed to add pin range\n"); pm8xxx_gpio_probe()
132 pm8xxx_read_bank(struct pm8xxx_gpio *pctrl, struct pm8xxx_pin_data *pin, int bank) pm8xxx_read_bank() argument
153 pm8xxx_write_bank(struct pm8xxx_gpio *pctrl, struct pm8xxx_pin_data *pin, int bank, u8 val) pm8xxx_write_bank() argument
601 pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl, struct pm8xxx_pin_data *pin) pm8xxx_pin_populate() argument
H A Dpinctrl-qdf2xxx.c13 * GPIO and pin control functions on this SOC are handled by the "TLMM"
16 * with pinctrl-msm.c. This means that all TLMM drivers are pin control
19 * This pin control driver is intended to be used only an ACPI-enabled
20 * system. As such, UEFI will handle all pin control configuration, so
21 * this driver does not provide pin control functions. It is effectively
121 MODULE_DESCRIPTION("Qualcomm Technologies QDF2xxx pin control driver");
H A Dpinctrl-spmi-gpio.c78 * Output type - indicates pin should be configured as push-pull,
90 /* Qualcomm specific pin configurations */
99 * @out_value: Cached pin output value
201 unsigned pin) pmic_gpio_get_group_name()
203 return pctldev->desc->pins[pin].name; pmic_gpio_get_group_name()
206 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin, pmic_gpio_get_group_pins() argument
209 *pins = &pctldev->desc->pins[pin].number; pmic_gpio_get_group_pins()
244 unsigned pin) pmic_gpio_set_mux()
251 pad = pctldev->desc->pins[pin].drv_data; pmic_gpio_set_mux()
284 unsigned int pin, unsigned long *config) pmic_gpio_config_get()
290 pad = pctldev->desc->pins[pin].drv_data; pmic_gpio_config_get()
337 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, pmic_gpio_config_set() argument
346 pad = pctldev->desc->pins[pin].drv_data; pmic_gpio_config_set()
443 struct seq_file *s, unsigned pin) pmic_gpio_config_dbg_show()
460 pad = pctldev->desc->pins[pin].drv_data; pmic_gpio_config_dbg_show()
462 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET); pmic_gpio_config_dbg_show()
496 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin) pmic_gpio_direction_input() argument
503 return pmic_gpio_config_set(state->ctrl, pin, &config, 1); pmic_gpio_direction_input()
507 unsigned pin, int val) pmic_gpio_direction_output()
514 return pmic_gpio_config_set(state->ctrl, pin, &config, 1); pmic_gpio_direction_output()
517 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin) pmic_gpio_get() argument
523 pad = state->ctrl->desc->pins[pin].drv_data; pmic_gpio_get()
539 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value) pmic_gpio_set() argument
546 pmic_gpio_config_set(state->ctrl, pin, &config, 1); pmic_gpio_set()
562 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin) pmic_gpio_to_irq() argument
567 pad = state->ctrl->desc->pins[pin].drv_data; pmic_gpio_to_irq()
782 dev_err(dev, "failed to add pin range\n"); pmic_gpio_probe()
825 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
200 pmic_gpio_get_group_name(struct pinctrl_dev *pctldev, unsigned pin) pmic_gpio_get_group_name() argument
243 pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function, unsigned pin) pmic_gpio_set_mux() argument
283 pmic_gpio_config_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) pmic_gpio_config_get() argument
442 pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin) pmic_gpio_config_dbg_show() argument
506 pmic_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int val) pmic_gpio_direction_output() argument
H A Dpinctrl-spmi-mpp.c104 /* Qualcomm specific pin configurations */
115 * @out_value: Cached pin output value.
221 unsigned pin) pmic_mpp_get_group_name()
223 return pctldev->desc->pins[pin].name; pmic_mpp_get_group_name()
227 unsigned pin, pmic_mpp_get_group_pins()
230 *pins = &pctldev->desc->pins[pin].number; pmic_mpp_get_group_pins()
312 unsigned pin) pmic_mpp_set_mux()
319 pad = pctldev->desc->pins[pin].drv_data; pmic_mpp_set_mux()
338 unsigned int pin, unsigned long *config) pmic_mpp_config_get()
344 pad = pctldev->desc->pins[pin].drv_data; pmic_mpp_config_get()
404 static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, pmic_mpp_config_set() argument
413 pad = pctldev->desc->pins[pin].drv_data; pmic_mpp_config_set()
415 /* Make it possible to enable the pin, by not setting high impedance */ pmic_mpp_config_set()
510 struct seq_file *s, unsigned pin) pmic_mpp_config_dbg_show()
520 pad = pctldev->desc->pins[pin].drv_data; pmic_mpp_config_dbg_show()
522 seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); pmic_mpp_config_dbg_show()
557 static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin) pmic_mpp_direction_input() argument
564 return pmic_mpp_config_set(state->ctrl, pin, &config, 1); pmic_mpp_direction_input()
568 unsigned pin, int val) pmic_mpp_direction_output()
575 return pmic_mpp_config_set(state->ctrl, pin, &config, 1); pmic_mpp_direction_output()
578 static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin) pmic_mpp_get() argument
584 pad = state->ctrl->desc->pins[pin].drv_data; pmic_mpp_get()
597 static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value) pmic_mpp_set() argument
604 pmic_mpp_config_set(state->ctrl, pin, &config, 1); pmic_mpp_set()
620 static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin) pmic_mpp_to_irq() argument
625 pad = state->ctrl->desc->pins[pin].drv_data; pmic_mpp_to_irq()
884 dev_err(dev, "failed to add pin range\n"); pmic_mpp_probe()
928 MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver");
220 pmic_mpp_get_group_name(struct pinctrl_dev *pctldev, unsigned pin) pmic_mpp_get_group_name() argument
226 pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin, const unsigned **pins, unsigned *num_pins) pmic_mpp_get_group_pins() argument
311 pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, unsigned pin) pmic_mpp_set_mux() argument
337 pmic_mpp_config_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) pmic_mpp_config_get() argument
509 pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin) pmic_mpp_config_dbg_show() argument
567 pmic_mpp_direction_output(struct gpio_chip *chip, unsigned pin, int val) pmic_mpp_direction_output() argument
/linux-4.4.14/fs/
H A Dfs_pin.c9 void pin_remove(struct fs_pin *pin) pin_remove() argument
12 hlist_del_init(&pin->m_list); pin_remove()
13 hlist_del_init(&pin->s_list); pin_remove()
15 spin_lock_irq(&pin->wait.lock); pin_remove()
16 pin->done = 1; pin_remove()
17 wake_up_locked(&pin->wait); pin_remove()
18 spin_unlock_irq(&pin->wait.lock); pin_remove()
21 void pin_insert_group(struct fs_pin *pin, struct vfsmount *m, struct hlist_head *p) pin_insert_group() argument
25 hlist_add_head(&pin->s_list, p); pin_insert_group()
26 hlist_add_head(&pin->m_list, &real_mount(m)->mnt_pins); pin_insert_group()
30 void pin_insert(struct fs_pin *pin, struct vfsmount *m) pin_insert() argument
32 pin_insert_group(pin, m, &m->mnt_sb->s_pins); pin_insert()
/linux-4.4.14/include/linux/platform_data/
H A Dst_sensors_pdata.h16 * @drdy_int_pin: Redirect DRDY on pin 1 (1) or pin 2 (2).
18 * Accelerometer DRDY on LSM330 available only on pin 1 (see datasheet).
H A Dad5449.h15 * enum ad5449_sdo_mode - AD5449 SDO pin configuration
16 * @AD5449_SDO_DRIVE_FULL: Drive the SDO pin with full strength.
17 * @AD5449_SDO_DRIVE_WEAK: Drive the SDO pin with not full strength.
18 * @AD5449_SDO_OPEN_DRAIN: Operate the SDO pin in open-drain mode.
19 * @AD5449_SDO_DISABLED: Disable the SDO pin, in this mode it is not possible to
31 * @sdo_mode: SDO pin mode
32 * @hardware_clear_to_midscale: Whether asserting the hardware CLR pin sets the
H A Dst1232_pdata.h7 * Use this if you want the driver to drive the reset pin.
H A Dssm2518.h15 * @enable_gpio: GPIO connected to the nSD pin. Set to -1 if the nSD pin is
H A Dleds-lm355x.h48 * @pin_torch : input pin
51 * @pin_tx2 : input pin
53 * lm3556-tx pin
54 * @ntc_pin : output pin
56 * lm3556-temp pin
H A Dad7266.h15 * (RANGE pin set to low)
17 * (RANGE pin set to high)
27 * (SGL/DIFF pin set to low, AD0 pin set to low)
29 * (SGL/DIFF pin set to low, AD0 pin set to high)
31 * (SGL/DIFF pin set to high)
H A Dgpio-ts5500.h16 * struct ts5500_dio_platform_data - TS-5500 pin block configuration
18 * @strap: The only pin connected to an interrupt in a block is input-only.
20 * may strap it with an in/out pin. This flag indicates this case.
H A Dusb-rcar-phy.h19 unsigned penc1:1; /* Output of the PENC1 pin in function mode */
20 struct { /* Overcurrent pin control for ports 0..2 */
21 bool select_3_3v:1; /* true: USB_OVCn pin, false: OVCn pin */
H A Dadau17x1.h24 * enum adau1761_digmic_jackdet_pin_mode - Configuration of the JACKDET/MICIN pin
25 * @ADAU1761_DIGMIC_JACKDET_PIN_MODE_NONE: Disable the pin
26 * @ADAU1761_DIGMIC_JACKDET_PIN_MODE_DIGMIC: Configure the pin for usage as
28 * @ADAU1761_DIGMIC_JACKDET_PIN_MODE_JACKDETECT: Configure the pin for jack
69 * @digmic_jackdetect_pin_mode: JACKDET/MICIN pin configuration
71 * Note: This value will only be used, if the JACKDET/MICIN pin is configured
H A Dgpio-rcar.h27 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
H A Di2c-davinci.h19 unsigned int sda_pin; /* GPIO pin ID to use for SDA */
20 unsigned int scl_pin; /* GPIO pin ID to use for SCL */
H A Dmax3421-hcd.h14 * A value of 0 indicates that the pin is not used/wired to anything.
20 u8 vbus_gpout; /* pin controlling Vbus */
H A Dad7303.h15 * to the REF pin, otherwise use the internal reference derived from Vdd.
H A Dad7793.h13 * @AD7793_CLK_SRC_INT: Internal 64 kHz clock, not available at the CLK pin.
14 * @AD7793_CLK_SRC_INT_CO: Internal 64 kHz clock, available at the CLK pin.
56 * @AD7793_IEXEC1_IOUT1_IEXEC2_IOUT2: Current source IEXC1 connected to pin
57 * IOUT1, current source IEXC2 connected to pin IOUT2.
58 * @AD7793_IEXEC1_IOUT2_IEXEC2_IOUT1: Current source IEXC2 connected to pin
59 * IOUT1, current source IEXC1 connected to pin IOUT2.
60 * @AD7793_IEXEC1_IEXEC2_IOUT1: Both current sources connected to pin IOUT1.
H A Dadau1977.h14 * enum adau1977_micbias - ADAU1977 MICBIAS pin voltage setting
39 * @micbias: Specifies the voltage for the MICBIAS pin
H A Dmv_usb.h37 struct mv_usb_addon_irq *id; /* Only valid for OTG. ID pin change*/
43 /* This flag is used for that needs id pin checked by otg */
/linux-4.4.14/drivers/pinctrl/freescale/
H A Dpinctrl-imx.h21 * struct imx_pin_group - describes a single i.MX pin
22 * @pin: the pin_id of this pin
23 * @mux_mode: the mux mode for this pin.
24 * @input_reg: the select input register offset for this pin if any
26 * @input_val: the select input value for this pin.
27 * @configs: the config for this pin.
30 unsigned int pin; member in struct:imx_pin
38 * struct imx_pin_group - describes an IMX pin group
39 * @name: the name of this specific pin group
55 * @groups: corresponding pin groups
65 * struct imx_pin_reg - describe a pin reg map
93 #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
H A Dpinctrl-imx1.h21 * struct imx1_pin - describes an IMX1/21/27 pin.
22 * @pin_id: ID of the described pin.
24 * @config: Configuration of the pin (currently only pullup-enable).
33 * struct imx1_pin_group - describes an IMX pin group
34 * @name: the name of this specific pin group
49 * @groups: corresponding pin groups
68 #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
H A Dpinctrl-mxs.h22 #define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
23 #define PINID(bank, pin) ((bank) * 32 + (pin))
29 * pin: 11..4 (8)
39 * pin config bit field definitions
H A Dpinctrl-imx.c2 * Core driver for the imx pin controller
32 #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
155 pin_get_name(pctldev, grp->pins[i].pin); imx_dt_node_to_map()
195 * Configure the mux mode for each pin in the group for a specific imx_pmx_set()
205 struct imx_pin *pin = &grp->pins[i]; imx_pmx_set() local
206 pin_id = pin->pin; imx_pmx_set()
219 reg |= (pin->mux_mode << 20); imx_pmx_set()
222 writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); imx_pmx_set()
225 pin_reg->mux_reg, pin->mux_mode); imx_pmx_set()
233 * input for some pin is not implemented in the select imx_pmx_set()
236 * the bit field into input_val cell of pin function ID imx_pmx_set()
240 if (pin->input_val >> 24 == 0xff) { imx_pmx_set()
241 u32 val = pin->input_val; imx_pmx_set()
250 val = readl(ipctl->base + pin->input_reg); imx_pmx_set()
253 writel(val, ipctl->base + pin->input_reg); imx_pmx_set()
254 } else if (pin->input_reg) { imx_pmx_set()
260 writel(pin->input_val, ipctl->input_sel_base + imx_pmx_set()
261 pin->input_reg); imx_pmx_set()
263 writel(pin->input_val, ipctl->base + imx_pmx_set()
264 pin->input_reg); imx_pmx_set()
267 pin->input_reg, pin->input_val); imx_pmx_set()
312 unsigned int pin, group; imx_pmx_gpio_request_enable() local
323 /* Find the pinctrl config with GPIO mux mode for the requested pin */ imx_pmx_gpio_request_enable()
326 for (pin = 0; pin < grp->npins; pin++) { imx_pmx_gpio_request_enable()
327 imx_pin = &grp->pins[pin]; imx_pmx_gpio_request_enable()
328 if (imx_pin->pin == offset && !imx_pin->mux_mode) imx_pmx_gpio_request_enable()
419 dev_dbg(ipctl->dev, "pinconf set pin %s\n", imx_pinconf_set()
472 struct imx_pin *pin = &grp->pins[i]; imx_pinconf_group_dbg_show() local
473 name = pin_get_name(pctldev, pin->pin); imx_pinconf_group_dbg_show()
474 ret = imx_pinconf_get(pctldev, pin->pin, &config); imx_pinconf_group_dbg_show()
496 * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
497 * 1 u32 CONFIG, so 24 types in total for each pin.
550 struct imx_pin *pin = &grp->pins[i]; imx_pinctrl_parse_groups() local
565 pin->pin = pin_id; imx_pinctrl_parse_groups()
569 pin->input_reg = be32_to_cpu(*list++); imx_pinctrl_parse_groups()
570 pin->mux_mode = be32_to_cpu(*list++); imx_pinctrl_parse_groups()
571 pin->input_val = be32_to_cpu(*list++); imx_pinctrl_parse_groups()
576 pin->mux_mode |= IOMUXC_CONFIG_SION; imx_pinctrl_parse_groups()
577 pin->config = config & ~IMX_PAD_SION; imx_pinctrl_parse_groups()
580 pin->mux_mode, pin->config); imx_pinctrl_parse_groups()
/linux-4.4.14/arch/arm/mach-s3c24xx/
H A Dpm.c75 * check to see if the pin is configured correctly for sleep mode, and
79 static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) s3c_pm_check_resume_pin() argument
83 int irq = gpio_to_irq(pin); s3c_pm_check_resume_pin()
90 pinstate = s3c_gpio_getcfg(pin); s3c_pm_check_resume_pin()
94 S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin); s3c_pm_check_resume_pin()
97 S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin); s3c_pm_check_resume_pin()
98 s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); s3c_pm_check_resume_pin()
110 int pin; s3c_pm_configure_extint() local
117 for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) { s3c_pm_configure_extint()
118 s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0)); s3c_pm_configure_extint()
121 for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) { s3c_pm_configure_extint()
122 s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8); s3c_pm_configure_extint()
/linux-4.4.14/drivers/gpio/
H A Dgpio-zevio.c66 static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin, zevio_gpio_port_get() argument
69 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; zevio_gpio_port_get()
73 static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin, zevio_gpio_port_set() argument
76 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; zevio_gpio_port_set()
81 static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin) zevio_gpio_get() argument
87 dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); zevio_gpio_get()
88 if (dir & BIT(ZEVIO_GPIO_BIT(pin))) zevio_gpio_get()
89 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT); zevio_gpio_get()
91 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); zevio_gpio_get()
94 return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1; zevio_gpio_get()
97 static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value) zevio_gpio_set() argument
103 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); zevio_gpio_set()
105 val |= BIT(ZEVIO_GPIO_BIT(pin)); zevio_gpio_set()
107 val &= ~BIT(ZEVIO_GPIO_BIT(pin)); zevio_gpio_set()
109 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); zevio_gpio_set()
113 static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin) zevio_gpio_direction_input() argument
120 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); zevio_gpio_direction_input()
121 val |= BIT(ZEVIO_GPIO_BIT(pin)); zevio_gpio_direction_input()
122 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val); zevio_gpio_direction_input()
130 unsigned pin, int value) zevio_gpio_direction_output()
136 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); zevio_gpio_direction_output()
138 val |= BIT(ZEVIO_GPIO_BIT(pin)); zevio_gpio_direction_output()
140 val &= ~BIT(ZEVIO_GPIO_BIT(pin)); zevio_gpio_direction_output()
142 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); zevio_gpio_direction_output()
143 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); zevio_gpio_direction_output()
144 val &= ~BIT(ZEVIO_GPIO_BIT(pin)); zevio_gpio_direction_output()
145 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val); zevio_gpio_direction_output()
152 static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin) zevio_gpio_to_irq() argument
129 zevio_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value) zevio_gpio_direction_output() argument
H A Dgpio-vr41xx.c127 unsigned int pin; mask_ack_giuint_low() local
129 pin = GPIO_PIN_OF_IRQ(d->irq); mask_ack_giuint_low()
130 giu_clear(GIUINTENL, 1 << pin); mask_ack_giuint_low()
131 giu_write(GIUINTSTATL, 1 << pin); mask_ack_giuint_low()
179 unsigned int pin; mask_ack_giuint_high() local
181 pin = GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET; mask_ack_giuint_high()
182 giu_clear(GIUINTENH, 1 << pin); mask_ack_giuint_high()
183 giu_write(GIUINTSTATH, 1 << pin); mask_ack_giuint_high()
232 void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, vr41xx_set_irq_trigger() argument
237 if (pin < GIUINT_HIGH_OFFSET) { vr41xx_set_irq_trigger()
238 mask = 1 << pin; vr41xx_set_irq_trigger()
261 irq_set_chip_and_handler(GIU_IRQ(pin), vr41xx_set_irq_trigger()
267 irq_set_chip_and_handler(GIU_IRQ(pin), vr41xx_set_irq_trigger()
272 } else if (pin < GIUINT_HIGH_MAX) { vr41xx_set_irq_trigger()
273 mask = 1 << (pin - GIUINT_HIGH_OFFSET); vr41xx_set_irq_trigger()
296 irq_set_chip_and_handler(GIU_IRQ(pin), vr41xx_set_irq_trigger()
302 irq_set_chip_and_handler(GIU_IRQ(pin), vr41xx_set_irq_trigger()
311 void vr41xx_set_irq_level(unsigned int pin, irq_level_t level) vr41xx_set_irq_level() argument
315 if (pin < GIUINT_HIGH_OFFSET) { vr41xx_set_irq_level()
316 mask = 1 << pin; vr41xx_set_irq_level()
322 } else if (pin < GIUINT_HIGH_MAX) { vr41xx_set_irq_level()
323 mask = 1 << (pin - GIUINT_HIGH_OFFSET); vr41xx_set_irq_level()
333 static int giu_set_direction(struct gpio_chip *chip, unsigned pin, int dir) giu_set_direction() argument
338 if (pin >= chip->ngpio) giu_set_direction()
341 if (pin < 16) { giu_set_direction()
343 mask = 1 << pin; giu_set_direction()
344 } else if (pin < 32) { giu_set_direction()
346 mask = 1 << (pin - 16); giu_set_direction()
350 mask = 1 << (pin - 32); giu_set_direction()
352 switch (pin) { giu_set_direction()
381 int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull) vr41xx_gpio_pullupdown() argument
389 if (pin >= 15) vr41xx_gpio_pullupdown()
392 mask = 1 << pin; vr41xx_gpio_pullupdown()
419 static int vr41xx_gpio_get(struct gpio_chip *chip, unsigned pin) vr41xx_gpio_get() argument
423 if (pin >= chip->ngpio) vr41xx_gpio_get()
426 if (pin < 16) { vr41xx_gpio_get()
428 mask = 1 << pin; vr41xx_gpio_get()
429 } else if (pin < 32) { vr41xx_gpio_get()
431 mask = 1 << (pin - 16); vr41xx_gpio_get()
432 } else if (pin < 48) { vr41xx_gpio_get()
434 mask = 1 << (pin - 32); vr41xx_gpio_get()
437 mask = 1 << (pin - 48); vr41xx_gpio_get()
446 static void vr41xx_gpio_set(struct gpio_chip *chip, unsigned pin, vr41xx_gpio_set() argument
452 if (pin >= chip->ngpio) vr41xx_gpio_set()
455 if (pin < 16) { vr41xx_gpio_set()
457 mask = 1 << pin; vr41xx_gpio_set()
458 } else if (pin < 32) { vr41xx_gpio_set()
460 mask = 1 << (pin - 16); vr41xx_gpio_set()
461 } else if (pin < 48) { vr41xx_gpio_set()
463 mask = 1 << (pin - 32); vr41xx_gpio_set()
466 mask = 1 << (pin - 48); vr41xx_gpio_set()
516 unsigned int trigger, i, pin; giu_probe() local
559 pin = GPIO_PIN_OF_IRQ(i); giu_probe()
560 if (pin < GIUINT_HIGH_OFFSET) giu_probe()
565 if (trigger & (1 << pin)) giu_probe()
H A Dgpio-lpc32xx.c175 unsigned pin, int input) __set_gpio_dir_p012()
178 __raw_writel(GPIO012_PIN_TO_BIT(pin), __set_gpio_dir_p012()
181 __raw_writel(GPIO012_PIN_TO_BIT(pin), __set_gpio_dir_p012()
186 unsigned pin, int input) __set_gpio_dir_p3()
188 u32 u = GPIO3_PIN_TO_BIT(pin); __set_gpio_dir_p3()
197 unsigned pin, int high) __set_gpio_level_p012()
200 __raw_writel(GPIO012_PIN_TO_BIT(pin), __set_gpio_level_p012()
203 __raw_writel(GPIO012_PIN_TO_BIT(pin), __set_gpio_level_p012()
208 unsigned pin, int high) __set_gpio_level_p3()
210 u32 u = GPIO3_PIN_TO_BIT(pin); __set_gpio_level_p3()
219 unsigned pin, int high) __set_gpo_level_p3()
222 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); __set_gpo_level_p3()
224 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); __set_gpo_level_p3()
228 unsigned pin) __get_gpio_state_p012()
231 pin); __get_gpio_state_p012()
235 unsigned pin) __get_gpio_state_p3()
240 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped __get_gpio_state_p3()
243 return GPIO3_PIN_IN_SEL(state, pin); __get_gpio_state_p3()
247 unsigned pin) __get_gpi_state_p3()
249 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); __get_gpi_state_p3()
253 unsigned pin) __get_gpo_state_p3()
255 return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin); __get_gpo_state_p3()
262 unsigned pin) lpc32xx_gpio_dir_input_p012()
266 __set_gpio_dir_p012(group, pin, 1); lpc32xx_gpio_dir_input_p012()
272 unsigned pin) lpc32xx_gpio_dir_input_p3()
276 __set_gpio_dir_p3(group, pin, 1); lpc32xx_gpio_dir_input_p3()
282 unsigned pin) lpc32xx_gpio_dir_in_always()
287 static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin) lpc32xx_gpio_get_value_p012() argument
291 return __get_gpio_state_p012(group, pin); lpc32xx_gpio_get_value_p012()
294 static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin) lpc32xx_gpio_get_value_p3() argument
298 return __get_gpio_state_p3(group, pin); lpc32xx_gpio_get_value_p3()
301 static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin) lpc32xx_gpi_get_value() argument
305 return __get_gpi_state_p3(group, pin); lpc32xx_gpi_get_value()
308 static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin, lpc32xx_gpio_dir_output_p012() argument
313 __set_gpio_level_p012(group, pin, value); lpc32xx_gpio_dir_output_p012()
314 __set_gpio_dir_p012(group, pin, 0); lpc32xx_gpio_dir_output_p012()
319 static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin, lpc32xx_gpio_dir_output_p3() argument
324 __set_gpio_level_p3(group, pin, value); lpc32xx_gpio_dir_output_p3()
325 __set_gpio_dir_p3(group, pin, 0); lpc32xx_gpio_dir_output_p3()
330 static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin, lpc32xx_gpio_dir_out_always() argument
335 __set_gpo_level_p3(group, pin, value); lpc32xx_gpio_dir_out_always()
339 static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin, lpc32xx_gpio_set_value_p012() argument
344 __set_gpio_level_p012(group, pin, value); lpc32xx_gpio_set_value_p012()
347 static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin, lpc32xx_gpio_set_value_p3() argument
352 __set_gpio_level_p3(group, pin, value); lpc32xx_gpio_set_value_p3()
355 static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin, lpc32xx_gpo_set_value() argument
360 __set_gpo_level_p3(group, pin, value); lpc32xx_gpo_set_value()
363 static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin) lpc32xx_gpo_get_value() argument
367 return __get_gpo_state_p3(group, pin); lpc32xx_gpo_get_value()
370 static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin) lpc32xx_gpio_request() argument
372 if (pin < chip->ngpio) lpc32xx_gpio_request()
174 __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, unsigned pin, int input) __set_gpio_dir_p012() argument
185 __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, unsigned pin, int input) __set_gpio_dir_p3() argument
196 __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, unsigned pin, int high) __set_gpio_level_p012() argument
207 __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, unsigned pin, int high) __set_gpio_level_p3() argument
218 __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, unsigned pin, int high) __set_gpo_level_p3() argument
227 __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, unsigned pin) __get_gpio_state_p012() argument
234 __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, unsigned pin) __get_gpio_state_p3() argument
246 __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, unsigned pin) __get_gpi_state_p3() argument
252 __get_gpo_state_p3(struct lpc32xx_gpio_chip *group, unsigned pin) __get_gpo_state_p3() argument
261 lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip, unsigned pin) lpc32xx_gpio_dir_input_p012() argument
271 lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip, unsigned pin) lpc32xx_gpio_dir_input_p3() argument
281 lpc32xx_gpio_dir_in_always(struct gpio_chip *chip, unsigned pin) lpc32xx_gpio_dir_in_always() argument
H A Dgpio-ks8695.c40 static void ks8695_gpio_mode(unsigned int pin, short gpio) ks8695_gpio_mode() argument
45 if (pin > KS8695_GPIO_5) /* only GPIO 0..5 have internal functions */ ks8695_gpio_mode()
52 x &= ~enable[pin]; ks8695_gpio_mode()
54 x |= enable[pin]; ks8695_gpio_mode()
64 * Configure GPIO pin as external interrupt source.
66 int ks8695_gpio_interrupt(unsigned int pin, unsigned int type) ks8695_gpio_interrupt() argument
70 if (pin > KS8695_GPIO_3) /* only GPIO 0..3 can generate IRQ */ ks8695_gpio_interrupt()
75 /* set pin as input */ ks8695_gpio_interrupt()
77 x &= ~IOPM(pin); ks8695_gpio_interrupt()
83 irq_set_irq_type(gpio_irq[pin], type); ks8695_gpio_interrupt()
86 ks8695_gpio_mode(pin, 0); ks8695_gpio_interrupt()
99 static int ks8695_gpio_direction_input(struct gpio_chip *gc, unsigned int pin) ks8695_gpio_direction_input() argument
103 if (pin > KS8695_GPIO_15) ks8695_gpio_direction_input()
106 /* set pin to GPIO mode */ ks8695_gpio_direction_input()
107 ks8695_gpio_mode(pin, 1); ks8695_gpio_direction_input()
111 /* set pin as input */ ks8695_gpio_direction_input()
113 x &= ~IOPM(pin); ks8695_gpio_direction_input()
126 unsigned int pin, int state) ks8695_gpio_direction_output()
130 if (pin > KS8695_GPIO_15) ks8695_gpio_direction_output()
133 /* set pin to GPIO mode */ ks8695_gpio_direction_output()
134 ks8695_gpio_mode(pin, 1); ks8695_gpio_direction_output()
141 x |= IOPD(pin); ks8695_gpio_direction_output()
143 x &= ~IOPD(pin); ks8695_gpio_direction_output()
146 /* set pin as output */ ks8695_gpio_direction_output()
148 x |= IOPM(pin); ks8695_gpio_direction_output()
161 unsigned int pin, int state) ks8695_gpio_set_value()
165 if (pin > KS8695_GPIO_15) ks8695_gpio_set_value()
173 x |= IOPD(pin); ks8695_gpio_set_value()
175 x &= ~IOPD(pin); ks8695_gpio_set_value()
185 static int ks8695_gpio_get_value(struct gpio_chip *gc, unsigned int pin) ks8695_gpio_get_value() argument
189 if (pin > KS8695_GPIO_15) ks8695_gpio_get_value()
193 return (x & IOPD(pin)) != 0; ks8695_gpio_get_value()
200 static int ks8695_gpio_to_irq(struct gpio_chip *gc, unsigned int pin) ks8695_gpio_to_irq() argument
202 if (pin > KS8695_GPIO_3) /* only GPIO 0..3 can generate IRQ */ ks8695_gpio_to_irq()
205 return gpio_irq[pin]; ks8695_gpio_to_irq()
125 ks8695_gpio_direction_output(struct gpio_chip *gc, unsigned int pin, int state) ks8695_gpio_direction_output() argument
160 ks8695_gpio_set_value(struct gpio_chip *gc, unsigned int pin, int state) ks8695_gpio_set_value() argument
H A Dgpio-dln2.c55 * Cache pin direction to save us one transfer, since the hardware has
69 __le16 pin; member in struct:dln2_gpio_pin
73 __le16 pin __packed;
92 static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin) dln2_gpio_pin_cmd() argument
95 .pin = cpu_to_le16(pin), dln2_gpio_pin_cmd()
101 static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin) dln2_gpio_pin_val() argument
105 .pin = cpu_to_le16(pin), dln2_gpio_pin_val()
113 if (len < sizeof(rsp) || req.pin != rsp.pin) dln2_gpio_pin_val()
119 static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin) dln2_gpio_pin_get_in_val() argument
123 ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin); dln2_gpio_pin_get_in_val()
129 static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin) dln2_gpio_pin_get_out_val() argument
133 ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin); dln2_gpio_pin_get_out_val()
140 unsigned int pin, int value) dln2_gpio_pin_set_out_val()
143 .pin = cpu_to_le16(pin), dln2_gpio_pin_set_out_val()
158 .pin = cpu_to_le16(offset), dln2_gpio_request()
168 /* cache the pin direction */ dln2_gpio_request()
173 if (len < sizeof(rsp) || req.pin != rsp.pin) { dln2_gpio_request()
239 .pin = cpu_to_le16(offset), dln2_gpio_set_direction()
285 static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin, dln2_gpio_set_event_cfg() argument
289 __le16 pin; dln2_gpio_set_event_cfg() member in struct:__anon3969
293 .pin = cpu_to_le16(pin), dln2_gpio_set_event_cfg()
306 int pin = irqd_to_hwirq(irqd); dln2_irq_unmask() local
308 set_bit(pin, dln2->unmasked_irqs); dln2_irq_unmask()
315 int pin = irqd_to_hwirq(irqd); dln2_irq_mask() local
317 clear_bit(pin, dln2->unmasked_irqs); dln2_irq_mask()
324 int pin = irqd_to_hwirq(irqd); dln2_irq_set_type() local
328 dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH; dln2_irq_set_type()
331 dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW; dln2_irq_set_type()
334 dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE; dln2_irq_set_type()
337 dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING; dln2_irq_set_type()
340 dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING; dln2_irq_set_type()
361 int pin = irqd_to_hwirq(irqd); dln2_irq_bus_unlock() local
366 enabled = test_bit(pin, dln2->enabled_irqs); dln2_irq_bus_unlock()
367 unmasked = test_bit(pin, dln2->unmasked_irqs); dln2_irq_bus_unlock()
371 type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK; dln2_irq_bus_unlock()
372 set_bit(pin, dln2->enabled_irqs); dln2_irq_bus_unlock()
375 clear_bit(pin, dln2->enabled_irqs); dln2_irq_bus_unlock()
378 ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0); dln2_irq_bus_unlock()
398 int pin, irq; dln2_gpio_event() local
403 __le16 pin; dln2_gpio_event() member in struct:__anon3970
413 pin = le16_to_cpu(event->pin); dln2_gpio_event()
414 if (pin >= dln2->gpio.ngpio) { dln2_gpio_event()
415 dev_err(dln2->gpio.dev, "out of bounds pin %d\n", pin); dln2_gpio_event()
419 irq = irq_find_mapping(dln2->gpio.irqdomain, pin); dln2_gpio_event()
421 dev_err(dln2->gpio.dev, "pin %d not mapped to IRQ\n", pin); dln2_gpio_event()
425 switch (dln2->irq_type[pin]) { dln2_gpio_event()
448 dev_err(dev, "failed to get pin count: %d\n", pins); dln2_gpio_probe()
139 dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2, unsigned int pin, int value) dln2_gpio_pin_set_out_val() argument
H A Dgpio-zynq.c93 /* Mid pin number of a bank */
120 * @bank_min: this array represents bank's min pin
121 * @bank_max: this array represents bank's max pin
140 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
141 * for a given pin in the GPIO device
142 * @pin_num: gpio pin number within the device
144 * pin
145 * @bank_pin_num: an output parameter used to return pin number within a bank
146 * for the given gpio pin
148 * Returns the bank number and pin offset within the bank.
168 WARN(true, "invalid GPIO pin number: %u", pin_num); zynq_gpio_get_bank_pin()
174 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
176 * @pin: gpio pin number within the device
178 * This function reads the state of the specified pin of the GPIO device.
180 * Return: 0 if the pin is low, 1 if pin is high.
182 static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin) zynq_gpio_get_value() argument
188 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); zynq_gpio_get_value()
197 * zynq_gpio_set_value - Modify the state of the pin with specified value
199 * @pin: gpio pin number within the device
200 * @state: value used to modify the state of the specified pin
203 * upper 16 bits) based on the given pin number and sets the state of a
204 * gpio pin to the specified value. The state is either 0 or non-zero.
206 static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin, zynq_gpio_set_value() argument
212 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); zynq_gpio_set_value()
234 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
236 * @pin: gpio pin number within the device
239 * the gpio pin as input.
243 static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) zynq_gpio_dir_in() argument
249 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); zynq_gpio_dir_in()
255 /* clear the bit in direction mode reg to set the pin as input */ zynq_gpio_dir_in()
264 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
266 * @pin: gpio pin number within the device
267 * @state: value to be written to specified pin
269 * This function sets the direction of specified GPIO pin as output, configures
270 * the Output Enable register for the pin and uses zynq_gpio_set to set
271 * the state of the pin to the value specified.
275 static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, zynq_gpio_dir_out() argument
282 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); zynq_gpio_dir_out()
284 /* set the GPIO pin as output */ zynq_gpio_dir_out()
289 /* configure the output enable reg for the pin */ zynq_gpio_dir_out()
294 /* set the state of the pin */ zynq_gpio_dir_out()
295 zynq_gpio_set_value(chip, pin, state); zynq_gpio_dir_out()
300 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
303 * This function calculates gpio pin number from irq number and sets the
305 * interrupts for that pin.
320 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
321 * @irq_data: irq data containing irq number of gpio pin for the interrupt
324 * This function calculates the gpio pin number from irq number and sets the
326 * interrupts for that pin.
341 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
342 * @irq_data: irq data containing irq number of gpio pin for the interrupt
345 * This function calculates gpio pin number from irq number and sets the bit
361 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
362 * @irq_data: irq data containing irq number of gpio pin for the interrupt
384 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
385 * @irq_data: irq data containing irq number of gpio pin
386 * @type: interrupt type that is to be set for the gpio pin
388 * This function gets the gpio pin number and its bank from the gpio pin number
523 * gpio pin number which has triggered an interrupt. It then acks the triggered
524 * interrupt and calls the pin specific handler set by the higher layer
525 * application for that pin.
526 * Note: A bug is reported if no handler is set for the gpio pin.
H A Dgpiolib-acpi.c28 unsigned int pin; member in struct:acpi_gpio_event
35 unsigned int pin; member in struct:acpi_gpio_connection
64 * @pin: ACPI GPIO pin number from GpioIo/GpioInt resource
66 * Function takes ACPI GpioIo/GpioInt pin number as a parameter and
70 * Typically the returned offset is same as @pin, but if the GPIO
71 * controller uses pin controller and the mapping is not contiguous the
74 static int acpi_gpiochip_pin_to_gpio_offset(struct gpio_chip *chip, int pin) acpi_gpiochip_pin_to_gpio_offset() argument
80 return pin; acpi_gpiochip_pin_to_gpio_offset()
88 if (range->pins[i] == pin) acpi_gpiochip_pin_to_gpio_offset()
92 if (pin >= range->pin_base && acpi_gpiochip_pin_to_gpio_offset()
93 pin < range->pin_base + range->npins) { acpi_gpiochip_pin_to_gpio_offset()
97 return gpio_base + pin - range->pin_base; acpi_gpiochip_pin_to_gpio_offset()
106 int pin) acpi_gpiochip_pin_to_gpio_offset()
108 return pin; acpi_gpiochip_pin_to_gpio_offset()
113 * acpi_get_gpiod() - Translate ACPI GPIO pin to GPIO descriptor usable with GPIO API
115 * @pin: ACPI GPIO pin number (0-based, controller-relative)
122 static struct gpio_desc *acpi_get_gpiod(char *path, int pin) acpi_get_gpiod() argument
137 offset = acpi_gpiochip_pin_to_gpio_offset(chip, pin); acpi_get_gpiod()
157 acpi_execute_simple_method(event->handle, NULL, event->pin); acpi_gpio_irq_handler_evt()
178 int ret, pin, irq; acpi_gpiochip_request_interrupt() local
188 pin = agpio->pin_table[0]; acpi_gpiochip_request_interrupt()
190 if (pin <= 255) { acpi_gpiochip_request_interrupt()
194 pin); acpi_gpiochip_request_interrupt()
205 pin = acpi_gpiochip_pin_to_gpio_offset(chip, pin); acpi_gpiochip_request_interrupt()
206 if (pin < 0) acpi_gpiochip_request_interrupt()
209 desc = gpiochip_request_own_desc(chip, pin, "ACPI:Event"); acpi_gpiochip_request_interrupt()
217 ret = gpiochip_lock_as_irq(chip, pin); acpi_gpiochip_request_interrupt()
256 event->pin = pin; acpi_gpiochip_request_interrupt()
273 gpiochip_unlock_as_irq(chip, pin); acpi_gpiochip_request_interrupt()
344 gpiochip_unlock_as_irq(chip, event->pin); acpi_gpiochip_free_interrupts()
507 * Note: if the GPIO resource has multiple entries in the pin list, this
649 int pin = agpio->pin_table[i]; acpi_gpio_adr_space_handler() local
654 pin = acpi_gpiochip_pin_to_gpio_offset(chip, pin); acpi_gpio_adr_space_handler()
655 if (pin < 0) { acpi_gpio_adr_space_handler()
664 if (conn->pin == pin) { acpi_gpio_adr_space_handler()
681 if (event->pin == pin) { acpi_gpio_adr_space_handler()
690 desc = gpiochip_request_own_desc(chip, pin, acpi_gpio_adr_space_handler()
707 * instead. If the pin is pulled up we acpi_gpio_adr_space_handler()
729 conn->pin = pin; acpi_gpio_adr_space_handler()
105 acpi_gpiochip_pin_to_gpio_offset(struct gpio_chip *chip, int pin) acpi_gpiochip_pin_to_gpio_offset() argument
H A Dgpio-mvebu.c188 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value) mvebu_gpio_set() argument
198 u |= 1 << pin; mvebu_gpio_set()
200 u &= ~(1 << pin); mvebu_gpio_set()
205 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin) mvebu_gpio_get() argument
211 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) { mvebu_gpio_get()
218 return (u >> pin) & 1; mvebu_gpio_get()
221 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) mvebu_gpio_blink() argument
231 u |= 1 << pin; mvebu_gpio_blink()
233 u &= ~(1 << pin); mvebu_gpio_blink()
238 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin) mvebu_gpio_direction_input() argument
246 /* Check with the pinctrl driver whether this pin is usable as mvebu_gpio_direction_input()
248 ret = pinctrl_gpio_direction_input(chip->base + pin); mvebu_gpio_direction_input()
254 u |= 1 << pin; mvebu_gpio_direction_input()
261 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin, mvebu_gpio_direction_output() argument
270 /* Check with the pinctrl driver whether this pin is usable as mvebu_gpio_direction_output()
272 ret = pinctrl_gpio_direction_output(chip->base + pin); mvebu_gpio_direction_output()
276 mvebu_gpio_blink(chip, pin, 0); mvebu_gpio_direction_output()
277 mvebu_gpio_set(chip, pin, value); mvebu_gpio_direction_output()
281 u &= ~(1 << pin); mvebu_gpio_direction_output()
288 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin) mvebu_gpio_to_irq() argument
292 return irq_create_mapping(mvchip->domain, pin); mvebu_gpio_to_irq()
396 int pin; mvebu_gpio_irq_set_type() local
399 pin = d->hwirq; mvebu_gpio_irq_set_type()
401 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); mvebu_gpio_irq_set_type()
421 u &= ~(1 << pin); mvebu_gpio_irq_set_type()
427 u |= 1 << pin; mvebu_gpio_irq_set_type()
440 if (v & (1 << pin)) mvebu_gpio_irq_set_type()
441 u |= 1 << pin; /* falling */ mvebu_gpio_irq_set_type()
443 u &= ~(1 << pin); /* rising */ mvebu_gpio_irq_set_type()
/linux-4.4.14/arch/arm/mach-imx/
H A Diomux-v1.c61 unsigned int port, unsigned int pin, int on) imx_iomuxv1_set_puen()
63 unsigned long mask = 1 << pin; imx_iomuxv1_set_puen()
69 unsigned int port, unsigned int pin, int out) imx_iomuxv1_set_ddir()
71 unsigned long mask = 1 << pin; imx_iomuxv1_set_ddir()
77 unsigned int port, unsigned int pin, int af) imx_iomuxv1_set_gpr()
79 unsigned long mask = 1 << pin; imx_iomuxv1_set_gpr()
85 unsigned int port, unsigned int pin, int inuse) imx_iomuxv1_set_gius()
87 unsigned long mask = 1 << pin; imx_iomuxv1_set_gius()
93 unsigned int port, unsigned int pin, unsigned int ocr) imx_iomuxv1_set_ocr()
95 unsigned long shift = (pin & 0xf) << 1; imx_iomuxv1_set_ocr()
98 unsigned long offset = pin < 16 ? MXC_OCR1(port) : MXC_OCR2(port); imx_iomuxv1_set_ocr()
104 unsigned int port, unsigned int pin, unsigned int aout) imx_iomuxv1_set_iconfa()
106 unsigned long shift = (pin & 0xf) << 1; imx_iomuxv1_set_iconfa()
109 unsigned long offset = pin < 16 ? MXC_ICONFA1(port) : MXC_ICONFA2(port); imx_iomuxv1_set_iconfa()
115 unsigned int port, unsigned int pin, unsigned int bout) imx_iomuxv1_set_iconfb()
117 unsigned long shift = (pin & 0xf) << 1; imx_iomuxv1_set_iconfb()
120 unsigned long offset = pin < 16 ? MXC_ICONFB1(port) : MXC_ICONFB2(port); imx_iomuxv1_set_iconfb()
127 unsigned int pin = gpio_mode & GPIO_PIN_MASK; mxc_gpio_mode() local
137 imx_iomuxv1_set_puen(port, pin, gpio_mode & GPIO_PUEN); mxc_gpio_mode()
140 imx_iomuxv1_set_ddir(port, pin, gpio_mode & GPIO_OUT); mxc_gpio_mode()
143 imx_iomuxv1_set_gpr(port, pin, gpio_mode & GPIO_AF); mxc_gpio_mode()
146 imx_iomuxv1_set_gius(port, pin, !(gpio_mode & (GPIO_PF | GPIO_AF))); mxc_gpio_mode()
148 imx_iomuxv1_set_ocr(port, pin, ocr); mxc_gpio_mode()
150 imx_iomuxv1_set_iconfa(port, pin, aout); mxc_gpio_mode()
152 imx_iomuxv1_set_iconfb(port, pin, bout); mxc_gpio_mode()
60 imx_iomuxv1_set_puen( unsigned int port, unsigned int pin, int on) imx_iomuxv1_set_puen() argument
68 imx_iomuxv1_set_ddir( unsigned int port, unsigned int pin, int out) imx_iomuxv1_set_ddir() argument
76 imx_iomuxv1_set_gpr( unsigned int port, unsigned int pin, int af) imx_iomuxv1_set_gpr() argument
84 imx_iomuxv1_set_gius( unsigned int port, unsigned int pin, int inuse) imx_iomuxv1_set_gius() argument
92 imx_iomuxv1_set_ocr( unsigned int port, unsigned int pin, unsigned int ocr) imx_iomuxv1_set_ocr() argument
103 imx_iomuxv1_set_iconfa( unsigned int port, unsigned int pin, unsigned int aout) imx_iomuxv1_set_iconfa() argument
114 imx_iomuxv1_set_iconfb( unsigned int port, unsigned int pin, unsigned int bout) imx_iomuxv1_set_iconfb() argument
H A Diomux-imx31.c45 * set the mode for a IOMUX pin.
69 * This function configures the pad value for a IOMUX pin.
71 void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) mxc_iomux_set_pad() argument
76 pin &= IOMUX_PADNUM_MASK; mxc_iomux_set_pad()
77 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4; mxc_iomux_set_pad()
78 field = (pin + 2) % 3; mxc_iomux_set_pad()
81 __func__, (pin + 2) / 3, field); mxc_iomux_set_pad()
94 * allocs a single pin:
95 * - reserves the pin so that it is not claimed by another driver
98 int mxc_iomux_alloc_pin(unsigned int pin, const char *label) mxc_iomux_alloc_pin() argument
100 unsigned pad = pin & IOMUX_PADNUM_MASK; mxc_iomux_alloc_pin()
103 printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n", mxc_iomux_alloc_pin()
109 printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n", mxc_iomux_alloc_pin()
113 mxc_iomux_mode(pin); mxc_iomux_alloc_pin()
138 void mxc_iomux_release_pin(unsigned int pin) mxc_iomux_release_pin() argument
140 unsigned pad = pin & IOMUX_PADNUM_MASK; mxc_iomux_release_pin()
/linux-4.4.14/drivers/media/dvb-frontends/
H A Dm88ds3103.h40 * @lnb_hv_pol: LNB H/V pin polarity. 0: pin high set to VOLTAGE_18, pin low to
41 * set VOLTAGE_13. 1: pin high set to VOLTAGE_13, pin low to set VOLTAGE_18.
42 * @lnb_en_pol: LNB enable pin polarity. 0: pin high to disable, pin low to
43 * enable. 1: pin high to enable, pin low to disable.
51 #define M88DS3103_TS_SERIAL 0 /* TS output pin D0, normal */
52 #define M88DS3103_TS_SERIAL_D7 1 /* TS output pin D7 */
105 #define M88DS3103_TS_SERIAL 0 /* TS output pin D0, normal */
106 #define M88DS3103_TS_SERIAL_D7 1 /* TS output pin D7 */
157 * LNB H/V pin polarity
159 * 1: pin high set to VOLTAGE_13, pin low to set VOLTAGE_18.
160 * 0: pin high set to VOLTAGE_18, pin low to set VOLTAGE_13.
165 * LNB enable pin polarity
167 * 1: pin high to enable, pin low to disable.
168 * 0: pin high to disable, pin low to enable.
/linux-4.4.14/drivers/media/i2c/
H A Dtea6415c.h6 I don't want to say "connect input pin 20 to output pin 17", I define
7 a "virtual" pin-order. */
H A Dtea6420.h18 /* gain on the output pins, ORed with the output pin */
/linux-4.4.14/include/sound/
H A Dmax9768.h12 * @shdn_gpio: GPIO to SHDN pin. If not valid, pin must be hardwired HIGH
13 * @mute_gpio: GPIO to MUTE pin. If not valid, control for mute won't be added
H A Dak4641.h17 * @gpio_npdn: GPIO connected to AK4641 nPDN pin
/linux-4.4.14/arch/sh/drivers/pci/
H A Dfixups-cayman.c8 int __init pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin) pcibios_map_platform_irq() argument
33 int pin; pcibios_map_platform_irq() member in struct:slot_pin
40 pin = path[i].pin = pci_swizzle_interrupt_pin(dev, pin); pcibios_map_platform_irq()
54 result = IRQ_INTA + pci_swizzle_interrupt_pin(dev, pin) - 1; pcibios_map_platform_irq()
58 pin = path[i].pin; pcibios_map_platform_irq()
66 pin = path[i].pin; pcibios_map_platform_irq()
67 /* 'pin' was swizzled earlier wrt slot, don't do it again. */ pcibios_map_platform_irq()
68 result = IRQ_P2INTA + (pin - 1); pcibios_map_platform_irq()
H A Dfixups-landisk.c23 int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin) pcibios_map_platform_irq() argument
31 int irq = ((slot + pin - 1) & 0x3) + evt2irq(0x2a0); pcibios_map_platform_irq()
33 if ((slot | (pin - 1)) > 0x3) { pcibios_map_platform_irq()
34 printk(KERN_WARNING "PCI: Bad IRQ mapping request for slot %d pin %c\n", pcibios_map_platform_irq()
35 slot, pin - 1 + 'A'); pcibios_map_platform_irq()
H A Dfixups-snapgear.c22 int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin) pcibios_map_platform_irq() argument
35 printk("PCI: Mapping SnapGear IRQ for slot %d, pin %c to irq %d\n", pcibios_map_platform_irq()
36 slot, pin - 1 + 'A', irq); pcibios_map_platform_irq()
H A Dfixups-titan.c30 int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin) pcibios_map_platform_irq() argument
34 printk("PCI: Mapping TITAN IRQ for slot %d, pin %c to irq %d\n", pcibios_map_platform_irq()
35 slot, pin - 1 + 'A', irq); pcibios_map_platform_irq()
H A Dfixups-sh03.c7 int __init pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin) pcibios_map_platform_irq() argument
22 switch (pin) { pcibios_map_platform_irq()
H A Dfixups-sdk7780.c40 int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin) pcibios_map_platform_irq() argument
42 return sdk7780_irq_tab[pin-1][slot]; pcibios_map_platform_irq()
H A Dfixups-r7780rp.c18 int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin) pcibios_map_platform_irq() argument
/linux-4.4.14/drivers/staging/iio/cdc/
H A Dad7746.h23 bool exca_en; /* enables EXCA pin as the excitation output */
24 bool exca_inv_en; /* enables /EXCA pin as the excitation output */
25 bool excb_en; /* enables EXCB pin as the excitation output */
26 bool excb_inv_en; /* enables /EXCB pin as the excitation output */
/linux-4.4.14/drivers/pinctrl/
H A Dpinctrl-adi2.h15 * struct adi_pin_group - describes a pin group
16 * @name: the name of this pin group
36 * struct adi_pmx_func - describes function mux setting of pin groups
38 * @groups: an array of pin groups
39 * @num_groups: the number of pin groups in this array
56 * struct adi_pinctrl_soc_data - ADI pin controller per-SoC configuration
59 * @groups: An array describing all pin groups the pin SoC supports.
61 * @pins: An array describing all pins the pin controller affects.
H A Dpinmux.c2 * Core driver for the pin muxing portions of the pin control subsystem
76 * pin_request() - request a single pin to be muxed in, typically for GPIO
77 * @pin: the pin number in the global pin space
78 * @owner: a representation of the owner of this pin; typically the device
80 * @gpio_range: the range matching the GPIO pin if this is a request for a
81 * single GPIO pin
84 int pin, const char *owner, pin_request()
91 desc = pin_desc_get(pctldev, pin); pin_request()
94 "pin %d is not registered so it cannot be requested\n", pin_request()
95 pin); pin_request()
99 dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n", pin_request()
100 pin, desc->name, owner); pin_request()
106 "pin %s already requested by %s; cannot claim for %s\n", pin_request()
113 "pin %s already requested by %s; cannot claim for %s\n", pin_request()
122 "pin %s already requested by %s; cannot claim for %s\n", pin_request()
128 "pin %s already requested by %s; cannot claim for %s\n", pin_request()
140 /* Let each pin increase references to this module */ pin_request()
143 "could not increase module refcount for pin %d\n", pin_request()
144 pin); pin_request()
150 * If there is no kind of request function for the pin we just assume pin_request()
154 /* This requests and enables a single GPIO pin */ pin_request()
155 status = ops->gpio_request_enable(pctldev, gpio_range, pin); pin_request()
157 status = ops->request(pctldev, pin); pin_request()
162 dev_err(pctldev->dev, "request() failed for pin %d\n", pin); pin_request()
178 dev_err(pctldev->dev, "pin-%d (%s) status %d\n", pin_request()
179 pin, owner, status); pin_request()
185 * pin_free() - release a single muxed in pin so something else can be muxed
186 * @pctldev: pin controller device handling this pin
187 * @pin: the pin to free
188 * @gpio_range: the range matching the GPIO pin if this is a request for a
189 * single GPIO pin
193 * once the pin is free. This is done for GPIO request functions.
195 static const char *pin_free(struct pinctrl_dev *pctldev, int pin, pin_free() argument
202 desc = pin_desc_get(pctldev, pin); pin_free()
205 "pin is not registered so it cannot be freed\n"); pin_free()
211 * A pin should not be freed more times than allocated. pin_free()
221 * If there is no kind of request function for the pin we just assume pin_free()
225 ops->gpio_disable_free(pctldev, gpio_range, pin); pin_free()
227 ops->free(pctldev, pin); pin_free()
244 * pinmux_request_gpio() - request pinmuxing for a GPIO pin
245 * @pctldev: pin controller device affected
246 * @pin: the pin to mux in for GPIO
251 unsigned pin, unsigned gpio) pinmux_request_gpio()
256 /* Conjure some name stating what chip and pin this is taken by */ pinmux_request_gpio()
261 ret = pin_request(pctldev, pin, owner, range); pinmux_request_gpio()
269 * pinmux_free_gpio() - release a pin from GPIO muxing
270 * @pctldev: the pin controller device for the pin
271 * @pin: the affected currently GPIO-muxed in pin
274 void pinmux_free_gpio(struct pinctrl_dev *pctldev, unsigned pin, pinmux_free_gpio() argument
279 owner = pin_free(pctldev, pin, range); pinmux_free_gpio()
284 * pinmux_gpio_direction() - set the direction of a single muxed-in GPIO pin
285 * @pctldev: the pin controller handling this pin
287 * @pin: the affected GPIO pin in this controller
288 * @input: true if we set the pin as input, false for output
292 unsigned pin, bool input) pinmux_gpio_direction()
300 ret = ops->gpio_set_direction(pctldev, range, pin, input); pinmux_gpio_direction()
439 "could not request pin %d (%s) from group %s " pinmux_enable_setting()
452 "could not get pin desc for pin %d\n", pinmux_enable_setting()
511 "could not get pin desc for pin %d\n", pinmux_disable_setting()
517 /* And release the pin */ pinmux_disable_setting()
525 "not freeing pin %d (%s) as part of " pinmux_disable_setting()
583 unsigned i, pin; pinmux_pins_show() local
588 seq_puts(s, "Pinmux settings per pin\n"); pinmux_pins_show()
591 "Format: pin (name): mux_owner|gpio_owner (strict) hog?\n"); pinmux_pins_show()
594 "Format: pin (name): mux_owner gpio_owner hog?\n"); pinmux_pins_show()
598 /* The pin number can be retrived from the pin controller descriptor */ pinmux_pins_show()
603 pin = pctldev->desc->pins[i].number; pinmux_pins_show()
604 desc = pin_desc_get(pctldev, pin); pinmux_pins_show()
605 /* Skip if we cannot search the pin */ pinmux_pins_show()
615 seq_printf(s, "pin %d (%s): device %s%s", pinmux_pins_show()
616 pin, pinmux_pins_show()
621 seq_printf(s, "pin %d (%s): GPIO %s", pinmux_pins_show()
622 pin, pinmux_pins_show()
626 seq_printf(s, "pin %d (%s): UNCLAIMED", pinmux_pins_show()
627 pin, pinmux_pins_show()
631 seq_printf(s, "pin %d (%s): %s %s%s", pin, pinmux_pins_show()
640 /* If mux: print function+group claiming the pin */ pinmux_pins_show()
83 pin_request(struct pinctrl_dev *pctldev, int pin, const char *owner, struct pinctrl_gpio_range *gpio_range) pin_request() argument
249 pinmux_request_gpio(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned pin, unsigned gpio) pinmux_request_gpio() argument
290 pinmux_gpio_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned pin, bool input) pinmux_gpio_direction() argument
H A Dcore.h2 * Core private header for the pin control subsystem
21 * struct pinctrl_dev - pin control class device
22 * @node: node to include this pin controller in the global pin controller list
23 * @desc: the pin controller descriptor supplied when initializing this pin
25 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
27 * @gpio_ranges: a list of GPIO ranges that is handled by this pin controller,
29 * @dev: the device entry for this pin controller
30 * @owner: module providing the pin controller, used for refcounting
31 * @driver_data: driver data for drivers registering to the pin controller
36 * @mutex: mutex taken on each pin controller specific action
57 * struct pinctrl - per-device pin control state holder
59 * @dev: the device using this pin control handle
99 * @group_or_pin: the group selector or pin ID to program
101 * hardware. Each individual pin controller defines the format and meaning
115 * @pctldev: pin control device handling to be programmed. Not used for
132 * struct pin_desc - pin descriptor for each physical pin in the arch
133 * @pctldev: corresponding pin control device
134 * @name: a name for the pin, e.g. the name of the pin/pad/finger on a
136 * @dynamic_name: if the name of this pin was dynamically allocated
137 * @mux_usecount: If zero, the pin is not claimed, and @owner should be NULL.
138 * If non-zero, this pin is claimed by @owner. This field is an integer
141 * or pin, and each of these will increment the @usecount.
143 * @mux_setting: The most recent selected mux setting for this pin, if any.
144 * @gpio_owner: If pinctrl_request_gpio() was called for this pin, this is
145 * the name of the GPIO that "owns" this pin.
175 const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
180 unsigned int pin) pin_desc_get()
182 return radix_tree_lookup(&pctldev->pin_desc_tree, pin); pin_desc_get()
179 pin_desc_get(struct pinctrl_dev *pctldev, unsigned int pin) pin_desc_get() argument
H A Dpinctrl-lantiq.c78 const char *group, *pin; ltq_pinctrl_dt_subnode_to_map() local
118 of_property_for_each_string(np, "lantiq,pins", prop, pin) { ltq_pinctrl_dt_subnode_to_map()
123 (*map)->name = pin; ltq_pinctrl_dt_subnode_to_map()
124 (*map)->data.configs.group_or_pin = pin; ltq_pinctrl_dt_subnode_to_map()
226 /* dont assume .mfp is linearly mapped. find the mfp with the correct .pin */ match_mfp()
227 static int match_mfp(const struct ltq_pinmux_info *info, int pin) match_mfp() argument
231 if (info->mfp[i].pin == pin) match_mfp()
237 /* check whether current pin configuration is valid. Negative for failure */ match_group_mux()
242 int i, pin, ret = 0; match_group_mux() local
244 pin = match_mfp(info, grp->pins[i]); match_group_mux()
245 if (pin < 0) { match_group_mux()
246 dev_err(info->dev, "could not find mfp for pin %d\n", match_group_mux()
250 ret = match_mux(&info->mfp[pin], mux); match_group_mux()
252 dev_err(info->dev, "Can't find mux %d on pin%d\n", match_group_mux()
253 mux, pin); match_group_mux()
266 int i, pin, pin_func, ret; ltq_pmx_set() local
270 dev_err(info->dev, "Failed to set the pin group: %s\n", ltq_pmx_set()
275 pin = match_mfp(info, pin_grp->pins[i]); ltq_pmx_set()
276 if (pin < 0) { ltq_pmx_set()
277 dev_err(info->dev, "could not find mfp for pin %d\n", ltq_pmx_set()
281 pin_func = match_mux(&info->mfp[pin], pin_grp->mux); ltq_pmx_set()
282 ret = info->apply_mux(pctrldev, pin, pin_func); ltq_pmx_set()
285 "failed to apply mux %d for pin %d\n", ltq_pmx_set()
286 pin_func, pin); ltq_pmx_set()
295 unsigned pin) ltq_pmx_gpio_request_enable()
298 int mfp = match_mfp(info, pin); ltq_pmx_gpio_request_enable()
302 dev_err(info->dev, "could not find mfp for pin %d\n", pin); ltq_pmx_gpio_request_enable()
308 dev_err(info->dev, "No GPIO function on pin%d\n", mfp); ltq_pmx_gpio_request_enable()
293 ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev, struct pinctrl_gpio_range *range, unsigned pin) ltq_pmx_gpio_request_enable() argument
H A Dpinctrl-at91.c83 * @groups: corresponding pin groups
101 * struct at91_pmx_pin - describes an At91 pin mux
102 * @bank: the bank of the pin
103 * @pin: the pin number in the @bank
104 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
105 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
109 uint32_t pin; member in struct:at91_pmx_pin
115 * struct at91_pin_group - describes an At91 pin group
116 * @name: the name of this specific pin group
117 * @pins_conf: the mux mode for each pin in this group. The size of this
120 * from the driver-local pin enumeration space
158 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
160 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
162 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
164 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
166 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
167 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
329 static inline int pin_to_bank(unsigned pin) pin_to_bank() argument
331 return pin /= MAX_NB_GPIO_PER_BANK; pin_to_bank()
334 static unsigned pin_to_mask(unsigned int pin) pin_to_mask() argument
336 return 1 << pin; pin_to_mask()
339 static unsigned two_bit_pin_value_shift_amount(unsigned int pin) two_bit_pin_value_shift_amount() argument
341 /* return the shift value for a pin for "two bit" per pin registers, two_bit_pin_value_shift_amount()
343 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2) two_bit_pin_value_shift_amount()
344 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); two_bit_pin_value_shift_amount()
347 static unsigned sama5d3_get_drive_register(unsigned int pin) sama5d3_get_drive_register() argument
350 * with two bits per pin */ sama5d3_get_drive_register()
351 return (pin >= MAX_NB_GPIO_PER_BANK/2) sama5d3_get_drive_register()
355 static unsigned at91sam9x5_get_drive_register(unsigned int pin) at91sam9x5_get_drive_register() argument
358 * with two bits per pin */ at91sam9x5_get_drive_register()
359 return (pin >= MAX_NB_GPIO_PER_BANK/2) at91sam9x5_get_drive_register()
368 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) at91_mux_get_pullup() argument
370 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); at91_mux_get_pullup()
381 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) at91_mux_get_multidrive() argument
383 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; at91_mux_get_multidrive()
455 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) at91_mux_get_deglitch() argument
457 return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1; at91_mux_get_deglitch()
465 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) at91_mux_pio3_get_deglitch() argument
467 if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) at91_mux_pio3_get_deglitch()
468 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); at91_mux_pio3_get_deglitch()
480 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) at91_mux_pio3_get_debounce() argument
484 return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) && at91_mux_pio3_get_debounce()
485 ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); at91_mux_pio3_get_debounce()
499 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) at91_mux_pio3_get_pulldown() argument
501 return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1); at91_mux_pio3_get_pulldown()
517 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) at91_mux_pio3_get_schmitt_trig() argument
519 return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1; at91_mux_pio3_get_schmitt_trig()
522 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) read_drive_strength() argument
526 tmp = tmp >> two_bit_pin_value_shift_amount(pin); read_drive_strength()
532 unsigned pin) at91_mux_sama5d3_get_drivestrength()
535 sama5d3_get_drive_register(pin), pin); at91_mux_sama5d3_get_drivestrength()
546 unsigned pin) at91_mux_sam9x5_get_drivestrength()
549 at91sam9x5_get_drive_register(pin), pin); at91_mux_sam9x5_get_drivestrength()
558 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) set_drive_strength() argument
561 unsigned shift = two_bit_pin_value_shift_amount(pin); set_drive_strength()
569 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, at91_mux_sama5d3_set_drivestrength() argument
577 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting); at91_mux_sama5d3_set_drivestrength()
580 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin, at91_mux_sam9x5_set_drivestrength() argument
591 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin, at91_mux_sam9x5_set_drivestrength()
642 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) at91_pin_dbg() argument
644 if (pin->mux) { at91_pin_dbg()
646 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); at91_pin_dbg()
649 pin->bank + 'A', pin->pin, pin->conf); at91_pin_dbg()
654 int index, const struct at91_pmx_pin *pin) pin_check_config()
659 if (pin->bank >= gpio_banks) { pin_check_config()
660 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", pin_check_config()
661 name, index, pin->bank, gpio_banks); pin_check_config()
665 if (!gpio_chips[pin->bank]) { pin_check_config()
666 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n", pin_check_config()
667 name, index, pin->bank); pin_check_config()
671 if (pin->pin >= MAX_NB_GPIO_PER_BANK) { pin_check_config()
672 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", pin_check_config()
673 name, index, pin->pin, MAX_NB_GPIO_PER_BANK); pin_check_config()
677 if (!pin->mux) pin_check_config()
680 mux = pin->mux - 1; pin_check_config()
683 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", pin_check_config()
688 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { pin_check_config()
689 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", pin_check_config()
690 name, index, mux, pin->bank + 'A', pin->pin); pin_check_config()
713 const struct at91_pmx_pin *pin; at91_pmx_set() local
725 pin = &pins_conf[i]; at91_pmx_set()
726 ret = pin_check_config(info, info->groups[group].name, i, pin); at91_pmx_set()
732 pin = &pins_conf[i]; at91_pmx_set()
733 at91_pin_dbg(info->dev, pin); at91_pmx_set()
734 pio = pin_to_controller(info, pin->bank); at91_pmx_set()
739 mask = pin_to_mask(pin->pin); at91_pmx_set()
741 switch (pin->mux) { at91_pmx_set()
762 if (pin->mux) at91_pmx_set()
816 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); at91_gpio_request_enable()
820 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", at91_gpio_request_enable()
834 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); at91_gpio_disable_free()
835 /* Set the pin to some default state, GPIO is usually default */ at91_gpio_disable_free()
852 unsigned pin; at91_pinconf_get() local
862 pin = pin_id % MAX_NB_GPIO_PER_BANK; at91_pinconf_get()
864 if (at91_mux_get_multidrive(pio, pin)) at91_pinconf_get()
867 if (at91_mux_get_pullup(pio, pin)) at91_pinconf_get()
870 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) at91_pinconf_get()
872 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) at91_pinconf_get()
874 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) at91_pinconf_get()
876 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) at91_pinconf_get()
879 *config |= (info->ops->get_drivestrength(pio, pin) at91_pinconf_get()
894 unsigned pin; at91_pinconf_set() local
907 pin = pin_id % MAX_NB_GPIO_PER_BANK; at91_pinconf_set()
908 mask = pin_to_mask(pin); at91_pinconf_set()
925 info->ops->set_drivestrength(pio, pin, at91_pinconf_set()
1051 struct at91_pmx_pin *pin; at91_pinctrl_parse_groups() local
1062 * the binding format is atmel,pins = <bank pin mux CONFIG ...>, at91_pinctrl_parse_groups()
1074 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin), at91_pinctrl_parse_groups()
1082 pin->bank = be32_to_cpu(*list++); at91_pinctrl_parse_groups()
1083 pin->pin = be32_to_cpu(*list++); at91_pinctrl_parse_groups()
1084 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; at91_pinctrl_parse_groups()
1085 pin->mux = be32_to_cpu(*list++); at91_pinctrl_parse_groups()
1086 pin->conf = be32_to_cpu(*list++); at91_pinctrl_parse_groups()
1088 at91_pin_dbg(info->dev, pin); at91_pinctrl_parse_groups()
1089 pin++; at91_pinctrl_parse_groups()
1392 * Then just request_irq() with the pin ID; it works like any ARM IRQ
531 at91_mux_sama5d3_get_drivestrength(void __iomem *pio, unsigned pin) at91_mux_sama5d3_get_drivestrength() argument
545 at91_mux_sam9x5_get_drivestrength(void __iomem *pio, unsigned pin) at91_mux_sam9x5_get_drivestrength() argument
653 pin_check_config(struct at91_pinctrl *info, const char *name, int index, const struct at91_pmx_pin *pin) pin_check_config() argument
H A Dpinconf.c2 * Core driver for the pin config portions of the pin control subsystem
43 pr_err("failed to register map %s (%d): no group/pin given\n", pinconf_validate_map()
58 int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin, pin_config_get_for_pin() argument
65 "cannot get pin configuration, .pin_config_get missing in driver\n"); pin_config_get_for_pin()
69 return ops->pin_config_get(pctldev, pin, config); pin_config_get_for_pin()
90 dev_dbg(pctldev->dev, "cannot get configuration for pin " pin_config_group_get()
114 int pin; pinconf_map_to_setting() local
118 pin = pin_get_from_name(pctldev, pinconf_map_to_setting()
120 if (pin < 0) { pinconf_map_to_setting()
121 dev_err(pctldev->dev, "could not map pin config for \"%s\"", pinconf_map_to_setting()
123 return pin; pinconf_map_to_setting()
125 setting->data.configs.group_or_pin = pin; pinconf_map_to_setting()
128 pin = pinctrl_get_group_selector(pctldev, pinconf_map_to_setting()
130 if (pin < 0) { pinconf_map_to_setting()
133 return pin; pinconf_map_to_setting()
135 setting->data.configs.group_or_pin = pin; pinconf_map_to_setting()
174 "pin_config_set op failed for pin %d\n", pinconf_apply_setting()
235 seq_printf(s, "pin "); pinconf_show_map()
261 seq_printf(s, "pin %s (%d)", pinconf_show_setting()
276 * FIXME: We should really get the pin controler to dump the config pinconf_show_setting()
284 struct seq_file *s, int pin) pinconf_dump_pin()
288 /* no-op when not using generic pin config */ pinconf_dump_pin()
289 pinconf_generic_dump_pins(pctldev, s, NULL, pin); pinconf_dump_pin()
291 ops->pin_config_dbg_show(pctldev, s, pin); pinconf_dump_pin()
297 unsigned i, pin; pinconf_pins_show() local
299 seq_puts(s, "Pin config settings per pin\n"); pinconf_pins_show()
300 seq_puts(s, "Format: pin (name): configs\n"); pinconf_pins_show()
304 /* The pin number can be retrived from the pin controller descriptor */ pinconf_pins_show()
308 pin = pctldev->desc->pins[i].number; pinconf_pins_show()
309 desc = pin_desc_get(pctldev, pin); pinconf_pins_show()
310 /* Skip if we cannot search the pin */ pinconf_pins_show()
314 seq_printf(s, "pin %d (%s):", pin, pinconf_pins_show()
317 pinconf_dump_pin(pctldev, s, pin); pinconf_pins_show()
333 /* no-op when not using generic pin config */ pinconf_dump_group()
346 seq_puts(s, "Pin config settings per pin group\n"); pinconf_groups_show()
403 * map, of the dev/pin/state that was last written to pinconf-config file.
418 /* Parse the pinctrl map and look for the elected pin/state */ for_each_maps()
428 /* We found the right pin */ for_each_maps()
435 seq_printf(s, "No config found for dev/state/pin, expected:\n");
438 seq_printf(s, "Searched pin:%s\n", dbg->pin_name);
458 * map, of a dev/pin/state entry based on user entries to pinconf-config
551 /* Parse the pinctrl map and look for the selected dev/state/pin */ for_each_maps()
560 /* we found the right pin / state, so overwrite config */ for_each_maps()
283 pinconf_dump_pin(struct pinctrl_dev *pctldev, struct seq_file *s, int pin) pinconf_dump_pin() argument
H A Dcore.c2 * Core driver for the pin control subsystem
52 /* Global list of pin control devices (struct pinctrl_dev) */
55 /* List of pin controller handles (struct pinctrl) */
95 * get_pinctrl_dev_from_devname() - look up pin controller device
98 * Looks up a pin control device matching a certain device name or pure device
141 * pin_get_from_name() - look up a pin number from a name
142 * @pctldev: the pin control device to lookup the pin on
143 * @name: the name of the pin to look up
147 unsigned i, pin; pin_get_from_name() local
149 /* The pin number can be retrived from the pin controller descriptor */ pin_get_from_name()
153 pin = pctldev->desc->pins[i].number; pin_get_from_name()
154 desc = pin_desc_get(pctldev, pin); pin_get_from_name()
157 return pin; pin_get_from_name()
164 * pin_get_name_from_id() - look up a pin name from a pin id
165 * @pctldev: the pin control device to lookup the pin on
166 * @name: the name of the pin to look up
168 const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin) pin_get_name() argument
172 desc = pin_desc_get(pctldev, pin); pin_get_name()
174 dev_err(pctldev->dev, "failed to get pin(%d) name\n", pin_get_name()
175 pin); pin_get_name()
183 * pin_is_valid() - check if pin exists on controller
184 * @pctldev: the pin control device to check the pin on
185 * @pin: pin to check, use the local pin controller index number
187 * This tells us whether a certain pin exist on a certain pin controller or
190 bool pin_is_valid(struct pinctrl_dev *pctldev, int pin) pin_is_valid() argument
194 if (pin < 0) pin_is_valid()
198 pindesc = pin_desc_get(pctldev, pin); pin_is_valid()
205 /* Deletes a range of pin descriptors */ pinctrl_free_pindescs()
234 dev_err(pctldev->dev, "pin %d already registered\n", number); pinctrl_register_one_pin()
247 /* Copy basic pin info */ pinctrl_register_one_pin()
260 pr_debug("registered pin %d (%s) on %s\n", pinctrl_register_one_pin()
283 * gpio_to_pin() - GPIO range GPIO number to pin number translation
285 * @gpio: gpio pin to translate to a pin number
287 * Finds the pin number for a given GPIO using the specified GPIO range
289 * and pin list based GPIO ranges is managed correctly by this function.
306 * pinctrl_match_gpio_range() - check if a certain GPIO pin is in range
307 * @pctldev: pin controller device to check
308 * @gpio: gpio pin to check taken from the global GPIO pin space
310 * Tries to match a GPIO pin number to the ranges handled by a certain pin
335 * @gpio: gpio pin to check taken from the global GPIO pin space
342 * certain GPIO pin doesn't have back-end pinctrl device. If the return value
357 /* Loop over the pin controllers */ pinctrl_ready_for_gpio_range()
383 * @gpio: the pin to locate the pin controller for pinctrl_ready_for_gpio_range()
384 * @outdev: the pin control device if found pinctrl_ready_for_gpio_range()
387 * Find the pin controller handling a certain GPIO pin from the pinspace of pinctrl_ready_for_gpio_range()
400 /* Loop over the pin controllers */ pinctrl_get_device_gpio_range()
420 * @pctldev: pin controller device to add the range to
423 * This adds a range of GPIOs to be handled by a certain pin controller. Call
424 * this to register handled ranges after registering your pin controller.
485 * pinctrl_find_gpio_range_from_pin() - locate the GPIO range for a pin
486 * @pctldev: the pin controller device to look in
487 * @pin: a controller-local number to find the range for
491 unsigned int pin) pinctrl_find_gpio_range_from_pin()
502 if (range->pins[a] == pin) pinctrl_find_gpio_range_from_pin()
505 } else if (pin >= range->pin_base && pinctrl_find_gpio_range_from_pin()
506 pin < range->pin_base + range->npins) pinctrl_find_gpio_range_from_pin()
517 * pinctrl_remove_gpio_range() - remove a range of GPIOs fro a pin controller
518 * @pctldev: pin controller device to remove the range from
532 * @pctldev: the pin controller handling the group
533 * @pin_group: the pin group to look up
556 dev_err(pctldev->dev, "does not have pin group %s\n", pinctrl_get_group_selector()
563 * pinctrl_request_gpio() - request a single pin to be used as GPIO
564 * @gpio: the GPIO pin number from the GPIO subsystem number space
575 int pin; pinctrl_request_gpio() local
586 /* Convert to the pin controllers number space */ pinctrl_request_gpio()
587 pin = gpio_to_pin(range, gpio); pinctrl_request_gpio()
589 ret = pinmux_request_gpio(pctldev, range, pin, gpio); pinctrl_request_gpio()
598 * pinctrl_free_gpio() - free control on a single pin, currently used as GPIO
599 * @gpio: the GPIO pin number from the GPIO subsystem number space
610 int pin; pinctrl_free_gpio() local
618 /* Convert to the pin controllers number space */ pinctrl_free_gpio()
619 pin = gpio_to_pin(range, gpio); pinctrl_free_gpio()
621 pinmux_free_gpio(pctldev, pin, range); pinctrl_free_gpio()
632 int pin; pinctrl_gpio_direction() local
641 /* Convert to the pin controllers number space */ pinctrl_gpio_direction()
642 pin = gpio_to_pin(range, gpio); pinctrl_gpio_direction()
643 ret = pinmux_gpio_direction(pctldev, range, pin, input); pinctrl_gpio_direction()
651 * pinctrl_gpio_direction_input() - request a GPIO pin to go into input mode
652 * @gpio: the GPIO pin number from the GPIO subsystem number space
656 * drivers shall *NOT* touch pin control GPIO calls.
665 * pinctrl_gpio_direction_output() - request a GPIO pin to go into output mode
666 * @gpio: the GPIO pin number from the GPIO subsystem number space
670 * drivers shall *NOT* touch pin control GPIO calls.
802 * a pin control handle with pinctrl_get() create_pinctrl()
822 /* Iterate over the pin control maps to locate the right ones */ for_each_maps()
1045 * "unmux a pin"!), but it's not a big deal since the pins pinctrl_select_state()
1138 pr_err("failed to register map %s (%d): no pin control device given\n", pinctrl_register_map()
1191 * pinctrl_register_mappings() - register a set of pin controller mappings
1221 * @pctldev: pin controller device
1233 * @pctldev: pin controller device
1343 unsigned i, pin; pinctrl_pins_show() local
1349 /* The pin number can be retrived from the pin controller descriptor */ pinctrl_pins_show()
1353 pin = pctldev->desc->pins[i].number; pinctrl_pins_show()
1354 desc = pin_desc_get(pctldev, pin); pinctrl_pins_show()
1359 seq_printf(s, "pin %d (%s) ", pin, pinctrl_pins_show()
1362 /* Driver-specific info per pin */ pinctrl_pins_show()
1364 ops->pin_dbg_show(pctldev, s, pin); pinctrl_pins_show()
1384 seq_puts(s, "registered pin groups:\n"); pinctrl_groups_show()
1407 seq_printf(s, "pin %d (%s)\n", pins[i], pname); pinctrl_groups_show()
1537 seq_puts(s, "Requested pin control handlers their pinmux maps:\n"); pinctrl_show()
1729 * pinctrl_register() - register a pin controller device
1730 * @pctldesc: descriptor for this pin controller
1731 * @dev: parent device for this pin controller
1732 * @driver_data: private pin controller data for this pin controller
1751 /* Initialize pin control device struct */ pinctrl_register()
1785 dev_err(dev, "error during pin registration\n"); pinctrl_register()
1829 * @pctldev: pin controller to unregister
490 pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev, unsigned int pin) pinctrl_find_gpio_range_from_pin() argument
H A Dpinctrl-tz1090.c68 * @groups: An array of pin groups that may select this function.
95 * struct tz1090_pingroup - TZ1090 pin group
96 * @name: Name of pin group.
97 * @pins: Array of pin numbers in this pin group.
98 * @npins: Number of pins in this pin group.
107 * A representation of a group of pins (possibly just one pin) in the TZ1090
108 * pin controller. Each group allows some parameter or parameters to be
339 /* Pins in each pin group */
488 /* Pins in each drive pin group */
543 /* individual pins not part of a pin mux group */
669 /* magic per-non-muxing-GPIO-pin peripheral mode mux */
754 * DEFINE_SUBMUX() - Defines a submux description separate from a pin group.
791 * MUX_PG() - Initialise a pin group with mux control
813 * SIMPLE_PG() - Initialise a simple convenience pin group
816 * A simple pin group is simply used for binding pins together so they can be
817 * referred to by a single name instead of having to list every pin
828 * DRV_PG() - Initialise a pin group with drive control
843 * Define main muxing pin groups
857 * These are the pin mux groups. Pin muxing can be enabled and disabled for each
858 * pin individually so these groups are internal. The mapping of pins to pin mux
862 /* Muxing pin groups */
873 * This is the mapping from GPIO pins to pin mux groups in tz1090_mux_groups[].
876 * peripheral control of the pin.
886 * tz1090_init_mux_pins() - Initialise GPIO pin to mux group mapping.
888 * Initialises the tz1090_mux_pins[] array to be the inverse of the pin lists in
889 * each pin mux group in tz1090_mux_groups[].
891 * It is assumed that no pin mux groups overlap (share pins).
897 const unsigned int *pin; tz1090_init_mux_pins() local
905 for (pin = grp->pins, p = 0; p < grp->npins; ++p, ++pin) tz1090_init_mux_pins()
906 tz1090_mux_pins[*pin] = g; tz1090_init_mux_pins()
910 * These are the externally visible pin groups. Some of them allow group control
912 * internal pin mux groups in tz1090_mux_groups[] are mirrored here with the
914 * Pseudo pin groups follow in the group numbers after this array for each GPIO
915 * pin. Any group used for muxing must have all pins belonging to the same pin
931 * Drive specific pin groups (with odd combinations of pins which makes
932 * the pin group naming somewhat arbitrary)
940 /* Convenience pin groups */
949 /* pseudo-pingroups for each GPIO pin follow */
984 /* each GPIO pin has it's own pseudo pingroup containing only itself */
998 /* individual gpio pin pseudo-pingroup */ tz1090_pinctrl_get_group_name()
999 unsigned int pin = group - ARRAY_SIZE(tz1090_groups); tz1090_pinctrl_get_group_name() local
1000 return tz1090_pins[pin].name; tz1090_pinctrl_get_group_name()
1014 /* individual gpio pin pseudo-pingroup */ tz1090_pinctrl_get_group_pins()
1015 unsigned int pin = group - ARRAY_SIZE(tz1090_groups); tz1090_pinctrl_get_group_pins() local
1016 *pins = &tz1090_pins[pin].number; tz1090_pinctrl_get_group_pins()
1244 * @pin: Pin number (must be within GPIO range)
1247 unsigned int pin) tz1090_pinctrl_select()
1254 pmx_index = pin >> 5; tz1090_pinctrl_select()
1255 pmx_shift = pin & 0x1f; tz1090_pinctrl_select()
1262 reg = REG_PINCTRL_SELECT + 4*(pin / 30); tz1090_pinctrl_select()
1263 reg_shift = pin % 30; tz1090_pinctrl_select()
1275 * tz1090_pinctrl_gpio_select() - enable/disable GPIO usage for a pin
1277 * @pin: Pin number
1278 * @gpio_select: true to enable pin as GPIO,
1285 unsigned int pin, tz1090_pinctrl_gpio_select()
1291 if (pin >= NUM_GPIOS) tz1090_pinctrl_gpio_select()
1295 index = pin >> 5; tz1090_pinctrl_gpio_select()
1296 shift = pin & 0x1f; tz1090_pinctrl_gpio_select()
1308 tz1090_pinctrl_select(pmx, pin); tz1090_pinctrl_gpio_select()
1314 * tz1090_pinctrl_perip_select() - enable/disable peripheral interface for a pin
1316 * @pin: Pin number
1318 * false to leave pin in GPIO mode
1324 unsigned int pin, tz1090_pinctrl_perip_select()
1330 if (pin >= NUM_GPIOS) tz1090_pinctrl_perip_select()
1334 index = pin >> 5; tz1090_pinctrl_perip_select()
1335 shift = pin & 0x1f; tz1090_pinctrl_perip_select()
1347 tz1090_pinctrl_select(pmx, pin); tz1090_pinctrl_perip_select()
1353 * tz1090_pinctrl_enable_mux() - Switch a pin mux group to a function.
1358 * Enable a particular function on a pin mux group. Since pin mux descriptions
1406 * tz1090_pinctrl_enable() - Enable a function on a pin group.
1411 * Enable a particular function on a group of pins. The per GPIO pin pseudo pin
1412 * groups can be used (in which case the pin will be enabled in peripheral mode
1413 * and if it belongs to a pin mux group the mux will be switched if it isn't
1414 * already in use. Some convenience pin groups can also be used in which case
1415 * the effect is the same as enabling the function on each individual pin in the
1434 * which allows us to just use the mux group of the first pin. tz1090_pinctrl_set_mux()
1456 "%s: can't mux pin(s) to '%s', group already muxed to '%s'\n", tz1090_pinctrl_set_mux()
1462 dev_dbg(pctldev->dev, "%s: muxing %u pin(s) in '%s' to '%s'\n", tz1090_pinctrl_set_mux()
1465 /* if first pin in mux group to be enabled, enable the group mux */ tz1090_pinctrl_set_mux()
1482 * tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode.
1485 * @pin: Pin number
1487 * Puts a particular pin into GPIO mode, disabling peripheral control until it's
1492 unsigned int pin) tz1090_pinctrl_gpio_request_enable()
1495 tz1090_pinctrl_gpio_select(pmx, pin, true); tz1090_pinctrl_gpio_request_enable()
1500 * tz1090_pinctrl_gpio_disable_free() - Take pin out of GPIO mode.
1503 * @pin: Pin number
1505 * Take a particular pin out of GPIO mode. If the pin is enabled for a
1510 unsigned int pin) tz1090_pinctrl_gpio_disable_free()
1513 tz1090_pinctrl_gpio_select(pmx, pin, false); tz1090_pinctrl_gpio_disable_free()
1534 /* The mapping of pin to pull up/down register index and shift */
1639 unsigned int pin, tz1090_pinconf_reg()
1667 pu = &tz1090_pinconf_pullup[pin]; tz1090_pinconf_reg()
1679 unsigned int pin, unsigned long *config) tz1090_pinconf_get()
1687 ret = tz1090_pinconf_reg(pctldev, pin, param, true, tz1090_pinconf_get()
1707 unsigned int pin, unsigned long *configs, tz1090_pinconf_set()
1722 dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", tz1090_pinconf_set()
1723 __func__, tz1090_pins[pin].name, configs[i]); tz1090_pinconf_set()
1726 ret = tz1090_pinconf_reg(pctldev, pin, param, true, tz1090_pinconf_set()
1810 unsigned int pin; tz1090_pinconf_group_get() local
1815 pin = group - ARRAY_SIZE(tz1090_groups); tz1090_pinconf_group_get()
1816 return tz1090_pinconf_get(pctldev, pin, config); tz1090_pinconf_group_get()
1821 pin = g->pins[0]; tz1090_pinconf_group_get()
1822 ret = tz1090_pinconf_get(pctldev, pin, config); tz1090_pinconf_group_get()
1852 unsigned int arg, pin, i; tz1090_pinconf_group_set() local
1861 pin = group - ARRAY_SIZE(tz1090_groups); tz1090_pinconf_group_set()
1862 return tz1090_pinconf_set(pctldev, pin, configs, num_configs); tz1090_pinconf_group_set()
1867 pin = g->pins[0]; tz1090_pinconf_group_set()
1868 ret = tz1090_pinconf_set(pctldev, pin, configs, num_configs); tz1090_pinconf_group_set()
1884 * Maybe we're trying to set a per-pin configuration tz1090_pinconf_group_set()
1246 tz1090_pinctrl_select(struct tz1090_pmx *pmx, unsigned int pin) tz1090_pinctrl_select() argument
1284 tz1090_pinctrl_gpio_select(struct tz1090_pmx *pmx, unsigned int pin, bool gpio_select) tz1090_pinctrl_gpio_select() argument
1323 tz1090_pinctrl_perip_select(struct tz1090_pmx *pmx, unsigned int pin, bool perip_select) tz1090_pinctrl_perip_select() argument
1490 tz1090_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin) tz1090_pinctrl_gpio_request_enable() argument
1508 tz1090_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin) tz1090_pinctrl_gpio_disable_free() argument
1638 tz1090_pinconf_reg(struct pinctrl_dev *pctldev, unsigned int pin, enum pin_config_param param, bool report_err, u32 *reg, u32 *width, u32 *mask, u32 *shift, u32 *val) tz1090_pinconf_reg() argument
1678 tz1090_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) tz1090_pinconf_get() argument
1706 tz1090_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned num_configs) tz1090_pinconf_set() argument
H A Dpinmux.h2 * Internal interface between the core pin control system and the
21 unsigned pin, unsigned gpio);
22 void pinmux_free_gpio(struct pinctrl_dev *pctldev, unsigned pin,
26 unsigned pin, bool input);
48 unsigned pin, unsigned gpio) pinmux_request_gpio()
54 unsigned pin, pinmux_free_gpio()
61 unsigned pin, bool input) pinmux_gpio_direction()
46 pinmux_request_gpio(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned pin, unsigned gpio) pinmux_request_gpio() argument
53 pinmux_free_gpio(struct pinctrl_dev *pctldev, unsigned pin, struct pinctrl_gpio_range *range) pinmux_free_gpio() argument
59 pinmux_gpio_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned pin, bool input) pinmux_gpio_direction() argument
H A Dpinconf.h2 * Internal interface between the core pin control system and the
3 * pin config portions
27 int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
90 * pin config.
97 unsigned pin);
105 const char *gname, unsigned pin) pinconf_generic_dump_pins()
103 pinconf_generic_dump_pins(struct pinctrl_dev *pctldev, struct seq_file *s, const char *gname, unsigned pin) pinconf_generic_dump_pins() argument
H A Dpinctrl-pistachio.c30 #define PADS_SCHMITT_EN_REG(pin) (PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32))
31 #define PADS_SCHMITT_EN_BIT(pin) BIT((pin) % 32)
34 #define PADS_PU_PD_REG(pin) (PADS_PU_PD0 + 0x4 * ((pin) / 16))
35 #define PADS_PU_PD_SHIFT(pin) (2 * ((pin) % 16))
48 #define PADS_SLEW_RATE_REG(pin) (PADS_SLEW_RATE0 + 0x4 * ((pin) / 32))
49 #define PADS_SLEW_RATE_BIT(pin) BIT((pin) % 32)
52 #define PADS_DRIVE_STRENGTH_REG(pin) \
53 (PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16))
54 #define PADS_DRIVE_STRENGTH_SHIFT(pin) (2 * ((pin) % 16))
90 unsigned int pin; member in struct:pistachio_pin_group
641 .pin = PISTACHIO_PIN_##_pin, \
655 .pin = PISTACHIO_PIN_MFIO(_pin), \
669 .pin = PISTACHIO_PIN_MFIO(_pin), \
910 *pins = &pctl->groups[group].pin; pistachio_pinctrl_get_group_pins()
968 dev_err(pctl->dev, "Cannot mux pin %u to function %u\n", pistachio_pinmux_enable()
993 range = pinctrl_find_gpio_range_from_pin(pctl->pctldev, pg->pin); pistachio_pinmux_enable()
995 gpio_disable(gc_to_bank(range->gc), pg->pin - range->pin_base); pistachio_pinmux_enable()
1007 static int pistachio_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, pistachio_pinconf_get() argument
1016 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin)); pistachio_pinconf_get()
1017 arg = !!(val & PADS_SCHMITT_EN_BIT(pin)); pistachio_pinconf_get()
1020 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> pistachio_pinconf_get()
1021 PADS_PU_PD_SHIFT(pin); pistachio_pinconf_get()
1025 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> pistachio_pinconf_get()
1026 PADS_PU_PD_SHIFT(pin); pistachio_pinconf_get()
1030 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> pistachio_pinconf_get()
1031 PADS_PU_PD_SHIFT(pin); pistachio_pinconf_get()
1035 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> pistachio_pinconf_get()
1036 PADS_PU_PD_SHIFT(pin); pistachio_pinconf_get()
1040 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin)); pistachio_pinconf_get()
1041 arg = !!(val & PADS_SLEW_RATE_BIT(pin)); pistachio_pinconf_get()
1044 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >> pistachio_pinconf_get()
1045 PADS_DRIVE_STRENGTH_SHIFT(pin); pistachio_pinconf_get()
1072 static int pistachio_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, pistachio_pinconf_set() argument
1086 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin)); pistachio_pinconf_set()
1088 val |= PADS_SCHMITT_EN_BIT(pin); pistachio_pinconf_set()
1090 val &= ~PADS_SCHMITT_EN_BIT(pin); pistachio_pinconf_set()
1091 pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin)); pistachio_pinconf_set()
1094 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); pistachio_pinconf_set()
1095 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); pistachio_pinconf_set()
1096 val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin); pistachio_pinconf_set()
1097 pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); pistachio_pinconf_set()
1100 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); pistachio_pinconf_set()
1101 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); pistachio_pinconf_set()
1102 val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin); pistachio_pinconf_set()
1103 pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); pistachio_pinconf_set()
1106 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); pistachio_pinconf_set()
1107 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); pistachio_pinconf_set()
1108 val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin); pistachio_pinconf_set()
1109 pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); pistachio_pinconf_set()
1112 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); pistachio_pinconf_set()
1113 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin)); pistachio_pinconf_set()
1114 val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin); pistachio_pinconf_set()
1115 pctl_writel(pctl, val, PADS_PU_PD_REG(pin)); pistachio_pinconf_set()
1118 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin)); pistachio_pinconf_set()
1120 val |= PADS_SLEW_RATE_BIT(pin); pistachio_pinconf_set()
1122 val &= ~PADS_SLEW_RATE_BIT(pin); pistachio_pinconf_set()
1123 pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin)); pistachio_pinconf_set()
1126 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)); pistachio_pinconf_set()
1128 PADS_DRIVE_STRENGTH_SHIFT(pin)); pistachio_pinconf_set()
1148 val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin); pistachio_pinconf_set()
1149 pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin)); pistachio_pinconf_set()
1309 unsigned int pin; pistachio_gpio_irq_handler() local
1314 for_each_set_bit(pin, &pending, 16) pistachio_gpio_irq_handler()
1315 generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin)); pistachio_gpio_irq_handler()
H A Dpinctrl-st.c76 * each register is dedicated per pin.
253 int pin; member in struct:st_pinconf
276 * of each gpio pin in a GPIO bank.
279 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
281 * bit allocation per pin is:
284 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
287 * A pin can have one of following the values in its edge configuration field.
305 #define ST_IRQ_RISING_EDGE_CONF(pin) \
306 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
308 #define ST_IRQ_FALLING_EDGE_CONF(pin) \
309 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
311 #define ST_IRQ_BOTH_EDGE_CONF(pin) \
312 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
314 #define ST_IRQ_EDGE_CONF(conf, pin) \
315 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
404 struct pinctrl_dev *pctldev, int pin) st_get_pio_control()
407 pinctrl_find_gpio_range_from_pin(pctldev, pin); st_get_pio_control()
425 int pin, unsigned long config) st_pinconf_set_config()
431 unsigned long mask = BIT(pin); st_pinconf_set_config()
463 int pin = st_gpio_pin(pin_id); st_pctl_set_function() local
464 int offset = pin * 4; st_pctl_set_function()
475 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin) st_pctl_get_pin_function() argument
479 int offset = pin * 4; st_pctl_get_pin_function()
545 int enable, int pin) st_regmap_field_bit_set_clear_pin()
551 val |= BIT(pin); st_regmap_field_bit_set_clear_pin()
553 val &= ~BIT(pin); st_regmap_field_bit_set_clear_pin()
558 struct st_pio_control *pc, unsigned long config, int pin) st_pinconf_set_retime_packed()
565 ST_PINCONF_UNPACK_RT_CLK(config), pin); st_pinconf_set_retime_packed()
568 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); st_pinconf_set_retime_packed()
571 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); st_pinconf_set_retime_packed()
574 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); st_pinconf_set_retime_packed()
577 ST_PINCONF_UNPACK_RT(config), pin); st_pinconf_set_retime_packed()
582 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); st_pinconf_set_retime_packed()
584 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); st_pinconf_set_retime_packed()
589 struct st_pio_control *pc, unsigned long config, int pin) st_pinconf_set_retime_dedicated()
612 regmap_field_write(rt_d->rt[pin], retime_config); st_pinconf_set_retime_dedicated()
616 int pin, unsigned long *config) st_pinconf_get_direction()
622 if (oe_value & BIT(pin)) st_pinconf_get_direction()
628 if (pu_value & BIT(pin)) st_pinconf_get_direction()
634 if (od_value & BIT(pin)) st_pinconf_get_direction()
640 struct st_pio_control *pc, int pin, unsigned long *config) st_pinconf_get_retime_packed()
647 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) st_pinconf_get_retime_packed()
650 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) st_pinconf_get_retime_packed()
653 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) st_pinconf_get_retime_packed()
656 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) st_pinconf_get_retime_packed()
659 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) st_pinconf_get_retime_packed()
664 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | st_pinconf_get_retime_packed()
665 (((delay0 & BIT(pin)) ? 1 : 0)); st_pinconf_get_retime_packed()
673 struct st_pio_control *pc, int pin, unsigned long *config) st_pinconf_get_retime_dedicated()
680 regmap_field_read(rt_d->rt[pin], &value); st_pinconf_get_retime_dedicated()
723 * PIO port pins. Each pin can be configured as an input, output, st_gpio_direction()
724 * bidirectional, or alternative function pin. Three bits, one bit st_gpio_direction()
898 /* create config map per pin */ st_pctl_dt_node_to_map()
961 pc = st_get_pio_control(pctldev, conf[i].pin); st_pmx_set_mux()
962 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); st_pmx_set_mux()
995 struct st_pio_control *pc, int pin, unsigned long *config) st_pinconf_get_retime()
998 st_pinconf_get_retime_packed(info, pc, pin, config); st_pinconf_get_retime()
1000 if ((BIT(pin) & pc->rt_pin_mask)) st_pinconf_get_retime()
1002 pin, config); st_pinconf_get_retime()
1006 struct st_pio_control *pc, int pin, unsigned long config) st_pinconf_set_retime()
1009 st_pinconf_set_retime_packed(info, pc, config, pin); st_pinconf_set_retime()
1011 if ((BIT(pin) & pc->rt_pin_mask)) st_pinconf_set_retime()
1013 config, pin); st_pinconf_set_retime()
1019 int pin = st_gpio_pin(pin_id); st_pinconf_set() local
1025 st_pinconf_set_config(pc, pin, configs[i]); st_pinconf_set()
1026 st_pinconf_set_retime(info, pc, pin, configs[i]); st_pinconf_set()
1035 int pin = st_gpio_pin(pin_id); st_pinconf_get() local
1040 st_pinconf_get_direction(pc, pin, config); st_pinconf_get()
1041 st_pinconf_get_retime(info, pc, pin, config); st_pinconf_get()
1208 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); st_parse_syscfgs()
1215 * Each pin is represented in of the below forms.
1265 conf->pin = of_get_named_gpio(pins, pp->name, 0); for_each_property_of_node()
1267 grp->pins[i] = conf->pin; for_each_property_of_node()
1346 int comp, pin = d->hwirq; st_gpio_irq_set_type() local
1356 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); st_gpio_irq_set_type()
1363 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); st_gpio_irq_set_type()
1366 comp = st_gpio_get(&bank->gpio_chip, pin); st_gpio_irq_set_type()
1367 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); st_gpio_irq_set_type()
1375 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); st_gpio_irq_set_type()
1380 val &= ~BIT(pin); st_gpio_irq_set_type()
1381 val |= (comp << pin); st_gpio_irq_set_type()
1393 * Step 1: CONFIGURE pin to detect level LOW interrupts.
1396 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
1397 * IGNORE calling the actual interrupt handler for the pin at this stage.
1400 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
1401 * DISPATCH the interrupt to the interrupt handler of the pin.
403 st_get_pio_control( struct pinctrl_dev *pctldev, int pin) st_get_pio_control() argument
424 st_pinconf_set_config(struct st_pio_control *pc, int pin, unsigned long config) st_pinconf_set_config() argument
544 st_regmap_field_bit_set_clear_pin(struct regmap_field *field, int enable, int pin) st_regmap_field_bit_set_clear_pin() argument
557 st_pinconf_set_retime_packed(struct st_pinctrl *info, struct st_pio_control *pc, unsigned long config, int pin) st_pinconf_set_retime_packed() argument
588 st_pinconf_set_retime_dedicated(struct st_pinctrl *info, struct st_pio_control *pc, unsigned long config, int pin) st_pinconf_set_retime_dedicated() argument
615 st_pinconf_get_direction(struct st_pio_control *pc, int pin, unsigned long *config) st_pinconf_get_direction() argument
639 st_pinconf_get_retime_packed(struct st_pinctrl *info, struct st_pio_control *pc, int pin, unsigned long *config) st_pinconf_get_retime_packed() argument
672 st_pinconf_get_retime_dedicated(struct st_pinctrl *info, struct st_pio_control *pc, int pin, unsigned long *config) st_pinconf_get_retime_dedicated() argument
994 st_pinconf_get_retime(struct st_pinctrl *info, struct st_pio_control *pc, int pin, unsigned long *config) st_pinconf_get_retime() argument
1005 st_pinconf_set_retime(struct st_pinctrl *info, struct st_pio_control *pc, int pin, unsigned long config) st_pinconf_set_retime() argument
H A Dpinctrl-at91-pio4.c37 * designed the pin id into this bank.
82 u32 pin; member in struct:atmel_group
100 * @groups: groups table to provide group name and pin in the group to pinctrl.
101 * @group_names: group names table to provide all the group/pin names to
163 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; atmel_gpio_irq_set_type() local
166 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, atmel_gpio_irq_set_type()
167 BIT(pin->line)); atmel_gpio_irq_set_type()
168 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); atmel_gpio_irq_set_type()
197 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); atmel_gpio_irq_set_type()
205 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; atmel_gpio_irq_mask() local
207 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, atmel_gpio_irq_mask()
208 BIT(pin->line)); atmel_gpio_irq_mask()
214 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; atmel_gpio_irq_unmask() local
216 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER, atmel_gpio_irq_unmask()
217 BIT(pin->line)); atmel_gpio_irq_unmask()
294 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; atmel_gpio_direction_input() local
297 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, atmel_gpio_direction_input()
298 BIT(pin->line)); atmel_gpio_direction_input()
299 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); atmel_gpio_direction_input()
301 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); atmel_gpio_direction_input()
309 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; atmel_gpio_get() local
312 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); atmel_gpio_get()
314 return !!(reg & BIT(pin->line)); atmel_gpio_get()
321 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; atmel_gpio_direction_output() local
324 atmel_gpio_write(atmel_pioctrl, pin->bank, atmel_gpio_direction_output()
326 BIT(pin->line)); atmel_gpio_direction_output()
328 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, atmel_gpio_direction_output()
329 BIT(pin->line)); atmel_gpio_direction_output()
330 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); atmel_gpio_direction_output()
332 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); atmel_gpio_direction_output()
340 struct atmel_pin *pin = atmel_pioctrl->pins[offset]; atmel_gpio_set() local
342 atmel_gpio_write(atmel_pioctrl, pin->bank, atmel_gpio_set()
344 BIT(pin->line)); atmel_gpio_set()
374 /* Have to set MSKR first, to access the right pin CFGR. */ atmel_pin_config_read()
390 /* Have to set MSKR first, to access the right pin CFGR. */ atmel_pin_config_write()
416 *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin; atmel_pctl_get_group_pins()
423 unsigned pin) atmel_pctl_find_group_by_pin()
431 if (grp->pin == pin) atmel_pctl_find_group_by_pin()
508 * map for each pin. atmel_pctl_dt_subnode_to_map()
622 unsigned pin; atmel_pmx_set_mux() local
628 pin = atmel_pioctrl->groups[group].pin; atmel_pmx_set_mux()
629 conf = atmel_pin_config_read(pctldev, pin); atmel_pmx_set_mux()
632 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf); atmel_pmx_set_mux()
633 atmel_pin_config_write(pctldev, pin, conf); atmel_pmx_set_mux()
652 unsigned pin_id = grp->pin; atmel_conf_pin_config_group_get()
700 unsigned bank, pin, pin_id = grp->pin; atmel_conf_pin_config_group_set() local
710 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", atmel_conf_pin_config_group_set()
757 pin = ATMEL_PIO_LINE(pin_id); atmel_conf_pin_config_group_set()
758 mask = 1 << pin; atmel_conf_pin_config_group_set()
933 /* One pin is one group since a pin can achieve all functions. */ atmel_pinctrl_probe()
965 group->pin = pin_desc[i].number; atmel_pinctrl_probe()
1051 dev_err(dev, "failed to add gpio pin range\n"); atmel_pinctrl_probe()
422 atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin) atmel_pctl_find_group_by_pin() argument
H A Dpinconf-generic.c2 * Core driver for the generic pin config portions of the pin control subsystem
36 "input bias pull to pin specific state", NULL, false),
46 PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode", true),
47 PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true),
48 PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
54 unsigned pin, pinconf_generic_dump_one()
70 ret = pin_config_get_for_pin(pctldev, pin, &config); pinconf_generic_dump_one()
94 * pinconf_generic_dump_pins - Print information about pin or group of pins
98 * @pin: Pin number specyfying pin
100 * Print the pinconf configuration for the requested pin(s) to @s. Pins can be
101 * specified either by pin using @pin or by group using @gname. Only one needs
105 const char *gname, unsigned pin) pinconf_generic_dump_pins()
113 pinconf_generic_dump_one(pctldev, s, gname, pin, conf_items, pinconf_generic_dump_pins()
118 pinconf_generic_dump_one(pctldev, s, gname, pin, pinconf_generic_dump_pins()
157 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
52 pinconf_generic_dump_one(struct pinctrl_dev *pctldev, struct seq_file *s, const char *gname, unsigned pin, const struct pin_config_item *items, int nitems) pinconf_generic_dump_one() argument
104 pinconf_generic_dump_pins(struct pinctrl_dev *pctldev, struct seq_file *s, const char *gname, unsigned pin) pinconf_generic_dump_pins() argument
H A Dpinctrl-tz1090-pdc.c70 * @groups: An array of pin groups that may select this function.
80 * struct tz1090_pdc_pingroup - TZ1090 PDC pin group
81 * @name: Name of pin group.
82 * @pins: Array of pin numbers in this pin group.
83 * @npins: Number of pins in this pin group.
90 * A representation of a group of pins (possibly just one pin) in the TZ1090
91 * PDC pin controller. Each group allows some parameter or parameters to be
186 * MUX_PG() - Initialise a pin group with mux control
203 * DRV_PG() - Initialise a pin group with drive control
215 /* Muxing pin groups */
220 /* Drive pin groups */
330 * @pin_group: the pin group to look up
366 * We support both pins and pin groups, but we need to figure out which add_map_configs()
570 /* record the pin being muxed and update mux bit */ tz1090_pdc_pinctrl_set_mux()
580 unsigned int pin) find_mux_group()
591 /* with a matching pin */ find_mux_group()
592 if (grp->pins[0] == pin) find_mux_group()
602 unsigned int pin) tz1090_pdc_pinctrl_gpio_request_enable()
605 const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin); tz1090_pdc_pinctrl_gpio_request_enable()
608 /* record the pin in GPIO use and update mux bit */ tz1090_pdc_pinctrl_gpio_request_enable()
610 pmx->gpio_en |= BIT(pin); tz1090_pdc_pinctrl_gpio_request_enable()
620 unsigned int pin) tz1090_pdc_pinctrl_gpio_disable_free()
623 const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin); tz1090_pdc_pinctrl_gpio_disable_free()
626 /* record the pin not in GPIO use and update mux bit */ tz1090_pdc_pinctrl_gpio_disable_free()
628 pmx->gpio_en &= ~BIT(pin); tz1090_pdc_pinctrl_gpio_disable_free()
648 unsigned int pin, tz1090_pdc_pinconf_reg()
675 *shift = REG_GPIO_CONTROL2_PU_PD_S + pin*2; tz1090_pdc_pinconf_reg()
685 unsigned int pin, unsigned long *config) tz1090_pdc_pinconf_get()
693 ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, tz1090_pdc_pinconf_get()
713 unsigned int pin, unsigned long *configs, tz1090_pdc_pinconf_set()
728 dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", tz1090_pdc_pinconf_set()
729 __func__, tz1090_pdc_pins[pin].name, configs[i]); tz1090_pdc_pinconf_set()
732 ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, tz1090_pdc_pinconf_set()
869 * Maybe we're trying to set a per-pin configuration tz1090_pdc_pinconf_group_set()
578 find_mux_group( struct tz1090_pdc_pmx *pmx, unsigned int pin) find_mux_group() argument
599 tz1090_pdc_pinctrl_gpio_request_enable( struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin) tz1090_pdc_pinctrl_gpio_request_enable() argument
617 tz1090_pdc_pinctrl_gpio_disable_free( struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin) tz1090_pdc_pinctrl_gpio_disable_free() argument
647 tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev, unsigned int pin, enum pin_config_param param, bool report_err, u32 *reg, u32 *width, u32 *mask, u32 *shift, u32 *val) tz1090_pdc_pinconf_reg() argument
684 tz1090_pdc_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) tz1090_pdc_pinconf_get() argument
712 tz1090_pdc_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned num_configs) tz1090_pdc_pinconf_set() argument
H A Dpinctrl-tegra.h70 * @groups: An array of pin groups that may select this function.
80 * struct tegra_pingroup - Tegra pin group
81 * @name The name of the pin group.
82 * @pins An array of pin IDs included in this pin group.
122 * A representation of a group of pins (possibly just one pin) in the Tegra
123 * pin controller. Each group allows some parameter or parameters to be
125 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
165 * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
166 * @ngpios: The number of GPIO pins the pin controller HW affects.
167 * @pins: An array describing all pins the pin controller affects.
174 * @groups: An array describing all pin groups the pin SoC supports.
H A Dpinctrl-xway.c33 /* we have 2 mux bits that can be set for each pin */
68 .pin = a, \
110 /* pin f0 f1 f2 f3 */
170 /* pin f0 f1 f2 f3 */
450 unsigned pin, xway_pinconf_get()
455 int port = PORT(pin); xway_pinconf_get()
463 reg = GPIO_OD(pin); xway_pinconf_get()
465 !gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); xway_pinconf_get()
472 reg = GPIO_PUDEN(pin); xway_pinconf_get()
473 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) { xway_pinconf_get()
481 reg = GPIO_PUDSEL(pin); xway_pinconf_get()
482 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) xway_pinconf_get()
489 reg = GPIO_DIR(pin); xway_pinconf_get()
491 gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); xway_pinconf_get()
501 unsigned pin, xway_pinconf_set()
508 int port = PORT(pin); xway_pinconf_set()
521 reg = GPIO_OD(pin); xway_pinconf_set()
525 PORT_PIN(pin)); xway_pinconf_set()
529 PORT_PIN(pin)); xway_pinconf_set()
536 reg = GPIO_PUDEN(pin); xway_pinconf_set()
540 PORT_PIN(pin)); xway_pinconf_set()
543 gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); xway_pinconf_set()
548 reg = GPIO_PUDSEL(pin); xway_pinconf_set()
552 PORT_PIN(pin)); xway_pinconf_set()
556 PORT_PIN(pin)); xway_pinconf_set()
563 reg = GPIO_DIR(pin); xway_pinconf_set()
567 PORT_PIN(pin)); xway_pinconf_set()
571 PORT_PIN(pin)); xway_pinconf_set()
613 int pin, int mux) xway_mux_apply()
616 int port = PORT(pin); xway_mux_apply()
617 u32 alt1_reg = GPIO_ALT1(pin); xway_mux_apply()
623 gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); xway_mux_apply()
625 gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); xway_mux_apply()
628 gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin)); xway_mux_apply()
630 gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin)); xway_mux_apply()
649 static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val) xway_gpio_set() argument
654 gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); xway_gpio_set()
656 gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); xway_gpio_set()
659 static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin) xway_gpio_get() argument
663 return gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin)); xway_gpio_get()
666 static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) xway_gpio_dir_in() argument
670 gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); xway_gpio_dir_in()
675 static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val) xway_gpio_dir_out() argument
679 gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); xway_gpio_dir_out()
680 xway_gpio_set(chip, pin, val); xway_gpio_dir_out()
449 xway_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config) xway_pinconf_get() argument
500 xway_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs, unsigned num_configs) xway_pinconf_set() argument
612 xway_mux_apply(struct pinctrl_dev *pctrldev, int pin, int mux) xway_mux_apply() argument
H A Dpinctrl-rockchip.c94 * @pin_base: first pin number
180 * @name: name of the pin group, used to lookup the group.
184 * @configs: the config values to be set for each pin
185 * @nconfigs: number of configs for each pin
195 * struct rockchip_pmx_func: represent a pin function.
196 * @name: name of the pin function, used to lookup the function.
197 * @groups: one or more names of pin groups that provide this function.
247 * given a pin number that is local to a pin controller, find out the pin bank
248 * and the register base of the pin bank.
251 unsigned pin) pin_to_bank()
255 while (pin >= (b->pin_base + b->nr_pins)) pin_to_bank()
385 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) rockchip_get_mux() argument
388 int iomux_num = (pin / 8); rockchip_get_mux()
398 dev_err(info->dev, "pin %d is unrouted\n", pin); rockchip_get_mux()
412 if ((pin % 8) >= 4) rockchip_get_mux()
414 bit = (pin % 4) * 4; rockchip_get_mux()
416 bit = (pin % 8) * 2; rockchip_get_mux()
427 * Set a new mux function for a pin.
433 * All pin settings seem to be 2 bit wide in both the upper and lower
435 * @bank: pin bank to change
436 * @pin: pin to change
439 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) rockchip_set_mux() argument
442 int iomux_num = (pin / 8); rockchip_set_mux()
453 dev_err(info->dev, "pin %d is unrouted\n", pin); rockchip_set_mux()
460 "pin %d only supports a gpio mux\n", pin); rockchip_set_mux()
468 bank->bank_num, pin, mux); rockchip_set_mux()
477 if ((pin % 8) >= 4) rockchip_set_mux()
479 bit = (pin % 4) * 4; rockchip_set_mux()
481 bit = (pin % 8) * 2; rockchip_set_mux()
546 * with the lowest pin being in bits 15:14 and the highest rk3188_calc_pull_reg_and_bit()
547 * pin in bits 1:0 rk3188_calc_pull_reg_and_bit()
907 * for each pin in the pin group selected, program the correspoding pin rockchip_pmx_set()
908 * pin function number in the config register. rockchip_pmx_set()
919 /* revert the already done pin settings */ rockchip_pmx_set()
935 int pin, bool input) _rockchip_pmx_gpio_set_direction()
944 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); _rockchip_pmx_gpio_set_direction()
954 data |= BIT(pin); _rockchip_pmx_gpio_set_direction()
956 data &= ~BIT(pin); _rockchip_pmx_gpio_set_direction()
971 int pin; rockchip_pmx_gpio_set_direction() local
974 pin = offset - chip->base; rockchip_pmx_gpio_set_direction()
975 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", rockchip_pmx_gpio_set_direction()
976 offset, range->name, pin, input ? "input" : "output"); rockchip_pmx_gpio_set_direction()
1015 /* set the pin config settings for a specified pin */ rockchip_pinconf_set()
1016 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, rockchip_pinconf_set() argument
1020 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); rockchip_pinconf_set()
1032 rc = rockchip_set_pull(bank, pin - bank->pin_base, rockchip_pinconf_set()
1047 rc = rockchip_set_pull(bank, pin - bank->pin_base, rockchip_pinconf_set()
1054 pin - bank->pin_base, arg); rockchip_pinconf_set()
1056 pin - bank->pin_base, false); rockchip_pinconf_set()
1061 /* rk3288 is the first with per-pin drive-strength */ rockchip_pinconf_set()
1066 pin - bank->pin_base, arg); rockchip_pinconf_set()
1079 /* get the pin config settings for a specified pin */ rockchip_pinconf_get()
1080 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, rockchip_pinconf_get() argument
1084 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); rockchip_pinconf_get()
1091 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) rockchip_pinconf_get()
1103 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) rockchip_pinconf_get()
1109 rc = rockchip_get_mux(bank, pin - bank->pin_base); rockchip_pinconf_get()
1113 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); rockchip_pinconf_get()
1120 /* rk3288 is the first with per-pin drive-strength */ rockchip_pinconf_get()
1124 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); rockchip_pinconf_get()
1184 * the binding format is rockchip,pins = <bank pin mux CONFIG>, rockchip_pinctrl_parse_groups()
1320 int pin, bank, ret; rockchip_pinctrl_register() local
1332 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); rockchip_pinctrl_register()
1341 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { rockchip_pinctrl_register()
1344 pin_bank->name, pin); rockchip_pinctrl_register()
1398 * Returns the level of the pin for input direction and setting of the DR
1415 * gpiolib gpio_direction_input callback function. The setting of the pin
1425 * gpiolib gpio_direction_output callback function. The setting of the pin
1437 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1540 /* make sure the pin is configured as gpio input */ rockchip_irq_set_type()
250 pin_to_bank(struct rockchip_pinctrl *info, unsigned pin) pin_to_bank() argument
934 _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, int pin, bool input) _rockchip_pmx_gpio_set_direction() argument
/linux-4.4.14/include/linux/
H A Dw1-gpio.h15 * @pin: GPIO pin to use
16 * @is_open_drain: GPIO pin is configured as open drain
19 unsigned int pin; member in struct:w1_gpio_platform_data
H A Dmdio-bitbang.h18 /* Configure the Management Data I/O pin as an input if
23 /* Set the Management Data I/O pin high if value is one,
25 * when the MDIO pin is configured as an output.
29 /* Retrieve the state Management Data I/O pin. */
H A Di2c-gpio.h15 * @sda_pin: GPIO pin ID to use for SDA
16 * @scl_pin: GPIO pin ID to use for SCL
20 * @sda_is_open_drain: SDA is configured as open drain, i.e. the pin
22 * gpio_get_value() must return the actual pin state even if the
23 * pin is configured as an output.
H A Di2c-pca-platform.h5 int gpio; /* pin to reset chip. driver will work when
H A Datmel-mci.h11 * @detect_pin: GPIO pin wired to the card detect switch
12 * @wp_pin: GPIO pin wired to the write protect sensor
13 * @detect_is_active_high: The state of the detect pin when it is active
/linux-4.4.14/include/linux/pinctrl/
H A Dpinconf.h23 * struct pinconf_ops - pin config operations, to be implemented by
24 * pin configuration capable drivers.
25 * @is_generic: for pin controllers that want to use the generic interface,
27 * @pin_config_get: get the config of a certain pin, if the requested config
30 * @pin_config_set: configure an individual pin
31 * @pin_config_group_get: get configurations for an entire pin group
33 * @pin_config_dbg_parse_modify: optional debugfs to modify a pin configuration
35 * per-device info for a certain pin in debugfs
39 * and display a driver's pin configuration parameter
46 unsigned pin,
49 unsigned pin,
H A Dpinctrl.h34 * @number: unique pin number from the global pin number space
35 * @name: a name for this pin
36 * @drv_data: driver-defined per-pin data. pinctrl core does not touch this
44 /* Convenience macro to define a single named or anonymous pin descriptor */
49 * struct pinctrl_gpio_range - each pin controller can provide subranges of
55 * @pin_base: base pin number of the GPIO range if pins == NULL
72 * struct pinctrl_ops - global pin control operations, to be implemented by
73 * pin controller drivers.
75 * @get_group_name: return the group name of the pin group
79 * info for a certain pin in debugfs
80 * @dt_node_to_map: parse a device tree "pin configuration node", and create
108 * struct pinctrl_desc - pin controller descriptor, register this to pin
110 * @name: name for the pin controller
111 * @pins: an array of pin descriptors describing all the pins handled by
112 * this pin controller
115 * @pctlops: pin control operation vtable, to support global concepts like
118 * @confops: pin config operations vtable, if you support pin configuration in
120 * @owner: module providing the pin controller, used for refcounting
143 /* External interface to pin controller */
147 extern bool pin_is_valid(struct pinctrl_dev *pctldev, int pin);
160 unsigned int pin);
183 static inline bool pin_is_valid(struct pinctrl_dev *pctldev, int pin) pin_is_valid() argument
185 return pin >= 0; pin_is_valid()
H A Dpinconf-generic.h17 * using generic pin config. That is why this is defined out.
22 * enum pin_config_param - possible pin configuration parameters
23 * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it
28 * @PIN_CONFIG_BIAS_DISABLE: disable any pin bias on the pin, a
31 * @PIN_CONFIG_BIAS_HIGH_IMPEDANCE: the pin will be set to a high impedance
33 * On output pins this effectively disconnects the pin, which is useful
34 * if for example some other pin is going to drive the signal connected
37 * @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high
39 * if it is 0, pull-down is total, i.e. the pin is connected to GROUND.
40 * @PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: the pin will be pulled up or down based
48 * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
50 * if it is 0, pull-up is total, i.e. the pin is connected to VDD.
51 * @PIN_CONFIG_DRIVE_OPEN_DRAIN: the pin will be driven with open drain (open
55 * @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source
58 * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
62 * @PIN_CONFIG_DRIVE_STRENGTH: the pin will sink or source at most the current
64 * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
68 * @PIN_CONFIG_INPUT_ENABLE: enable the pin's input. Note that this does not
69 * affect the pin's ability to drive output. 1 enables input, 0 disables
71 * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in
75 * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin.
78 * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
82 * @PIN_CONFIG_OUTPUT: this will configure the pin as an output. Use argument
86 * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
89 * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to
92 * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
93 * you need to pass in custom configurations to the pin controller, use
137 * into and out of an unsigned long argument, as used by the generic pin config
H A Dpinmux.h24 * struct pinmux_ops - pinmux operations, to be implemented by pin controller
26 * @request: called by the core to see if a certain pin can be made
30 * @free: the reverse function of the request() callback, frees a pin after
42 * @set_mux: enable a certain muxing function with a certain pin group. The
48 * @gpio_request_enable: requests and enables GPIO on a certain pin.
49 * Implement this only if you can mux every pin individually as GPIO. The
50 * affected GPIO range is passed along with an offset(pin number) into that
51 * specific GPIO range - function selectors and pin groups are orthogonal
53 * @gpio_disable_free: free up GPIO muxing on a certain pin, the reverse of
58 * to the GPIO controllers that need pin muxing.
59 * @strict: do not allow simultaneous use of the same pin for GPIO and another
61 * the pin request.
H A Dmachine.h41 * @group_or_pin: the name of the pin or group whose configuration parameters
44 * hardware. Each individual pin controller defines the format and meaning
58 * same name as the pin controllers own dev_name(), the map entry will be
109 #define PIN_MAP_CONFIGS_PIN(dev, state, pinctrl, pin, cfgs) \
116 .group_or_pin = pin, \
122 #define PIN_MAP_CONFIGS_PIN_DEFAULT(dev, pinctrl, pin, cfgs) \
123 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_DEFAULT, pinctrl, pin, cfgs)
125 #define PIN_MAP_CONFIGS_PIN_HOG(dev, state, pin, cfgs) \
126 PIN_MAP_CONFIGS_PIN(dev, state, dev, pin, cfgs)
128 #define PIN_MAP_CONFIGS_PIN_HOG_DEFAULT(dev, pin, cfgs) \
129 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_DEFAULT, dev, pin, cfgs)
/linux-4.4.14/arch/arm/plat-orion/
H A Dgpio.c96 __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input) __set_direction() argument
102 u |= 1 << pin; __set_direction()
104 u &= ~(1 << pin); __set_direction()
108 static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high) __set_level() argument
114 u |= 1 << pin; __set_level()
116 u &= ~(1 << pin); __set_level()
121 __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink) __set_blinking() argument
127 u |= 1 << pin; __set_blinking()
129 u &= ~(1 << pin); __set_blinking()
134 orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode) orion_gpio_is_valid() argument
136 if (pin >= ochip->chip.ngpio) orion_gpio_is_valid()
139 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input)) orion_gpio_is_valid()
142 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output)) orion_gpio_is_valid()
148 pr_debug("%s: invalid GPIO %d\n", __func__, pin); orion_gpio_is_valid()
155 static int orion_gpio_request(struct gpio_chip *chip, unsigned pin) orion_gpio_request() argument
160 if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) || orion_gpio_request()
161 orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) orion_gpio_request()
167 static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin) orion_gpio_direction_input() argument
173 if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK)) orion_gpio_direction_input()
177 __set_direction(ochip, pin, 1); orion_gpio_direction_input()
183 static int orion_gpio_get(struct gpio_chip *chip, unsigned pin) orion_gpio_get() argument
189 if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) { orion_gpio_get()
195 return (val >> pin) & 1; orion_gpio_get()
199 orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value) orion_gpio_direction_output() argument
205 if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) orion_gpio_direction_output()
209 __set_blinking(ochip, pin, 0); orion_gpio_direction_output()
210 __set_level(ochip, pin, value); orion_gpio_direction_output()
211 __set_direction(ochip, pin, 0); orion_gpio_direction_output()
217 static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value) orion_gpio_set() argument
224 __set_level(ochip, pin, value); orion_gpio_set()
228 static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin) orion_gpio_to_irq() argument
234 ochip->secondary_irq_base + pin); orion_gpio_to_irq()
240 static struct orion_gpio_chip *orion_gpio_chip_find(int pin) orion_gpio_chip_find() argument
248 if (pin >= chip->base && pin < chip->base + chip->ngpio) orion_gpio_chip_find()
255 void __init orion_gpio_set_unused(unsigned pin) orion_gpio_set_unused() argument
257 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); orion_gpio_set_unused()
262 pin -= ochip->chip.base; orion_gpio_set_unused()
265 __set_level(ochip, pin, 0); orion_gpio_set_unused()
266 __set_direction(ochip, pin, 0); orion_gpio_set_unused()
269 void __init orion_gpio_set_valid(unsigned pin, int mode) orion_gpio_set_valid() argument
271 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); orion_gpio_set_valid()
276 pin -= ochip->chip.base; orion_gpio_set_valid()
282 __set_bit(pin, &ochip->valid_input); orion_gpio_set_valid()
284 __clear_bit(pin, &ochip->valid_input); orion_gpio_set_valid()
287 __set_bit(pin, &ochip->valid_output); orion_gpio_set_valid()
289 __clear_bit(pin, &ochip->valid_output); orion_gpio_set_valid()
292 void orion_gpio_set_blink(unsigned pin, int blink) orion_gpio_set_blink() argument
294 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); orion_gpio_set_blink()
301 __set_level(ochip, pin & 31, 0); orion_gpio_set_blink()
302 __set_blinking(ochip, pin & 31, blink); orion_gpio_set_blink()
362 int pin; gpio_irq_set_type() local
365 pin = d->hwirq - ochip->secondary_irq_base; gpio_irq_set_type()
367 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin); gpio_irq_set_type()
386 u &= ~(1 << pin); gpio_irq_set_type()
390 u |= 1 << pin; gpio_irq_set_type()
401 if (v & (1 << pin)) gpio_irq_set_type()
402 u |= 1 << pin; /* falling */ gpio_irq_set_type()
404 u &= ~(1 << pin); /* rising */ gpio_irq_set_type()
/linux-4.4.14/arch/arm/plat-samsung/include/plat/
H A Dgpio-cfg.h8 * S3C Platform - GPIO pin configuration
16 * pin configuration done such as setting a pin to input or output or
68 /* Defines for generic pin configurations */
77 * s3c_gpio_cfgpin() - Change the GPIO function of a pin.
78 * @pin pin The pin number to configure.
79 * @to to The configuration for the pin's function.
82 * pin, such as an gpio input, output or some form of special function
99 extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
102 * s3c_gpio_getcfg - Read the current function for a GPIO pin
103 * @pin: The pin to read the configuration value for.
105 * Read the configuration state of the given @pin, returning a value that
110 extern unsigned s3c_gpio_getcfg(unsigned int pin);
113 * s3c_gpio_cfgpin_range() - Change the GPIO function for configuring pin range
114 * @start: The pin number to start at
116 * @cfg: The configuration for the pin's function
125 /* Define values for the pull-{up,down} available for each gpio pin.
137 * s3c_gpio_setpull() - set the state of a gpio pin pull resistor
138 * @pin: The pin number to configure the pull resistor.
142 * specified pin. It will return 0 if successful, or a negative error
143 * code if the pin cannot support the requested pull setting.
147 extern int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull);
150 * s3c_gpio_getpull() - get the pull resistor state of a gpio pin
151 * @pin: The pin number to get the settings for
153 * Read the pull resistor value for the specified pin.
155 extern samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
176 static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size, s3c_gpio_cfgrange_nopull() argument
179 return s3c_gpio_cfgall_range(pin, size, cfg, S3C_GPIO_PULL_NONE); s3c_gpio_cfgrange_nopull()
H A Dgpio-core.h90 * samsung_gpiolib_to_irq - convert gpio pin to irq number
91 * @chip: The gpio chip that the pin belongs to.
92 * @offset: The offset of the pin in the chip.
114 static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin) samsung_gpiolib_getchip() argument
118 if (pin > S3C_GPIO_END) samsung_gpiolib_getchip()
121 chip = &s3c24xx_gpios[pin/32]; samsung_gpiolib_getchip()
122 return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL; samsung_gpiolib_getchip()
/linux-4.4.14/drivers/pci/
H A Dsetup-irq.c29 u8 pin, slot; pdev_fixup_irq() local
33 which interrupt pin it will come in on. We know which slot it pdev_fixup_irq()
38 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); pdev_fixup_irq()
40 if (pin > 4) pdev_fixup_irq()
41 pin = 1; pdev_fixup_irq()
43 if (pin != 0) { pdev_fixup_irq()
45 slot = (*swizzle)(dev, &pin); pdev_fixup_irq()
47 irq = (*map_irq)(dev, slot, pin); pdev_fixup_irq()
/linux-4.4.14/drivers/input/mouse/
H A Dgpio_mouse.c53 int pin, i; gpio_mouse_probe() local
69 pin = pdata->pins[i]; gpio_mouse_probe()
71 if (pin < 0) { gpio_mouse_probe()
85 error = gpio_request(pin, "gpio_mouse"); gpio_mouse_probe()
87 dev_err(&pdev->dev, "fail %d pin (%d idx)\n", gpio_mouse_probe()
88 pin, i); gpio_mouse_probe()
92 gpio_direction_input(pin); gpio_mouse_probe()
143 pin = pdata->pins[i]; gpio_mouse_probe()
144 if (pin) gpio_mouse_probe()
145 gpio_free(pin); gpio_mouse_probe()
155 int pin, i; gpio_mouse_remove() local
161 pin = pdata->pins[i]; gpio_mouse_remove()
162 if (pin >= 0) gpio_mouse_remove()
163 gpio_free(pin); gpio_mouse_remove()
/linux-4.4.14/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.c55 * When pin number greater than type1_start and less than type1_end,
59 unsigned long pin) mtk_get_regmap()
61 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) mtk_get_regmap()
66 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin) mtk_get_port() argument
69 return ((pin >> 4) & pctl->devdata->port_mask) mtk_get_port()
111 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, mtk_pconf_set_ies_smt() argument
136 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), mtk_pconf_set_ies_smt()
137 pin, pctl->devdata->port_align, value, arg); mtk_pconf_set_ies_smt()
140 bit = BIT(pin & 0xf); mtk_pconf_set_ies_smt()
148 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl); mtk_pconf_set_ies_smt()
150 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); mtk_pconf_set_ies_smt()
152 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); mtk_pconf_set_ies_smt()
158 unsigned int pin, unsigned char align, int value) mtk_pconf_spec_set_ies_smt_range()
163 if (pin >= ies_smt_infos[i].start && mtk_pconf_spec_set_ies_smt_range()
164 pin <= ies_smt_infos[i].end) { mtk_pconf_spec_set_ies_smt_range()
183 struct mtk_pinctrl *pctl, unsigned long pin) { mtk_find_pin_drv_grp_by_pin()
189 if (pin == pin_drv->pin) mtk_find_pin_drv_grp_by_pin()
197 unsigned int pin, unsigned char driving) mtk_pconf_set_driving()
204 if (pin >= pctl->devdata->npins) mtk_pconf_set_driving()
207 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin); mtk_pconf_set_driving()
220 return regmap_update_bits(mtk_get_regmap(pctl, pin), mtk_pconf_set_driving()
229 unsigned int info_num, unsigned int pin, mtk_pctrl_spec_pull_set_samereg()
239 if (pin == pupd_infos[i].pin) { mtk_pctrl_spec_pull_set_samereg()
288 unsigned int pin, bool enable, bool isup, unsigned int arg) mtk_pconf_set_pull_select()
299 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), mtk_pconf_set_pull_select()
300 pin, pctl->devdata->port_align, isup, arg); mtk_pconf_set_pull_select()
307 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", mtk_pconf_set_pull_select()
308 arg, pin); mtk_pconf_set_pull_select()
312 bit = BIT(pin & 0xf); mtk_pconf_set_pull_select()
314 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + mtk_pconf_set_pull_select()
317 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) + mtk_pconf_set_pull_select()
321 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) + mtk_pconf_set_pull_select()
324 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + mtk_pconf_set_pull_select()
327 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); mtk_pconf_set_pull_select()
328 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); mtk_pconf_set_pull_select()
333 unsigned int pin, enum pin_config_param param, mtk_pconf_parse_conf()
341 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg); mtk_pconf_parse_conf()
344 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg); mtk_pconf_parse_conf()
347 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg); mtk_pconf_parse_conf()
350 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); mtk_pconf_parse_conf()
353 mtk_gpio_set(pctl->chip, pin, arg); mtk_pconf_parse_conf()
354 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); mtk_pconf_parse_conf()
357 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); mtk_pconf_parse_conf()
360 ret = mtk_pconf_set_driving(pctl, pin, arg); mtk_pconf_parse_conf()
388 ret = mtk_pconf_parse_conf(pctldev, g->pin, mtk_pconf_group_set()
406 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin) mtk_pctrl_find_group_by_pin() argument
413 if (grp->pin == pin) mtk_pctrl_find_group_by_pin()
423 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num; mtk_pctrl_find_function_by_pin() local
424 const struct mtk_desc_function *func = pin->functions; mtk_pctrl_find_function_by_pin()
441 const struct mtk_desc_pin *pin = pctl->devdata->pins + i; mtk_pctrl_is_function_valid() local
443 if (pin->pin.number == pin_num) { mtk_pctrl_is_function_valid()
445 pin->functions; mtk_pctrl_is_function_valid()
461 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp, mtk_pctrl_dt_node_to_map_func()
473 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum); mtk_pctrl_dt_node_to_map_func()
475 dev_err(pctl->dev, "invalid function %d on pin %d .\n", mtk_pctrl_dt_node_to_map_func()
476 fnum, pin); mtk_pctrl_dt_node_to_map_func()
493 u32 pinfunc, pin, func; mtk_pctrl_dt_subnode_to_map() local
539 pin = MTK_GET_PIN_NO(pinfunc); mtk_pctrl_dt_subnode_to_map()
542 if (pin >= pctl->devdata->npins || mtk_pctrl_dt_subnode_to_map()
549 grp = mtk_pctrl_find_group_by_pin(pctl, pin); mtk_pctrl_dt_subnode_to_map()
551 dev_err(pctl->dev, "unable to match pin %d to group\n", mtk_pctrl_dt_subnode_to_map()
552 pin); mtk_pctrl_dt_subnode_to_map()
556 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, mtk_pctrl_dt_subnode_to_map()
623 *pins = (unsigned *)&pctl->groups[group].pin; mtk_pctrl_get_group_pins()
662 unsigned long pin, unsigned long mode) mtk_pmx_set_mode()
670 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf) mtk_pmx_set_mode()
673 bit = pin % MAX_GPIO_MODE_PER_REG; mtk_pmx_set_mode()
676 return regmap_update_bits(mtk_get_regmap(pctl, pin), mtk_pmx_set_mode()
684 const struct mtk_desc_pin *pin; mtk_find_pin_by_eint_num() local
687 pin = pctl->devdata->pins + i; mtk_find_pin_by_eint_num()
688 if (pin->eint.eintnum == eint_num) mtk_find_pin_by_eint_num()
689 return pin; mtk_find_pin_by_eint_num()
704 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function); mtk_pmx_set_mux()
711 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function); mtk_pmx_set_mux()
714 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval); mtk_pmx_set_mux()
770 const struct mtk_desc_pin *pin; mtk_gpio_to_irq() local
774 pin = pctl->devdata->pins + offset; mtk_gpio_to_irq()
775 if (pin->eint.eintnum == NO_EINT_SUPPORT) mtk_gpio_to_irq()
778 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum); mtk_gpio_to_irq()
788 const struct mtk_desc_pin *pin; mtk_pinctrl_irq_request_resources() local
791 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); mtk_pinctrl_irq_request_resources()
793 if (!pin) { mtk_pinctrl_irq_request_resources()
794 dev_err(pctl->dev, "Can not find pin\n"); mtk_pinctrl_irq_request_resources()
798 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number); mtk_pinctrl_irq_request_resources()
806 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux); mtk_pinctrl_irq_request_resources()
814 const struct mtk_desc_pin *pin; mtk_pinctrl_irq_release_resources() local
816 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); mtk_pinctrl_irq_release_resources()
818 if (!pin) { mtk_pinctrl_irq_release_resources()
819 dev_err(pctl->dev, "Can not find pin\n"); mtk_pinctrl_irq_release_resources()
823 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number); mtk_pinctrl_irq_release_resources()
891 const struct mtk_desc_pin *pin; mtk_eint_flip_edge() local
893 pin = mtk_find_pin_by_eint_num(pctl, hwirq); mtk_eint_flip_edge()
894 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); mtk_eint_flip_edge()
903 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); mtk_eint_flip_edge()
944 const struct mtk_desc_pin *pin; mtk_gpio_set_debounce() local
947 pin = pctl->devdata->pins + offset; mtk_gpio_set_debounce()
948 if (pin->eint.eintnum == NO_EINT_SUPPORT) mtk_gpio_set_debounce()
951 eint_num = pin->eint.eintnum; mtk_gpio_set_debounce()
1191 const struct mtk_desc_pin *pin; mtk_eint_irq_handler() local
1211 pin = mtk_find_pin_by_eint_num(pctl, index); mtk_eint_irq_handler()
1213 pin->pin.number); mtk_eint_irq_handler()
1249 /* We assume that one pin is one group, use pin name as group name. */ mtk_pctrl_build_state()
1256 const struct mtk_desc_pin *pin = pctl->devdata->pins + i; mtk_pctrl_build_state() local
1259 group->name = pin->pin.name; mtk_pctrl_build_state()
1260 group->pin = pin->pin.number; mtk_pctrl_build_state()
1262 pctl->grp_names[i] = pin->pin.name; mtk_pctrl_build_state()
1324 pins[i] = pctl->devdata->pins[i].pin; mtk_pctrl_init()
1359 /* Register the GPIO to pin mappings. */ mtk_pctrl_init()
58 mtk_get_regmap(struct mtk_pinctrl *pctl, unsigned long pin) mtk_get_regmap() argument
156 mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, unsigned int pin, unsigned char align, int value) mtk_pconf_spec_set_ies_smt_range() argument
182 mtk_find_pin_drv_grp_by_pin( struct mtk_pinctrl *pctl, unsigned long pin) mtk_find_pin_drv_grp_by_pin() argument
196 mtk_pconf_set_driving(struct mtk_pinctrl *pctl, unsigned int pin, unsigned char driving) mtk_pconf_set_driving() argument
227 mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, unsigned int info_num, unsigned int pin, unsigned char align, bool isup, unsigned int r1r0) mtk_pctrl_spec_pull_set_samereg() argument
287 mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, unsigned int pin, bool enable, bool isup, unsigned int arg) mtk_pconf_set_pull_select() argument
332 mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, unsigned int pin, enum pin_config_param param, enum pin_config_param arg) mtk_pconf_parse_conf() argument
460 mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, u32 pin, u32 fnum, struct mtk_pinctrl_group *grp, struct pinctrl_map **map, unsigned *reserved_maps, unsigned *num_maps) mtk_pctrl_dt_node_to_map_func() argument
661 mtk_pmx_set_mode(struct pinctrl_dev *pctldev, unsigned long pin, unsigned long mode) mtk_pmx_set_mode() argument
H A Dpinctrl-mtk-common.h42 struct pinctrl_pin_desc pin; member in struct:mtk_desc_pin
49 .pin = _pin, \
73 unsigned pin; member in struct:mtk_pinctrl_group
102 * struct mtk_pin_drv_grp - Provide each pin driving info.
103 * @pin: The pin number.
104 * @offset: The offset of driving register for this pin.
105 * @bit: The bit of driving register for this pin.
106 * @grp: The group for this pin belongs to.
109 unsigned short pin; member in struct:mtk_pin_drv_grp
117 .pin = _pin, \
126 * @pin: The pin number.
133 unsigned short pin; member in struct:mtk_pin_spec_pupd_set_samereg
142 .pin = _pin, \
151 * @start: The start pin number of those special pins.
152 * @end: The end pin number of those special pins.
197 * @pins: An array describing all pins the pin controller affects.
219 * member record the start of pin number to use the second address.
220 * @type1_end: The end of pin number to use the second address.
233 int (*spec_pull_set)(struct regmap *reg, unsigned int pin,
235 int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
280 unsigned int info_num, unsigned int pin,
285 unsigned int pin, unsigned char align, int value);
/linux-4.4.14/arch/avr32/mach-at32ap/include/mach/
H A Dportmux.h14 * Set up pin multiplexing, called from board init only.
16 * The following flags determine the initial state of the pin.
24 void at32_select_periph(unsigned int port, unsigned int pin,
26 void at32_select_gpio(unsigned int pin, unsigned long flags);
27 void at32_deselect_pin(unsigned int pin);
/linux-4.4.14/drivers/pinctrl/sunxi/
H A Dpinctrl-sunxi.h32 #define SUNXI_PINCTRL_PIN(bank, pin) \
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
91 struct pinctrl_pin_desc pin; member in struct:sunxi_desc_pin
113 unsigned pin; member in struct:sunxi_pinctrl_group
134 .pin = _pin, \
163 * 8 pins per register, each pin having a 4bits value
165 * 32 bits per register, each pin corresponding to one bit
167 * 16 pins per register, each pin having a 2bits value
169 * 16 pins per register, each pin having a 2bits value
174 * The following functions calculate from the pin number the register
177 static inline u32 sunxi_mux_reg(u16 pin) sunxi_mux_reg() argument
179 u8 bank = pin / PINS_PER_BANK; sunxi_mux_reg()
182 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04; sunxi_mux_reg()
186 static inline u32 sunxi_mux_offset(u16 pin) sunxi_mux_offset() argument
188 u32 pin_num = pin % MUX_PINS_PER_REG; sunxi_mux_offset()
192 static inline u32 sunxi_data_reg(u16 pin) sunxi_data_reg() argument
194 u8 bank = pin / PINS_PER_BANK; sunxi_data_reg()
197 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04; sunxi_data_reg()
201 static inline u32 sunxi_data_offset(u16 pin) sunxi_data_offset() argument
203 u32 pin_num = pin % DATA_PINS_PER_REG; sunxi_data_offset()
207 static inline u32 sunxi_dlevel_reg(u16 pin) sunxi_dlevel_reg() argument
209 u8 bank = pin / PINS_PER_BANK; sunxi_dlevel_reg()
212 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04; sunxi_dlevel_reg()
216 static inline u32 sunxi_dlevel_offset(u16 pin) sunxi_dlevel_offset() argument
218 u32 pin_num = pin % DLEVEL_PINS_PER_REG; sunxi_dlevel_offset()
222 static inline u32 sunxi_pull_reg(u16 pin) sunxi_pull_reg() argument
224 u8 bank = pin / PINS_PER_BANK; sunxi_pull_reg()
227 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04; sunxi_pull_reg()
231 static inline u32 sunxi_pull_offset(u16 pin) sunxi_pull_offset() argument
233 u32 pin_num = pin % PULL_PINS_PER_REG; sunxi_pull_offset()
H A Dpinctrl-sunxi.c79 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; sunxi_pinctrl_desc_find_function_by_name() local
81 if (!strcmp(pin->pin.name, pin_name)) { sunxi_pinctrl_desc_find_function_by_name()
82 struct sunxi_desc_function *func = pin->functions; sunxi_pinctrl_desc_find_function_by_name()
104 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; sunxi_pinctrl_desc_find_function_by_pin() local
106 if (pin->pin.number == pin_num) { sunxi_pinctrl_desc_find_function_by_pin()
107 struct sunxi_desc_function *func = pin->functions; sunxi_pinctrl_desc_find_function_by_pin()
143 *pins = (unsigned *)&pctl->groups[group].pin; sunxi_pctrl_get_group_pins()
191 dev_err(pctl->dev, "unknown pin %s", group); sunxi_pctrl_dt_node_to_map()
198 dev_err(pctl->dev, "unsupported function %s on pin %s", sunxi_pctrl_dt_node_to_map()
291 unsigned pin = g->pin - pctl->desc->pin_base; sunxi_pconf_group_set() local
315 val = readl(pctl->membase + sunxi_dlevel_reg(pin)); sunxi_pconf_group_set()
316 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin); sunxi_pconf_group_set()
318 | dlevel << sunxi_dlevel_offset(pin), sunxi_pconf_group_set()
319 pctl->membase + sunxi_dlevel_reg(pin)); sunxi_pconf_group_set()
322 val = readl(pctl->membase + sunxi_pull_reg(pin)); sunxi_pconf_group_set()
323 mask = PULL_PINS_MASK << sunxi_pull_offset(pin); sunxi_pconf_group_set()
324 writel((val & ~mask) | 1 << sunxi_pull_offset(pin), sunxi_pconf_group_set()
325 pctl->membase + sunxi_pull_reg(pin)); sunxi_pconf_group_set()
328 val = readl(pctl->membase + sunxi_pull_reg(pin)); sunxi_pconf_group_set()
329 mask = PULL_PINS_MASK << sunxi_pull_offset(pin); sunxi_pconf_group_set()
330 writel((val & ~mask) | 2 << sunxi_pull_offset(pin), sunxi_pconf_group_set()
331 pctl->membase + sunxi_pull_reg(pin)); sunxi_pconf_group_set()
379 unsigned pin, sunxi_pmx_set()
388 pin -= pctl->desc->pin_base; sunxi_pmx_set()
389 val = readl(pctl->membase + sunxi_mux_reg(pin)); sunxi_pmx_set()
390 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); sunxi_pmx_set()
391 writel((val & ~mask) | config << sunxi_mux_offset(pin), sunxi_pmx_set()
392 pctl->membase + sunxi_mux_reg(pin)); sunxi_pmx_set()
412 sunxi_pmx_set(pctldev, g->pin, desc->muxval); sunxi_pmx_set_mux()
509 int pin, base; sunxi_pinctrl_gpio_of_xlate() local
512 pin = base + gpiospec->args[1]; sunxi_pinctrl_gpio_of_xlate()
514 if (pin > gc->ngpio) sunxi_pinctrl_gpio_of_xlate()
520 return pin; sunxi_pinctrl_gpio_of_xlate()
712 int pin, base; sunxi_pinctrl_irq_of_xlate() local
718 pin = pctl->desc->pin_base + base + intspec[1]; sunxi_pinctrl_irq_of_xlate()
720 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); sunxi_pinctrl_irq_of_xlate()
801 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; sunxi_pinctrl_build_state() local
804 group->name = pin->pin.name; sunxi_pinctrl_build_state()
805 group->pin = pin->pin.number; sunxi_pinctrl_build_state()
820 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; sunxi_pinctrl_build_state() local
821 struct sunxi_desc_function *func = pin->functions; sunxi_pinctrl_build_state()
827 pctl->irq_array[irqnum] = pin->pin.number; sunxi_pinctrl_build_state()
840 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; sunxi_pinctrl_build_state() local
841 struct sunxi_desc_function *func = pin->functions; sunxi_pinctrl_build_state()
865 *func_grp = pin->pin.name; sunxi_pinctrl_build_state()
919 pins[i] = pctl->desc->pins[i].pin; sunxi_pinctrl_init()
948 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; sunxi_pinctrl_init()
971 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; sunxi_pinctrl_init() local
974 pin->pin.number - pctl->desc->pin_base, sunxi_pinctrl_init()
975 pin->pin.number, 1); sunxi_pinctrl_init()
378 sunxi_pmx_set(struct pinctrl_dev *pctldev, unsigned pin, u8 config) sunxi_pmx_set() argument
/linux-4.4.14/drivers/input/misc/
H A Dixp4xx-beeper.c33 static void ixp4xx_spkr_control(unsigned int pin, unsigned int count) ixp4xx_spkr_control() argument
40 gpio_direction_output(pin, 0); ixp4xx_spkr_control()
43 gpio_direction_output(pin, 1); ixp4xx_spkr_control()
44 gpio_direction_input(pin); ixp4xx_spkr_control()
53 unsigned int pin = (unsigned int) input_get_drvdata(dev); ixp4xx_spkr_event() local
72 ixp4xx_spkr_control(pin, count); ixp4xx_spkr_event()
79 unsigned int pin = (unsigned int) dev_id; ixp4xx_spkr_interrupt() local
85 gpio_set_value(pin, !gpio_get_value(pin)); ixp4xx_spkr_interrupt()
144 unsigned int pin = (unsigned int) input_get_drvdata(input_dev); ixp4xx_spkr_remove() local
150 ixp4xx_spkr_control(pin, 0); ixp4xx_spkr_remove()
161 unsigned int pin = (unsigned int) input_get_drvdata(input_dev); ixp4xx_spkr_shutdown() local
165 ixp4xx_spkr_control(pin, 0); ixp4xx_spkr_shutdown()
/linux-4.4.14/drivers/pinctrl/meson/
H A Dpinctrl-meson.c27 * 1) pin muxing
36 * register range of the domain; when all groups for a given pin are
37 * disabled the pin acts as a GPIO.
68 * meson_get_bank() - find the bank containing a given pin
70 * @domain: the domain containing the pin
71 * @pin: the pin number
76 static int meson_get_bank(struct meson_domain *domain, unsigned int pin, meson_get_bank() argument
82 if (pin >= domain->data->banks[i].first && meson_get_bank()
83 pin <= domain->data->banks[i].last) { meson_get_bank()
93 * meson_get_domain_and_bank() - find domain and bank containing a given pin
95 * @pc: Meson pin controller device
96 * @pin: the pin number
102 static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin, meson_get_domain_and_bank() argument
111 if (pin >= d->data->pin_base && meson_get_domain_and_bank()
112 pin < d->data->pin_base + d->data->num_pins) { meson_get_domain_and_bank()
114 return meson_get_bank(d, pin, bank); meson_get_domain_and_bank()
122 * meson_calc_reg_and_bit() - calculate register and bit for a pin
124 * @bank: the bank containing the pin
125 * @pin: the pin number
130 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, meson_calc_reg_and_bit() argument
137 *bit = desc->bit + pin - bank->first; meson_calc_reg_and_bit()
182 * meson_pmx_disable_other_groups() - disable other groups using a given pin
184 * @pc: meson pin controller device
185 * @pin: number of the pin
188 * The function disables all pinmux groups using a pin except the
190 * the pin in GPIO mode.
193 unsigned int pin, int sel_group) meson_pmx_disable_other_groups()
205 if (group->pins[j] == pin) { meson_pmx_disable_other_groups()
206 /* We have found a group using the pin */ meson_pmx_disable_other_groups()
229 * Disable groups using the same pin. meson_pmx_set_mux()
289 static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, meson_pinconf_set() argument
300 ret = meson_get_domain_and_bank(pc, pin, &domain, &bank); meson_pinconf_set()
310 dev_dbg(pc->dev, "pin %u: disable bias\n", pin); meson_pinconf_set()
312 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit); meson_pinconf_set()
319 dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin); meson_pinconf_set()
321 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, meson_pinconf_set()
328 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit); meson_pinconf_set()
335 dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin); meson_pinconf_set()
337 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, meson_pinconf_set()
344 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit); meson_pinconf_set()
358 static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) meson_pinconf_get_pull() argument
365 ret = meson_get_domain_and_bank(pc, pin, &domain, &bank); meson_pinconf_get_pull()
369 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit); meson_pinconf_get_pull()
378 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit); meson_pinconf_get_pull()
393 static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, meson_pinconf_get() argument
404 if (meson_pinconf_get_pull(pc, pin) == param) meson_pinconf_get()
414 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); meson_pinconf_get()
471 unsigned int reg, bit, pin; meson_gpio_direction_input() local
475 pin = domain->data->pin_base + gpio; meson_gpio_direction_input()
476 ret = meson_get_bank(domain, pin, &bank); meson_gpio_direction_input()
480 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit); meson_gpio_direction_input()
489 unsigned int reg, bit, pin; meson_gpio_direction_output() local
493 pin = domain->data->pin_base + gpio; meson_gpio_direction_output()
494 ret = meson_get_bank(domain, pin, &bank); meson_gpio_direction_output()
498 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit); meson_gpio_direction_output()
503 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit); meson_gpio_direction_output()
511 unsigned int reg, bit, pin; meson_gpio_set() local
515 pin = domain->data->pin_base + gpio; meson_gpio_set()
516 ret = meson_get_bank(domain, pin, &bank); meson_gpio_set()
520 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit); meson_gpio_set()
528 unsigned int reg, bit, val, pin; meson_gpio_get() local
532 pin = domain->data->pin_base + gpio; meson_gpio_get()
533 ret = meson_get_bank(domain, pin, &bank); meson_gpio_get()
537 meson_calc_reg_and_bit(bank, pin, REG_IN, &reg, &bit); meson_gpio_get()
589 dev_err(pc->dev, "can't add pin range\n"); meson_gpiolib_register()
192 meson_pmx_disable_other_groups(struct meson_pinctrl *pc, unsigned int pin, int sel_group) meson_pmx_disable_other_groups() argument
/linux-4.4.14/drivers/pinctrl/uniphier/
H A Dpinctrl-uniphier-core.c66 const struct pinctrl_pin_desc *pin = &pctldev->desc->pins[offset]; uniphier_pctl_pin_dbg_show() local
69 switch (uniphier_pin_get_pull_dir(pin->drv_data)) { uniphier_pctl_pin_dbg_show()
83 switch (uniphier_pin_get_drv_str(pin->drv_data)) { uniphier_pctl_pin_dbg_show()
122 const struct pinctrl_pin_desc *pin, uniphier_conf_pin_bias_get()
127 uniphier_pin_get_pull_dir(pin->drv_data); uniphier_conf_pin_bias_get()
157 pupdctrl = uniphier_pin_get_pupdctrl(pin->drv_data); uniphier_conf_pin_bias_get()
172 const struct pinctrl_pin_desc *pin, uniphier_conf_pin_drive_get()
177 uniphier_pin_get_drv_str(pin->drv_data); uniphier_conf_pin_drive_get()
203 /* drive strength control is not supported for this pin */ uniphier_conf_pin_drive_get()
207 drvctrl = uniphier_pin_get_drvctrl(pin->drv_data); uniphier_conf_pin_drive_get()
227 const struct pinctrl_pin_desc *pin) uniphier_conf_pin_input_enable_get()
230 unsigned int iectrl = uniphier_pin_get_iectrl(pin->drv_data); uniphier_conf_pin_input_enable_get()
235 /* This pin is always input-enabled. */ uniphier_conf_pin_input_enable_get()
246 unsigned pin, uniphier_conf_pin_config_get()
249 const struct pinctrl_pin_desc *pin_desc = &pctldev->desc->pins[pin]; uniphier_conf_pin_config_get()
281 const struct pinctrl_pin_desc *pin, uniphier_conf_pin_bias_set()
287 uniphier_pin_get_pull_dir(pin->drv_data); uniphier_conf_pin_bias_set()
298 "can not disable pull register for pin %u (%s)\n", uniphier_conf_pin_bias_set()
299 pin->number, pin->name); uniphier_conf_pin_bias_set()
309 "pull-up is unsupported for pin %u (%s)\n", uniphier_conf_pin_bias_set()
310 pin->number, pin->name); uniphier_conf_pin_bias_set()
323 "pull-down is unsupported for pin %u (%s)\n", uniphier_conf_pin_bias_set()
324 pin->number, pin->name); uniphier_conf_pin_bias_set()
335 "pull-up/down is unsupported for pin %u (%s)\n", uniphier_conf_pin_bias_set()
336 pin->number, pin->name); uniphier_conf_pin_bias_set()
347 pupdctrl = uniphier_pin_get_pupdctrl(pin->drv_data); uniphier_conf_pin_bias_set()
356 const struct pinctrl_pin_desc *pin, uniphier_conf_pin_drive_set()
361 uniphier_pin_get_drv_str(pin->drv_data); uniphier_conf_pin_drive_set()
378 "cannot change drive strength for pin %u (%s)\n", uniphier_conf_pin_drive_set()
379 pin->number, pin->name); uniphier_conf_pin_drive_set()
390 "unsupported drive strength %u mA for pin %u (%s)\n", uniphier_conf_pin_drive_set()
391 strength, pin->number, pin->name); uniphier_conf_pin_drive_set()
397 drvctrl = uniphier_pin_get_drvctrl(pin->drv_data); uniphier_conf_pin_drive_set()
412 const struct pinctrl_pin_desc *pin, uniphier_conf_pin_input_enable()
416 unsigned int iectrl = uniphier_pin_get_iectrl(pin->drv_data); uniphier_conf_pin_input_enable()
420 * Multiple pins share one input enable, so per-pin disabling uniphier_conf_pin_input_enable()
428 /* This pin is always input-enabled. nothing to do. */ uniphier_conf_pin_input_enable()
436 unsigned pin, uniphier_conf_pin_config_set()
440 const struct pinctrl_pin_desc *pin_desc = &pctldev->desc->pins[pin]; uniphier_conf_pin_config_set()
533 static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin, uniphier_pmx_set_one_mux() argument
544 &pctldev->desc->pins[pin], 1); uniphier_pmx_set_one_mux()
548 reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; uniphier_pmx_set_one_mux()
550 shift = pin * mux_bits % 32; uniphier_pmx_set_one_mux()
619 dev_err(pctldev->dev, "pin %u does not support GPIO\n", offset); uniphier_pmx_gpio_request_enable()
121 uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin, enum pin_config_param param) uniphier_conf_pin_bias_get() argument
171 uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin, u16 *strength) uniphier_conf_pin_drive_get() argument
226 uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin) uniphier_conf_pin_input_enable_get() argument
245 uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs) uniphier_conf_pin_config_get() argument
280 uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin, enum pin_config_param param, u16 arg) uniphier_conf_pin_bias_set() argument
355 uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin, u16 strength) uniphier_conf_pin_drive_set() argument
411 uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin, u16 enable) uniphier_conf_pin_input_enable() argument
435 uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs, unsigned num_configs) uniphier_conf_pin_config_set() argument
/linux-4.4.14/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.c179 dev_err(bank->gpio_chip.dev, "unable to lock pin %s-%lu IRQ\n", exynos_irq_request_resources()
274 unsigned int svc, group, pin, virq; exynos_eint_gpio_irq() local
278 pin = svc & EXYNOS_SVC_NUM_MASK; exynos_eint_gpio_irq()
284 virq = irq_linear_revmap(bank->irq_domain, pin); exynos_eint_gpio_irq()
646 /* pin banks of s5pv210 pin-controller */
686 /* pin-controller instance 0 data */
696 /* pin banks of exynos3250 pin-controller 0 */
707 /* pin banks of exynos3250 pin-controller 1 */
729 * two gpio/pin-mux/pinconfig controllers.
733 /* pin-controller instance 0 data */
740 /* pin-controller instance 1 data */
750 /* pin banks of exynos4210 pin-controller 0 */
770 /* pin banks of exynos4210 pin-controller 1 */
794 /* pin banks of exynos4210 pin-controller 2 */
801 * three gpio/pin-mux/pinconfig controllers.
805 /* pin-controller instance 0 data */
812 /* pin-controller instance 1 data */
820 /* pin-controller instance 2 data */
826 /* pin banks of exynos4x12 pin-controller 0 */
843 /* pin banks of exynos4x12 pin-controller 1 */
870 /* pin banks of exynos4x12 pin-controller 2 */
875 /* pin banks of exynos4x12 pin-controller 3 */
886 * four gpio/pin-mux/pinconfig controllers.
890 /* pin-controller instance 0 data */
897 /* pin-controller instance 1 data */
905 /* pin-controller instance 2 data */
912 /* pin-controller instance 3 data */
921 /* pin banks of exynos4415 pin-controller 0 */
935 /* pin banks of exynos4415 pin-controller 1 */
960 /* pin banks of exynos4415 pin-controller 2 */
968 * three gpio/pin-mux/pinconfig controllers.
972 /* pin-controller instance 0 data */
979 /* pin-controller instance 1 data */
987 /* pin-controller instance 2 data */
996 /* pin banks of exynos5250 pin-controller 0 */
1025 /* pin banks of exynos5250 pin-controller 1 */
1038 /* pin banks of exynos5250 pin-controller 2 */
1047 /* pin banks of exynos5250 pin-controller 3 */
1054 * four gpio/pin-mux/pinconfig controllers.
1058 /* pin-controller instance 0 data */
1066 /* pin-controller instance 1 data */
1073 /* pin-controller instance 2 data */
1080 /* pin-controller instance 3 data */
1089 /* pin banks of exynos5260 pin-controller 0 */
1114 /* pin banks of exynos5260 pin-controller 1 */
1123 /* pin banks of exynos5260 pin-controller 2 */
1131 * three gpio/pin-mux/pinconfig controllers.
1135 /* pin-controller instance 0 data */
1141 /* pin-controller instance 1 data */
1146 /* pin-controller instance 2 data */
1153 /* pin banks of exynos5420 pin-controller 0 */
1162 /* pin banks of exynos5420 pin-controller 1 */
1179 /* pin banks of exynos5420 pin-controller 2 */
1191 /* pin banks of exynos5420 pin-controller 3 */
1204 /* pin banks of exynos5420 pin-controller 4 */
1211 * four gpio/pin-mux/pinconfig controllers.
1215 /* pin-controller instance 0 data */
1221 /* pin-controller instance 1 data */
1226 /* pin-controller instance 2 data */
1231 /* pin-controller instance 3 data */
1236 /* pin-controller instance 4 data */
1243 /* pin banks of exynos5433 pin-controller - ALIVE */
1251 /* pin banks of exynos5433 pin-controller - AUD */
1257 /* pin banks of exynos5433 pin-controller - CPIF */
1262 /* pin banks of exynos5433 pin-controller - eSE */
1267 /* pin banks of exynos5433 pin-controller - FINGER */
1272 /* pin banks of exynos5433 pin-controller - FSYS */
1282 /* pin banks of exynos5433 pin-controller - IMEM */
1287 /* pin banks of exynos5433 pin-controller - NFC */
1292 /* pin banks of exynos5433 pin-controller - PERIC */
1313 /* pin banks of exynos5433 pin-controller - TOUCH */
1320 * ten gpio/pin-mux/pinconfig controllers.
1324 /* pin-controller instance 0 data */
1331 /* pin-controller instance 1 data */
1338 /* pin-controller instance 2 data */
1345 /* pin-controller instance 3 data */
1352 /* pin-controller instance 4 data */
1359 /* pin-controller instance 5 data */
1366 /* pin-controller instance 6 data */
1373 /* pin-controller instance 7 data */
1380 /* pin-controller instance 8 data */
1387 /* pin-controller instance 9 data */
1396 /* pin banks of exynos7 pin-controller - ALIVE */
1404 /* pin banks of exynos7 pin-controller - BUS0 */
1423 /* pin banks of exynos7 pin-controller - NFC */
1428 /* pin banks of exynos7 pin-controller - TOUCH */
1433 /* pin banks of exynos7 pin-controller - FF */
1438 /* pin banks of exynos7 pin-controller - ESE */
1443 /* pin banks of exynos7 pin-controller - FSYS0 */
1448 /* pin banks of exynos7 pin-controller - FSYS1 */
1456 /* pin banks of exynos7 pin-controller - BUS1 */
1477 /* pin-controller instance 0 Alive data */
1482 /* pin-controller instance 1 BUS0 data */
1487 /* pin-controller instance 2 NFC data */
1492 /* pin-controller instance 3 TOUCH data */
1497 /* pin-controller instance 4 FF data */
1502 /* pin-controller instance 5 ESE data */
1507 /* pin-controller instance 6 FSYS0 data */
1512 /* pin-controller instance 7 FSYS1 data */
1517 /* pin-controller instance 8 BUS1 data */
1522 /* pin-controller instance 9 AUD data */
H A Dpinctrl-samsung.h2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
28 /* pinmux function number for pin as gpio output line */
33 * enum pincfg_type - possible pin configuration types supported.
53 * pin configuration (pull up/down and drive strength) type and its value are
72 * in a pin bank can support external gpio interrupts or external wakeup
85 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
106 * struct samsung_pin_bank_type: pin bank type description
116 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
118 * @pctl_offset: starting offset of the pin-bank registers.
120 * @eint_func: function to set in CON register to configure pin as EINT.
124 * @name: name to be prefixed for each pin in this pin bank.
138 * struct samsung_pin_bank: represent a controller pin-bank.
140 * @pctl_offset: starting offset of the pin-bank registers.
142 * @eint_func: function to set in CON register to configure pin as EINT.
146 * @name: name to be prefixed for each pin in this pin bank.
147 * @pin_base: starting pin number of the bank.
153 * @grange: linux gpio pin range supported by this bank.
182 * struct samsung_pin_ctrl: represent a pin controller.
183 * @pin_banks: list of pin banks included in this controller.
184 * @nr_banks: number of pin banks.
206 * @ctrl: pin controller instance managed by the driver.
207 * @pctl: pin controller descriptor registered with the pinctrl subsystem.
209 * @pin_groups: list of pin groups available to the driver.
210 * @nr_groups: number of such pin groups.
211 * @pmx_functions: list of pin functions available to the driver.
212 * @nr_function: number of such pin functions.
213 * @pin_base: starting system wide pin number.
241 * @name: name of the pin group, used to lookup the group.
254 * struct samsung_pmx_func: represent a pin function.
255 * @name: name of the pin function, used to lookup the function.
256 * @groups: one or more names of pin groups that provide this function.
H A Dpinctrl-exynos5440.c2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
50 * pin configuration type and its value are packed together into a 16-bits.
63 * enum pincfg_type - possible pin configuration types supported.
78 * @name: name of the pin group, used to lookup the group.
89 * struct exynos5440_pmx_func: represent a pin function.
90 * @name: name of the pin function, used to lookup the function.
91 * @groups: one or more names of pin groups that provide this function.
106 * @pin_groups: list of pin groups parsed from device tree.
107 * @nr_groups: number of pin groups available.
108 * @pmx_functions: list of pin functions parsed from device tree.
109 * @nr_functions: number of pin functions available.
139 { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
140 { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
141 { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
142 { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
145 /* check if the selector is a valid pin group selector */ exynos5440_get_group_count()
164 /* return the pin numbers associated with the specified group */ exynos5440_get_group_pins()
198 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) exynos5440_dt_node_to_map()
206 /* Allocate memory for pin-map entries */ exynos5440_dt_node_to_map()
213 * Allocate memory for pin group name. The pin group name is derived exynos5440_dt_node_to_map()
249 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) { exynos5440_dt_node_to_map()
273 /* free the memory allocated to hold the pin-map table */ exynos5440_dt_free_map()
303 /* check if the selector is a valid pin function selector */ exynos5440_get_functions_count()
312 /* return the name of the pin function specified */ exynos5440_pinmux_get_fname()
385 /* set the pin config settings for a specified pin */ exynos5440_pinconf_set()
386 static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, exynos5440_pinconf_set() argument
408 data &= ~(1 << pin); exynos5440_pinconf_set()
410 data |= (1 << pin); exynos5440_pinconf_set()
415 data &= ~(1 << pin); exynos5440_pinconf_set()
417 data |= (1 << pin); exynos5440_pinconf_set()
424 data &= ~(1 << pin); exynos5440_pinconf_set()
425 data |= ((cfg_value & 1) << pin); exynos5440_pinconf_set()
431 data &= ~(1 << pin); exynos5440_pinconf_set()
432 data |= ((cfg_value & 1) << pin); exynos5440_pinconf_set()
437 data &= ~(1 << pin); exynos5440_pinconf_set()
438 data |= ((cfg_value & 1) << pin); exynos5440_pinconf_set()
443 data &= ~(1 << pin); exynos5440_pinconf_set()
444 data |= ((cfg_value & 1) << pin); exynos5440_pinconf_set()
456 /* get the pin config settings for a specified pin */ exynos5440_pinconf_get()
457 static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, exynos5440_pinconf_get() argument
471 data = (data >> pin) & 1; exynos5440_pinconf_get()
475 *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1; exynos5440_pinconf_get()
479 data = (data >> pin) & 1; exynos5440_pinconf_get()
482 data = (data >> pin) & 1; exynos5440_pinconf_get()
487 *config = (data >> pin) & 1; exynos5440_pinconf_get()
491 *config = (data >> pin) & 1; exynos5440_pinconf_get()
501 /* set the pin config settings for a specified pin group */ exynos5440_pinconf_group_set()
520 /* get the pin config settings for a specified pin group */ exynos5440_pinconf_group_get()
575 /* first disable the data output enable on this pin */ exynos5440_gpio_direction_input()
580 /* now enable input on this pin */ exynos5440_gpio_direction_input()
597 /* first disable the data input enable on this pin */ exynos5440_gpio_direction_output()
602 /* now enable output on this pin */ exynos5440_gpio_direction_output()
625 /* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */ exynos5440_pinctrl_parse_dt_pins()
639 dev_err(dev, "invalid pin list in %s node", cfg_np->name); exynos5440_pinctrl_parse_dt_pins()
652 * Parse the information about all the available pin groups and pin functions
653 * from device node of the pin-controller.
685 * Iterate over all the child nodes of the pin controller node exynos5440_pinctrl_parse_dt()
686 * and create pin groups and pin function lists. exynos5440_pinctrl_parse_dt()
698 /* derive pin group name from the node name */ for_each_child_of_node()
710 ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function", for_each_child_of_node()
748 int pin, ret; exynos5440_pinctrl_register() local
767 /* dynamically populate the pin number and pin name for pindesc */ exynos5440_pinctrl_register()
768 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++) exynos5440_pinctrl_register()
769 pdesc->number = pin; exynos5440_pinctrl_register()
773 * the pins which belong to this pin-controller. exynos5440_pinctrl_register()
780 /* for each pin, set the name of the pin */ exynos5440_pinctrl_register()
781 for (pin = 0; pin < ctrldesc->npins; pin++) { exynos5440_pinctrl_register()
782 snprintf(pin_names, 6, "gpio%02d", pin); exynos5440_pinctrl_register()
783 pdesc = pindesc + pin; exynos5440_pinctrl_register()
H A Dpinctrl-samsung.c2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
41 { "samsung,pin-pud", PINCFG_TYPE_PUD },
42 { "samsung,pin-drv", PINCFG_TYPE_DRV },
43 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
44 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
45 { "samsung,pin-val", PINCFG_TYPE_DAT },
204 ret = of_property_read_u32(np, "samsung,pin-function", &val); samsung_dt_subnode_to_map()
305 /* check if the selector is a valid pin function selector */ samsung_get_functions_count()
314 /* return the name of the pin function specified */ samsung_pinmux_get_fname()
338 * given a pin number that is local to a pin controller, find out the pin bank
339 * and the register base of the pin bank.
342 unsigned pin, void __iomem **reg, u32 *offset, pin_to_reg_bank()
349 while ((pin >= b->pin_base) && pin_to_reg_bank()
350 ((b->pin_base + b->nr_pins - 1) < pin)) pin_to_reg_bank()
354 *offset = pin - b->pin_base; pin_to_reg_bank()
415 /* set or get the pin config settings for a specified pin */ samsung_pinconf_rw()
416 static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin, samsung_pinconf_rw() argument
429 pin_to_reg_bank(drvdata, pin - drvdata->pin_base, &reg_base, samsung_pinconf_rw()
461 /* set the pin config settings for a specified pin */ samsung_pinconf_set()
462 static int samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, samsung_pinconf_set() argument
468 ret = samsung_pinconf_rw(pctldev, pin, &configs[i], true); samsung_pinconf_set()
476 /* get the pin config settings for a specified pin */ samsung_pinconf_get()
477 static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, samsung_pinconf_get() argument
480 return samsung_pinconf_rw(pctldev, pin, config, false); samsung_pinconf_get()
483 /* set the pin config settings for a specified pin group */ samsung_pinconf_group_set()
501 /* get the pin config settings for a specified pin group */ samsung_pinconf_group_get()
617 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
669 if (of_property_read_u32(func_np, "samsung,pin-function", &func->val)) samsung_pinctrl_create_function()
674 dev_err(dev, "invalid pin list in %s node", func_np->name); samsung_pinctrl_create_function()
691 "failed to read pin name %d from %s node\n", samsung_pinctrl_create_function()
715 * Iterate over all the child nodes of the pin controller node samsung_pinctrl_create_functions()
716 * and create pin groups and pin function lists. samsung_pinctrl_create_functions()
723 "samsung,pin-function", NULL)) for_each_child_of_node()
731 "samsung,pin-function", NULL)) for_each_child_of_node()
746 * Iterate over all the child nodes of the pin controller node
747 * and create pin groups and pin function lists.
782 * Parse the information about all the available pin groups and pin functions
783 * from device node of the pin-controller. A pin group is formed with all
797 dev_err(dev, "failed to parse pin groups\n"); samsung_pinctrl_parse_dt()
803 dev_err(dev, "failed to parse pin functions\n"); samsung_pinctrl_parse_dt()
823 int pin, bank, ret; samsung_pinctrl_register() local
834 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); samsung_pinctrl_register()
840 /* dynamically populate the pin number and pin name for pindesc */ samsung_pinctrl_register()
841 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++) samsung_pinctrl_register()
842 pdesc->number = pin + drvdata->pin_base; samsung_pinctrl_register()
846 * the pins which belong to this pin-controller. samsung_pinctrl_register()
851 dev_err(&pdev->dev, "mem alloc for pin names failed\n"); samsung_pinctrl_register()
855 /* for each pin, the name of the pin is pin-bank name + pin number */ samsung_pinctrl_register()
858 for (pin = 0; pin < pin_bank->nr_pins; pin++) { samsung_pinctrl_register()
859 sprintf(pin_names, "%s-%d", pin_bank->name, pin); samsung_pinctrl_register()
860 pdesc = pindesc + pin_bank->pin_base + pin; samsung_pinctrl_register()
341 pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata, unsigned pin, void __iomem **reg, u32 *offset, struct samsung_pin_bank **bank) pin_to_reg_bank() argument
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Ddce6_afmt.c67 offset = rdev->audio.pin[i].offset; dce6_afmt_get_connected_pins()
71 rdev->audio.pin[i].connected = false; dce6_afmt_get_connected_pins()
73 rdev->audio.pin[i].connected = true; dce6_afmt_get_connected_pins()
82 struct r600_audio_pin *pin = NULL; dce6_audio_get_pin() local
88 if (rdev->audio.pin[i].connected) { dce6_audio_get_pin()
89 pin = &rdev->audio.pin[i]; dce6_audio_get_pin()
96 if (dig->pin == pin) dce6_audio_get_pin()
102 return pin; dce6_audio_get_pin()
105 if (!pin) dce6_audio_get_pin()
107 return pin; dce6_audio_get_pin()
116 if (!dig || !dig->afmt || !dig->pin) dce6_afmt_select_pin()
120 AFMT_AUDIO_SRC_SELECT(dig->pin->id)); dce6_afmt_select_pin()
132 if (!dig || !dig->afmt || !dig->pin) dce6_afmt_write_latency_fields()
148 WREG32_ENDPOINT(dig->pin->offset, dce6_afmt_write_latency_fields()
160 if (!dig || !dig->afmt || !dig->pin) dce6_afmt_hdmi_write_speaker_allocation()
164 tmp = RREG32_ENDPOINT(dig->pin->offset, dce6_afmt_hdmi_write_speaker_allocation()
173 WREG32_ENDPOINT(dig->pin->offset, dce6_afmt_hdmi_write_speaker_allocation()
185 if (!dig || !dig->afmt || !dig->pin) dce6_afmt_dp_write_speaker_allocation()
189 tmp = RREG32_ENDPOINT(dig->pin->offset, dce6_afmt_dp_write_speaker_allocation()
198 WREG32_ENDPOINT(dig->pin->offset, dce6_afmt_dp_write_speaker_allocation()
224 if (!dig || !dig->afmt || !dig->pin) dce6_afmt_write_sad_regs()
253 WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value); dce6_afmt_write_sad_regs()
258 struct r600_audio_pin *pin, dce6_audio_enable()
261 if (!pin) dce6_audio_enable()
264 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, dce6_audio_enable()
257 dce6_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin, u8 enable_mask) dce6_audio_enable() argument
/linux-4.4.14/arch/powerpc/sysdev/qe_lib/
H A Dqe_io.c52 void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir, __par_io_config_pin() argument
60 /* calculate pin location for single and 2 bits information */ __par_io_config_pin()
61 pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1))); __par_io_config_pin()
71 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? __par_io_config_pin()
77 (pin % (QE_PIO_PINS / 2) + 1) * 2)); __par_io_config_pin()
81 (pin % (QE_PIO_PINS / 2) + 1) * 2)); __par_io_config_pin()
84 if (pin > (QE_PIO_PINS / 2) - 1) { __par_io_config_pin()
95 /* define pin assignment */ __par_io_config_pin()
96 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? __par_io_config_pin()
101 (pin % (QE_PIO_PINS / 2) + 1) * 2)); __par_io_config_pin()
103 if (pin > (QE_PIO_PINS / 2) - 1) { __par_io_config_pin()
117 int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, par_io_config_pin() argument
123 __par_io_config_pin(&par_io[port], pin, dir, open_drain, assignment, par_io_config_pin()
129 int par_io_data_set(u8 port, u8 pin, u8 val) par_io_data_set() argument
135 if (pin >= QE_PIO_PINS) par_io_data_set()
137 /* calculate pin location */ par_io_data_set()
138 pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin)); par_io_data_set()
H A Dgpio.c131 * qe_pin_request - Request a QE pin
132 * @np: device node to get a pin from
133 * @index: index of a pin in the device tree
162 pr_debug("%s: tried to get a non-qe pin\n", __func__); qe_pin_request()
193 * qe_pin_free - Free a pin
197 * This function frees the qe_pin structure and makes a pin available
204 const int pin = qe_pin->num; qe_pin_free() local
207 test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]); qe_pin_free()
215 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
219 * This function resets a pin to a dedicated peripheral function that
227 int pin = qe_pin->num; qe_pin_set_dedicated() local
228 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); qe_pin_set_dedicated()
229 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); qe_pin_set_dedicated()
230 bool second_reg = pin > (QE_PIO_PINS / 2) - 1; qe_pin_set_dedicated()
256 * qe_pin_set_gpio - Set a pin to the GPIO mode
260 * This function sets a pin to the GPIO mode.
/linux-4.4.14/arch/mn10300/unit-asb2305/
H A Dpci-irq.c11 * This is simple: All PCI interrupts route through the CPU's XIRQ1 pin [IRQ 35]
30 u8 line, pin; pcibios_fixup_irqs() local
33 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); for_each_pci_dev()
34 if (pin) { for_each_pci_dev()
/linux-4.4.14/arch/frv/mb93090-mb00/
H A Dpci-irq.c46 uint8_t line, pin; pcibios_fixup_irqs() local
49 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); for_each_pci_dev()
50 if (pin) { for_each_pci_dev()
51 dev->irq = pci_bus0_irq_routing[PCI_SLOT(dev->devfn)][pin - 1]; for_each_pci_dev()
/linux-4.4.14/arch/arm/mach-mmp/include/mach/
H A Dmfp.h28 #define MFP_CFG(pin, af) \
29 (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
31 #define MFP_CFG_DRV(pin, af, drv) \
32 (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
/linux-4.4.14/arch/arm/mach-pxa/include/mach/
H A Dmioa701.h4 #define MIO_CFG_IN(pin, af) \
6 (MFP_PIN(pin) | MFP_##af | MFP_DIR_IN))
8 #define MIO_CFG_OUT(pin, af, state) \
10 (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
/linux-4.4.14/include/linux/i2c/
H A Dds620.h11 * Thermostat output pin PO mode:
/linux-4.4.14/drivers/acpi/
H A Dpci_irq.c44 u8 pin; member in struct:acpi_prt_entry
49 static inline char pin_name(int pin) pin_name() argument
51 return 'A' + pin - 1; pin_name()
100 unsigned char pin; member in struct:prt_quirk
109 * interrupt at the listed segment/bus/device/pin is connected to the first
141 entry->pin == quirk->pin && do_prt_fixups()
148 entry->id.device, pin_name(entry->pin), do_prt_fixups()
156 int pin, struct acpi_pci_routing_table *prt, acpi_pci_irq_check_entry()
165 prt->pin + 1 != pin) acpi_pci_irq_check_entry()
180 entry->pin = prt->pin + 1; acpi_pci_irq_check_entry()
190 * configure the IRQ assigned to this slot|dev|pin. The 'source_index' acpi_pci_irq_check_entry()
213 entry->id.device, pin_name(entry->pin), acpi_pci_irq_check_entry()
222 int pin, struct acpi_prt_entry **entry_ptr) acpi_pci_irq_find_prt_entry()
244 if (!acpi_pci_irq_check_entry(handle, dev, pin, acpi_pci_irq_find_prt_entry()
313 static struct acpi_prt_entry *acpi_pci_irq_lookup(struct pci_dev *dev, int pin) acpi_pci_irq_lookup() argument
317 u8 bridge_pin, orig_pin = pin; acpi_pci_irq_lookup()
320 ret = acpi_pci_irq_find_prt_entry(dev, pin, &entry); acpi_pci_irq_lookup()
326 pci_name(dev), pin_name(pin))); acpi_pci_irq_lookup()
336 pin = pci_swizzle_interrupt_pin(dev, pin); acpi_pci_irq_lookup()
340 bridge_pin = bridge->pin; acpi_pci_irq_lookup()
343 "No interrupt pin configured for device %s\n", acpi_pci_irq_lookup()
347 pin = bridge_pin; acpi_pci_irq_lookup()
350 ret = acpi_pci_irq_find_prt_entry(bridge, pin, &entry); acpi_pci_irq_lookup()
378 pin_name(dev->pin), dev->irq); acpi_isa_register_gsi()
397 u8 pin; acpi_pci_irq_enable() local
404 pin = dev->pin; acpi_pci_irq_enable()
405 if (!pin) { acpi_pci_irq_enable()
407 "No interrupt pin configured for device %s\n", acpi_pci_irq_enable()
415 entry = acpi_pci_irq_lookup(dev, pin); acpi_pci_irq_enable()
444 pin_name(pin)); acpi_pci_irq_enable()
453 pin_name(pin)); acpi_pci_irq_enable()
466 pin_name(pin), link_desc, gsi, acpi_pci_irq_enable()
478 u8 pin; acpi_pci_irq_disable() local
480 pin = dev->pin; acpi_pci_irq_disable()
481 if (!pin || !dev->irq_managed || dev->irq <= 0) acpi_pci_irq_disable()
484 /* Keep IOAPIC pin configuration when suspending */ acpi_pci_irq_disable()
492 entry = acpi_pci_irq_lookup(dev, pin); acpi_pci_irq_disable()
508 dev_dbg(&dev->dev, "PCI INT %c disabled\n", pin_name(pin)); acpi_pci_irq_disable()
155 acpi_pci_irq_check_entry(acpi_handle handle, struct pci_dev *dev, int pin, struct acpi_pci_routing_table *prt, struct acpi_prt_entry **entry_ptr) acpi_pci_irq_check_entry() argument
221 acpi_pci_irq_find_prt_entry(struct pci_dev *dev, int pin, struct acpi_prt_entry **entry_ptr) acpi_pci_irq_find_prt_entry() argument
/linux-4.4.14/drivers/staging/iio/adc/
H A Dad7606.h20 * @gpio_convst: number of gpio connected to the CONVST pin
21 * @gpio_reset: gpio connected to the RESET pin, if not used set to -1
22 * @gpio_range: gpio connected to the RANGE pin, if not used set to -1
23 * @gpio_os0: gpio connected to the OS0 pin, if not used set to -1
24 * @gpio_os1: gpio connected to the OS1 pin, if not used set to -1
25 * @gpio_os2: gpio connected to the OS2 pin, if not used set to -1
26 * @gpio_frstdata: gpio connected to the FRSTDAT pin, if not used set to -1
27 * @gpio_stby: gpio connected to the STBY pin, if not used set to -1
H A Dad7192.h21 * 2 Internal 4.92 MHz Clock not available at the MCLK2 pin
22 * 3 Internal 4.92 MHz Clock available at the MCLK2 pin
/linux-4.4.14/arch/m32r/include/asm/
H A Dirq.h10 * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
23 * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
24 * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
25 * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
47 * ICU of OPSPUT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
48 * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
49 * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
72 * ICU of M32104UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
/linux-4.4.14/arch/arm/mach-ixp4xx/
H A Dfsg-pci.c28 /* PCI controller GPIO to IRQ pin mappings */
41 static int __init fsg_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) fsg_map_irq() argument
52 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) fsg_map_irq()
54 printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n", fsg_map_irq()
55 __func__, slot, pin, irq); fsg_map_irq()
H A Dgtwx5715-pci.c52 static int __init gtwx5715_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) gtwx5715_map_irq() argument
56 if ((slot == SLOT0_DEVID && pin == 1) || gtwx5715_map_irq()
57 (slot == SLOT1_DEVID && pin == 2)) gtwx5715_map_irq()
59 else if ((slot == SLOT0_DEVID && pin == 2) || gtwx5715_map_irq()
60 (slot == SLOT1_DEVID && pin == 1)) gtwx5715_map_irq()
63 printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n", gtwx5715_map_irq()
64 __func__, slot, pin, rc); gtwx5715_map_irq()
H A Davila-pci.c34 /* PCI controller GPIO to IRQ pin mappings */
49 static int __init avila_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) avila_map_irq() argument
60 pin >= 1 && pin <= IRQ_LINES) avila_map_irq()
61 return pci_irq_table[(slot + pin - 2) % 4]; avila_map_irq()
H A Ddsmg600-pci.c28 /* PCI controller GPIO to IRQ pin mappings */
47 static int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) dsmg600_map_irq() argument
57 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) dsmg600_map_irq()
58 return pci_irq_table[slot - 1][pin - 1]; dsmg600_map_irq()
H A Dixdp425-pci.c30 /* PCI controller GPIO to IRQ pin mappings */
46 static int __init ixdp425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ixdp425_map_irq() argument
55 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) ixdp425_map_irq()
56 return pci_irq_table[(slot + pin - 2) % 4]; ixdp425_map_irq()
H A Dmiccpt-pci.c31 /* PCI controller GPIO to IRQ pin mappings */
47 static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) miccpt_map_irq() argument
56 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) miccpt_map_irq()
57 return pci_irq_table[(slot + pin - 2) % 4]; miccpt_map_irq()
H A Dnas100d-pci.c27 /* PCI controller GPIO to IRQ pin mappings */
44 static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) nas100d_map_irq() argument
53 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) nas100d_map_irq()
54 return pci_irq_table[slot - 1][pin - 1]; nas100d_map_irq()
H A Dnslu2-pci.c27 /* PCI controller GPIO to IRQ pin mappings */
41 static int __init nslu2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) nslu2_map_irq() argument
49 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) nslu2_map_irq()
50 return pci_irq_table[(slot + pin - 2) % IRQ_LINES]; nslu2_map_irq()
H A Dcoyote-pci.c29 /* PCI controller GPIO to IRQ pin mappings */
40 static int __init coyote_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) coyote_map_irq() argument
/linux-4.4.14/arch/sh/include/mach-se/mach/
H A Dse7780.h92 /* interrupt pin */
93 #define IRQPIN_EXTINT1 0 /* IRQ0 pin */
94 #define IRQPIN_EXTINT2 1 /* IRQ1 pin */
95 #define IRQPIN_EXTINT3 2 /* IRQ2 pin */
96 #define IRQPIN_SMC91CX 3 /* IRQ3 pin */
97 #define IRQPIN_EXTINT4 4 /* IRQ4 pin */
98 #define IRQPIN_PCC0 5 /* IRQ5 pin */
99 #define IRQPIN_PCC2 6 /* IRQ6 pin */
100 #define IRQPIN_SM501 7 /* IRQ7 pin */
101 #define IRQPIN_PCCPW 7 /* IRQ7 pin */
/linux-4.4.14/sound/pci/lola/
H A Dlola_mixer.c31 static int lola_init_pin(struct lola *chip, struct lola_pin *pin, lola_init_pin() argument
37 pin->nid = nid; lola_init_pin()
45 pin->is_analog = false; lola_init_pin()
47 pin->is_analog = true; lola_init_pin()
49 pin->is_analog = true; lola_init_pin()
55 /* analog parameters only following, so continue in case of Digital pin lola_init_pin()
57 if (!pin->is_analog) lola_init_pin()
69 pin->amp_mute = LOLA_AMP_MUTE_CAPABLE(val); lola_init_pin()
70 pin->amp_step_size = LOLA_AMP_STEP_SIZE(val); lola_init_pin()
71 pin->amp_num_steps = LOLA_AMP_NUM_STEPS(val); lola_init_pin()
72 if (pin->amp_num_steps) { lola_init_pin()
74 pin->amp_num_steps++; lola_init_pin()
75 pin->amp_step_size++; lola_init_pin()
77 pin->amp_offset = LOLA_AMP_OFFSET(val); lola_init_pin()
85 pin->max_level = val & 0x3ff; /* 10 bits */ lola_init_pin()
87 pin->config_default_reg = 0; lola_init_pin()
88 pin->fixed_gain_list_len = 0; lola_init_pin()
89 pin->cur_gain_step = 0; lola_init_pin()
98 for (i = 0; i < chip->pin[dir].num_pins; i++, nid++) { lola_init_pins()
99 err = lola_init_pin(chip, &chip->pin[dir].pins[i], dir, nid); lola_init_pins()
102 if (chip->pin[dir].pins[i].is_analog) lola_init_pins()
103 chip->pin[dir].num_analog_pins++; lola_init_pins()
140 chip->mixer.src_phys_ins = chip->pin[CAPT].num_pins; lola_init_mixer_widget()
144 chip->mixer.dest_phys_outs = chip->pin[PLAY].num_pins; lola_init_mixer_widget()
335 struct lola_pin *pin; lola_setup_all_analog_gains() local
338 pin = chip->pin[dir].pins; lola_setup_all_analog_gains()
339 max_idx = chip->pin[dir].num_pins; lola_setup_all_analog_gains()
341 if (pin[idx].is_analog) { lola_setup_all_analog_gains()
342 unsigned int val = mute ? 0 : pin[idx].cur_gain_step; lola_setup_all_analog_gains()
400 struct lola_pin *pin; set_analog_volume() local
403 if (idx >= chip->pin[dir].num_pins) set_analog_volume()
405 pin = &chip->pin[dir].pins[idx]; set_analog_volume()
406 if (!pin->is_analog || pin->amp_num_steps <= val) set_analog_volume()
408 if (external_call && pin->cur_gain_step == val) set_analog_volume()
415 err = lola_codec_write(chip, pin->nid, set_analog_volume()
420 pin->cur_gain_step = val; set_analog_volume()
434 for (n = 0; n < chip->pin[CAPT].num_pins; n += 2) { lola_set_src_config()
467 lola_set_src_config(chip, (1 << chip->pin[CAPT].num_pins) - 1, false); init_mixer_values()
519 uinfo->count = chip->pin[dir].num_pins; lola_analog_vol_info()
521 uinfo->value.integer.max = chip->pin[dir].pins[0].amp_num_steps; lola_analog_vol_info()
532 for (i = 0; i < chip->pin[dir].num_pins; i++) lola_analog_vol_get()
534 chip->pin[dir].pins[i].cur_gain_step; lola_analog_vol_get()
545 for (i = 0; i < chip->pin[dir].num_pins; i++) { lola_analog_vol_put()
561 struct lola_pin *pin; lola_analog_vol_tlv() local
565 pin = &chip->pin[dir].pins[0]; lola_analog_vol_tlv()
567 val2 = pin->amp_step_size * 25; lola_analog_vol_tlv()
568 val1 = -1 * (int)pin->amp_offset * (int)val2; lola_analog_vol_tlv()
596 if (!chip->pin[dir].num_pins) create_analog_mixer()
599 if (chip->pin[dir].num_pins != chip->pin[dir].num_analog_pins) create_analog_mixer()
616 uinfo->count = chip->pin[CAPT].num_pins; lola_input_src_info()
628 for (i = 0; i < chip->pin[CAPT].num_pins; i++) lola_input_src_get()
642 for (i = 0; i < chip->pin[CAPT].num_pins; i++) lola_input_src_put()
/linux-4.4.14/drivers/pinctrl/nomadik/
H A Dpinctrl-nomadik.h27 .pin = pin_num,\
84 * struct prcm_gpio_altcx_pin_desc - Other alternate-C pin
85 * @pin: The pin number
89 unsigned short pin; member in struct:prcm_gpiocr_altcx_pin_desc
96 * @groups: An array of pin groups that may select this function.
106 * struct nmk_pingroup - describes a Nomadik pin group
107 * @name: the name of this specific pin group
109 * from the driver-local pin enumeration space
123 * struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration
124 * @pins: An array describing all pins the pin controller affects.
131 * @groups: An array describing all pin groups the pin SoC supports.
H A Dpinctrl-abx500.h33 * @groups: An array of pin groups that may select this function.
43 * struct abx500_pingroup - describes a ABx500 pin group
44 * @name: the name of this specific pin group
46 * from the driver-local pin enumeration space
59 #define ALTERNATE_FUNCTIONS(pin, sel_bit, alt1, alt2, alta, altb, altc) \
61 .pin_number = pin, \
73 * @pin_number: The pin number
100 * @first_pin: The pin number of the first pins which support
102 * @last_pin: The pin number of the last pins
119 * @start: The pin number of the first pin interrupt capable
120 * @end: The pin number of the last pin interrupt capable
134 * struct abx500_pinrange - map pin numbers to GPIO offsets
136 * identical to the offset into the local pin numberspace
138 * @altfunc: altfunc setting to be used to enable GPIO on a pin in
150 * struct abx500_pinctrl_soc_data - ABx500 pin controller per-SoC configuration
153 * @pins: An array describing all pins the pin controller affects.
160 * @groups: An array describing all pin groups the pin SoC supports.
/linux-4.4.14/arch/mips/ath79/
H A Dpci.c31 .pin = 1,
35 .pin = 1,
39 .pin = 1,
47 .pin = 1,
56 .pin = 1,
62 .pin = 1,
67 int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) pcibios_map_irq() argument
98 entry->pin == pin) { pcibios_map_irq()
105 pr_crit("pci %s: no irq found for pin %u\n", pcibios_map_irq()
106 pci_name((struct pci_dev *) dev), pin); pcibios_map_irq()
108 pr_info("pci %s: using irq %d for pin %u\n", pcibios_map_irq()
109 pci_name((struct pci_dev *) dev), irq, pin); pcibios_map_irq()
/linux-4.4.14/drivers/pwm/
H A Dpwm-bfin.c22 unsigned short pin; member in struct:bfin_pwm
42 priv->pin = pwm_to_gptimer_per[pwm->hwpwm]; bfin_pwm_request()
44 ret = peripheral_request(priv->pin, NULL); bfin_pwm_request()
60 peripheral_free(priv->pin); bfin_pwm_free()
83 set_gptimer_config(priv->pin, TIMER_MODE_PWM | TIMER_PERIOD_CNT); bfin_pwm_config()
84 set_gptimer_pwidth(priv->pin, duty); bfin_pwm_config()
85 set_gptimer_period(priv->pin, period); bfin_pwm_config()
94 enable_gptimer(priv->pin); bfin_pwm_enable()
103 disable_gptimer(priv->pin); bfin_pwm_disable()
/linux-4.4.14/arch/arm/plat-orion/include/plat/
H A Dorion-gpio.h23 void orion_gpio_set_unused(unsigned pin);
24 void orion_gpio_set_blink(unsigned pin, int blink);
30 void orion_gpio_set_valid(unsigned pin, int mode);
/linux-4.4.14/drivers/w1/masters/
H A Dw1-gpio.c34 gpio_direction_output(pdata->pin, 1); w1_gpio_set_pullup()
38 gpio_direction_input(pdata->pin); w1_gpio_set_pullup()
51 gpio_direction_input(pdata->pin); w1_gpio_write_bit_dir()
53 gpio_direction_output(pdata->pin, 0); w1_gpio_write_bit_dir()
60 gpio_set_value(pdata->pin, bit); w1_gpio_write_bit_val()
67 return gpio_get_value(pdata->pin) ? 1 : 0; w1_gpio_read_bit()
95 "Failed to parse gpio property for data pin (%d)\n", w1_gpio_probe_dt()
100 pdata->pin = gpio; w1_gpio_probe_dt()
139 err = devm_gpio_request(&pdev->dev, pdata->pin, "w1"); w1_gpio_probe()
141 dev_err(&pdev->dev, "gpio_request (pin) failed\n"); w1_gpio_probe()
160 gpio_direction_output(pdata->pin, 1); w1_gpio_probe()
163 gpio_direction_input(pdata->pin); w1_gpio_probe()
/linux-4.4.14/arch/powerpc/platforms/8xx/
H A Dadder875.c26 int port, pin, flags; member in struct:cpm_pin
73 const struct cpm_pin *pin = &adder875_pins[i]; init_ioports() local
74 cpm1_set_pin(pin->port, pin->pin, pin->flags); init_ioports()
H A Dtqm8xx_setup.c48 int port, pin, flags; member in struct:cpm_pin
83 static void __init init_pins(int n, struct cpm_pin *pin) init_pins() argument
88 cpm1_set_pin(pin->port, pin->pin, pin->flags); init_pins()
89 pin++; init_pins()
H A Dep88xc.c25 int port, pin, flags; member in struct:cpm_pin
93 struct cpm_pin *pin = &ep88xc_pins[i]; init_ioports() local
94 cpm1_set_pin(pin->port, pin->pin, pin->flags); init_ioports()
H A Dmpc86xads_setup.c34 int port, pin, flags; member in struct:cpm_pin
80 struct cpm_pin *pin = &mpc866ads_pins[i]; init_ioports() local
81 cpm1_set_pin(pin->port, pin->pin, pin->flags); init_ioports()
/linux-4.4.14/include/media/
H A Dnoon010pc30.h18 * @gpio_nreset: GPIO driving nRESET pin
19 * @gpio_nstby: GPIO driving nSTBY pin
H A Dov9650.h16 * @gpio_pwdn: number of a GPIO connected to OV965X PWDN pin
17 * @gpio_reset: number of a GPIO connected to OV965X RESET pin
H A Ds5k4ecgx.h28 * @gpio_reset: GPIO driving RESET pin
29 * @gpio_stby : GPIO driving STBY pin
H A Dm5mols.h21 * @gpio_reset: GPIO driving the reset pin of M-5MOLS
22 * @reset_polarity: active state for gpio_reset pin, 0 or 1
H A Dsii9234.h17 * @gpio_n_reset: GPIO driving nRESET pin
/linux-4.4.14/arch/mips/pci/
H A Dfixup-lantiq.c26 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) pcibios_map_irq() argument
28 return of_irq_parse_and_map_pci(dev, slot, pin); pcibios_map_irq()
H A Dfixup-bcm63xx.c13 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) pcibios_map_irq() argument
H A Dfixup-ip32.c36 * Given a PCI slot number (a la PCI_SLOT(...)) and the interrupt pin of
39 * irqs. I suppose a device without a pin A will thank us for doing it
42 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) pcibios_map_irq() argument
44 return irq_tab_mace[slot][pin]; pcibios_map_irq()
H A Dfixup-lemote2f.c32 /* all the pci device has the PCIA pin, check the datasheet. */
54 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) pcibios_map_irq() argument
60 virq = irq_tab[slot][pin]; pcibios_map_irq()
61 printk(KERN_INFO "slot: %d, pin: %d, irq: %d\n", slot, pin, pcibios_map_irq()
108 /* setting the mutex pin as IDE function */ loongson_cs5536_ide_fixup()
H A Dfixup-rbtx4938.c16 int __init rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) rbtx4938_pci_map_irq() argument
22 irq = pin; rbtx4938_pci_map_irq()
/linux-4.4.14/arch/m68k/68000/
H A Dm68VZ328.c74 /* PK3: hardware sleep function pin, active low */ init_hardware()
75 PKSEL |= PK(3); /* select pin as I/O */ init_hardware()
76 PKDIR |= PK(3); /* select pin as output */ init_hardware()
77 PKDATA |= PK(3); /* set pin high */ init_hardware()
79 /* PF5: hardware reset function pin, active high */ init_hardware()
80 PFSEL |= PF(5); /* select pin as I/O */ init_hardware()
81 PFDIR |= PF(5); /* select pin as output */ init_hardware()
82 PFDATA &= ~PF(5); /* set pin low */ init_hardware()
/linux-4.4.14/arch/arm/mach-footbridge/
H A Debsa285-pci.c18 static int __init ebsa285_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ebsa285_map_irq() argument
28 return irqmap_ebsa285[(slot + pin) & 3]; ebsa285_map_irq()
H A Dcats-pci.c19 static u8 cats_no_swizzle(struct pci_dev *dev, u8 *pin) cats_no_swizzle() argument
24 static int __init cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) cats_map_irq() argument
/linux-4.4.14/arch/arm/mach-ks8695/include/mach/
H A Dgpio-ks8695.h32 * Configure GPIO pin as external interrupt source.
34 extern int ks8695_gpio_interrupt(unsigned int pin, unsigned int type);
/linux-4.4.14/drivers/pinctrl/spear/
H A Dpinctrl-plgpio.c25 #define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
26 #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \
57 * p2o: function ptr for pin to offset conversion. This is required only for
58 * machines where mapping b/w pin and offset is not 1-to-1.
59 * o2p: function ptr for offset to pin conversion. This is required only for
60 * machines where mapping b/w pin and offset is not 1-to-1.
70 int (*p2o)(int pin); /* pin_to_offset */
80 static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg) is_plgpio_set() argument
82 u32 offset = PIN_OFFSET(pin); is_plgpio_set()
83 void __iomem *reg_off = REG_OFFSET(base, reg, pin); is_plgpio_set()
89 static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg) plgpio_reg_set() argument
91 u32 offset = PIN_OFFSET(pin); plgpio_reg_set()
92 void __iomem *reg_off = REG_OFFSET(base, reg, pin); plgpio_reg_set()
98 static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg) plgpio_reg_reset() argument
100 u32 offset = PIN_OFFSET(pin); plgpio_reg_reset()
101 void __iomem *reg_off = REG_OFFSET(base, reg, pin); plgpio_reg_reset()
113 /* get correct offset for "offset" pin */ plgpio_direction_input()
134 /* get correct offset for "offset" pin */ plgpio_direction_output()
167 /* get correct offset for "offset" pin */ plgpio_get_value()
184 /* get correct offset for "offset" pin */ plgpio_set_value()
227 /* get correct offset for "offset" pin */ plgpio_request()
261 /* get correct offset for "offset" pin */ plgpio_free()
287 /* get correct offset for "offset" pin */ plgpio_irq_disable()
306 /* get correct offset for "offset" pin */ plgpio_irq_enable()
364 int regs_count, count, pin, offset, i = 0; plgpio_irq_handler() local
393 /* get correct pin for "offset" */ plgpio_irq_handler()
395 pin = plgpio->o2p(offset); plgpio_irq_handler()
396 if (pin == -1) plgpio_irq_handler()
399 pin = offset; plgpio_irq_handler()
402 pin = i * MAX_GPIO_PER_REG + pin; plgpio_irq_handler()
404 irq_find_mapping(gc->irqdomain, pin)); plgpio_irq_handler()
411 * pin to offset and offset to pin converter functions
414 * for different plgpio pins. For example: for pin 27, bit offset is 23, pin
415 * 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1
417 static int spear310_p2o(int pin) spear310_p2o() argument
419 int offset = pin; spear310_p2o()
421 if (pin <= 27) spear310_p2o()
423 else if (pin <= 33) spear310_p2o()
425 else if (pin <= 97) spear310_p2o()
427 else if (pin <= 101) spear310_p2o()
428 offset = 101 - pin; spear310_p2o()
/linux-4.4.14/arch/x86/kernel/apic/
H A Dio_apic.c71 #define for_each_pin(idx, pin) \
72 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
73 #define for_each_ioapic_pin(idx, pin) \
75 for_each_pin((idx), (pin))
86 int apic, pin; member in struct:irq_pin_list
145 static inline u32 mp_pin_to_gsi(int ioapic, int pin) mp_pin_to_gsi() argument
147 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; mp_pin_to_gsi()
305 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) __ioapic_read_entry() argument
309 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); __ioapic_read_entry()
310 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); __ioapic_read_entry()
315 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) ioapic_read_entry() argument
321 eu.entry = __ioapic_read_entry(apic, pin); ioapic_read_entry()
333 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) __ioapic_write_entry() argument
338 io_apic_write(apic, 0x11 + 2*pin, eu.w2); __ioapic_write_entry()
339 io_apic_write(apic, 0x10 + 2*pin, eu.w1); __ioapic_write_entry()
342 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) ioapic_write_entry() argument
347 __ioapic_write_entry(apic, pin, e); ioapic_write_entry()
356 static void ioapic_mask_entry(int apic, int pin) ioapic_mask_entry() argument
362 io_apic_write(apic, 0x10 + 2*pin, eu.w1); ioapic_mask_entry()
363 io_apic_write(apic, 0x11 + 2*pin, eu.w2); ioapic_mask_entry()
368 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
373 int node, int apic, int pin) __add_pin_to_irq_node()
379 if (entry->apic == apic && entry->pin == pin) __add_pin_to_irq_node()
385 node, apic, pin); __add_pin_to_irq_node()
389 entry->pin = pin; __add_pin_to_irq_node()
395 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin) __remove_pin_from_irq() argument
400 if (entry->apic == apic && entry->pin == pin) { __remove_pin_from_irq()
408 int node, int apic, int pin) add_pin_to_irq_node()
410 if (__add_pin_to_irq_node(data, node, apic, pin)) add_pin_to_irq_node()
411 panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); add_pin_to_irq_node()
415 * Reroute an IRQ to a different pin.
424 if (entry->apic == oldapic && entry->pin == oldpin) { replace_pin_at_irq_node()
426 entry->pin = newpin; replace_pin_at_irq_node()
432 /* old apic/pin didn't exist, so just add new ones */ replace_pin_at_irq_node()
449 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1); io_apic_modify_irq()
508 static void __eoi_ioapic_pin(int apic, int pin, int vector) __eoi_ioapic_pin() argument
515 entry = entry1 = __ioapic_read_entry(apic, pin); __eoi_ioapic_pin()
523 __ioapic_write_entry(apic, pin, entry1); __eoi_ioapic_pin()
528 __ioapic_write_entry(apic, pin, entry); __eoi_ioapic_pin()
539 __eoi_ioapic_pin(entry->apic, entry->pin, vector); eoi_ioapic_pin()
543 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) clear_IO_APIC_pin() argument
547 /* Check delivery_mode to be sure we're not clearing an SMI pin */ clear_IO_APIC_pin()
548 entry = ioapic_read_entry(apic, pin); clear_IO_APIC_pin()
554 * if it is a level triggered pin and if the remote-IRR is set. clear_IO_APIC_pin()
558 ioapic_write_entry(apic, pin, entry); clear_IO_APIC_pin()
559 entry = ioapic_read_entry(apic, pin); clear_IO_APIC_pin()
572 ioapic_write_entry(apic, pin, entry); clear_IO_APIC_pin()
575 __eoi_ioapic_pin(apic, pin, entry.vector); clear_IO_APIC_pin()
583 ioapic_mask_entry(apic, pin); clear_IO_APIC_pin()
584 entry = ioapic_read_entry(apic, pin); clear_IO_APIC_pin()
586 pr_err("Unable to reset IRR for apic: %d, pin :%d\n", clear_IO_APIC_pin()
587 mpc_ioapic_id(apic), pin); clear_IO_APIC_pin()
592 int apic, pin; clear_IO_APIC() local
594 for_each_ioapic_pin(apic, pin) clear_IO_APIC()
595 clear_IO_APIC_pin(apic, pin); clear_IO_APIC()
641 int apic, pin; save_ioapic_entries() local
650 for_each_pin(apic, pin) for_each_ioapic()
651 ioapics[apic].saved_registers[pin] = for_each_ioapic()
652 ioapic_read_entry(apic, pin); for_each_ioapic()
663 int apic, pin; mask_ioapic_entries() local
669 for_each_pin(apic, pin) { for_each_pin()
672 entry = ioapics[apic].saved_registers[pin]; for_each_pin()
675 ioapic_write_entry(apic, pin, entry); for_each_pin()
686 int apic, pin; restore_ioapic_entries() local
692 for_each_pin(apic, pin) for_each_ioapic()
693 ioapic_write_entry(apic, pin, for_each_ioapic()
694 ioapics[apic].saved_registers[pin]); for_each_ioapic()
700 * Find the IRQ entry number of a certain pin.
702 static int find_irq_entry(int ioapic_idx, int pin, int type) find_irq_entry() argument
710 mp_irqs[i].dstirq == pin) find_irq_entry()
717 * Find the pin to which IRQ[irq] (ISA) is connected
884 u32 gsi, int ioapic_idx, int pin) ioapic_copy_alloc_attr()
891 dst->ioapic_pin = pin; ioapic_copy_alloc_attr()
942 * pin with real trigger and polarity attributes. mp_check_pin_attr()
990 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
991 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
998 int irq, int ioapic, int pin, alloc_isa_irq_from_domain()
1006 * Legacy ISA IRQ has already been allocated, just add pin to alloc_isa_irq_from_domain()
1007 * the pin list assoicated with this IRQ and program the IOAPIC alloc_isa_irq_from_domain()
1028 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, mp_map_pin_to_irq() argument
1048 irq = irq_find_mapping(domain, pin); mp_map_pin_to_irq()
1053 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin); mp_map_pin_to_irq()
1056 ioapic, pin, &tmp); mp_map_pin_to_irq()
1057 else if ((irq = irq_find_mapping(domain, pin)) == 0) mp_map_pin_to_irq()
1071 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags) pin_2_irq() argument
1073 u32 gsi = mp_pin_to_gsi(ioapic, pin); pin_2_irq()
1078 if (mp_irqs[idx].dstirq != pin) pin_2_irq()
1085 if ((pin >= 16) && (pin <= 23)) { pin_2_irq()
1086 if (pirq_entries[pin-16] != -1) { pin_2_irq()
1087 if (!pirq_entries[pin-16]) { pin_2_irq()
1089 "disabling PIRQ%d\n", pin-16); pin_2_irq()
1091 int irq = pirq_entries[pin-16]; pin_2_irq()
1094 pin-16, irq); pin_2_irq()
1101 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL); pin_2_irq()
1106 int ioapic, pin, idx; mp_map_gsi_to_irq() local
1112 pin = mp_find_ioapic_pin(ioapic, gsi); mp_map_gsi_to_irq()
1113 idx = find_irq_entry(ioapic, pin, mp_INT); mp_map_gsi_to_irq()
1117 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info); mp_map_gsi_to_irq()
1142 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) IO_APIC_get_PCI_irq_vector() argument
1147 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", IO_APIC_get_PCI_irq_vector()
1148 bus, slot, pin); IO_APIC_get_PCI_irq_vector()
1177 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1184 * Use the first all-but-pin matching entry as a
1206 int apic, idx, pin; IO_APIC_irq_trigger() local
1208 for_each_ioapic_pin(apic, pin) { for_each_ioapic_pin()
1209 idx = find_irq_entry(apic, pin, mp_INT); for_each_ioapic_pin()
1210 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0))) for_each_ioapic_pin()
1227 unsigned int ioapic, pin; setup_IO_APIC_irqs() local
1232 for_each_ioapic_pin(ioapic, pin) { for_each_ioapic_pin()
1233 idx = find_irq_entry(ioapic, pin, mp_INT); for_each_ioapic_pin()
1236 KERN_DEBUG " apic %d pin %d not connected\n", for_each_ioapic_pin()
1237 mpc_ioapic_id(ioapic), pin); for_each_ioapic_pin()
1239 pin_2_irq(idx, ioapic, pin, for_each_ioapic_pin()
1260 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", io_apic_print_entries()
1355 printk(KERN_DEBUG "IRQ to pin mappings:\n"); for_each_active_irq()
1372 pr_cont("-> %d:%d", entry->apic, entry->pin); for_each_active_irq()
1380 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; member in struct:__anon3137
1385 int apic, pin; enable_IO_APIC() local
1393 for_each_ioapic_pin(apic, pin) { for_each_ioapic_pin()
1395 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); for_each_ioapic_pin()
1398 * I have found the pin where the i8259 is connected. for_each_ioapic_pin()
1402 ioapic_i8259.pin = pin; for_each_ioapic_pin()
1408 /* If we could not find the appropriate pin by looking at the ioapic
1415 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1417 ioapic_i8259.pin = i8259_pin;
1421 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1422 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1440 if (ioapic_i8259.pin != -1) { native_disable_io_apic()
1454 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); native_disable_io_apic()
1458 disconnect_bsp_APIC(ioapic_i8259.pin != -1); native_disable_io_apic()
1696 int pin; io_apic_level_ack_pending() local
1698 pin = entry->pin; io_apic_level_ack_pending()
1699 reg = io_apic_read(entry->apic, 0x10 + pin*2); io_apic_level_ack_pending()
1836 * Intr-remapping uses pin number as the virtual vector ioapic_ir_ack_level()
1839 * EOI we use the pin number. ioapic_ir_ack_level()
1862 __ioapic_write_entry(entry->apic, entry->pin, ioapic_set_affinity()
1962 int apic, pin, i; unlock_ExtINT_logic() local
1966 pin = find_isa_irq_pin(8, mp_INT); unlock_ExtINT_logic()
1967 if (pin == -1) { unlock_ExtINT_logic()
1977 entry0 = ioapic_read_entry(apic, pin); unlock_ExtINT_logic()
1978 clear_IO_APIC_pin(apic, pin); unlock_ExtINT_logic()
1990 ioapic_write_entry(apic, pin, entry1); unlock_ExtINT_logic()
2007 clear_IO_APIC_pin(apic, pin); unlock_ExtINT_logic()
2009 ioapic_write_entry(apic, pin, entry0); unlock_ExtINT_logic()
2021 static int mp_alloc_timer_irq(int ioapic, int pin) mp_alloc_timer_irq() argument
2031 info.ioapic_pin = pin; mp_alloc_timer_irq()
2033 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info); mp_alloc_timer_irq()
2079 pin2 = ioapic_i8259.pin; check_timer()
2089 * interrupt input. So just in case, if only one pin check_timer()
2134 "..... (found apic %d pin %d) ...\n", apic2, pin2); check_timer()
2197 * to devices. However there may be an I/O APIC pin available for
2198 * this interrupt regardless. The pin may be left unconnected, but
2200 * the master 8259A. In the MPS case such a pin will normally be
2492 int ioapic, pin, idx; acpi_get_override_irq() local
2501 pin = mp_find_ioapic_pin(ioapic, gsi); acpi_get_override_irq()
2502 if (pin < 0) acpi_get_override_irq()
2505 idx = find_irq_entry(ioapic, pin, mp_INT); acpi_get_override_irq()
2522 int pin, ioapic, irq, irq_entry; setup_ioapic_dest() local
2531 for_each_ioapic_pin(ioapic, pin) { for_each_ioapic_pin()
2532 irq_entry = find_irq_entry(ioapic, pin, mp_INT); for_each_ioapic_pin()
2536 irq = pin_2_irq(irq_entry, ioapic, pin, 0); for_each_ioapic_pin()
2823 int ioapic, pin; mp_unregister_ioapic() local
2836 for_each_pin(ioapic, pin) { for_each_pin()
2837 u32 gsi = mp_pin_to_gsi(ioapic, pin); for_each_pin()
2844 pr_warn("pin%d on IOAPIC%d is still in use.\n", for_each_pin()
2845 pin, ioapic); for_each_pin()
2911 int ret, ioapic, pin; mp_irqdomain_alloc() local
2925 pin = info->ioapic_pin; mp_irqdomain_alloc()
2926 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0) mp_irqdomain_alloc()
2945 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info); mp_irqdomain_alloc()
2948 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin); mp_irqdomain_alloc()
2960 ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector, mp_irqdomain_alloc()
2993 __ioapic_write_entry(entry->apic, entry->pin, data->entry); mp_irqdomain_activate()
372 __add_pin_to_irq_node(struct mp_chip_data *data, int node, int apic, int pin) __add_pin_to_irq_node() argument
407 add_pin_to_irq_node(struct mp_chip_data *data, int node, int apic, int pin) add_pin_to_irq_node() argument
882 ioapic_copy_alloc_attr(struct irq_alloc_info *dst, struct irq_alloc_info *src, u32 gsi, int ioapic_idx, int pin) ioapic_copy_alloc_attr() argument
997 alloc_isa_irq_from_domain(struct irq_domain *domain, int irq, int ioapic, int pin, struct irq_alloc_info *info) alloc_isa_irq_from_domain() argument
/linux-4.4.14/drivers/media/usb/dvb-usb-v2/
H A Dmxl111sf-gpio.c35 static int mxl111sf_set_gpo_state(struct mxl111sf_state *state, u8 pin, u8 val) mxl111sf_set_gpo_state() argument
40 mxl_debug_adv("(%d, %d)", pin, val); mxl111sf_set_gpo_state()
42 if ((pin > 0) && (pin < 8)) { mxl111sf_set_gpo_state()
46 tmp &= ~(1 << (pin - 1)); mxl111sf_set_gpo_state()
47 tmp |= (val << (pin - 1)); mxl111sf_set_gpo_state()
51 } else if (pin <= 10) { mxl111sf_set_gpo_state()
52 if (pin == 0) mxl111sf_set_gpo_state()
53 pin += 7; mxl111sf_set_gpo_state()
57 tmp &= ~(1 << (pin - 3)); mxl111sf_set_gpo_state()
58 tmp |= (val << (pin - 3)); mxl111sf_set_gpo_state()
68 static int mxl111sf_get_gpi_state(struct mxl111sf_state *state, u8 pin, u8 *val) mxl111sf_get_gpi_state() argument
73 mxl_debug("(0x%02x)", pin); mxl111sf_get_gpi_state()
77 switch (pin) { mxl111sf_get_gpi_state()
85 *val = (tmp >> (pin + 4)) & 0x01; mxl111sf_get_gpi_state()
94 *val = (tmp >> pin) & 0x01; mxl111sf_get_gpi_state()
102 *val = (tmp >> (pin - 3)) & 0x01; mxl111sf_get_gpi_state()
105 return -EINVAL; /* invalid pin */ mxl111sf_get_gpi_state()
112 u8 pin; member in struct:mxl_gpio_cfg
123 mxl_debug_adv("(%d, %d)", gpio_cfg->pin, gpio_cfg->dir); mxl111sf_config_gpio_pins()
125 switch (gpio_cfg->pin) { mxl111sf_config_gpio_pins()
133 tmp &= ~(1 << (gpio_cfg->pin + 4)); mxl111sf_config_gpio_pins()
134 tmp |= (gpio_cfg->dir << (gpio_cfg->pin + 4)); mxl111sf_config_gpio_pins()
146 tmp &= ~(1 << gpio_cfg->pin); mxl111sf_config_gpio_pins()
147 tmp |= (gpio_cfg->dir << gpio_cfg->pin); mxl111sf_config_gpio_pins()
158 tmp &= ~(1 << (gpio_cfg->pin - 3)); mxl111sf_config_gpio_pins()
159 tmp |= (gpio_cfg->dir << (gpio_cfg->pin - 3)); mxl111sf_config_gpio_pins()
165 return -EINVAL; /* invalid pin */ mxl111sf_config_gpio_pins()
170 gpio_cfg->pin, gpio_cfg->val) : mxl111sf_config_gpio_pins()
172 gpio_cfg->pin, &gpio_cfg->val); mxl111sf_config_gpio_pins()
182 .pin = gpio, mxl111sf_hw_do_set_gpio()
/linux-4.4.14/drivers/of/
H A Dof_pci_irq.c22 u8 pin; of_irq_parse_pci() local
39 rc = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin); of_irq_parse_pci()
42 /* No pin, exit with no error message. */ of_irq_parse_pci()
43 if (pin == 0) of_irq_parse_pci()
82 pin = pci_swizzle_interrupt_pin(pdev, pin); of_irq_parse_pci()
88 out_irq->args[0] = pin; of_irq_parse_pci()
105 * @pin: PCI irq pin number; passed when used as map_irq callback. Unused
107 * @slot and @pin are unused, but included in the function so that this
110 int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin) of_irq_parse_and_map_pci() argument
/linux-4.4.14/arch/arm/plat-pxa/include/plat/
H A Dmfp.h349 * pin drive strength
353 * pin drive strength and low power mode
410 #define MFP_CFG(pin, af) \
412 (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
414 #define MFP_CFG_DRV(pin, af, drv) \
416 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
418 #define MFP_CFG_LPM(pin, af, lpm) \
420 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
422 #define MFP_CFG_X(pin, af, drv, lpm) \
424 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
428 * each MFP pin will have a MFPR register, since the offset of the
430 * should initialize the pin offsets by mfp_init()
437 * beginning at "offset", to define a single pin, let "end" = -1.
442 * MFP_ADDR() to define a single pin
443 * MFP_ADDR_END to signal the end of pin offset definitions
454 #define MFP_ADDR(pin, offset) \
455 { MFP_PIN_##pin, -1, offset }
/linux-4.4.14/drivers/pinctrl/intel/
H A Dpinctrl-intel.c87 * @pctldev: Pointer to the pin controller device
88 * @chip: GPIO chip in this pin controller
89 * @soc: SoC/PCH specific pin configuration data
90 * @communities: All communities in this pin controller
91 * @ncommunities: Number of communities in this pin controller
110 unsigned pin) intel_get_community()
117 if (pin >= community->pin_base && intel_get_community()
118 pin < community->pin_base + community->npins) intel_get_community()
122 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); intel_get_community()
126 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, intel_get_padcfg() argument
132 community = intel_get_community(pctrl, pin); intel_get_padcfg()
136 padno = pin_to_padno(community, pin); intel_get_padcfg()
140 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) intel_pad_owned_by_host() argument
146 community = intel_get_community(pctrl, pin); intel_pad_owned_by_host()
152 padno = pin_to_padno(community, pin); intel_pad_owned_by_host()
161 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) intel_pad_acpi_mode() argument
167 community = intel_get_community(pctrl, pin); intel_pad_acpi_mode()
173 padno = pin_to_padno(community, pin); intel_pad_acpi_mode()
181 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) intel_pad_locked() argument
187 community = intel_get_community(pctrl, pin); intel_pad_locked()
193 padno = pin_to_padno(community, pin); intel_pad_locked()
203 if (value & BIT(pin % community->gpp_size)) intel_pad_locked()
208 if (value & BIT(pin % community->gpp_size)) intel_pad_locked()
214 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) intel_pad_usable() argument
216 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_usable()
217 !intel_pad_locked(pctrl, pin); intel_pad_usable()
246 unsigned pin) intel_pin_dbg_show()
252 if (!intel_pad_owned_by_host(pctrl, pin)) { intel_pin_dbg_show()
257 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); intel_pin_dbg_show()
258 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); intel_pin_dbg_show()
268 locked = intel_pad_locked(pctrl, pin); intel_pin_dbg_show()
269 acpi = intel_pad_acpi_mode(pctrl, pin); intel_pin_dbg_show()
339 /* Now enable the mux setting for each pin in the group */ intel_pinmux_set_mux()
360 unsigned pin) intel_gpio_request_enable()
369 if (!intel_pad_usable(pctrl, pin)) { intel_gpio_request_enable()
374 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); intel_gpio_request_enable()
392 unsigned pin, bool input) intel_gpio_set_direction()
401 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); intel_gpio_set_direction()
424 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, intel_config_get() argument
432 if (!intel_pad_owned_by_host(pctrl, pin)) intel_config_get()
435 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); intel_config_get()
488 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, intel_config_set_pull() argument
500 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); intel_config_set_pull()
557 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, intel_config_set() argument
563 if (!intel_pad_usable(pctrl, pin)) intel_config_set()
571 ret = intel_config_set_pull(pctrl, pin, configs[i]); intel_config_set()
657 unsigned pin = irqd_to_hwirq(d); intel_gpio_irq_ack() local
661 community = intel_get_community(pctrl, pin); intel_gpio_irq_ack()
663 unsigned padno = pin_to_padno(community, pin); intel_gpio_irq_ack()
678 unsigned pin = irqd_to_hwirq(d); intel_gpio_irq_mask_unmask() local
683 community = intel_get_community(pctrl, pin); intel_gpio_irq_mask_unmask()
685 unsigned padno = pin_to_padno(community, pin); intel_gpio_irq_mask_unmask()
717 unsigned pin = irqd_to_hwirq(d); intel_gpio_irq_type() local
722 reg = intel_get_padcfg(pctrl, pin, PADCFG0); intel_gpio_irq_type()
727 * If the pin is in ACPI mode it is still usable as a GPIO but it intel_gpio_irq_type()
731 if (intel_pad_acpi_mode(pctrl, pin)) { intel_gpio_irq_type()
732 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); intel_gpio_irq_type()
772 unsigned pin = irqd_to_hwirq(d); intel_gpio_irq_wake() local
776 community = intel_get_community(pctrl, pin); intel_gpio_irq_wake()
780 padno = pin_to_padno(community, pin); intel_gpio_irq_wake()
799 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); intel_gpio_irq_wake()
887 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); intel_gpio_probe()
1133 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", intel_pinctrl_resume()
1141 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", intel_pinctrl_resume()
109 intel_get_community(struct intel_pinctrl *pctrl, unsigned pin) intel_get_community() argument
245 intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin) intel_pin_dbg_show() argument
358 intel_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned pin) intel_gpio_request_enable() argument
390 intel_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned pin, bool input) intel_gpio_set_direction() argument
H A Dpinctrl-cherryview.c72 * struct chv_alternate_function - A per group or per pin alternate function
73 * @pin: Pin number (only used in per pin configs)
74 * @mode: Mode the pin should be set in
75 * @invert_oe: Invert OE for this pin
78 unsigned pin; member in struct:chv_alternate_function
84 * struct chv_pincgroup - describes a CHV pin group
89 * @overrides: Alternate function override per pin or %NULL if not used
90 * @noverrides: Number of per pin alternate function overrides if
116 * @base: Start pin number
160 * @pctldev: Pointer to the pin controller device
161 * @chip: GPIO chip in this pin controller
188 .pin = (p), \
797 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", chv_pinmux_set_mux()
806 int pin = grp->pins[i]; chv_pinmux_set_mux() local
810 /* Check if there is pin-specific config */ chv_pinmux_set_mux()
815 if (grp->overrides[j].pin == pin) { chv_pinmux_set_mux()
822 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); chv_pinmux_set_mux()
832 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); chv_pinmux_set_mux()
838 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", chv_pinmux_set_mux()
839 pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); chv_pinmux_set_mux()
887 * If the pin is in HiZ mode (both TX and RX buffers are chv_gpio_request_enable()
958 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, chv_config_get() argument
969 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); chv_config_get()
970 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); chv_config_get()
1038 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin, chv_config_set_pull() argument
1041 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); chv_config_set_pull()
1104 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin, chv_config_set() argument
1112 if (chv_pad_locked(pctrl, pin)) chv_config_set()
1123 ret = chv_config_set_pull(pctrl, pin, param, arg); chv_config_set()
1132 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, chv_config_set()
1161 int pin = chv_gpio_offset_to_pin(pctrl, offset); chv_gpio_get() local
1166 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); chv_gpio_get()
1180 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); chv_gpio_set() local
1187 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); chv_gpio_set()
1203 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); chv_gpio_get_direction() local
1208 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); chv_gpio_get_direction()
1244 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); chv_gpio_irq_ack() local
1249 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); chv_gpio_irq_ack()
1261 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); chv_gpio_irq_mask_unmask() local
1267 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); chv_gpio_irq_mask_unmask()
1307 int pin = chv_gpio_offset_to_pin(pctrl, offset); chv_gpio_irq_startup() local
1313 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); chv_gpio_irq_startup()
1317 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); chv_gpio_irq_startup()
1339 int pin = chv_gpio_offset_to_pin(pctrl, offset); chv_gpio_irq_type() local
1350 * Driver needs to save the mapping between each pin and chv_gpio_irq_type()
1352 * 1. If the pin cfg is locked in BIOS: chv_gpio_irq_type()
1355 * 2. If the pin cfg is not locked in BIOS: chv_gpio_irq_type()
1358 if (!chv_pad_locked(pctrl, pin)) { chv_gpio_irq_type()
1359 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); chv_gpio_irq_type()
1381 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); chv_gpio_irq_type()
1453 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); chv_gpio_probe()
1595 * Mask all interrupts before restoring per-pin configuration chv_pinctrl_resume()
1618 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", chv_pinctrl_resume()
1626 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", chv_pinctrl_resume()
/linux-4.4.14/drivers/pinctrl/vt8500/
H A Dpinctrl-wmt.c86 /* every pin does every function */ wmt_pmx_get_function_groups()
94 unsigned pin) wmt_set_pinmux()
96 u32 bank = WMT_BANK_FROM_PIN(pin); wmt_set_pinmux()
97 u32 bit = WMT_BIT_FROM_PIN(pin); wmt_set_pinmux()
102 dev_err(data->dev, "pin:%d no direction register defined\n", wmt_set_pinmux()
103 pin); wmt_set_pinmux()
124 dev_err(data->dev, "pin:%d no alt function available\n", wmt_set_pinmux()
125 pin); wmt_set_pinmux()
204 static int wmt_pctl_find_group_by_pin(struct wmt_pinctrl_data *data, u32 pin) wmt_pctl_find_group_by_pin() argument
209 if (data->pins[i].number == pin) wmt_pctl_find_group_by_pin()
218 u32 pin, u32 fnum, wmt_pctl_dt_node_to_map_func()
229 group = wmt_pctl_find_group_by_pin(data, pin); wmt_pctl_dt_node_to_map_func()
231 dev_err(data->dev, "unable to match pin %d to group\n", pin); wmt_pctl_dt_node_to_map_func()
245 u32 pin, u32 pull, wmt_pctl_dt_node_to_map_pull()
257 group = wmt_pctl_find_group_by_pin(data, pin); wmt_pctl_dt_node_to_map_pull()
259 dev_err(data->dev, "unable to match pin %d to group\n", pin); wmt_pctl_dt_node_to_map_pull()
311 u32 pin, func, pull; wmt_pctl_dt_node_to_map() local
362 err = of_property_read_u32_index(np, "wm,pins", i, &pin); wmt_pctl_dt_node_to_map()
366 if (pin >= (data->nbanks * 32)) { wmt_pctl_dt_node_to_map()
378 err = wmt_pctl_dt_node_to_map_func(data, np, pin, func, wmt_pctl_dt_node_to_map()
390 err = wmt_pctl_dt_node_to_map_pull(data, np, pin, pull, wmt_pctl_dt_node_to_map()
421 static int wmt_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, wmt_pinconf_get() argument
427 static int wmt_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, wmt_pinconf_set() argument
433 u32 bank = WMT_BANK_FROM_PIN(pin); wmt_pinconf_set()
434 u32 bit = WMT_BIT_FROM_PIN(pin); wmt_pinconf_set()
440 dev_err(data->dev, "bias functions not supported on pin %d\n", wmt_pinconf_set()
441 pin); wmt_pinconf_set()
93 wmt_set_pinmux(struct wmt_pinctrl_data *data, unsigned func, unsigned pin) wmt_set_pinmux() argument
216 wmt_pctl_dt_node_to_map_func(struct wmt_pinctrl_data *data, struct device_node *np, u32 pin, u32 fnum, struct pinctrl_map **maps) wmt_pctl_dt_node_to_map_func() argument
243 wmt_pctl_dt_node_to_map_pull(struct wmt_pinctrl_data *data, struct device_node *np, u32 pin, u32 pull, struct pinctrl_map **maps) wmt_pctl_dt_node_to_map_pull() argument
/linux-4.4.14/drivers/pinctrl/sh-pfc/
H A Dsh_pfc.h34 u16 pin; member in struct:sh_pfc_pin
57 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
140 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
141 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
143 int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin);
144 int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin,
181 * Helper macros to create pin and port lists
205 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
206 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
246 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
252 .pin = (bank * 32) + _pin, \
260 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
264 * PORT style (linear pin space)
290 .pin = (u16)-1, \
298 .pin = _pin, \
307 .pin = PIN_NUMBER(row, col), \
352 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
H A Dpinctrl.c120 const char *pin; sh_pfc_dt_subnode_to_map() local
175 dev_err(dev, "Invalid pin groups list in DT\n"); sh_pfc_dt_subnode_to_map()
182 dev_err(dev, "No pin or group provided in DT node\n"); sh_pfc_dt_subnode_to_map()
226 of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) { sh_pfc_dt_subnode_to_map()
227 ret = sh_pfc_map_add_config(&maps[idx], pin, sh_pfc_dt_subnode_to_map()
396 /* If GPIOs are handled externally the pin mux type need to be sh_pfc_gpio_request_enable()
399 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; sh_pfc_gpio_request_enable() local
401 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); sh_pfc_gpio_request_enable()
439 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; sh_pfc_gpio_set_direction() local
445 /* Check if the requested direction is supported by the pin. Not all SoC sh_pfc_gpio_set_direction()
446 * provide pin config data, so perform the check conditionally. sh_pfc_gpio_set_direction()
448 if (pin->configs) { sh_pfc_gpio_set_direction()
450 if (!(pin->configs & dir)) sh_pfc_gpio_set_direction()
456 ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); sh_pfc_gpio_set_direction()
477 /* Check whether the requested parameter is supported for a pin. */ sh_pfc_pinconf_validate()
482 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; sh_pfc_pinconf_validate() local
489 return pin->configs & SH_PFC_PIN_CFG_PULL_UP; sh_pfc_pinconf_validate()
492 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; sh_pfc_pinconf_validate()
495 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE; sh_pfc_pinconf_validate()
637 /* PFC ranges -> pinctrl pin descs */ sh_pfc_map_pins()
658 struct pinctrl_pin_desc *pin = &pmx->pins[i]; sh_pfc_map_pins() local
660 /* If the pin number is equal to -1 all pins are considered */ sh_pfc_map_pins()
661 pin->number = info->pin != (u16)-1 ? info->pin : i; sh_pfc_map_pins()
662 pin->name = info->name; sh_pfc_map_pins()
/linux-4.4.14/drivers/pcmcia/
H A Dsa1111_jornada720.c100 unsigned int pin = GPIO_A0 | GPIO_A1 | GPIO_A2 | GPIO_A3; pcmcia_jornada720_init() local
105 sa1111_set_io_dir(sadev, pin, 0, 0); pcmcia_jornada720_init()
106 sa1111_set_io(sadev, pin, 0); pcmcia_jornada720_init()
107 sa1111_set_sleep_io(sadev, pin, 0); pcmcia_jornada720_init()
/linux-4.4.14/include/trace/events/
H A Dkvm.h93 TP_PROTO(__u64 e, int pin, bool coalesced),
94 TP_ARGS(e, pin, coalesced),
98 __field( int, pin )
104 __entry->pin = pin;
108 TP_printk("pin %u dst %x vec=%u (%s|%s|%s%s)%s",
109 __entry->pin, (u8)(__entry->e >> 56), (u8)__entry->e,
169 #define kvm_ack_irq_string "irqchip %s pin %u"
170 #define kvm_ack_irq_parm __print_symbolic(__entry->irqchip, kvm_irqchips), __entry->pin
172 #define kvm_ack_irq_string "irqchip %d pin %u"
173 #define kvm_ack_irq_parm __entry->irqchip, __entry->pin
177 TP_PROTO(unsigned int irqchip, unsigned int pin),
178 TP_ARGS(irqchip, pin),
182 __field( unsigned int, pin )
187 __entry->pin = pin;
/linux-4.4.14/include/linux/power/
H A Dbq24190_charger.h13 unsigned int gpio_int; /* GPIO pin that's connected to INT# */
/linux-4.4.14/arch/sparc/include/asm/
H A Dleon_pci.h16 int (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
/linux-4.4.14/arch/mn10300/proc-mn103e010/include/proc/
H A Dintctl-regs.h24 /* external pin intr spec reg */
/linux-4.4.14/arch/mn10300/proc-mn2ws0050/include/proc/
H A Dintctl-regs.h24 /* external pin intr spec reg */
/linux-4.4.14/arch/blackfin/include/asm/
H A Dreboot.h18 extern void bfin_reset_boot_spi_cs(unsigned short pin);
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_hotplug.c64 * number of interrupts per hotplug pin per a period of time, and if the number
79 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port) intel_hpd_pin_to_port() argument
81 switch (pin) { intel_hpd_pin_to_port()
107 * intel_hpd_irq_storm_detect - gather stats and detect HPD irq storm on a pin
109 * @pin: the pin to gather stats on
111 * Gather stats about HPD irqs from the specified @pin, and detect irq
112 * storms. Only the pin specific stats and state are changed, the caller is
119 * Return true if an irq storm was detected on @pin.
122 enum hpd_pin pin) intel_hpd_irq_storm_detect()
124 unsigned long start = dev_priv->hotplug.stats[pin].last_jiffies; intel_hpd_irq_storm_detect()
129 dev_priv->hotplug.stats[pin].last_jiffies = jiffies; intel_hpd_irq_storm_detect()
130 dev_priv->hotplug.stats[pin].count = 0; intel_hpd_irq_storm_detect()
131 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", pin); intel_hpd_irq_storm_detect()
132 } else if (dev_priv->hotplug.stats[pin].count > HPD_STORM_THRESHOLD) { intel_hpd_irq_storm_detect()
133 dev_priv->hotplug.stats[pin].state = HPD_MARK_DISABLED; intel_hpd_irq_storm_detect()
134 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", pin); intel_hpd_irq_storm_detect()
137 dev_priv->hotplug.stats[pin].count++; intel_hpd_irq_storm_detect()
138 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", pin, intel_hpd_irq_storm_detect()
139 dev_priv->hotplug.stats[pin].count); intel_hpd_irq_storm_detect()
152 enum hpd_pin pin; intel_hpd_irq_storm_disable() local
166 pin = intel_encoder->hpd_pin; intel_hpd_irq_storm_disable()
167 if (pin == HPD_NONE || intel_hpd_irq_storm_disable()
168 dev_priv->hotplug.stats[pin].state != HPD_MARK_DISABLED) intel_hpd_irq_storm_disable()
175 dev_priv->hotplug.stats[pin].state = HPD_DISABLED; intel_hpd_irq_storm_disable()
332 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", i915_hotplug_work_func()
357 * (@long_mask). The @long_mask is ignored if the port corresponding to the pin
411 "Received HPD interrupt on pin %d although disabled\n", i); for_each_hpd_pin()
121 intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv, enum hpd_pin pin) intel_hpd_irq_storm_detect() argument
H A Dintel_i2c.c42 /* Map gmbus pin pairs to names and registers. */
71 /* pin is expected to be valid */ get_gmbus_pin()
73 unsigned int pin) get_gmbus_pin()
76 return &gmbus_pins_bxt[pin]; get_gmbus_pin()
78 return &gmbus_pins_skl[pin]; get_gmbus_pin()
80 return &gmbus_pins_bdw[pin]; get_gmbus_pin()
82 return &gmbus_pins[pin]; get_gmbus_pin()
86 unsigned int pin) intel_gmbus_is_valid_pin()
99 return pin < size && get_gmbus_pin(dev_priv, pin)->reg; intel_gmbus_is_valid_pin()
236 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) intel_gpio_setup() argument
244 get_gmbus_pin(dev_priv, pin)->reg; intel_gpio_setup()
588 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", gmbus_xfer()
626 unsigned int pin; intel_setup_gmbus() local
641 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { intel_setup_gmbus()
642 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) intel_setup_gmbus()
645 bus = &dev_priv->gmbus[pin]; intel_setup_gmbus()
652 get_gmbus_pin(dev_priv, pin)->name); intel_setup_gmbus()
660 bus->reg0 = pin | GMBUS_RATE_100KHZ; intel_setup_gmbus()
666 intel_gpio_setup(bus, pin); intel_setup_gmbus()
678 while (pin--) { intel_setup_gmbus()
679 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) intel_setup_gmbus()
682 bus = &dev_priv->gmbus[pin]; intel_setup_gmbus()
689 unsigned int pin) intel_gmbus_get_adapter()
691 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) intel_gmbus_get_adapter()
694 return &dev_priv->gmbus[pin].adapter; intel_gmbus_get_adapter()
718 unsigned int pin; intel_teardown_gmbus() local
720 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { intel_teardown_gmbus()
721 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) intel_teardown_gmbus()
724 bus = &dev_priv->gmbus[pin]; intel_teardown_gmbus()
72 get_gmbus_pin(struct drm_i915_private *dev_priv, unsigned int pin) get_gmbus_pin() argument
85 intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, unsigned int pin) intel_gmbus_is_valid_pin() argument
688 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin) intel_gmbus_get_adapter() argument
/linux-4.4.14/sound/pci/hda/
H A Dhda_auto_parser.c21 * Helper for automatic pin configuration
32 /* a pair of input pin and its sequence */
34 hda_nid_t pin; member in struct:auto_out_pin
47 * then store it to a pin array.
55 pins[i] = list[i].pin; sort_pins_by_sequence()
59 /* add the found input-pin to the cfg->inputs[] table */ add_auto_cfg_input_pin()
64 cfg->inputs[cfg->num_inputs].pin = nid; add_auto_cfg_input_pin()
105 /* check whether the given pin has a proper pin I/O capability bit */ check_pincap_validity()
106 static bool check_pincap_validity(struct hda_codec *codec, hda_nid_t pin, check_pincap_validity() argument
109 unsigned int pincap = snd_hda_query_pin_caps(codec, pin); check_pincap_validity()
139 def_conf = snd_hda_codec_get_pincfg(codec, item->pin); can_be_headset_mic()
154 * Parse all pin widgets and store the useful pin nids to cfg
198 /* read all default configuration for pin complex */ for_each_hda_codec_node()
236 "ignore pin 0x%x with mismatching assoc# 0x%x vs 0x%x\n", for_each_hda_codec_node()
242 "ignore pin 0x%x, too many assigned pins\n", for_each_hda_codec_node()
246 line_out[cfg->line_outs].pin = nid; for_each_hda_codec_node()
255 "ignore pin 0x%x, too many assigned pins\n", for_each_hda_codec_node()
259 speaker_out[cfg->speaker_outs].pin = nid; for_each_hda_codec_node()
268 "ignore pin 0x%x, too many assigned pins\n", for_each_hda_codec_node()
272 hp_out[cfg->hp_outs].pin = nid; for_each_hda_codec_node()
292 "ignore pin 0x%x, too many assigned pins\n", for_each_hda_codec_node()
313 /* Find a pin that could be a headset or headphone mic */
378 * FIX-UP: if no line-outs are detected, try to use speaker or HP pin
434 cfg->inputs[i].pin);
444 * snd_hda_get_input_pin_attr - Get the input pin attribute from pin config
445 * @def_conf: pin configuration value
447 * Guess the input pin attribute (INPUT_PIN_ATTR_XXX) from the given
448 * default pin configuration value.
472 * hda_get_input_pin_label - Give a label for the given input pin
475 * @pin: the pin NID
478 * When @check_location is true, the function checks the pin location
484 hda_nid_t pin, bool check_location) hda_get_input_pin_label()
492 def_conf = snd_hda_codec_get_pincfg(codec, pin); hda_get_input_pin_label()
541 defc = snd_hda_codec_get_pincfg(codec, cfg->inputs[input].pin); check_mic_location_need()
549 defc = snd_hda_codec_get_pincfg(codec, cfg->inputs[i].pin); check_mic_location_need()
563 * @cfg: the parsed pin configuration
566 * Get a label for the given input pin defined by the autocfg item.
584 cfg->inputs[input].pin, hda_get_autocfg_input_label()
691 * snd_hda_get_pin_label - Get a label for the given I/O pin
693 * @nid: pin NID
694 * @cfg: the parsed pin configuration
699 * Get a label for the given pin. This function works for both input and
703 * This function tries to give a unique label string for the pin as much as
739 hda_nid_t pin = cfg->dig_out_pins[i]; snd_hda_get_pin_label() local
741 if (pin == nid) snd_hda_get_pin_label()
743 c = snd_hda_codec_get_pincfg(codec, pin); snd_hda_get_pin_label()
751 if (cfg->inputs[i].pin != nid) snd_hda_get_pin_label()
804 * snd_hda_apply_pincfgs - Set each pin config in the given list
806 * @cfg: NULL-terminated pin config table
893 struct hda_pincfg *pin = snd_array_elem(&codec->init_pins, i); pin_config_match() local
894 hda_nid_t nid = pin->nid; pin_config_match()
895 u32 cfg = pin->cfg; pin_config_match()
920 * snd_hda_pick_pin_fixup - Pick up a fixup matching with the pin quirk list
922 * @pin_quirk: zero-terminated pin quirk list
943 codec_dbg(codec, "%s: picked fixup %s (pin match)\n", snd_hda_pick_pin_fixup()
482 hda_get_input_pin_label(struct hda_codec *codec, const struct auto_pin_cfg_item *item, hda_nid_t pin, bool check_location) hda_get_input_pin_label() argument
H A Dhda_jack.c24 * is_jack_detectable - Check whether the given pin is jack-detectable
26 * @nid: pin NID
28 * Check whether the given pin is capable to report the jack detection.
30 * detection is prohibited in the codec level, the pin config has
49 /* execute pin sense measurement */ read_pin_sense()
71 * @nid: pin NID to refer to
111 * @nid: pin NID to assign
198 * snd_hda_pin_sense - execute pin sense measurement
200 * @nid: the pin NID to sense
202 * Execute necessary pin sense measurement and return its Presence Detect,
217 * snd_hda_jack_detect_state - query pin Presence Detect status
219 * @nid: the pin NID to sense
221 * Query and return the pin's Presence Detect status, as either
239 * @nid: pin NID to enable
282 * snd_hda_jack_detect_enable - Enable the jack detection on the given pin
284 * @nid: pin NID to enable jack detection
298 * @gated_nid: gated pin NID
299 * @gating_nid: gating pin NID
349 /* guess the jack type from the pin-config */ get_input_jack_type()
377 * snd_hda_jack_add_kctl - Add a kctl for the given pin
379 * @nid: pin NID to assign
383 * This assigns a jack-detection kctl to the given pin. The kcontrol
452 * @cfg: pin config table to parse
468 err = add_jack_kctl(codec, cfg->inputs[i].pin, snd_hda_jack_add_kctls()
471 err = add_jack_kctl(codec, cfg->inputs[i].pin, cfg, snd_hda_jack_add_kctls()
/linux-4.4.14/drivers/net/wireless/ath/ath5k/
H A Dgpio.c32 * We can set a GPIO pin to be an input or an output pin on GPIO control
103 * @gpio: GPIO pin to set as input
121 * @gpio: The GPIO pin to set as output
139 * @gpio: The GPIO pin to read
155 * @gpio: The GPIO pin to set
180 * @gpio: The GPIO pin to use
181 * @interrupt_level: True to generate interrupt on active pin (high)
184 * That switch is connected to a GPIO pin and it's number is stored on EEPROM.
/linux-4.4.14/arch/mips/sgi-ip27/
H A Dip27-irq-pci.c140 int pin, swlevel; startup_bridge_irq() local
143 pin = SLOT_FROM_PCI_IRQ(d->irq); startup_bridge_irq()
147 pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin); startup_bridge_irq()
153 bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8)); startup_bridge_irq()
154 bridge->b_int_enable |= (1 << pin); startup_bridge_irq()
159 * low transition of the interrupt pin. startup_bridge_irq()
164 bridge->b_int_mode |= (1UL << pin); startup_bridge_irq()
171 device &= ~(7 << (pin*3)); startup_bridge_irq()
172 device |= (pin << (pin*3)); startup_bridge_irq()
187 int pin, swlevel; shutdown_bridge_irq() local
191 pin = SLOT_FROM_PCI_IRQ(d->irq); shutdown_bridge_irq()
200 bridge->b_int_enable &= ~(1 << pin); shutdown_bridge_irq()
/linux-4.4.14/drivers/pinctrl/bcm/
H A Dpinctrl-bcm281xx.c29 /* Function Select bits are the same for all pin control registers */
33 /* Standard pin register */
47 /* I2C pin register */
55 /* HDMI pin register */
62 * bcm281xx_pin_type - types of pin register
76 * bcm281xx_pin_function- define pin function
379 * the PADCTRLREG block in the RDB, since the pin number is used as an index
927 /* Every pin can implement all ALT1-ALT4 functions */
950 unsigned pin) pin_type_get()
954 if (pin >= pdata->npins) pin_type_get()
957 return *(enum bcm281xx_pin_type *)(pdata->pins[pin].drv_data); pin_type_get()
968 * a pin register, but does not actually write to the register.
1068 "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n", bcm281xx_pinmux_set()
1077 "Error updating register for pin %s (%d).\n", bcm281xx_pinmux_set()
1091 unsigned pin, bcm281xx_pinctrl_pin_config_get()
1100 unsigned pin, bcm281xx_std_pin_update()
1123 * The pin bias can only be one of pull-up, pull-down, or bcm281xx_std_pin_update()
1175 "pin %s (%d). Valid values are " bcm281xx_std_pin_update()
1177 arg, pdata->pins[pin].name, pin); bcm281xx_std_pin_update()
1187 "Unrecognized pin config %d for pin %s (%d).\n", bcm281xx_std_pin_update()
1188 param, pdata->pins[pin].name, pin); bcm281xx_std_pin_update()
1198 * The pull-up strength for an I2C pin is represented by bits 4-6 in the
1216 unsigned pin, bcm281xx_i2c_pin_update()
1239 "Invalid pull-up value (%d) for pin %s " bcm281xx_i2c_pin_update()
1242 arg, pdata->pins[pin].name, pin); bcm281xx_i2c_pin_update()
1274 "Unrecognized pin config %d for pin %s (%d).\n", bcm281xx_i2c_pin_update()
1275 param, pdata->pins[pin].name, pin); bcm281xx_i2c_pin_update()
1286 unsigned pin, bcm281xx_hdmi_pin_update()
1319 "Unrecognized pin config %d for pin %s (%d).\n", bcm281xx_hdmi_pin_update()
1320 param, pdata->pins[pin].name, pin); bcm281xx_hdmi_pin_update()
1330 unsigned pin, bcm281xx_pinctrl_pin_config_set()
1336 u32 offset = 4 * pin; bcm281xx_pinctrl_pin_config_set()
1342 pin_type = pin_type_get(pctldev, pin); bcm281xx_pinctrl_pin_config_set()
1347 rc = bcm281xx_std_pin_update(pctldev, pin, configs, bcm281xx_pinctrl_pin_config_set()
1352 rc = bcm281xx_i2c_pin_update(pctldev, pin, configs, bcm281xx_pinctrl_pin_config_set()
1357 rc = bcm281xx_hdmi_pin_update(pctldev, pin, configs, bcm281xx_pinctrl_pin_config_set()
1362 dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n", bcm281xx_pinctrl_pin_config_set()
1363 pdata->pins[pin].name, pin); bcm281xx_pinctrl_pin_config_set()
1366 } /* switch pin type */ bcm281xx_pinctrl_pin_config_set()
1372 "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n", bcm281xx_pinctrl_pin_config_set()
1373 __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask); bcm281xx_pinctrl_pin_config_set()
1378 "Error updating register for pin %s (%d).\n", bcm281xx_pinctrl_pin_config_set()
1379 pdata->pins[pin].name, pin); bcm281xx_pinctrl_pin_config_set()
949 pin_type_get(struct pinctrl_dev *pctldev, unsigned pin) pin_type_get() argument
1090 bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config) bcm281xx_pinctrl_pin_config_get() argument
1099 bcm281xx_std_pin_update(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs, unsigned num_configs, u32 *val, u32 *mask) bcm281xx_std_pin_update() argument
1215 bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs, unsigned num_configs, u32 *val, u32 *mask) bcm281xx_i2c_pin_update() argument
1285 bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs, unsigned num_configs, u32 *val, u32 *mask) bcm281xx_hdmi_pin_update() argument
1329 bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs, unsigned num_configs) bcm281xx_pinctrl_pin_config_set() argument
/linux-4.4.14/drivers/input/keyboard/
H A Dadp5588-keys.c173 pin_used[kpad->gpimap[i].pin - GPI_PIN_BASE] = true; adp5588_build_gpiomap()
277 if (key_val == kpad->gpimap[j].pin) { adp5588_report_events()
351 unsigned short pin = pdata->gpimap[i].pin; adp5588_setup() local
353 if (pin <= GPI_PIN_ROW_END) { adp5588_setup()
354 evt_mode1 |= (1 << (pin - GPI_PIN_ROW_BASE)); adp5588_setup()
356 evt_mode2 |= ((1 << (pin - GPI_PIN_COL_BASE)) & 0xFF); adp5588_setup()
357 evt_mode3 |= ((1 << (pin - GPI_PIN_COL_BASE)) >> 8); adp5588_setup()
402 unsigned short pin = kpad->gpimap[i].pin; adp5588_report_switch_state() local
404 if (pin <= GPI_PIN_ROW_END) { adp5588_report_switch_state()
406 pin_loc = pin - GPI_PIN_ROW_BASE; adp5588_report_switch_state()
407 } else if ((pin - GPI_PIN_COL_BASE) < 8) { adp5588_report_switch_state()
409 pin_loc = pin - GPI_PIN_COL_BASE; adp5588_report_switch_state()
412 pin_loc = pin - GPI_PIN_COL_BASE - 8; adp5588_report_switch_state()
418 pin); adp5588_report_switch_state()
474 unsigned short pin = pdata->gpimap[i].pin; adp5588_probe() local
476 if (pin < GPI_PIN_BASE || pin > GPI_PIN_END) { adp5588_probe()
477 dev_err(&client->dev, "invalid gpi pin data\n"); adp5588_probe()
481 if (pin <= GPI_PIN_ROW_END) { adp5588_probe()
482 if (pin - GPI_PIN_ROW_BASE + 1 <= pdata->rows) { adp5588_probe()
487 if (pin - GPI_PIN_COL_BASE + 1 <= pdata->cols) { adp5588_probe()
/linux-4.4.14/arch/powerpc/platforms/82xx/
H A Dpq2fads.c50 int port, pin, flags; member in struct:cpm_pin
104 struct cpm_pin *pin = &pq2fads_pins[i]; init_ioports() local
105 cpm2_set_pin(pin->port, pin->pin, pin->flags); init_ioports()
/linux-4.4.14/arch/powerpc/platforms/85xx/
H A Dksi8560.c72 int port, pin, flags; member in struct:cpm_pin
111 struct cpm_pin *pin = &ksi8560_pins[i]; init_ioports() local
112 cpm2_set_pin(pin->port, pin->pin, pin->flags); init_ioports()
H A Dmpc85xx_ads.c65 int port, pin, flags; member in struct:cpm_pin
123 const struct cpm_pin *pin = &mpc8560_ads_pins[i]; init_ioports() local
124 cpm2_set_pin(pin->port, pin->pin, pin->flags); init_ioports()
/linux-4.4.14/arch/arm/mach-dove/
H A Dirq.c26 int pin = irq_to_pmu(d->irq); pmu_irq_mask() local
30 u &= ~(1 << (pin & 31)); pmu_irq_mask()
36 int pin = irq_to_pmu(d->irq); pmu_irq_unmask() local
40 u |= 1 << (pin & 31); pmu_irq_unmask()
46 int pin = irq_to_pmu(d->irq); pmu_irq_ack() local
60 u = ~(1 << (pin & 31)); pmu_irq_ack()
/linux-4.4.14/arch/arm/plat-pxa/
H A Dmfp.c69 * The pullup and pulldown state of the MFP pin at run mode is by default
174 int pin, af, drv, lpm, edge, pull; mfp_config() local
176 pin = MFP_PIN(c); mfp_config()
177 BUG_ON(pin >= MFP_PIN_MAX); mfp_config()
178 p = &mfp_table[pin]; mfp_config()
272 int pin; mfp_config_lpm() local
274 for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++) mfp_config_lpm()
281 int pin; mfp_config_run() local
283 for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++) mfp_config_run()
/linux-4.4.14/sound/soc/omap/
H A Dams-delta.c68 /* Selection <-> pin translation */
105 int pin, changed = 0; ams_delta_set_audio_mode() local
120 pin = !!(pins & (1 << AMS_DELTA_MOUTHPIECE)); ams_delta_set_audio_mode()
122 if (pin != snd_soc_dapm_get_pin_status(dapm, "Mouthpiece")) { ams_delta_set_audio_mode()
124 if (pin) ams_delta_set_audio_mode()
129 pin = !!(pins & (1 << AMS_DELTA_EARPIECE)); ams_delta_set_audio_mode()
130 if (pin != snd_soc_dapm_get_pin_status(dapm, "Earpiece")) { ams_delta_set_audio_mode()
132 if (pin) ams_delta_set_audio_mode()
137 pin = !!(pins & (1 << AMS_DELTA_MICROPHONE)); ams_delta_set_audio_mode()
138 if (pin != snd_soc_dapm_get_pin_status(dapm, "Microphone")) { ams_delta_set_audio_mode()
140 if (pin) ams_delta_set_audio_mode()
145 pin = !!(pins & (1 << AMS_DELTA_SPEAKER)); ams_delta_set_audio_mode()
146 if (pin != snd_soc_dapm_get_pin_status(dapm, "Speaker")) { ams_delta_set_audio_mode()
148 if (pin) ams_delta_set_audio_mode()
153 pin = !!(pins & (1 << AMS_DELTA_AGC)); ams_delta_set_audio_mode()
154 if (pin != ams_delta_audio_agc) { ams_delta_set_audio_mode()
155 ams_delta_audio_agc = pin; ams_delta_set_audio_mode()
157 if (pin) ams_delta_set_audio_mode()
229 .pin = "Mouthpiece",
233 .pin = "Earpiece",
238 .pin = "Microphone",
243 .pin = "Speaker",
507 /* Set up initial pin constellation */ ams_delta_cx20442_init()
H A Domap-mcbsp.h31 OMAP_MCBSP_SYSCLK_CLKS_EXT, /* External CLKS pin */
33 OMAP_MCBSP_SYSCLK_CLKX_EXT, /* External CLKX pin */
34 OMAP_MCBSP_SYSCLK_CLKR_EXT, /* External CLKR pin */
/linux-4.4.14/drivers/media/pci/sta2x11/
H A Dsta2x11_vip.h27 * @pwr_pin: ADV powerdown pin
29 * @reset_pin: ADV reset pin
/linux-4.4.14/drivers/net/ethernet/sfc/
H A Dphy.h47 void falcon_txc_set_gpio_dir(struct efx_nic *efx, int pin, int dir);
48 void falcon_txc_set_gpio_val(struct efx_nic *efx, int pin, int val);
/linux-4.4.14/include/linux/mfd/da9055/
H A Dpdata.h31 * GPI muxed pin to control
36 * GPI muxed pin to control
/linux-4.4.14/include/linux/mfd/
H A Dlp3943.h96 * @mux_cfg: Register configuration for pin MUX
97 * @pin_used: Bit mask for output pin used.
98 * This bitmask is used for pin assignment management.
99 * 1 = pin used, 0 = available.
H A Dmax8998.h80 * @buck1_set1: BUCK1 gpio pin 1 to set output voltage
81 * @buck1_set2: BUCK1 gpio pin 2 to set output voltage
82 * @buck1_default_idx: Default for BUCK1 gpio pin 1, 2
83 * @buck2_set3: BUCK2 gpio pin to set output voltage
84 * @buck2_default_idx: Default for BUCK2 gpio pin.
/linux-4.4.14/include/linux/amba/
H A Dmmci.h23 * @gpio_wp: read this GPIO pin to see if the card is write protected
24 * @gpio_cd: read this GPIO pin to detect card insertion
25 * @cd_invert: true if the gpio_cd pin value is active low
/linux-4.4.14/arch/mips/include/asm/vr41xx/
H A Dgiu.h44 extern void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
52 extern void vr41xx_set_irq_level(unsigned int pin, irq_level_t level);
60 extern int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull);
/linux-4.4.14/arch/arm/mach-dove/include/mach/
H A Dpm.h56 static inline int pmu_to_irq(int pin) pmu_to_irq() argument
58 if (pin < NR_PMU_IRQS) pmu_to_irq()
59 return pin + IRQ_DOVE_PMU_START; pmu_to_irq()
/linux-4.4.14/arch/avr32/mach-at32ap/
H A Dpio.c71 printk(KERN_WARNING "%s: pin(s) busy (requested 0x%x, busy 0x%x)\n", at32_select_periph()
103 void __init at32_select_gpio(unsigned int pin, unsigned long flags) at32_select_gpio() argument
106 unsigned int pin_index = pin & 0x1f; at32_select_gpio()
109 pio = gpio_to_pio(pin); at32_select_gpio()
111 printk("pio: invalid pin %u\n", pin); at32_select_gpio()
116 printk("%s: pin %u is busy\n", pio->name, pin_index); at32_select_gpio()
152 * Undo a previous pin reservation. Will not affect the hardware
155 void at32_deselect_pin(unsigned int pin) at32_deselect_pin() argument
158 unsigned int pin_index = pin & 0x1f; at32_deselect_pin()
160 pio = gpio_to_pio(pin); at32_deselect_pin()
162 printk("pio: invalid pin %u\n", pin); at32_deselect_pin()
170 /* Reserve a pin, preventing anyone else from changing its configuration. */ at32_reserve_pin()
185 printk(KERN_WARNING "%s: pin(s) busy (req. 0x%x, busy 0x%x)\n", at32_reserve_pin()
/linux-4.4.14/arch/arm/mach-iop32x/
H A Diq80321.c71 iq80321_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) iq80321_pci_map_irq() argument
75 if ((slot == 2 || slot == 6) && pin == 1) { iq80321_pci_map_irq()
78 } else if ((slot == 2 || slot == 6) && pin == 2) { iq80321_pci_map_irq()
81 } else if ((slot == 2 || slot == 6) && pin == 3) { iq80321_pci_map_irq()
84 } else if ((slot == 2 || slot == 6) && pin == 4) { iq80321_pci_map_irq()
/linux-4.4.14/arch/arm/mach-iop33x/
H A Diq80331.c53 iq80331_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) iq80331_pci_map_irq() argument
57 if (slot == 1 && pin == 1) { iq80331_pci_map_irq()
60 } else if (slot == 1 && pin == 2) { iq80331_pci_map_irq()
63 } else if (slot == 1 && pin == 3) { iq80331_pci_map_irq()
66 } else if (slot == 1 && pin == 4) { iq80331_pci_map_irq()
H A Diq80332.c53 iq80332_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) iq80332_pci_map_irq() argument
57 if (slot == 4 && pin == 1) { iq80332_pci_map_irq()
60 } else if (slot == 4 && pin == 2) { iq80332_pci_map_irq()
63 } else if (slot == 4 && pin == 3) { iq80332_pci_map_irq()
66 } else if (slot == 4 && pin == 4) { iq80332_pci_map_irq()
/linux-4.4.14/arch/powerpc/sysdev/
H A Dcpm2.c334 void cpm2_set_pin(int port, int pin, int flags) cpm2_set_pin() argument
339 pin = 1 << (31 - pin); cpm2_set_pin()
342 setbits32(&iop[port].dir, pin); cpm2_set_pin()
344 clrbits32(&iop[port].dir, pin); cpm2_set_pin()
347 setbits32(&iop[port].par, pin); cpm2_set_pin()
349 clrbits32(&iop[port].par, pin); cpm2_set_pin()
352 setbits32(&iop[port].sor, pin); cpm2_set_pin()
354 clrbits32(&iop[port].sor, pin); cpm2_set_pin()
357 setbits32(&iop[port].odr, pin); cpm2_set_pin()
359 clrbits32(&iop[port].odr, pin); cpm2_set_pin()
/linux-4.4.14/arch/mips/pnx833x/common/
H A Dinterrupts.c114 int pin; pic_dispatch() local
115 while ((pin = ffs(mask & 0xffff))) { pic_dispatch()
116 pin -= 1; pic_dispatch()
117 do_IRQ(PNX833X_GPIO_IRQ_BASE + pin); pic_dispatch()
118 mask &= ~(1 << pin); pic_dispatch()
193 int pin = d->irq - PNX833X_GPIO_IRQ_BASE; pnx833x_enable_gpio_irq() local
196 pnx833x_gpio_enable_irq(pin); pnx833x_enable_gpio_irq()
202 int pin = d->irq - PNX833X_GPIO_IRQ_BASE; pnx833x_disable_gpio_irq() local
205 pnx833x_gpio_disable_irq(pin); pnx833x_disable_gpio_irq()
211 int pin = d->irq - PNX833X_GPIO_IRQ_BASE; pnx833x_set_type_gpio_irq() local
235 pnx833x_gpio_setup_irq(gpio_mode, pin); pnx833x_set_type_gpio_irq()
/linux-4.4.14/drivers/leds/
H A Dleds-bcm6358.c39 * @pin: LED pin number
46 unsigned long pin; member in struct:bcm6358_led
80 val |= BIT(led->pin); bcm6358_led_mode()
82 val &= ~(BIT(led->pin)); bcm6358_led_mode()
110 led->pin = reg; bcm6358_led()
132 val &= BIT(led->pin); bcm6358_led()
/linux-4.4.14/sound/soc/
H A Dsoc-jack.c79 struct snd_soc_jack_pin *pin; snd_soc_jack_report() local
97 list_for_each_entry(pin, &jack->pins, list) { snd_soc_jack_report()
98 enable = pin->mask & jack->status; snd_soc_jack_report()
100 if (pin->invert) snd_soc_jack_report()
104 snd_soc_dapm_enable_pin(dapm, pin->pin); snd_soc_jack_report()
106 snd_soc_dapm_disable_pin(dapm, pin->pin); snd_soc_jack_report()
187 if (!pins[i].pin) { snd_soc_jack_add_pins()
188 dev_err(jack->card->dev, "ASoC: No name for pin %d\n", snd_soc_jack_add_pins()
193 dev_err(jack->card->dev, "ASoC: No mask for pin %d" snd_soc_jack_add_pins()
194 " (%s)\n", i, pins[i].pin); snd_soc_jack_add_pins()
200 snd_jack_add_new_kctl(jack->jack, pins[i].pin, pins[i].mask); snd_soc_jack_add_pins()
270 /* irq handler for gpio pin */ gpio_handler()

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