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Searched refs:pin (Results 1 – 200 of 1207) sorted by relevance

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/linux-4.4.14/arch/mips/include/asm/mach-pnx833x/
Dgpio.h56 static inline void pnx833x_gpio_select_input(unsigned int pin) in pnx833x_gpio_select_input() argument
58 if (pin < 32) in pnx833x_gpio_select_input()
59 CLEAR_REG_BIT(PNX833X_PIO_DIR, pin); in pnx833x_gpio_select_input()
61 CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31); in pnx833x_gpio_select_input()
63 static inline void pnx833x_gpio_select_output(unsigned int pin) in pnx833x_gpio_select_output() argument
65 if (pin < 32) in pnx833x_gpio_select_output()
66 SET_REG_BIT(PNX833X_PIO_DIR, pin); in pnx833x_gpio_select_output()
68 SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31); in pnx833x_gpio_select_output()
72 static inline void pnx833x_gpio_select_function_io(unsigned int pin) in pnx833x_gpio_select_function_io() argument
74 if (pin < 32) in pnx833x_gpio_select_function_io()
[all …]
/linux-4.4.14/arch/arm/boot/dts/
Ds5pv210-pinctrl.dtsi273 samsung,pin-function = <2>;
274 samsung,pin-pud = <0>;
275 samsung,pin-drv = <0>;
280 samsung,pin-function = <2>;
281 samsung,pin-pud = <0>;
282 samsung,pin-drv = <0>;
287 samsung,pin-function = <2>;
288 samsung,pin-pud = <0>;
289 samsung,pin-drv = <0>;
294 samsung,pin-function = <2>;
[all …]
Dexynos4210-pinctrl.dtsi2 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
9 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
149 samsung,pin-function = <0x2>;
150 samsung,pin-pud = <0>;
151 samsung,pin-drv = <0>;
156 samsung,pin-function = <2>;
157 samsung,pin-pud = <0>;
158 samsung,pin-drv = <0>;
163 samsung,pin-function = <2>;
164 samsung,pin-pud = <0>;
[all …]
Dexynos4415-pinctrl.dtsi2 * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source
6 * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device
97 samsung,pin-function = <0x2>;
98 samsung,pin-pud = <0>;
99 samsung,pin-drv = <0>;
104 samsung,pin-function = <2>;
105 samsung,pin-pud = <0>;
106 samsung,pin-drv = <0>;
111 samsung,pin-function = <2>;
112 samsung,pin-pud = <0>;
[all …]
Dsama5d3_lcd.dtsi61 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
62 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
63 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
64 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
65 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
66 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
67 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
68 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
69 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
70 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
Dexynos5420-pinctrl.dtsi2 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
7 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
64 samsung,pin-function = <3>;
65 samsung,pin-pud = <0>;
66 samsung,pin-drv = <0>;
156 samsung,pin-function = <2>;
157 samsung,pin-pud = <0>;
158 samsung,pin-drv = <3>;
163 samsung,pin-function = <2>;
164 samsung,pin-pud = <0>;
[all …]
Dexynos4x12-pinctrl.dtsi2 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
7 * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device
27 samsung,pin-con-pdn = <PIN_PDN_ ##_mode>; \
28 samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>; \
139 samsung,pin-function = <0x2>;
140 samsung,pin-pud = <0>;
141 samsung,pin-drv = <0>;
146 samsung,pin-function = <2>;
147 samsung,pin-pud = <0>;
148 samsung,pin-drv = <0>;
[all …]
Dexynos5250-pinctrl.dtsi2 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
7 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
203 samsung,pin-function = <2>;
204 samsung,pin-pud = <0>;
205 samsung,pin-drv = <0>;
210 samsung,pin-function = <2>;
211 samsung,pin-pud = <0>;
212 samsung,pin-drv = <0>;
217 samsung,pin-function = <3>;
218 samsung,pin-pud = <3>;
[all …]
Ds3c64xx-pinctrl.dtsi3 * - pin control-related definitions
7 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
141 samsung,pin-function = <2>;
142 samsung,pin-pud = <PIN_PULL_NONE>;
147 samsung,pin-function = <2>;
148 samsung,pin-pud = <PIN_PULL_NONE>;
153 samsung,pin-function = <2>;
154 samsung,pin-pud = <PIN_PULL_NONE>;
159 samsung,pin-function = <2>;
160 samsung,pin-pud = <PIN_PULL_NONE>;
[all …]
Dexynos3250-pinctrl.dtsi2 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
7 * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device
27 samsung,pin-con-pdn = <PIN_PDN_ ##_mode>; \
28 samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>; \
90 samsung,pin-function = <0x2>;
91 samsung,pin-pud = <0>;
92 samsung,pin-drv = <0>;
97 samsung,pin-function = <2>;
98 samsung,pin-pud = <0>;
99 samsung,pin-drv = <0>;
[all …]
Dexynos5260-pinctrl.dtsi2 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
7 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
190 samsung,pin-function = <2>;
191 samsung,pin-pud = <PIN_PULL_NONE>;
192 samsung,pin-drv = <0>;
197 samsung,pin-function = <2>;
198 samsung,pin-pud = <PIN_PULL_NONE>;
199 samsung,pin-drv = <0>;
204 samsung,pin-function = <2>;
205 samsung,pin-pud = <PIN_PULL_NONE>;
[all …]
Dat91sam9x5_lcd.dtsi61 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
62 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
63 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
64 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
65 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
66 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
67 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
68 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
69 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
70 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
Ds3c2416-pinctrl.dtsi86 samsung,pin-function = <2>;
91 samsung,pin-function = <2>;
96 samsung,pin-function = <2>;
101 samsung,pin-function = <2>;
106 samsung,pin-function = <2>;
111 samsung,pin-function = <2>;
116 samsung,pin-function = <2>;
121 samsung,pin-function = <2>;
126 samsung,pin-function = <2>;
131 samsung,pin-function = <2>;
[all …]
Dexynos5420-peach-pit.dts750 samsung,pin-function = <1>;
751 samsung,pin-pud = <0>;
752 samsung,pin-drv = <0>;
757 samsung,pin-function = <0>;
758 samsung,pin-pud = <0>;
759 samsung,pin-drv = <0>;
765 samsung,pin-function = <1>;
766 samsung,pin-pud = <0>;
767 samsung,pin-drv = <0>;
768 samsung,pin-val = <0>;
[all …]
Dexynos5800-peach-pi.dts713 samsung,pin-function = <1>;
714 samsung,pin-pud = <0>;
715 samsung,pin-drv = <0>;
720 samsung,pin-function = <0>;
721 samsung,pin-pud = <0>;
722 samsung,pin-drv = <0>;
728 samsung,pin-function = <1>;
729 samsung,pin-pud = <0>;
730 samsung,pin-drv = <0>;
731 samsung,pin-val = <0>;
[all …]
Dexynos5250-spring.dts361 samsung,pin-pud = <0>;
469 samsung,pin-function = <0>;
470 samsung,pin-pud = <1>;
471 samsung,pin-drv = <0>;
476 samsung,pin-function = <0>;
477 samsung,pin-pud = <3>;
478 samsung,pin-drv = <0>;
483 samsung,pin-function = <0xf>;
484 samsung,pin-pud = <0>;
485 samsung,pin-drv = <0>;
[all …]
Dexynos5250-snow-common.dtsi445 samsung,pin-pud = <0>;
572 samsung,pin-function = <1>;
573 samsung,pin-pud = <0>;
574 samsung,pin-drv = <0>;
579 samsung,pin-function = <1>;
580 samsung,pin-pud = <0>;
581 samsung,pin-drv = <0>;
586 samsung,pin-function = <0xf>;
587 samsung,pin-pud = <0>;
588 samsung,pin-drv = <0>;
[all …]
Dsama5d4.dtsi1360 /* WARNING: revisit as pin spec has changed */
1425 /* pinctrl pin settings */
1525 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1526 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1527 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1528 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1529 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1530 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1531 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1532 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
[all …]
Dat91sam9n12.dtsi524 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
525 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
526 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
527 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
528 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
529 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
530 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
531 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
532 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
533 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
Darmada-xp-netgear-rn2120.dts304 power_button_pin: power-button-pin {
309 reset_button_pin: reset-button-pin {
314 sata1_led_pin: sata1-led-pin {
319 sata2_led_pin: sata2-led-pin {
324 sata3_led_pin: sata3-led-pin {
329 sata4_led_pin: sata4-led-pin {
334 sata1_power_pin: sata1-power-pin {
339 sata2_power_pin: sata2-power-pin {
344 sata3_power_pin: sata3-power-pin {
349 sata4_power_pin: sata4-power-pin {
[all …]
Darmada-370-dlink-dns327l.dts195 sata-r-amber-pin {
201 sata-l-amber-pin {
207 backup-led-pin {
266 sata_l_white_pin: sata-l-white-pin {
271 sata_r_white_pin: sata-r-white-pin {
276 sata_r_amber_pin: sata-r-amber-pin {
281 sata_l_amber_pin: sata-l-amber-pin {
286 backup_led_pin: backup-led-pin {
291 xhci_pwr_pin: xhci-pwr-pin {
296 sata_r_pwr_pin: sata-r-pwr-pin {
[all …]
/linux-4.4.14/arch/arm64/boot/dts/exynos/
Dexynos7-pinctrl.dtsi2 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
7 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
178 samsung,pin-function = <2>;
179 samsung,pin-pud = <3>;
180 samsung,pin-drv = <0>;
185 samsung,pin-function = <2>;
186 samsung,pin-pud = <3>;
187 samsung,pin-drv = <0>;
192 samsung,pin-function = <3>;
193 samsung,pin-pud = <3>;
[all …]
/linux-4.4.14/drivers/pinctrl/qcom/
Dpinctrl-ssbi-mpp.c172 struct pm8xxx_pin_data *pin) in pm8xxx_mpp_update() argument
180 switch (pin->mode) { in pm8xxx_mpp_update()
182 if (pin->dtest) { in pm8xxx_mpp_update()
184 ctrl = pin->dtest - 1; in pm8xxx_mpp_update()
185 } else if (pin->input && pin->output) { in pm8xxx_mpp_update()
187 if (pin->high_z) in pm8xxx_mpp_update()
189 else if (pin->pullup == 600) in pm8xxx_mpp_update()
191 else if (pin->pullup == 10000) in pm8xxx_mpp_update()
195 } else if (pin->input) { in pm8xxx_mpp_update()
197 if (pin->dtest) in pm8xxx_mpp_update()
[all …]
Dpinctrl-ssbi-gpio.c133 struct pm8xxx_pin_data *pin, int bank) in pm8xxx_read_bank() argument
138 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_read_bank()
144 ret = regmap_read(pctrl->regmap, pin->reg, &val); in pm8xxx_read_bank()
154 struct pm8xxx_pin_data *pin, in pm8xxx_write_bank() argument
163 ret = regmap_write(pctrl->regmap, pin->reg, val); in pm8xxx_write_bank()
233 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; in pm8xxx_pinmux_set_mux() local
236 pin->function = function; in pm8xxx_pinmux_set_mux()
237 val = pin->function << 1; in pm8xxx_pinmux_set_mux()
239 pm8xxx_write_bank(pctrl, pin, 4, val); in pm8xxx_pinmux_set_mux()
256 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; in pm8xxx_pin_config_get() local
[all …]
Dpinctrl-spmi-gpio.c201 unsigned pin) in pmic_gpio_get_group_name() argument
203 return pctldev->desc->pins[pin].name; in pmic_gpio_get_group_name()
206 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin, in pmic_gpio_get_group_pins() argument
209 *pins = &pctldev->desc->pins[pin].number; in pmic_gpio_get_group_pins()
244 unsigned pin) in pmic_gpio_set_mux() argument
251 pad = pctldev->desc->pins[pin].drv_data; in pmic_gpio_set_mux()
284 unsigned int pin, unsigned long *config) in pmic_gpio_config_get() argument
290 pad = pctldev->desc->pins[pin].drv_data; in pmic_gpio_config_get()
337 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, in pmic_gpio_config_set() argument
346 pad = pctldev->desc->pins[pin].drv_data; in pmic_gpio_config_set()
[all …]
DKconfig11 tristate "Qualcomm APQ8064 pin controller driver"
19 tristate "Qualcomm APQ8084 pin controller driver"
27 tristate "Qualcomm IPQ8064 pin controller driver"
35 tristate "Qualcomm 8660 pin controller driver"
43 tristate "Qualcomm 8960 pin controller driver"
51 tristate "Qualcomm 8x74 pin controller driver"
59 tristate "Qualcomm 8916 pin controller driver"
67 tristate "Qualcomm Technologies QDF2xxx pin controller driver"
75 tristate "Qualcomm SPMI PMIC pin controller driver"
88 tristate "Qualcomm SSBI PMIC pin controller driver"
Dpinctrl-spmi-mpp.c221 unsigned pin) in pmic_mpp_get_group_name() argument
223 return pctldev->desc->pins[pin].name; in pmic_mpp_get_group_name()
227 unsigned pin, in pmic_mpp_get_group_pins() argument
230 *pins = &pctldev->desc->pins[pin].number; in pmic_mpp_get_group_pins()
312 unsigned pin) in pmic_mpp_set_mux() argument
319 pad = pctldev->desc->pins[pin].drv_data; in pmic_mpp_set_mux()
338 unsigned int pin, unsigned long *config) in pmic_mpp_config_get() argument
344 pad = pctldev->desc->pins[pin].drv_data; in pmic_mpp_config_get()
404 static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, in pmic_mpp_config_set() argument
413 pad = pctldev->desc->pins[pin].drv_data; in pmic_mpp_config_set()
[all …]
/linux-4.4.14/arch/arm/mach-orion5x/
Dboard-rd88f5182.c42 int pin; in rd88f5182_pci_preinit() local
47 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; in rd88f5182_pci_preinit()
48 if (gpio_request(pin, "PCI IntA") == 0) { in rd88f5182_pci_preinit()
49 if (gpio_direction_input(pin) == 0) { in rd88f5182_pci_preinit()
50 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); in rd88f5182_pci_preinit()
53 "set_irq_type pin %d\n", pin); in rd88f5182_pci_preinit()
54 gpio_free(pin); in rd88f5182_pci_preinit()
57 printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); in rd88f5182_pci_preinit()
60 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; in rd88f5182_pci_preinit()
61 if (gpio_request(pin, "PCI IntB") == 0) { in rd88f5182_pci_preinit()
[all …]
Drd88f5182-setup.c113 int pin; in rd88f5182_pci_preinit() local
118 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; in rd88f5182_pci_preinit()
119 if (gpio_request(pin, "PCI IntA") == 0) { in rd88f5182_pci_preinit()
120 if (gpio_direction_input(pin) == 0) { in rd88f5182_pci_preinit()
121 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); in rd88f5182_pci_preinit()
124 "set_irq_type pin %d\n", pin); in rd88f5182_pci_preinit()
125 gpio_free(pin); in rd88f5182_pci_preinit()
128 printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); in rd88f5182_pci_preinit()
131 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; in rd88f5182_pci_preinit()
132 if (gpio_request(pin, "PCI IntB") == 0) { in rd88f5182_pci_preinit()
[all …]
Dts209-setup.c111 int pin; in qnap_ts209_pci_preinit() local
116 pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; in qnap_ts209_pci_preinit()
117 if (gpio_request(pin, "PCI Int1") == 0) { in qnap_ts209_pci_preinit()
118 if (gpio_direction_input(pin) == 0) { in qnap_ts209_pci_preinit()
119 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); in qnap_ts209_pci_preinit()
122 "set_irq_type pin %d\n", pin); in qnap_ts209_pci_preinit()
123 gpio_free(pin); in qnap_ts209_pci_preinit()
127 "%d\n", pin); in qnap_ts209_pci_preinit()
130 pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; in qnap_ts209_pci_preinit()
131 if (gpio_request(pin, "PCI Int2") == 0) { in qnap_ts209_pci_preinit()
[all …]
Ddb88f5281-setup.c207 int pin; in db88f5281_pci_preinit() local
212 pin = DB88F5281_PCI_SLOT0_IRQ_PIN; in db88f5281_pci_preinit()
213 if (gpio_request(pin, "PCI Int1") == 0) { in db88f5281_pci_preinit()
214 if (gpio_direction_input(pin) == 0) { in db88f5281_pci_preinit()
215 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); in db88f5281_pci_preinit()
218 "set_irq_type pin %d\n", pin); in db88f5281_pci_preinit()
219 gpio_free(pin); in db88f5281_pci_preinit()
222 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); in db88f5281_pci_preinit()
225 pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; in db88f5281_pci_preinit()
226 if (gpio_request(pin, "PCI Int2") == 0) { in db88f5281_pci_preinit()
[all …]
Dterastation_pro2-setup.c82 int pin; in tsp2_pci_preinit() local
87 pin = TSP2_PCI_SLOT0_IRQ_PIN; in tsp2_pci_preinit()
88 if (gpio_request(pin, "PCI Int1") == 0) { in tsp2_pci_preinit()
89 if (gpio_direction_input(pin) == 0) { in tsp2_pci_preinit()
90 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); in tsp2_pci_preinit()
93 "to set_irq_type pin %d\n", pin); in tsp2_pci_preinit()
94 gpio_free(pin); in tsp2_pci_preinit()
98 "gpio_request %d\n", pin); in tsp2_pci_preinit()
102 static int __init tsp2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in tsp2_pci_map_irq() argument
109 irq = orion5x_pci_map_irq(dev, slot, pin); in tsp2_pci_map_irq()
/linux-4.4.14/arch/arm/mach-s3c24xx/
Dpm.c79 static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) in s3c_pm_check_resume_pin() argument
83 int irq = gpio_to_irq(pin); in s3c_pm_check_resume_pin()
90 pinstate = s3c_gpio_getcfg(pin); in s3c_pm_check_resume_pin()
94 S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin); in s3c_pm_check_resume_pin()
97 S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin); in s3c_pm_check_resume_pin()
98 s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); in s3c_pm_check_resume_pin()
110 int pin; in s3c_pm_configure_extint() local
117 for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) { in s3c_pm_configure_extint()
118 s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0)); in s3c_pm_configure_extint()
121 for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) { in s3c_pm_configure_extint()
[all …]
/linux-4.4.14/arch/arm/mach-imx/
Diomux-v1.c61 unsigned int port, unsigned int pin, int on) in imx_iomuxv1_set_puen() argument
63 unsigned long mask = 1 << pin; in imx_iomuxv1_set_puen()
69 unsigned int port, unsigned int pin, int out) in imx_iomuxv1_set_ddir() argument
71 unsigned long mask = 1 << pin; in imx_iomuxv1_set_ddir()
77 unsigned int port, unsigned int pin, int af) in imx_iomuxv1_set_gpr() argument
79 unsigned long mask = 1 << pin; in imx_iomuxv1_set_gpr()
85 unsigned int port, unsigned int pin, int inuse) in imx_iomuxv1_set_gius() argument
87 unsigned long mask = 1 << pin; in imx_iomuxv1_set_gius()
93 unsigned int port, unsigned int pin, unsigned int ocr) in imx_iomuxv1_set_ocr() argument
95 unsigned long shift = (pin & 0xf) << 1; in imx_iomuxv1_set_ocr()
[all …]
Diomux-imx31.c71 void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) in mxc_iomux_set_pad() argument
76 pin &= IOMUX_PADNUM_MASK; in mxc_iomux_set_pad()
77 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4; in mxc_iomux_set_pad()
78 field = (pin + 2) % 3; in mxc_iomux_set_pad()
81 __func__, (pin + 2) / 3, field); in mxc_iomux_set_pad()
98 int mxc_iomux_alloc_pin(unsigned int pin, const char *label) in mxc_iomux_alloc_pin() argument
100 unsigned pad = pin & IOMUX_PADNUM_MASK; in mxc_iomux_alloc_pin()
113 mxc_iomux_mode(pin); in mxc_iomux_alloc_pin()
138 void mxc_iomux_release_pin(unsigned int pin) in mxc_iomux_release_pin() argument
140 unsigned pad = pin & IOMUX_PADNUM_MASK; in mxc_iomux_release_pin()
/linux-4.4.14/drivers/gpio/
Dgpio-vr41xx.c127 unsigned int pin; in mask_ack_giuint_low() local
129 pin = GPIO_PIN_OF_IRQ(d->irq); in mask_ack_giuint_low()
130 giu_clear(GIUINTENL, 1 << pin); in mask_ack_giuint_low()
131 giu_write(GIUINTSTATL, 1 << pin); in mask_ack_giuint_low()
179 unsigned int pin; in mask_ack_giuint_high() local
181 pin = GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET; in mask_ack_giuint_high()
182 giu_clear(GIUINTENH, 1 << pin); in mask_ack_giuint_high()
183 giu_write(GIUINTSTATH, 1 << pin); in mask_ack_giuint_high()
232 void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, in vr41xx_set_irq_trigger() argument
237 if (pin < GIUINT_HIGH_OFFSET) { in vr41xx_set_irq_trigger()
[all …]
Dgpio-zevio.c66 static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin, in zevio_gpio_port_get() argument
69 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; in zevio_gpio_port_get()
73 static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin, in zevio_gpio_port_set() argument
76 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; in zevio_gpio_port_set()
81 static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin) in zevio_gpio_get() argument
87 dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); in zevio_gpio_get()
88 if (dir & BIT(ZEVIO_GPIO_BIT(pin))) in zevio_gpio_get()
89 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT); in zevio_gpio_get()
91 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); in zevio_gpio_get()
94 return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1; in zevio_gpio_get()
[all …]
Dgpio-lpc32xx.c175 unsigned pin, int input) in __set_gpio_dir_p012() argument
178 __raw_writel(GPIO012_PIN_TO_BIT(pin), in __set_gpio_dir_p012()
181 __raw_writel(GPIO012_PIN_TO_BIT(pin), in __set_gpio_dir_p012()
186 unsigned pin, int input) in __set_gpio_dir_p3() argument
188 u32 u = GPIO3_PIN_TO_BIT(pin); in __set_gpio_dir_p3()
197 unsigned pin, int high) in __set_gpio_level_p012() argument
200 __raw_writel(GPIO012_PIN_TO_BIT(pin), in __set_gpio_level_p012()
203 __raw_writel(GPIO012_PIN_TO_BIT(pin), in __set_gpio_level_p012()
208 unsigned pin, int high) in __set_gpio_level_p3() argument
210 u32 u = GPIO3_PIN_TO_BIT(pin); in __set_gpio_level_p3()
[all …]
Dgpio-ks8695.c40 static void ks8695_gpio_mode(unsigned int pin, short gpio) in ks8695_gpio_mode() argument
45 if (pin > KS8695_GPIO_5) /* only GPIO 0..5 have internal functions */ in ks8695_gpio_mode()
52 x &= ~enable[pin]; in ks8695_gpio_mode()
54 x |= enable[pin]; in ks8695_gpio_mode()
66 int ks8695_gpio_interrupt(unsigned int pin, unsigned int type) in ks8695_gpio_interrupt() argument
70 if (pin > KS8695_GPIO_3) /* only GPIO 0..3 can generate IRQ */ in ks8695_gpio_interrupt()
77 x &= ~IOPM(pin); in ks8695_gpio_interrupt()
83 irq_set_irq_type(gpio_irq[pin], type); in ks8695_gpio_interrupt()
86 ks8695_gpio_mode(pin, 0); in ks8695_gpio_interrupt()
99 static int ks8695_gpio_direction_input(struct gpio_chip *gc, unsigned int pin) in ks8695_gpio_direction_input() argument
[all …]
Dgpio-dln2.c69 __le16 pin; member
73 __le16 pin __packed;
92 static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin) in dln2_gpio_pin_cmd() argument
95 .pin = cpu_to_le16(pin), in dln2_gpio_pin_cmd()
101 static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin) in dln2_gpio_pin_val() argument
105 .pin = cpu_to_le16(pin), in dln2_gpio_pin_val()
113 if (len < sizeof(rsp) || req.pin != rsp.pin) in dln2_gpio_pin_val()
119 static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin) in dln2_gpio_pin_get_in_val() argument
123 ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin); in dln2_gpio_pin_get_in_val()
129 static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin) in dln2_gpio_pin_get_out_val() argument
[all …]
Dgpiolib-acpi.c28 unsigned int pin; member
35 unsigned int pin; member
74 static int acpi_gpiochip_pin_to_gpio_offset(struct gpio_chip *chip, int pin) in acpi_gpiochip_pin_to_gpio_offset() argument
80 return pin; in acpi_gpiochip_pin_to_gpio_offset()
88 if (range->pins[i] == pin) in acpi_gpiochip_pin_to_gpio_offset()
92 if (pin >= range->pin_base && in acpi_gpiochip_pin_to_gpio_offset()
93 pin < range->pin_base + range->npins) { in acpi_gpiochip_pin_to_gpio_offset()
97 return gpio_base + pin - range->pin_base; in acpi_gpiochip_pin_to_gpio_offset()
106 int pin) in acpi_gpiochip_pin_to_gpio_offset() argument
108 return pin; in acpi_gpiochip_pin_to_gpio_offset()
[all …]
Dgpio-mvebu.c188 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value) in mvebu_gpio_set() argument
198 u |= 1 << pin; in mvebu_gpio_set()
200 u &= ~(1 << pin); in mvebu_gpio_set()
205 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin) in mvebu_gpio_get() argument
211 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) { in mvebu_gpio_get()
218 return (u >> pin) & 1; in mvebu_gpio_get()
221 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) in mvebu_gpio_blink() argument
231 u |= 1 << pin; in mvebu_gpio_blink()
233 u &= ~(1 << pin); in mvebu_gpio_blink()
238 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin) in mvebu_gpio_direction_input() argument
[all …]
/linux-4.4.14/arch/arm/plat-orion/
Dgpio.c96 __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input) in __set_direction() argument
102 u |= 1 << pin; in __set_direction()
104 u &= ~(1 << pin); in __set_direction()
108 static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high) in __set_level() argument
114 u |= 1 << pin; in __set_level()
116 u &= ~(1 << pin); in __set_level()
121 __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink) in __set_blinking() argument
127 u |= 1 << pin; in __set_blinking()
129 u &= ~(1 << pin); in __set_blinking()
134 orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode) in orion_gpio_is_valid() argument
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/
Dpincfg.txt4 - pio-map : array of pin configurations. Each pin is defined by 6
5 integers. The six numbers are respectively: port, pin, dir,
7 - port : port number of the pin; 0-6 represent port A-G in UM.
8 - pin : pin number in the port.
9 - dir : direction of the pin, should encode as follows:
11 0 = The pin is disabled
12 1 = The pin is an output
13 2 = The pin is an input
14 3 = The pin is I/O
16 - open_drain : indicates the pin is normal or wired-OR:
[all …]
/linux-4.4.14/drivers/acpi/
Dpci_irq.c44 u8 pin; member
49 static inline char pin_name(int pin) in pin_name() argument
51 return 'A' + pin - 1; in pin_name()
100 unsigned char pin; member
141 entry->pin == quirk->pin && in do_prt_fixups()
148 entry->id.device, pin_name(entry->pin), in do_prt_fixups()
156 int pin, struct acpi_pci_routing_table *prt, in acpi_pci_irq_check_entry() argument
165 prt->pin + 1 != pin) in acpi_pci_irq_check_entry()
180 entry->pin = prt->pin + 1; in acpi_pci_irq_check_entry()
213 entry->id.device, pin_name(entry->pin), in acpi_pci_irq_check_entry()
[all …]
/linux-4.4.14/drivers/pinctrl/sunxi/
Dpinctrl-sunxi.h32 #define SUNXI_PINCTRL_PIN(bank, pin) \ argument
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
91 struct pinctrl_pin_desc pin; member
113 unsigned pin; member
134 .pin = _pin, \
177 static inline u32 sunxi_mux_reg(u16 pin) in sunxi_mux_reg() argument
179 u8 bank = pin / PINS_PER_BANK; in sunxi_mux_reg()
182 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04; in sunxi_mux_reg()
186 static inline u32 sunxi_mux_offset(u16 pin) in sunxi_mux_offset() argument
188 u32 pin_num = pin % MUX_PINS_PER_REG; in sunxi_mux_offset()
[all …]
Dpinctrl-sunxi.c79 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; in sunxi_pinctrl_desc_find_function_by_name() local
81 if (!strcmp(pin->pin.name, pin_name)) { in sunxi_pinctrl_desc_find_function_by_name()
82 struct sunxi_desc_function *func = pin->functions; in sunxi_pinctrl_desc_find_function_by_name()
104 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; in sunxi_pinctrl_desc_find_function_by_pin() local
106 if (pin->pin.number == pin_num) { in sunxi_pinctrl_desc_find_function_by_pin()
107 struct sunxi_desc_function *func = pin->functions; in sunxi_pinctrl_desc_find_function_by_pin()
143 *pins = (unsigned *)&pctl->groups[group].pin; in sunxi_pctrl_get_group_pins()
291 unsigned pin = g->pin - pctl->desc->pin_base; in sunxi_pconf_group_set() local
315 val = readl(pctl->membase + sunxi_dlevel_reg(pin)); in sunxi_pconf_group_set()
316 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin); in sunxi_pconf_group_set()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/pinctrl/
Dsamsung-pinctrl.txt10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
17 - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
18 - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
19 - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
[all …]
Drenesas,pfc-pinctrl.txt13 - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
14 - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
15 - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
16 - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
17 - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
18 - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
19 - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
20 - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
21 - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
22 - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
[all …]
Dpinctrl-bindings.txt3 Hardware modules that control pin multiplexing or configuration parameters
4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
5 controllers. Each pin controller must be represented as a node in device tree,
8 Hardware modules whose signals are affected by pin configuration are
12 For a client device to operate correctly, certain pin controllers must
13 set up certain specific pin configurations. Some client devices need a
14 single static pin configuration, e.g. set up during initialization. Others
21 for client device device tree nodes to map those state names to the pin
24 Note that pin controllers themselves may also be client devices of themselves.
25 For example, a pin controller may set up its own "active" state when the
[all …]
Dcnxt,cx92755-pinctrl.txt3 This document describes the device tree binding of the pin mapping hardware
15 - #gpio-cells: Must be <2>. The first cell is the pin number and the
28 As a pin controller device, in addition to the required properties, this node
29 should also contain the pin configuration nodes that client devices reference,
36 Each pin configuration node is a sub-node of the pin controller node and is a
37 container of an arbitrary number of subnodes, called pin group nodes in this
42 "pin configuration node".
46 A pin group node specifies the desired pin mux for an arbitrary number of
47 pins. The name of the pin group node is optional and not used.
49 A pin group node only affects the properties specified in the node, and has no
[all …]
Datmel,at91-pinctrl.txt12 phrase "pin configuration node".
14 Atmel AT91 pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'pins' selects the function mode(also named pin
17 mode) this pin can work on and the 'config' configures various pad settings
23 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
41 For each peripheral/bank we will descibe in a u32 if a pin can be
42 configured in it by putting 1 to the pin bit (1 << pin)
82 Required properties for pin configuration node:
89 PULL_UP (1 << 0): indicate this pin needs a pull up.
90 MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive.
[all …]
Dbrcm,bcm11351-pinctrl.txt3 This is a pin controller for the Broadcom BCM281xx SoC family, which includes
21 As a pin controller device, in addition to the required properties, this node
22 should also contain the pin configuration nodes that client devices reference,
27 Each pin configuration node is a sub-node of the pin controller node and is a
28 container of an arbitrary number of subnodes, called pin group nodes in this
33 "pin configuration node".
37 A pin group node specifies the desired pin mux and/or pin configuration for an
38 arbitrary number of pins. The name of the pin group node is optional and not
41 A pin group node only affects the properties specified in the node, and has no
44 The pin group node accepts a subset of the generic pin config properties. For
[all …]
Dste,nomadik.txt7 (these have the register ranges used by the pin controller).
8 - prcm: phandle to the PRCMU managing the back end of this pin controller
12 phrase "pin configuration node".
14 ST Ericsson's pin configuration nodes act as a container for an arbitrary number of
16 pin, a group, or a list of pins or groups. This configuration can include the
17 mux function to select on those pin(s)/group(s), and various pin configuration
22 pin multiplexing node layout from the standard pin control bindings
25 Required pin multiplexing subnode properties:
27 pin or group.
28 - groups : An array of strings. Each string contains the name of a pin
[all …]
Dbrcm,cygnus-gpio.txt14 Must be two. The first cell is the GPIO pin number (within the
15 controller's pin space) and the second cell is used for the following:
30 Specifies the mapping between gpio controller and pin-controllers pins.
32 1. Phandle of pin-controller.
33 2. GPIO base pin offset.
34 3 Pin-control base pin offset.
35 4. number of gpio pins which are linearly mapped from pin base.
40 The list of pins (within the controller's own pin space) that properties
41 in the node apply to. Pin names are "gpio-<pin>"
44 Disable pin bias
Dabilis,tb10x-iomux.txt1 Abilis Systems TB10x pin controller
8 - reg: should contain the physical address and size of the pin controller's
15 Functions are defined (and referenced) by sub-nodes of the pin controller.
17 Every function is associated to one named pin group inside the pin controller
18 driver and these names are used to associate pin group predefinitions to pin
22 - abilis,function: should be set to the name of the function's pin group.
24 The following pin groups are available:
45 The named pin groups of GPIO ports can be used to define GPIO ranges as
Dpinctrl-st.txt1 *ST pin controller.
3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
6 the pin to different hardware blocks.
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
12 gpio driver to configure a pin.
36 - st,retime-pin-mask : Should be mask to specify which pins can be retimed.
40 - ranges : defines mapping between pin controller node (parent) to gpio-bank
53 - #gpio-cells : Should be one. The first cell is the pin number.
78 pin-controller-sbc {
[all …]
Dfsl,imx-pinctrl.txt12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
17 mode) this pin can work on and the 'config' configures various pad settings
24 Required properties for pin configuration node:
26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
33 NO_PAD_CTL(1 << 31): indicate this pin does not need config.
46 1. We have pin function node defined under iomux controller node to represent
48 2. The pin configuration node intends to work on a specific function should
51 this group of pins in this pin configuration node are working on.
[all …]
Dlantiq,pinctrl-xway.txt10 phrase "pin configuration node".
12 Lantiq's pin configuration nodes act as a container for an arbitrary number of
14 pin, a group, or a list of pins or groups. This configuration can include the
15 mux function to select on those group(s), and two pin configuration parameters:
22 other words, a subnode that lists a mux function but no pin configuration
23 parameters implies no information about any pin configuration parameters.
24 Similarly, a pin subnode that describes a pullup parameter implies no
54 Definition of pin configurations:
57 - lantiq,pins : An array of strings. Each string contains the name of a pin.
61 - lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
[all …]
Dnvidia,tegra210-pinmux.txt11 phrase "pin configuration node".
13 Tegra's pin configuration nodes act as a container for an arbitrary number of
15 pin, a group, or a list of pins or groups. This configuration can include the
16 mux function to select on those pin(s)/group(s), and various pin configuration
23 other words, a subnode that lists a mux function but no pin configuration
24 parameters implies no information about any pin configuration parameters.
25 Similarly, a pin subnode that describes a pullup parameter implies no
31 See the TRM to determine which properties and values apply to each pin/group.
36 - nvidia,pins : An array of strings. Each string contains the name of a pin or
41 pin or group.
[all …]
Dpinctrl-vt8500.txt3 These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
13 - #gpio-cells : Should be two. The first cell is the pin number and the
21 phrase "pin configuration node".
23 Each pin configuration node lists the pin(s) to which it applies, and one or
24 more of the mux functions to select on those pin(s), and pull-up/down
31 - wm,pins: An array of cells. Each cell contains the ID of a pin.
34 - wm,function: Integer, containing the function to mux to the pin(s):
39 - wm,pull: Integer, representing the pull-down/up to apply to the pin(s):
Dlantiq,pinctrl-falcon.txt10 phrase "pin configuration node".
12 Lantiq's pin configuration nodes act as a container for an arbitrary number of
14 pin, a group, or a list of pins or groups. This configuration can include the
15 mux function to select on those group(s), and two pin configuration parameters:
22 other words, a subnode that lists a mux function but no pin configuration
23 parameters implies no information about any pin configuration parameters.
24 Similarly, a pin subnode that describes a pullup parameter implies no
47 Definition of pin configurations:
50 - lantiq,pins : An array of strings. Each string contains the name of a pin.
54 - lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
Dqcom,apq8064-pinctrl.txt11 The first cell is the gpio pin number and the
19 phrase "pin configuration node".
21 Qualcomm's pin configuration nodes act as a container for an arbitrary number of
23 pin, a group, or a list of pins or groups. This configuration can include the
24 mux function to select on those pin(s)/group(s), and various pin configuration
31 other words, a subnode that lists a mux function but no pin configuration
32 parameters implies no information about any pin configuration parameters.
33 Similarly, a pin subnode that describes a pullup parameter implies no
38 to specify in a pin configuration subnode:
Dqcom,msm8660-pinctrl.txt11 The first cell is the gpio pin number and the
19 phrase "pin configuration node".
21 Qualcomm's pin configuration nodes act as a container for an arbitrary number of
23 pin, a group, or a list of pins or groups. This configuration can include the
24 mux function to select on those pin(s)/group(s), and various pin configuration
31 other words, a subnode that lists a mux function but no pin configuration
32 parameters implies no information about any pin configuration parameters.
33 Similarly, a pin subnode that describes a pullup parameter implies no
38 to specify in a pin configuration subnode:
Dqcom,ipq8064-pinctrl.txt11 The first cell is the gpio pin number and the
19 phrase "pin configuration node".
21 Qualcomm's pin configuration nodes act as a container for an arbitrary number of
23 pin, a group, or a list of pins or groups. This configuration can include the
24 mux function to select on those pin(s)/group(s), and various pin configuration
31 other words, a subnode that lists a mux function but no pin configuration
32 parameters implies no information about any pin configuration parameters.
33 Similarly, a pin subnode that describes a pullup parameter implies no
38 to specify in a pin configuration subnode:
Dimg,tz1090-pdc-pinctrl.txt1 ImgTec TZ1090 PDC pin controller
10 phrase "pin configuration node".
12 TZ1090-PDC's pin configuration nodes act as a container for an arbitrary number
14 pin, a group, or a list of pins or groups. This configuration can include the
15 mux function to select on those pin(s)/group(s), and various pin configuration
22 other words, a subnode that lists a mux function but no pin configuration
23 parameters implies no information about any pin configuration parameters.
24 Similarly, a pin subnode that describes a pullup parameter implies no
31 - tz1090,pins : An array of strings. Each string contains the name of a pin or
36 pin or group. Valid values for function names are listed below, including
[all …]
Dpinctrl-palmas.txt14 phrase "pin configuration node".
16 Palmas's pin configuration nodes act as a container for an arbitrary number of
19 those pin(s), and various pin configuration parameters, such as pull-up,
26 other words, a subnode that lists a mux function but no pin configuration
27 parameters implies no information about any pin configuration parameters.
28 Similarly, a pin subnode that describes a pullup parameter implies no
34 I2C2_SDA_SDO pin/pad for DVFS1 interface
37 and SYSEN2 pin/pad for DVFS2 interface
50 Valid values for pin names are:
Dfsl,mxs-pinctrl.txt3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
11 pin controller.
16 The node of mxs pin controller acts as a container for an arbitrary number of
25 Those subnodes under mxs pin controller node will fall into two categories.
26 One is to set up a group of pins for a function, both mux selection and pin
28 one is to adjust the pin configuration for some particular pins that need a
32 On mxs, there is no hardware pin group. The pin group in this binding only
42 - fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
43 with given mux function, with bank, pin and mux packed as below.
[all …]
Dqcom,msm8974-pinctrl.txt11 The first cell is the gpio pin number and the
19 phrase "pin configuration node".
21 Qualcomm's pin configuration nodes act as a container for an arbitrary number of
23 pin, a group, or a list of pins or groups. This configuration can include the
24 mux function to select on those pin(s)/group(s), and various pin configuration
31 other words, a subnode that lists a mux function but no pin configuration
32 parameters implies no information about any pin configuration parameters.
33 Similarly, a pin subnode that describes a pullup parameter implies no
38 to specify in a pin configuration subnode:
Dnxp,lpc1850-scu.txt1 NXP LPC18xx/43xx SCU pin controller Device Tree Bindings
9 The lpc1850-scu driver uses the generic pin multiplexing and generic pin
26 user manual or the pin table in the pinctrl-lpc18xx driver for supported
27 pin properties.
Dmarvell,mvebu-pinctrl.txt9 phrase "pin configuration node".
11 A Marvell SoC pin configuration node is a node of a group of pins which can
19 Required properties for pin configuration node:
22 marvell,pins given in this pin configuration node. The function has to be
24 valid pin/pin group names and available function names for each SoC.
Dbrcm,bcm2835-gpio.txt10 - #gpio-cells : Should be two. The first cell is the pin number and the
30 phrase "pin configuration node".
32 Each pin configuration node lists the pin(s) to which it applies, and one or
33 more of the mux function to select on those pin(s), and pull-up/down
40 - brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs
44 - brcm,function: Integer, containing the function to mux to the pin(s):
53 - brcm,pull: Integer, representing the pull-down/up to apply to the pin(s):
Dberlin,pinctrl.txt6 controlled are organized in groups, so no actual pin information is
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
34 sys_pinctrl: pin-controller {
Dpinctrl-single.txt1 One-register-per-pin type device tree based pinctrl driver
18 pin functions is ignored
21 more than one pin, for which "pinctrl-single,function-mask" property specifies
22 position mask of pin.
67 low power mode of this pin. For some silicons, the low power mode will
68 control the output of the pin when the pad including the pin enter low
74 range. They're value of subnode phandle, pin base in pinctrl device, pin
79 /* pin base, nr pins & gpio function */
89 This driver assumes that there is only one register for each pin (unless the
93 The pin configuration nodes for pinctrl-single are specified as pinctrl
[all …]
/linux-4.4.14/drivers/pinctrl/mediatek/
Dpinctrl-mtk-common.c59 unsigned long pin) in mtk_get_regmap() argument
61 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) in mtk_get_regmap()
66 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin) in mtk_get_port() argument
69 return ((pin >> 4) & pctl->devdata->port_mask) in mtk_get_port()
111 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, in mtk_pconf_set_ies_smt() argument
136 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), in mtk_pconf_set_ies_smt()
137 pin, pctl->devdata->port_align, value, arg); in mtk_pconf_set_ies_smt()
140 bit = BIT(pin & 0xf); in mtk_pconf_set_ies_smt()
148 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl); in mtk_pconf_set_ies_smt()
150 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); in mtk_pconf_set_ies_smt()
[all …]
Dpinctrl-mtk-common.h42 struct pinctrl_pin_desc pin; member
49 .pin = _pin, \
73 unsigned pin; member
109 unsigned short pin; member
117 .pin = _pin, \
133 unsigned short pin; member
142 .pin = _pin, \
233 int (*spec_pull_set)(struct regmap *reg, unsigned int pin,
235 int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
280 unsigned int info_num, unsigned int pin,
[all …]
DKconfig13 bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
19 bool "Mediatek MT8127 pin control" if COMPILE_TEST && !MACH_MT8127
26 bool "Mediatek MT8173 pin control"
34 bool "Mediatek MT6397 pin control" if COMPILE_TEST && !MFD_MT6397
/linux-4.4.14/arch/sh/drivers/pci/
Dfixups-cayman.c8 int __init pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin) in pcibios_map_platform_irq() argument
33 int pin; in pcibios_map_platform_irq() member
40 pin = path[i].pin = pci_swizzle_interrupt_pin(dev, pin); in pcibios_map_platform_irq()
54 result = IRQ_INTA + pci_swizzle_interrupt_pin(dev, pin) - 1; in pcibios_map_platform_irq()
58 pin = path[i].pin; in pcibios_map_platform_irq()
66 pin = path[i].pin; in pcibios_map_platform_irq()
68 result = IRQ_P2INTA + (pin - 1); in pcibios_map_platform_irq()
Dfixups-landisk.c23 int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin) in pcibios_map_platform_irq() argument
31 int irq = ((slot + pin - 1) & 0x3) + evt2irq(0x2a0); in pcibios_map_platform_irq()
33 if ((slot | (pin - 1)) > 0x3) { in pcibios_map_platform_irq()
35 slot, pin - 1 + 'A'); in pcibios_map_platform_irq()
/linux-4.4.14/Documentation/devicetree/bindings/sound/
Drt5645.txt16 a GPIO spec for the external headphone detect pin. If jd-mode = 0,
22 - realtek,dmic1-data-pin
24 1: using IN2P pin as dmic1 data pin
25 2: using GPIO6 pin as dmic1 data pin
26 3: using GPIO10 pin as dmic1 data pin
27 4: using GPIO12 pin as dmic1 data pin
29 - realtek,dmic2-data-pin
31 1: using IN2N pin as dmic2 data pin
32 2: using GPIO5 pin as dmic2 data pin
33 3: using GPIO11 pin as dmic2 data pin
Dpcm512x.txt3 These devices support both I2C and SPI (configured with pin strapping
22 configured to accept clock input on a specified gpio pin.
26 given pll-in pin and PLL output on the given pll-out pin. An
27 external connection from the pll-out pin to the SCLK pin is assumed.
Dssm2518.txt7 - reg : the I2C address of the device. This will either be 0x34 (ADDR pin low)
8 or 0x35 (ADDR pin high)
11 - gpios : GPIO connected to the nSD pin. If the property is not present it is
12 assumed that the nSD pin is hardwired to always on.
Dadi,adau1701.txt11 - reset-gpio: A GPIO spec to define which pin is connected to the
12 chip's !RESET pin. If specified, the driver will
19 - adi,pin-config: An array of 12 numerical values selecting one of the
20 pin configurations as described in the datasheet,
36 adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4
/linux-4.4.14/drivers/gpu/drm/radeon/
Ddce6_afmt.c67 offset = rdev->audio.pin[i].offset; in dce6_afmt_get_connected_pins()
71 rdev->audio.pin[i].connected = false; in dce6_afmt_get_connected_pins()
73 rdev->audio.pin[i].connected = true; in dce6_afmt_get_connected_pins()
82 struct r600_audio_pin *pin = NULL; in dce6_audio_get_pin() local
88 if (rdev->audio.pin[i].connected) { in dce6_audio_get_pin()
89 pin = &rdev->audio.pin[i]; in dce6_audio_get_pin()
96 if (dig->pin == pin) in dce6_audio_get_pin()
102 return pin; in dce6_audio_get_pin()
105 if (!pin) in dce6_audio_get_pin()
107 return pin; in dce6_audio_get_pin()
[all …]
Dradeon_audio.c32 void r600_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin,
34 void dce4_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin,
36 void dce6_audio_enable(struct radeon_device *rdev, struct r600_audio_pin *pin,
246 struct r600_audio_pin *pin, u8 enable_mask) in radeon_audio_enable() argument
253 if (!pin) in radeon_audio_enable()
261 if (dig->pin == pin) in radeon_audio_enable()
271 rdev->audio.funcs->enable(rdev, pin, enable_mask); in radeon_audio_enable()
325 rdev->audio.pin[i].channels = -1; in radeon_audio_init()
326 rdev->audio.pin[i].rate = -1; in radeon_audio_init()
327 rdev->audio.pin[i].bits_per_sample = -1; in radeon_audio_init()
[all …]
/linux-4.4.14/drivers/pinctrl/
Dpinctrl-at91.c109 uint32_t pin; member
158 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
160 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
162 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
164 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
166 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
167 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
329 static inline int pin_to_bank(unsigned pin) in pin_to_bank() argument
331 return pin /= MAX_NB_GPIO_PER_BANK; in pin_to_bank()
334 static unsigned pin_to_mask(unsigned int pin) in pin_to_mask() argument
[all …]
Dpinctrl-pistachio.c30 #define PADS_SCHMITT_EN_REG(pin) (PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32)) argument
31 #define PADS_SCHMITT_EN_BIT(pin) BIT((pin) % 32) argument
34 #define PADS_PU_PD_REG(pin) (PADS_PU_PD0 + 0x4 * ((pin) / 16)) argument
35 #define PADS_PU_PD_SHIFT(pin) (2 * ((pin) % 16)) argument
48 #define PADS_SLEW_RATE_REG(pin) (PADS_SLEW_RATE0 + 0x4 * ((pin) / 32)) argument
49 #define PADS_SLEW_RATE_BIT(pin) BIT((pin) % 32) argument
52 #define PADS_DRIVE_STRENGTH_REG(pin) \ argument
53 (PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16))
54 #define PADS_DRIVE_STRENGTH_SHIFT(pin) (2 * ((pin) % 16)) argument
90 unsigned int pin; member
[all …]
Dpinctrl-lantiq.c78 const char *group, *pin; in ltq_pinctrl_dt_subnode_to_map() local
118 of_property_for_each_string(np, "lantiq,pins", prop, pin) { in ltq_pinctrl_dt_subnode_to_map()
123 (*map)->name = pin; in ltq_pinctrl_dt_subnode_to_map()
124 (*map)->data.configs.group_or_pin = pin; in ltq_pinctrl_dt_subnode_to_map()
227 static int match_mfp(const struct ltq_pinmux_info *info, int pin) in match_mfp() argument
231 if (info->mfp[i].pin == pin) in match_mfp()
242 int i, pin, ret = 0; in match_group_mux() local
244 pin = match_mfp(info, grp->pins[i]); in match_group_mux()
245 if (pin < 0) { in match_group_mux()
250 ret = match_mux(&info->mfp[pin], mux); in match_group_mux()
[all …]
Dpinctrl-xway.c68 .pin = a, \
450 unsigned pin, in xway_pinconf_get() argument
455 int port = PORT(pin); in xway_pinconf_get()
463 reg = GPIO_OD(pin); in xway_pinconf_get()
465 !gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); in xway_pinconf_get()
472 reg = GPIO_PUDEN(pin); in xway_pinconf_get()
473 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) { in xway_pinconf_get()
481 reg = GPIO_PUDSEL(pin); in xway_pinconf_get()
482 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) in xway_pinconf_get()
489 reg = GPIO_DIR(pin); in xway_pinconf_get()
[all …]
Dpinctrl-at91-pio4.c82 u32 pin; member
163 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; in atmel_gpio_irq_set_type() local
166 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, in atmel_gpio_irq_set_type()
167 BIT(pin->line)); in atmel_gpio_irq_set_type()
168 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); in atmel_gpio_irq_set_type()
197 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); in atmel_gpio_irq_set_type()
205 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; in atmel_gpio_irq_mask() local
207 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, in atmel_gpio_irq_mask()
208 BIT(pin->line)); in atmel_gpio_irq_mask()
214 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; in atmel_gpio_irq_unmask() local
[all …]
Dpinctrl-st.c253 int pin; member
305 #define ST_IRQ_RISING_EDGE_CONF(pin) \ argument
306 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
308 #define ST_IRQ_FALLING_EDGE_CONF(pin) \ argument
309 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
311 #define ST_IRQ_BOTH_EDGE_CONF(pin) \ argument
312 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
314 #define ST_IRQ_EDGE_CONF(conf, pin) \ argument
315 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
404 struct pinctrl_dev *pctldev, int pin) in st_get_pio_control() argument
[all …]
Dpinmux.c84 int pin, const char *owner, in pin_request()
91 desc = pin_desc_get(pctldev, pin); in pin_request()
95 pin); in pin_request()
100 pin, desc->name, owner); in pin_request()
144 pin); in pin_request()
155 status = ops->gpio_request_enable(pctldev, gpio_range, pin); in pin_request()
157 status = ops->request(pctldev, pin); in pin_request()
162 dev_err(pctldev->dev, "request() failed for pin %d\n", pin); in pin_request()
179 pin, owner, status); in pin_request()
195 static const char *pin_free(struct pinctrl_dev *pctldev, int pin, in pin_free() argument
[all …]
Dpinctrl-tz1090.c897 const unsigned int *pin; in tz1090_init_mux_pins() local
905 for (pin = grp->pins, p = 0; p < grp->npins; ++p, ++pin) in tz1090_init_mux_pins()
906 tz1090_mux_pins[*pin] = g; in tz1090_init_mux_pins()
999 unsigned int pin = group - ARRAY_SIZE(tz1090_groups); in tz1090_pinctrl_get_group_name() local
1000 return tz1090_pins[pin].name; in tz1090_pinctrl_get_group_name()
1015 unsigned int pin = group - ARRAY_SIZE(tz1090_groups); in tz1090_pinctrl_get_group_pins() local
1016 *pins = &tz1090_pins[pin].number; in tz1090_pinctrl_get_group_pins()
1247 unsigned int pin) in tz1090_pinctrl_select() argument
1254 pmx_index = pin >> 5; in tz1090_pinctrl_select()
1255 pmx_shift = pin & 0x1f; in tz1090_pinctrl_select()
[all …]
Dpinmux.h21 unsigned pin, unsigned gpio);
22 void pinmux_free_gpio(struct pinctrl_dev *pctldev, unsigned pin,
26 unsigned pin, bool input);
48 unsigned pin, unsigned gpio) in pinmux_request_gpio() argument
54 unsigned pin, in pinmux_free_gpio() argument
61 unsigned pin, bool input) in pinmux_gpio_direction() argument
Dpinconf.c58 int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin, in pin_config_get_for_pin() argument
69 return ops->pin_config_get(pctldev, pin, config); in pin_config_get_for_pin()
114 int pin; in pinconf_map_to_setting() local
118 pin = pin_get_from_name(pctldev, in pinconf_map_to_setting()
120 if (pin < 0) { in pinconf_map_to_setting()
123 return pin; in pinconf_map_to_setting()
125 setting->data.configs.group_or_pin = pin; in pinconf_map_to_setting()
128 pin = pinctrl_get_group_selector(pctldev, in pinconf_map_to_setting()
130 if (pin < 0) { in pinconf_map_to_setting()
133 return pin; in pinconf_map_to_setting()
[all …]
/linux-4.4.14/arch/x86/kernel/apic/
Dio_apic.c71 #define for_each_pin(idx, pin) \ argument
72 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
73 #define for_each_ioapic_pin(idx, pin) \ argument
75 for_each_pin((idx), (pin))
86 int apic, pin; member
145 static inline u32 mp_pin_to_gsi(int ioapic, int pin) in mp_pin_to_gsi() argument
147 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; in mp_pin_to_gsi()
305 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) in __ioapic_read_entry() argument
309 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); in __ioapic_read_entry()
310 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); in __ioapic_read_entry()
[all …]
/linux-4.4.14/drivers/pinctrl/uniphier/
Dpinctrl-uniphier-core.c66 const struct pinctrl_pin_desc *pin = &pctldev->desc->pins[offset]; in uniphier_pctl_pin_dbg_show() local
69 switch (uniphier_pin_get_pull_dir(pin->drv_data)) { in uniphier_pctl_pin_dbg_show()
83 switch (uniphier_pin_get_drv_str(pin->drv_data)) { in uniphier_pctl_pin_dbg_show()
122 const struct pinctrl_pin_desc *pin, in uniphier_conf_pin_bias_get() argument
127 uniphier_pin_get_pull_dir(pin->drv_data); in uniphier_conf_pin_bias_get()
157 pupdctrl = uniphier_pin_get_pupdctrl(pin->drv_data); in uniphier_conf_pin_bias_get()
172 const struct pinctrl_pin_desc *pin, in uniphier_conf_pin_drive_get() argument
177 uniphier_pin_get_drv_str(pin->drv_data); in uniphier_conf_pin_drive_get()
207 drvctrl = uniphier_pin_get_drvctrl(pin->drv_data); in uniphier_conf_pin_drive_get()
227 const struct pinctrl_pin_desc *pin) in uniphier_conf_pin_input_enable_get() argument
[all …]
/linux-4.4.14/Documentation/video4linux/
Dlifeview.txt16 /* GP27 MDT2005 PB4 pin 10 */
17 /* GP26 MDT2005 PB3 pin 9 */
18 /* GP25 MDT2005 PB2 pin 8 */
19 /* GP23 MDT2005 PB1 pin 7 */
20 /* GP22 MDT2005 PB0 pin 6 */
21 /* GP21 MDT2005 PB5 pin 11 */
22 /* GP20 MDT2005 PB6 pin 12 */
23 /* GP19 MDT2005 PB7 pin 13 */
24 /* nc MDT2005 PA3 pin 2 */
25 /* Remote MDT2005 PA2 pin 1 */
[all …]
/linux-4.4.14/fs/
Dfs_pin.c9 void pin_remove(struct fs_pin *pin) in pin_remove() argument
12 hlist_del_init(&pin->m_list); in pin_remove()
13 hlist_del_init(&pin->s_list); in pin_remove()
15 spin_lock_irq(&pin->wait.lock); in pin_remove()
16 pin->done = 1; in pin_remove()
17 wake_up_locked(&pin->wait); in pin_remove()
18 spin_unlock_irq(&pin->wait.lock); in pin_remove()
21 void pin_insert_group(struct fs_pin *pin, struct vfsmount *m, struct hlist_head *p) in pin_insert_group() argument
25 hlist_add_head(&pin->s_list, p); in pin_insert_group()
26 hlist_add_head(&pin->m_list, &real_mount(m)->mnt_pins); in pin_insert_group()
[all …]
/linux-4.4.14/drivers/pinctrl/meson/
Dpinctrl-meson.c76 static int meson_get_bank(struct meson_domain *domain, unsigned int pin, in meson_get_bank() argument
82 if (pin >= domain->data->banks[i].first && in meson_get_bank()
83 pin <= domain->data->banks[i].last) { in meson_get_bank()
102 static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin, in meson_get_domain_and_bank() argument
111 if (pin >= d->data->pin_base && in meson_get_domain_and_bank()
112 pin < d->data->pin_base + d->data->num_pins) { in meson_get_domain_and_bank()
114 return meson_get_bank(d, pin, bank); in meson_get_domain_and_bank()
130 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, in meson_calc_reg_and_bit() argument
137 *bit = desc->bit + pin - bank->first; in meson_calc_reg_and_bit()
193 unsigned int pin, int sel_group) in meson_pmx_disable_other_groups() argument
[all …]
/linux-4.4.14/drivers/input/misc/
Dixp4xx-beeper.c33 static void ixp4xx_spkr_control(unsigned int pin, unsigned int count) in ixp4xx_spkr_control() argument
40 gpio_direction_output(pin, 0); in ixp4xx_spkr_control()
43 gpio_direction_output(pin, 1); in ixp4xx_spkr_control()
44 gpio_direction_input(pin); in ixp4xx_spkr_control()
53 unsigned int pin = (unsigned int) input_get_drvdata(dev); in ixp4xx_spkr_event() local
72 ixp4xx_spkr_control(pin, count); in ixp4xx_spkr_event()
79 unsigned int pin = (unsigned int) dev_id; in ixp4xx_spkr_interrupt() local
85 gpio_set_value(pin, !gpio_get_value(pin)); in ixp4xx_spkr_interrupt()
144 unsigned int pin = (unsigned int) input_get_drvdata(input_dev); in ixp4xx_spkr_remove() local
150 ixp4xx_spkr_control(pin, 0); in ixp4xx_spkr_remove()
[all …]
/linux-4.4.14/sound/pci/lola/
Dlola_mixer.c31 static int lola_init_pin(struct lola *chip, struct lola_pin *pin, in lola_init_pin() argument
37 pin->nid = nid; in lola_init_pin()
45 pin->is_analog = false; in lola_init_pin()
47 pin->is_analog = true; in lola_init_pin()
49 pin->is_analog = true; in lola_init_pin()
57 if (!pin->is_analog) in lola_init_pin()
69 pin->amp_mute = LOLA_AMP_MUTE_CAPABLE(val); in lola_init_pin()
70 pin->amp_step_size = LOLA_AMP_STEP_SIZE(val); in lola_init_pin()
71 pin->amp_num_steps = LOLA_AMP_NUM_STEPS(val); in lola_init_pin()
72 if (pin->amp_num_steps) { in lola_init_pin()
[all …]
/linux-4.4.14/arch/powerpc/sysdev/qe_lib/
Dqe_io.c52 void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir, in __par_io_config_pin() argument
61 pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1))); in __par_io_config_pin()
71 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? in __par_io_config_pin()
77 (pin % (QE_PIO_PINS / 2) + 1) * 2)); in __par_io_config_pin()
81 (pin % (QE_PIO_PINS / 2) + 1) * 2)); in __par_io_config_pin()
84 if (pin > (QE_PIO_PINS / 2) - 1) { in __par_io_config_pin()
96 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? in __par_io_config_pin()
101 (pin % (QE_PIO_PINS / 2) + 1) * 2)); in __par_io_config_pin()
103 if (pin > (QE_PIO_PINS / 2) - 1) { in __par_io_config_pin()
117 int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, in par_io_config_pin() argument
[all …]
/linux-4.4.14/drivers/pinctrl/vt8500/
DKconfig13 bool "VIA VT8500 pin controller driver"
17 Say yes here to support the gpio/pin control module on
21 bool "Wondermedia WM8505 pin controller driver"
25 Say yes here to support the gpio/pin control module on
29 bool "Wondermedia WM8650 pin controller driver"
33 Say yes here to support the gpio/pin control module on
37 bool "Wondermedia WM8750 pin controller driver"
41 Say yes here to support the gpio/pin control module on
45 bool "Wondermedia WM8850 pin controller driver"
49 Say yes here to support the gpio/pin control module on
Dpinctrl-wmt.c94 unsigned pin) in wmt_set_pinmux() argument
96 u32 bank = WMT_BANK_FROM_PIN(pin); in wmt_set_pinmux()
97 u32 bit = WMT_BIT_FROM_PIN(pin); in wmt_set_pinmux()
103 pin); in wmt_set_pinmux()
125 pin); in wmt_set_pinmux()
204 static int wmt_pctl_find_group_by_pin(struct wmt_pinctrl_data *data, u32 pin) in wmt_pctl_find_group_by_pin() argument
209 if (data->pins[i].number == pin) in wmt_pctl_find_group_by_pin()
218 u32 pin, u32 fnum, in wmt_pctl_dt_node_to_map_func() argument
229 group = wmt_pctl_find_group_by_pin(data, pin); in wmt_pctl_dt_node_to_map_func()
231 dev_err(data->dev, "unable to match pin %d to group\n", pin); in wmt_pctl_dt_node_to_map_func()
[all …]
/linux-4.4.14/drivers/input/mouse/
Dgpio_mouse.c53 int pin, i; in gpio_mouse_probe() local
69 pin = pdata->pins[i]; in gpio_mouse_probe()
71 if (pin < 0) { in gpio_mouse_probe()
85 error = gpio_request(pin, "gpio_mouse"); in gpio_mouse_probe()
88 pin, i); in gpio_mouse_probe()
92 gpio_direction_input(pin); in gpio_mouse_probe()
143 pin = pdata->pins[i]; in gpio_mouse_probe()
144 if (pin) in gpio_mouse_probe()
145 gpio_free(pin); in gpio_mouse_probe()
155 int pin, i; in gpio_mouse_remove() local
[all …]
/linux-4.4.14/drivers/media/usb/dvb-usb-v2/
Dmxl111sf-gpio.c35 static int mxl111sf_set_gpo_state(struct mxl111sf_state *state, u8 pin, u8 val) in mxl111sf_set_gpo_state() argument
40 mxl_debug_adv("(%d, %d)", pin, val); in mxl111sf_set_gpo_state()
42 if ((pin > 0) && (pin < 8)) { in mxl111sf_set_gpo_state()
46 tmp &= ~(1 << (pin - 1)); in mxl111sf_set_gpo_state()
47 tmp |= (val << (pin - 1)); in mxl111sf_set_gpo_state()
51 } else if (pin <= 10) { in mxl111sf_set_gpo_state()
52 if (pin == 0) in mxl111sf_set_gpo_state()
53 pin += 7; in mxl111sf_set_gpo_state()
57 tmp &= ~(1 << (pin - 3)); in mxl111sf_set_gpo_state()
58 tmp |= (val << (pin - 3)); in mxl111sf_set_gpo_state()
[all …]
/linux-4.4.14/drivers/pinctrl/intel/
Dpinctrl-intel.c110 unsigned pin) in intel_get_community() argument
117 if (pin >= community->pin_base && in intel_get_community()
118 pin < community->pin_base + community->npins) in intel_get_community()
122 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); in intel_get_community()
126 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, in intel_get_padcfg() argument
132 community = intel_get_community(pctrl, pin); in intel_get_padcfg()
136 padno = pin_to_padno(community, pin); in intel_get_padcfg()
140 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) in intel_pad_owned_by_host() argument
146 community = intel_get_community(pctrl, pin); in intel_pad_owned_by_host()
152 padno = pin_to_padno(community, pin); in intel_pad_owned_by_host()
[all …]
Dpinctrl-cherryview.c78 unsigned pin; member
188 .pin = (p), \
806 int pin = grp->pins[i]; in chv_pinmux_set_mux() local
815 if (grp->overrides[j].pin == pin) { in chv_pinmux_set_mux()
822 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); in chv_pinmux_set_mux()
832 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); in chv_pinmux_set_mux()
839 pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); in chv_pinmux_set_mux()
958 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, in chv_config_get() argument
969 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); in chv_config_get()
970 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); in chv_config_get()
[all …]
/linux-4.4.14/sound/soc/omap/
Dams-delta.c105 int pin, changed = 0; in ams_delta_set_audio_mode() local
120 pin = !!(pins & (1 << AMS_DELTA_MOUTHPIECE)); in ams_delta_set_audio_mode()
122 if (pin != snd_soc_dapm_get_pin_status(dapm, "Mouthpiece")) { in ams_delta_set_audio_mode()
124 if (pin) in ams_delta_set_audio_mode()
129 pin = !!(pins & (1 << AMS_DELTA_EARPIECE)); in ams_delta_set_audio_mode()
130 if (pin != snd_soc_dapm_get_pin_status(dapm, "Earpiece")) { in ams_delta_set_audio_mode()
132 if (pin) in ams_delta_set_audio_mode()
137 pin = !!(pins & (1 << AMS_DELTA_MICROPHONE)); in ams_delta_set_audio_mode()
138 if (pin != snd_soc_dapm_get_pin_status(dapm, "Microphone")) { in ams_delta_set_audio_mode()
140 if (pin) in ams_delta_set_audio_mode()
[all …]
/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_i2c.c73 unsigned int pin) in get_gmbus_pin() argument
76 return &gmbus_pins_bxt[pin]; in get_gmbus_pin()
78 return &gmbus_pins_skl[pin]; in get_gmbus_pin()
80 return &gmbus_pins_bdw[pin]; in get_gmbus_pin()
82 return &gmbus_pins[pin]; in get_gmbus_pin()
86 unsigned int pin) in intel_gmbus_is_valid_pin() argument
99 return pin < size && get_gmbus_pin(dev_priv, pin)->reg; in intel_gmbus_is_valid_pin()
236 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) in intel_gpio_setup() argument
244 get_gmbus_pin(dev_priv, pin)->reg; in intel_gpio_setup()
626 unsigned int pin; in intel_setup_gmbus() local
[all …]
Dintel_hotplug.c79 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port) in intel_hpd_pin_to_port() argument
81 switch (pin) { in intel_hpd_pin_to_port()
122 enum hpd_pin pin) in intel_hpd_irq_storm_detect() argument
124 unsigned long start = dev_priv->hotplug.stats[pin].last_jiffies; in intel_hpd_irq_storm_detect()
129 dev_priv->hotplug.stats[pin].last_jiffies = jiffies; in intel_hpd_irq_storm_detect()
130 dev_priv->hotplug.stats[pin].count = 0; in intel_hpd_irq_storm_detect()
131 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", pin); in intel_hpd_irq_storm_detect()
132 } else if (dev_priv->hotplug.stats[pin].count > HPD_STORM_THRESHOLD) { in intel_hpd_irq_storm_detect()
133 dev_priv->hotplug.stats[pin].state = HPD_MARK_DISABLED; in intel_hpd_irq_storm_detect()
134 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", pin); in intel_hpd_irq_storm_detect()
[all …]
/linux-4.4.14/drivers/pinctrl/freescale/
Dpinctrl-imx.c155 pin_get_name(pctldev, grp->pins[i].pin); in imx_dt_node_to_map()
205 struct imx_pin *pin = &grp->pins[i]; in imx_pmx_set() local
206 pin_id = pin->pin; in imx_pmx_set()
219 reg |= (pin->mux_mode << 20); in imx_pmx_set()
222 writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); in imx_pmx_set()
225 pin_reg->mux_reg, pin->mux_mode); in imx_pmx_set()
240 if (pin->input_val >> 24 == 0xff) { in imx_pmx_set()
241 u32 val = pin->input_val; in imx_pmx_set()
250 val = readl(ipctl->base + pin->input_reg); in imx_pmx_set()
253 writel(val, ipctl->base + pin->input_reg); in imx_pmx_set()
[all …]
Dpinctrl-mxs.h22 #define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) argument
23 #define PINID(bank, pin) ((bank) * 32 + (pin)) argument
Dpinctrl-imx.h30 unsigned int pin; member
93 #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) argument
/linux-4.4.14/drivers/pci/
Dsetup-irq.c29 u8 pin, slot; in pdev_fixup_irq() local
38 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); in pdev_fixup_irq()
40 if (pin > 4) in pdev_fixup_irq()
41 pin = 1; in pdev_fixup_irq()
43 if (pin != 0) { in pdev_fixup_irq()
45 slot = (*swizzle)(dev, &pin); in pdev_fixup_irq()
47 irq = (*map_irq)(dev, slot, pin); in pdev_fixup_irq()
/linux-4.4.14/drivers/pinctrl/nomadik/
DKconfig11 bool "AB8500 pin controller driver"
15 bool "AB8540 pin controller driver"
19 bool "AB9540 pin controller driver"
23 bool "AB8505 pin controller driver"
31 bool "Nomadik pin controller driver"
40 bool "STN8815 pin controller driver"
44 bool "DB8500 pin controller driver"
48 bool "DB8540 pin controller driver"
/linux-4.4.14/Documentation/
Dpinctrl.txt2 This document outlines the pin control subsystem in Linux
19 - A pin controller is a piece of hardware, usually a set of registers, that
28 there may be several such number spaces in a system. This pin space may
30 pin exists.
33 pin control framework, and this descriptor contains an array of pin descriptors
34 describing the pins handled by this specific pin controller.
56 To register a pin controller and name all the pins on this package we can do
84 pr_err("could not register foo pin driver\n");
100 the pin controller.
118 Many controllers need to deal with groups of pins, so the pin controller
[all …]
Dbt8xxgpio.txt26 GPIO pin and solder that to some tiny wire. As the chip package really is tiny
38 --| pin 86 pin 67 |--
40 --| pin 61 > |-- G18
45 --| pin 56 > |-- G23
66 This is pin 1
/linux-4.4.14/arch/mips/pnx833x/common/
Dinterrupts.c114 int pin; in pic_dispatch() local
115 while ((pin = ffs(mask & 0xffff))) { in pic_dispatch()
116 pin -= 1; in pic_dispatch()
117 do_IRQ(PNX833X_GPIO_IRQ_BASE + pin); in pic_dispatch()
118 mask &= ~(1 << pin); in pic_dispatch()
193 int pin = d->irq - PNX833X_GPIO_IRQ_BASE; in pnx833x_enable_gpio_irq() local
196 pnx833x_gpio_enable_irq(pin); in pnx833x_enable_gpio_irq()
202 int pin = d->irq - PNX833X_GPIO_IRQ_BASE; in pnx833x_disable_gpio_irq() local
205 pnx833x_gpio_disable_irq(pin); in pnx833x_disable_gpio_irq()
211 int pin = d->irq - PNX833X_GPIO_IRQ_BASE; in pnx833x_set_type_gpio_irq() local
[all …]
/linux-4.4.14/arch/mips/sgi-ip27/
Dip27-irq-pci.c140 int pin, swlevel; in startup_bridge_irq() local
143 pin = SLOT_FROM_PCI_IRQ(d->irq); in startup_bridge_irq()
147 pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin); in startup_bridge_irq()
153 bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8)); in startup_bridge_irq()
154 bridge->b_int_enable |= (1 << pin); in startup_bridge_irq()
164 bridge->b_int_mode |= (1UL << pin); in startup_bridge_irq()
171 device &= ~(7 << (pin*3)); in startup_bridge_irq()
172 device |= (pin << (pin*3)); in startup_bridge_irq()
187 int pin, swlevel; in shutdown_bridge_irq() local
191 pin = SLOT_FROM_PCI_IRQ(d->irq); in shutdown_bridge_irq()
[all …]
/linux-4.4.14/drivers/of/
Dof_pci_irq.c22 u8 pin; in of_irq_parse_pci() local
39 rc = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin); in of_irq_parse_pci()
43 if (pin == 0) in of_irq_parse_pci()
82 pin = pci_swizzle_interrupt_pin(pdev, pin); in of_irq_parse_pci()
88 out_irq->args[0] = pin; in of_irq_parse_pci()
110 int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin) in of_irq_parse_and_map_pci() argument
/linux-4.4.14/arch/arm/mach-ixp4xx/
Dgtwx5715-pci.c52 static int __init gtwx5715_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in gtwx5715_map_irq() argument
56 if ((slot == SLOT0_DEVID && pin == 1) || in gtwx5715_map_irq()
57 (slot == SLOT1_DEVID && pin == 2)) in gtwx5715_map_irq()
59 else if ((slot == SLOT0_DEVID && pin == 2) || in gtwx5715_map_irq()
60 (slot == SLOT1_DEVID && pin == 1)) in gtwx5715_map_irq()
64 __func__, slot, pin, rc); in gtwx5715_map_irq()
Dnslu2-pci.c41 static int __init nslu2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in nslu2_map_irq() argument
49 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) in nslu2_map_irq()
50 return pci_irq_table[(slot + pin - 2) % IRQ_LINES]; in nslu2_map_irq()
Dmiccpt-pci.c47 static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in miccpt_map_irq() argument
56 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) in miccpt_map_irq()
57 return pci_irq_table[(slot + pin - 2) % 4]; in miccpt_map_irq()
Dfsg-pci.c41 static int __init fsg_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in fsg_map_irq() argument
52 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) in fsg_map_irq()
55 __func__, slot, pin, irq); in fsg_map_irq()
Dixdp425-pci.c46 static int __init ixdp425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in ixdp425_map_irq() argument
55 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) in ixdp425_map_irq()
56 return pci_irq_table[(slot + pin - 2) % 4]; in ixdp425_map_irq()
Davila-pci.c49 static int __init avila_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in avila_map_irq() argument
60 pin >= 1 && pin <= IRQ_LINES) in avila_map_irq()
61 return pci_irq_table[(slot + pin - 2) % 4]; in avila_map_irq()
Dnas100d-pci.c44 static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in nas100d_map_irq() argument
53 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) in nas100d_map_irq()
54 return pci_irq_table[slot - 1][pin - 1]; in nas100d_map_irq()
Ddsmg600-pci.c47 static int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in dsmg600_map_irq() argument
57 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) in dsmg600_map_irq()
58 return pci_irq_table[slot - 1][pin - 1]; in dsmg600_map_irq()
/linux-4.4.14/Documentation/spi/
Dbutterfly32 SCK = J403.PB1/SCK = pin 2/D0
33 RESET = J403.nRST = pin 3/D1
34 VCC = J403.VCC_EXT = pin 8/D6
35 MOSI = J403.PB2/MOSI = pin 9/D7
36 MISO = J403.PB3/MISO = pin 11/S7,nBUSY
37 GND = J403.GND = pin 23/GND
46 VCC = J400.VCC_EXT = pin 7/D5
47 SELECT = J400.PB0/nSS = pin 17/C3,nSELECT
48 GND = J400.GND = pin 24/GND
61 SCK = J403.PE4/USCK = pin 5/D3
[all …]
/linux-4.4.14/arch/arm/plat-pxa/
Dmfp.c174 int pin, af, drv, lpm, edge, pull; in mfp_config() local
176 pin = MFP_PIN(c); in mfp_config()
177 BUG_ON(pin >= MFP_PIN_MAX); in mfp_config()
178 p = &mfp_table[pin]; in mfp_config()
272 int pin; in mfp_config_lpm() local
274 for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++) in mfp_config_lpm()
281 int pin; in mfp_config_run() local
283 for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++) in mfp_config_run()
/linux-4.4.14/drivers/pwm/
Dpwm-bfin.c22 unsigned short pin; member
42 priv->pin = pwm_to_gptimer_per[pwm->hwpwm]; in bfin_pwm_request()
44 ret = peripheral_request(priv->pin, NULL); in bfin_pwm_request()
60 peripheral_free(priv->pin); in bfin_pwm_free()
83 set_gptimer_config(priv->pin, TIMER_MODE_PWM | TIMER_PERIOD_CNT); in bfin_pwm_config()
84 set_gptimer_pwidth(priv->pin, duty); in bfin_pwm_config()
85 set_gptimer_period(priv->pin, period); in bfin_pwm_config()
94 enable_gptimer(priv->pin); in bfin_pwm_enable()
103 disable_gptimer(priv->pin); in bfin_pwm_disable()
/linux-4.4.14/arch/powerpc/sysdev/
Dcpm1.c306 static void cpm1_set_pin32(int port, int pin, int flags) in cpm1_set_pin32() argument
309 pin = 1 << (31 - pin); in cpm1_set_pin32()
319 setbits32(&iop->dir, pin); in cpm1_set_pin32()
321 clrbits32(&iop->dir, pin); in cpm1_set_pin32()
324 setbits32(&iop->par, pin); in cpm1_set_pin32()
326 clrbits32(&iop->par, pin); in cpm1_set_pin32()
330 setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); in cpm1_set_pin32()
332 clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); in cpm1_set_pin32()
337 setbits32(&iop->sor, pin); in cpm1_set_pin32()
339 clrbits32(&iop->sor, pin); in cpm1_set_pin32()
[all …]
Dcpm2.c334 void cpm2_set_pin(int port, int pin, int flags) in cpm2_set_pin() argument
339 pin = 1 << (31 - pin); in cpm2_set_pin()
342 setbits32(&iop[port].dir, pin); in cpm2_set_pin()
344 clrbits32(&iop[port].dir, pin); in cpm2_set_pin()
347 setbits32(&iop[port].par, pin); in cpm2_set_pin()
349 clrbits32(&iop[port].par, pin); in cpm2_set_pin()
352 setbits32(&iop[port].sor, pin); in cpm2_set_pin()
354 clrbits32(&iop[port].sor, pin); in cpm2_set_pin()
357 setbits32(&iop[port].odr, pin); in cpm2_set_pin()
359 clrbits32(&iop[port].odr, pin); in cpm2_set_pin()
/linux-4.4.14/arch/arm/plat-samsung/include/plat/
Dgpio-cfg.h99 extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
110 extern unsigned s3c_gpio_getcfg(unsigned int pin);
147 extern int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull);
155 extern samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
176 static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size, in s3c_gpio_cfgrange_nopull() argument
179 return s3c_gpio_cfgall_range(pin, size, cfg, S3C_GPIO_PULL_NONE); in s3c_gpio_cfgrange_nopull()
Dgpio-core.h114 static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin) in samsung_gpiolib_getchip() argument
118 if (pin > S3C_GPIO_END) in samsung_gpiolib_getchip()
121 chip = &s3c24xx_gpios[pin/32]; in samsung_gpiolib_getchip()
122 return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL; in samsung_gpiolib_getchip()
/linux-4.4.14/Documentation/input/
Djoystick-parport.txt52 some data pin. For most gamepad and parport implementations only one pin is
53 needed, and I'd recommend pin 9 for that, the highest data bit. On the other
55 port, anything between and including pin 4 and pin 9 will work.
57 (pin 9) -----> Power
65 (pin 9) ----|>|-------+------> Power
67 (pin 8) ----|>|-------+
69 (pin 7) ----|>|-------+
73 (pin 4) ----|>|-------+
76 pins from pin 18 to pin 25. So use any pin of these you like for the ground.
78 (pin 18) -----> Ground
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/net/ieee802154/
Dcc2520.txt8 - pinctrl-0: pin control group to be used for this controller.
10 - fifo-gpio: GPIO spec for the FIFO pin
11 - fifop-gpio: GPIO spec for the FIFOP pin
12 - sfd-gpio: GPIO spec for the SFD pin
13 - cca-gpio: GPIO spec for the CCA pin
14 - vreg-gpio: GPIO spec for the VREG pin
15 - reset-gpio: GPIO spec for the RESET pin
/linux-4.4.14/drivers/w1/masters/
Dw1-gpio.c34 gpio_direction_output(pdata->pin, 1); in w1_gpio_set_pullup()
38 gpio_direction_input(pdata->pin); in w1_gpio_set_pullup()
51 gpio_direction_input(pdata->pin); in w1_gpio_write_bit_dir()
53 gpio_direction_output(pdata->pin, 0); in w1_gpio_write_bit_dir()
60 gpio_set_value(pdata->pin, bit); in w1_gpio_write_bit_val()
67 return gpio_get_value(pdata->pin) ? 1 : 0; in w1_gpio_read_bit()
100 pdata->pin = gpio; in w1_gpio_probe_dt()
139 err = devm_gpio_request(&pdev->dev, pdata->pin, "w1"); in w1_gpio_probe()
160 gpio_direction_output(pdata->pin, 1); in w1_gpio_probe()
163 gpio_direction_input(pdata->pin); in w1_gpio_probe()
/linux-4.4.14/Documentation/arm/pxa/
Dmfp.txt5 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
13 mechanism is introduced from PXA3xx to completely move the pin-mux functions
14 out of the GPIO controller. In addition to pin-mux configurations, the MFP
16 detection of each pin. Below is a diagram of internal connections between
42 mean it's dedicated for GPIO19, only as a hint that internally this pin
61 3. Low power state for each pin is now controlled by MFP, this means the
69 mean it is a GPIO signal, and by MFP<xxx> or pin xxx, we mean a physical
86 because pin configuration definitions may conflict in these file (i.e.
93 NOTE: PXA300 and PXA310 are almost identical in pin configurations (with
97 2. prepare an array for the initial pin configurations, e.g.:
[all …]
/linux-4.4.14/drivers/pinctrl/spear/
Dpinctrl-plgpio.c25 #define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG) argument
26 #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \ argument
70 int (*p2o)(int pin); /* pin_to_offset */
80 static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg) in is_plgpio_set() argument
82 u32 offset = PIN_OFFSET(pin); in is_plgpio_set()
83 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in is_plgpio_set()
89 static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg) in plgpio_reg_set() argument
91 u32 offset = PIN_OFFSET(pin); in plgpio_reg_set()
92 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_set()
98 static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg) in plgpio_reg_reset() argument
[all …]
DKconfig12 This enables pin control drivers for SPEAr Platform
20 bool "ST Microelectronics SPEAr300 SoC pin controller driver"
25 bool "ST Microelectronics SPEAr310 SoC pin controller driver"
31 bool "ST Microelectronics SPEAr320 SoC pin controller driver"
37 bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
43 bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
/linux-4.4.14/arch/mips/ath79/
Dpci.c31 .pin = 1,
35 .pin = 1,
39 .pin = 1,
47 .pin = 1,
56 .pin = 1,
62 .pin = 1,
67 int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) in pcibios_map_irq() argument
98 entry->pin == pin) { in pcibios_map_irq()
106 pci_name((struct pci_dev *) dev), pin); in pcibios_map_irq()
109 pci_name((struct pci_dev *) dev), irq, pin); in pcibios_map_irq()
/linux-4.4.14/include/linux/pinctrl/
Dmachine.h109 #define PIN_MAP_CONFIGS_PIN(dev, state, pinctrl, pin, cfgs) \ argument
116 .group_or_pin = pin, \
122 #define PIN_MAP_CONFIGS_PIN_DEFAULT(dev, pinctrl, pin, cfgs) \ argument
123 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_DEFAULT, pinctrl, pin, cfgs)
125 #define PIN_MAP_CONFIGS_PIN_HOG(dev, state, pin, cfgs) \ argument
126 PIN_MAP_CONFIGS_PIN(dev, state, dev, pin, cfgs)
128 #define PIN_MAP_CONFIGS_PIN_HOG_DEFAULT(dev, pin, cfgs) \ argument
129 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_DEFAULT, dev, pin, cfgs)
/linux-4.4.14/arch/powerpc/platforms/8xx/
Dtqm8xx_setup.c48 int port, pin, flags; member
83 static void __init init_pins(int n, struct cpm_pin *pin) in init_pins() argument
88 cpm1_set_pin(pin->port, pin->pin, pin->flags); in init_pins()
89 pin++; in init_pins()
Dadder875.c26 int port, pin, flags; member
73 const struct cpm_pin *pin = &adder875_pins[i]; in init_ioports() local
74 cpm1_set_pin(pin->port, pin->pin, pin->flags); in init_ioports()
Dmpc86xads_setup.c34 int port, pin, flags; member
80 struct cpm_pin *pin = &mpc866ads_pins[i]; in init_ioports() local
81 cpm1_set_pin(pin->port, pin->pin, pin->flags); in init_ioports()
Dep88xc.c25 int port, pin, flags; member
93 struct cpm_pin *pin = &ep88xc_pins[i]; in init_ioports() local
94 cpm1_set_pin(pin->port, pin->pin, pin->flags); in init_ioports()
Dmpc885ads_setup.c49 int port, pin, flags; member
116 struct cpm_pin *pin = &mpc885ads_pins[i]; in init_ioports() local
117 cpm1_set_pin(pin->port, pin->pin, pin->flags); in init_ioports()
/linux-4.4.14/drivers/pinctrl/samsung/
Dpinctrl-exynos5440.c386 static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, in exynos5440_pinconf_set() argument
408 data &= ~(1 << pin); in exynos5440_pinconf_set()
410 data |= (1 << pin); in exynos5440_pinconf_set()
415 data &= ~(1 << pin); in exynos5440_pinconf_set()
417 data |= (1 << pin); in exynos5440_pinconf_set()
424 data &= ~(1 << pin); in exynos5440_pinconf_set()
425 data |= ((cfg_value & 1) << pin); in exynos5440_pinconf_set()
431 data &= ~(1 << pin); in exynos5440_pinconf_set()
432 data |= ((cfg_value & 1) << pin); in exynos5440_pinconf_set()
437 data &= ~(1 << pin); in exynos5440_pinconf_set()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/
Dnetwork.txt30 fsl,mdio-pin : pin of port C controlling mdio data
31 fsl,mdc-pin : pin of port C controlling mdio clock
41 fsl,mdio-pin = <12>;
42 fsl,mdc-pin = <13>;
/linux-4.4.14/drivers/char/
Dtb0219.c100 static inline char get_gpio_input_pin(unsigned int pin) in get_gpio_input_pin() argument
105 if (values & (1 << pin)) in get_gpio_input_pin()
111 static inline char get_gpio_output_pin(unsigned int pin) in get_gpio_output_pin() argument
116 if (values & (1 << pin)) in get_gpio_output_pin()
122 static inline char get_dip_switch(unsigned int pin) in get_dip_switch() argument
127 if (values & (1 << pin)) in get_dip_switch()
140 static inline int set_gpio_output_pin(unsigned int pin, char command) in set_gpio_output_pin() argument
151 value &= ~(1 << pin); in set_gpio_output_pin()
153 value |= 1 << pin; in set_gpio_output_pin()
/linux-4.4.14/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
23 "ohci-phy-3pin-datse0",
24 "ohci-phy-4pin-dpdm",
25 "ohci-tll-6pin-datse0",
26 "ohci-tll-6pin-dpdm",
27 "ohci-tll-3pin-datse0",
28 "ohci-tll-4pin-dpdm",
29 "ohci-tll-2pin-datse0",
30 "ohci-tll-2pin-dpdm",
/linux-4.4.14/arch/arm/mach-mmp/include/mach/
Dmfp.h28 #define MFP_CFG(pin, af) \ argument
29 (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
31 #define MFP_CFG_DRV(pin, af, drv) \ argument
32 (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
/linux-4.4.14/drivers/pinctrl/sh-pfc/
Dsh_pfc.h34 u16 pin; member
140 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
141 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
143 int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin);
144 int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin,
205 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg) argument
206 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
246 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx argument
252 .pin = (bank * 32) + _pin, \
260 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) argument
[all …]
Dpinctrl.c120 const char *pin; in sh_pfc_dt_subnode_to_map() local
226 of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) { in sh_pfc_dt_subnode_to_map()
227 ret = sh_pfc_map_add_config(&maps[idx], pin, in sh_pfc_dt_subnode_to_map()
399 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; in sh_pfc_gpio_request_enable() local
401 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); in sh_pfc_gpio_request_enable()
439 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; in sh_pfc_gpio_set_direction() local
448 if (pin->configs) { in sh_pfc_gpio_set_direction()
450 if (!(pin->configs & dir)) in sh_pfc_gpio_set_direction()
456 ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); in sh_pfc_gpio_set_direction()
482 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; in sh_pfc_pinconf_validate() local
[all …]
/linux-4.4.14/drivers/pinctrl/bcm/
Dpinctrl-bcm2835.c291 struct bcm2835_pinctrl *pc, unsigned pin) in bcm2835_pinctrl_fsel_get() argument
293 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); in bcm2835_pinctrl_fsel_get()
294 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; in bcm2835_pinctrl_fsel_get()
296 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin, in bcm2835_pinctrl_fsel_get()
303 struct bcm2835_pinctrl *pc, unsigned pin, in bcm2835_pinctrl_fsel_set() argument
306 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); in bcm2835_pinctrl_fsel_set()
307 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; in bcm2835_pinctrl_fsel_set()
309 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin, in bcm2835_pinctrl_fsel_set()
317 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); in bcm2835_pinctrl_fsel_set()
318 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin); in bcm2835_pinctrl_fsel_set()
[all …]
Dpinctrl-bcm281xx.c950 unsigned pin) in pin_type_get() argument
954 if (pin >= pdata->npins) in pin_type_get()
957 return *(enum bcm281xx_pin_type *)(pdata->pins[pin].drv_data); in pin_type_get()
1091 unsigned pin, in bcm281xx_pinctrl_pin_config_get() argument
1100 unsigned pin, in bcm281xx_std_pin_update() argument
1177 arg, pdata->pins[pin].name, pin); in bcm281xx_std_pin_update()
1188 param, pdata->pins[pin].name, pin); in bcm281xx_std_pin_update()
1216 unsigned pin, in bcm281xx_i2c_pin_update() argument
1242 arg, pdata->pins[pin].name, pin); in bcm281xx_i2c_pin_update()
1275 param, pdata->pins[pin].name, pin); in bcm281xx_i2c_pin_update()
[all …]
/linux-4.4.14/drivers/input/keyboard/
Dadp5588-keys.c173 pin_used[kpad->gpimap[i].pin - GPI_PIN_BASE] = true; in adp5588_build_gpiomap()
277 if (key_val == kpad->gpimap[j].pin) { in adp5588_report_events()
351 unsigned short pin = pdata->gpimap[i].pin; in adp5588_setup() local
353 if (pin <= GPI_PIN_ROW_END) { in adp5588_setup()
354 evt_mode1 |= (1 << (pin - GPI_PIN_ROW_BASE)); in adp5588_setup()
356 evt_mode2 |= ((1 << (pin - GPI_PIN_COL_BASE)) & 0xFF); in adp5588_setup()
357 evt_mode3 |= ((1 << (pin - GPI_PIN_COL_BASE)) >> 8); in adp5588_setup()
402 unsigned short pin = kpad->gpimap[i].pin; in adp5588_report_switch_state() local
404 if (pin <= GPI_PIN_ROW_END) { in adp5588_report_switch_state()
406 pin_loc = pin - GPI_PIN_ROW_BASE; in adp5588_report_switch_state()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/mmc/
Dmmci.txt20 - st,sig-dir-dat0 : bus signal direction pin used for DAT[0].
21 - st,sig-dir-dat2 : bus signal direction pin used for DAT[2].
22 - st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1].
23 - st,sig-dir-dat74 : bus signal direction pin used for DAT[4] to DAT[7].
24 - st,sig-dir-cmd : cmd signal direction pin used for CMD.
25 - st,sig-pin-fbclk : feedback clock signal pin used.
53 st,sig-pin-fbclk;
/linux-4.4.14/Documentation/devicetree/bindings/leds/
Dleds-aat1290.txt7 of the flash chip. The switch is controlled with pin control.
12 - flen-gpios : Must be device tree identifier of the flash device FL_EN pin.
13 - enset-gpios : Must be device tree identifier of the flash device EN_SET pin.
17 "default" and "host" must refer to the same pin configuration
19 "isp" must refer to the pin configuration node, which sets the
64 samsung,pin-function = <1>;
65 samsung,pin-val = <0>;
70 samsung,pin-function = <1>;
71 samsung,pin-val = <1>;
/linux-4.4.14/drivers/md/bcache/
Djournal.h84 atomic_t *pin; member
114 DECLARE_FIFO(atomic_t, pin);
157 (fifo_idx(&(c)->journal.pin, (l)) > fifo_idx(&(c)->journal.pin, (r)))
162 (!(j)->blocks_free || fifo_free(&(j)->pin) <= 1)
Djournal.c283 i->pin = NULL; in bch_journal_mark()
286 if (fifo_free(&j->pin) > 1) { in bch_journal_mark()
287 fifo_push_front(&j->pin, p); in bch_journal_mark()
288 atomic_set(&fifo_front(&j->pin), 0); in bch_journal_mark()
291 if (fifo_free(&j->pin) > 1) { in bch_journal_mark()
292 fifo_push_front(&j->pin, p); in bch_journal_mark()
293 i->pin = &fifo_front(&j->pin); in bch_journal_mark()
294 atomic_set(i->pin, 1); in bch_journal_mark()
305 atomic_inc(&PTR_BUCKET(c, k, j)->pin); in bch_journal_mark()
323 BUG_ON(i->pin && atomic_read(i->pin) != 1); in bch_journal_replay()
[all …]
/linux-4.4.14/include/trace/events/
Dkvm.h93 TP_PROTO(__u64 e, int pin, bool coalesced),
94 TP_ARGS(e, pin, coalesced),
98 __field( int, pin )
104 __entry->pin = pin;
109 __entry->pin, (u8)(__entry->e >> 56), (u8)__entry->e,
170 #define kvm_ack_irq_parm __print_symbolic(__entry->irqchip, kvm_irqchips), __entry->pin
173 #define kvm_ack_irq_parm __entry->irqchip, __entry->pin
177 TP_PROTO(unsigned int irqchip, unsigned int pin),
178 TP_ARGS(irqchip, pin),
182 __field( unsigned int, pin )
[all …]
/linux-4.4.14/Documentation/arm/Samsung-S3C24XX/
DGPIO.txt22 of the GPIO functions such as reading and writing a pin will
55 as they have the same arguments, and can either take the pin specific
72 5) s3c2410_gpio_getpin() is replaceable by gpio_get_value() if the pin
74 when using gpio_get_value() on an output pin (s3c2410_gpio_getpin
75 would return the value the pin is supposed to be outputting).
96 Each pin has an unique number associated with it in regs-gpio.h,
98 the GPIO functions which pin is to be used.
101 from gpio pin number to register base address as in earlier kernels. This
106 Configuring a pin
109 The following function allows the configuration of a given pin to
[all …]
/linux-4.4.14/arch/x86/pci/
Dirq.c532 int pin = pci_get_interrupt_pin(dev, &bridge); in pirq_bios_set() local
533 return pcibios_set_irq_routing(bridge, pin - 1, irq); in pirq_bios_set()
881 u8 pin; in pcibios_lookup_irq() local
891 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); in pcibios_lookup_irq()
892 if (!pin) { in pcibios_lookup_irq()
908 'A' + pin - 1); in pcibios_lookup_irq()
911 pirq = info->irq[pin - 1].link; in pcibios_lookup_irq()
912 mask = info->irq[pin - 1].bitmap; in pcibios_lookup_irq()
914 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1); in pcibios_lookup_irq()
918 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs); in pcibios_lookup_irq()
[all …]
/linux-4.4.14/arch/frv/mb93090-mb00/
Dpci-irq.c46 uint8_t line, pin; in pcibios_fixup_irqs() local
49 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); in pcibios_fixup_irqs()
50 if (pin) { in pcibios_fixup_irqs()
51 dev->irq = pci_bus0_irq_routing[PCI_SLOT(dev->devfn)][pin - 1]; in pcibios_fixup_irqs()
/linux-4.4.14/arch/arm/mach-iop33x/
Diq80332.c53 iq80332_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in iq80332_pci_map_irq() argument
57 if (slot == 4 && pin == 1) { in iq80332_pci_map_irq()
60 } else if (slot == 4 && pin == 2) { in iq80332_pci_map_irq()
63 } else if (slot == 4 && pin == 3) { in iq80332_pci_map_irq()
66 } else if (slot == 4 && pin == 4) { in iq80332_pci_map_irq()
Diq80331.c53 iq80331_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in iq80331_pci_map_irq() argument
57 if (slot == 1 && pin == 1) { in iq80331_pci_map_irq()
60 } else if (slot == 1 && pin == 2) { in iq80331_pci_map_irq()
63 } else if (slot == 1 && pin == 3) { in iq80331_pci_map_irq()
66 } else if (slot == 1 && pin == 4) { in iq80331_pci_map_irq()
/linux-4.4.14/Documentation/devicetree/bindings/display/panel/
Dsharp,ls037v7dw01.txt9 - enable-gpios: a GPIO spec for the optional enable pin.
10 This pin is the INI pin as specified in the LS037V7DW01.pdf file.
11 - reset-gpios: a GPIO spec for the optional reset pin.
12 This pin is the RESB pin as specified in the LS037V7DW01.pdf file.
/linux-4.4.14/arch/arm/mach-dove/
Dirq.c26 int pin = irq_to_pmu(d->irq); in pmu_irq_mask() local
30 u &= ~(1 << (pin & 31)); in pmu_irq_mask()
36 int pin = irq_to_pmu(d->irq); in pmu_irq_unmask() local
40 u |= 1 << (pin & 31); in pmu_irq_unmask()
46 int pin = irq_to_pmu(d->irq); in pmu_irq_ack() local
60 u = ~(1 << (pin & 31)); in pmu_irq_ack()
/linux-4.4.14/arch/arm/plat-pxa/include/plat/
Dmfp.h410 #define MFP_CFG(pin, af) \ argument
412 (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
414 #define MFP_CFG_DRV(pin, af, drv) \ argument
416 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
418 #define MFP_CFG_LPM(pin, af, lpm) \ argument
420 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
422 #define MFP_CFG_X(pin, af, drv, lpm) \ argument
424 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
454 #define MFP_ADDR(pin, offset) \ argument
455 { MFP_PIN_##pin, -1, offset }
/linux-4.4.14/arch/mips/pci/
Dfixup-pmcmsp.c205 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in pcibios_map_irq() argument
211 irq_tab[slot][pin], slot, pin); in pcibios_map_irq()
213 return irq_tab[slot][pin]; in pcibios_map_irq()
Dfixup-sni.c133 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in pcibios_map_irq() argument
147 return irq_tab_pcit_cplus[slot][pin]; in pcibios_map_irq()
149 return irq_tab_pcit[slot][pin]; in pcibios_map_irq()
153 return irq_tab_rm300d[slot][pin]; in pcibios_map_irq()
157 return irq_tab_rm200[slot][pin]; in pcibios_map_irq()
160 return irq_tab_rm300e[slot][pin]; in pcibios_map_irq()
Dpci-bcm47xx.c31 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in pcibios_map_irq() argument
40 u8 slot, pin; in bcm47xx_pcibios_plat_dev_init_ssb() local
49 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); in bcm47xx_pcibios_plat_dev_init_ssb()
51 res = ssb_pcibios_map_irq(dev, slot, pin); in bcm47xx_pcibios_plat_dev_init_ssb()
/linux-4.4.14/Documentation/devicetree/bindings/w1/
Dw1-gpio.txt7 - the first one is used as data I/O pin
9 enable pin for an external pin pullup.
13 - linux,open-drain: if specified, the data pin is considered in
/linux-4.4.14/arch/powerpc/platforms/85xx/
Dksi8560.c72 int port, pin, flags; member
111 struct cpm_pin *pin = &ksi8560_pins[i]; in init_ioports() local
112 cpm2_set_pin(pin->port, pin->pin, pin->flags); in init_ioports()
Dmpc85xx_ads.c65 int port, pin, flags; member
123 const struct cpm_pin *pin = &mpc8560_ads_pins[i]; in init_ioports() local
124 cpm2_set_pin(pin->port, pin->pin, pin->flags); in init_ioports()
/linux-4.4.14/Documentation/w1/masters/
Dw1-gpio11 wire and the GPIO pin can be specified using platform data.
20 .pin = AT91_PIN_PB20,
31 at91_set_GPIO_periph(foo_w1_gpio_pdata.pin, 1);
32 at91_set_multi_drive(foo_w1_gpio_pdata.pin, 1);
/linux-4.4.14/sound/soc/
Dsoc-jack.c79 struct snd_soc_jack_pin *pin; in snd_soc_jack_report() local
97 list_for_each_entry(pin, &jack->pins, list) { in snd_soc_jack_report()
98 enable = pin->mask & jack->status; in snd_soc_jack_report()
100 if (pin->invert) in snd_soc_jack_report()
104 snd_soc_dapm_enable_pin(dapm, pin->pin); in snd_soc_jack_report()
106 snd_soc_dapm_disable_pin(dapm, pin->pin); in snd_soc_jack_report()
187 if (!pins[i].pin) { in snd_soc_jack_add_pins()
194 " (%s)\n", i, pins[i].pin); in snd_soc_jack_add_pins()
200 snd_jack_add_new_kctl(jack->jack, pins[i].pin, pins[i].mask); in snd_soc_jack_add_pins()
/linux-4.4.14/arch/arm/mach-pxa/include/mach/
Dmioa701.h4 #define MIO_CFG_IN(pin, af) \ argument
6 (MFP_PIN(pin) | MFP_##af | MFP_DIR_IN))
8 #define MIO_CFG_OUT(pin, af, state) \ argument
10 (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
/linux-4.4.14/drivers/staging/panel/
DKconfig166 int "Parallel port pin number & polarity connected to the LCD E signal (-17...17) "
170 This describes the number of the parallel port pin to which the LCD 'E'
175 -1..-17 : connected to the same pin through an inverter (eg: transistor).
177 Default for the 'E' pin in custom profile is '14' (AUTOFEED).
181 int "Parallel port pin number & polarity connected to the LCD RS signal (-17...17) "
185 This describes the number of the parallel port pin to which the LCD 'RS'
190 -1..-17 : connected to the same pin through an inverter (eg: transistor).
192 Default for the 'RS' pin in custom profile is '17' (SELECT IN).
196 int "Parallel port pin number & polarity connected to the LCD RW signal (-17...17) "
200 This describes the number of the parallel port pin to which the LCD 'RW'
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/display/msm/
Dhdmi.txt16 - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
17 - qcom,hdmi-tx-ddc-data-gpio: ddc data pin
18 - qcom,hdmi-tx-hpd-gpio: hpd pin
23 - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
24 - qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
26 - pinctrl-names: the pin control state names; should contain "default"
/linux-4.4.14/drivers/net/ethernet/intel/igb/
Digb_ptp.c356 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext) in igb_pin_direction() argument
358 u32 *ptr = pin < 2 ? ctrl : ctrl_ext; in igb_pin_direction()
367 *ptr &= ~mask[pin]; in igb_pin_direction()
369 *ptr |= mask[pin]; in igb_pin_direction()
372 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin) in igb_pin_extts() argument
390 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext); in igb_pin_extts()
393 tssdp &= ~ts_sdp_en[pin]; in igb_pin_extts()
397 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN; in igb_pin_extts()
400 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN; in igb_pin_extts()
408 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq) in igb_pin_perout() argument
[all …]
/linux-4.4.14/arch/powerpc/platforms/82xx/
Dpq2fads.c50 int port, pin, flags; member
104 struct cpm_pin *pin = &pq2fads_pins[i]; in init_ioports() local
105 cpm2_set_pin(pin->port, pin->pin, pin->flags); in init_ioports()
Dmpc8272_ads.c53 int port, pin, flags; member
120 struct cpm_pin *pin = &mpc8272_ads_pins[i]; in init_ioports() local
121 cpm2_set_pin(pin->port, pin->pin, pin->flags); in init_ioports()
Dkm82xx.c48 int port, pin, flags; member
143 const struct cpm_pin *pin = &km82xx_pins[i]; in init_ioports() local
144 cpm2_set_pin(pin->port, pin->pin, pin->flags); in init_ioports()
/linux-4.4.14/arch/alpha/kernel/
Dsys_takara.c159 takara_map_irq_srm(const struct pci_dev *dev, u8 slot, u8 pin) in takara_map_irq_srm() argument
190 takara_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in takara_map_irq() argument
217 int pin = *pinp; in takara_swizzle() local
229 if (pin == 1) in takara_swizzle()
230 pin += (20 - busslot); in takara_swizzle()
241 *pinp = pin; in takara_swizzle()
Dsys_ruffian.c121 ruffian_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in ruffian_map_irq() argument
145 int slot, pin = *pinp; in ruffian_swizzle() local
162 pin = pci_swizzle_interrupt_pin(dev, pin); in ruffian_swizzle()
170 *pinp = pin; in ruffian_swizzle()
Dsys_miata.c153 miata_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in miata_map_irq() argument
202 int slot, pin = *pinp; in miata_swizzle() local
221 pin = pci_swizzle_interrupt_pin(dev, pin); in miata_swizzle()
229 *pinp = pin; in miata_swizzle()
/linux-4.4.14/arch/xtensa/lib/
Dpci-auto.c137 u8 pin; in pciauto_setup_irq() local
140 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); in pciauto_setup_irq()
144 if (pin == 0 || pin > 4) in pciauto_setup_irq()
145 pin = 1; in pciauto_setup_irq()
148 irq = pci_ctrl->map_irq(dev, PCI_SLOT(devfn), pin); in pciauto_setup_irq()
153 DBG("PCI Autoconfig: Interrupt %d, pin %d\n", irq, pin); in pciauto_setup_irq()
/linux-4.4.14/arch/avr32/mach-at32ap/include/mach/
Dportmux.h24 void at32_select_periph(unsigned int port, unsigned int pin,
26 void at32_select_gpio(unsigned int pin, unsigned long flags);
27 void at32_deselect_pin(unsigned int pin);
/linux-4.4.14/arch/arm/mach-iop32x/
Diq80321.c71 iq80321_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) in iq80321_pci_map_irq() argument
75 if ((slot == 2 || slot == 6) && pin == 1) { in iq80321_pci_map_irq()
78 } else if ((slot == 2 || slot == 6) && pin == 2) { in iq80321_pci_map_irq()
81 } else if ((slot == 2 || slot == 6) && pin == 3) { in iq80321_pci_map_irq()
84 } else if ((slot == 2 || slot == 6) && pin == 4) { in iq80321_pci_map_irq()
/linux-4.4.14/Documentation/devicetree/bindings/gpio/
Dcavium-octeon-gpio.txt12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
26 - interrupts: Interrupt routing for each pin.
36 * 1) GPIO pin number (0..15)
44 /* The GPIO pin connect to 16 consecutive CUI bits */
/linux-4.4.14/sound/pci/hda/
Dhda_generic.c208 #define update_pin_ctl(codec, pin, val) \ argument
209 snd_hda_codec_update_cache(codec, pin, 0, \
213 static inline void restore_pin_ctl(struct hda_codec *codec, hda_nid_t pin) in restore_pin_ctl() argument
215 update_pin_ctl(codec, pin, snd_hda_codec_get_pin_target(codec, pin)); in restore_pin_ctl()
219 static void set_pin_target(struct hda_codec *codec, hda_nid_t pin, in set_pin_target() argument
222 if (!pin) in set_pin_target()
224 val = snd_hda_correct_pin_ctl(codec, pin, val); in set_pin_target()
225 snd_hda_codec_set_pin_target(codec, pin, val); in set_pin_target()
227 update_pin_ctl(codec, pin, val); in set_pin_target()
533 static hda_nid_t get_preferred_dac(struct hda_codec *codec, hda_nid_t pin) in get_preferred_dac() argument
[all …]
/linux-4.4.14/arch/arm/plat-orion/include/plat/
Dorion-gpio.h23 void orion_gpio_set_unused(unsigned pin);
24 void orion_gpio_set_blink(unsigned pin, int blink);
30 void orion_gpio_set_valid(unsigned pin, int mode);
/linux-4.4.14/arch/powerpc/platforms/52xx/
Dmpc52xx_pm.c36 int mpc52xx_set_wakeup_gpio(u8 pin, u8 level) in mpc52xx_set_wakeup_gpio() argument
41 out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
43 out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin)); in mpc52xx_set_wakeup_gpio()
45 out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
48 tmp &= ~(0x3 << (pin * 2)); in mpc52xx_set_wakeup_gpio()
49 tmp |= (!level + 1) << (pin * 2); in mpc52xx_set_wakeup_gpio()
/linux-4.4.14/arch/mips/include/asm/vr41xx/
Dgiu.h44 extern void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
52 extern void vr41xx_set_irq_level(unsigned int pin, irq_level_t level);
60 extern int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull);
/linux-4.4.14/drivers/pcmcia/
Dsa1111_jornada720.c100 unsigned int pin = GPIO_A0 | GPIO_A1 | GPIO_A2 | GPIO_A3; in pcmcia_jornada720_init() local
105 sa1111_set_io_dir(sadev, pin, 0, 0); in pcmcia_jornada720_init()
106 sa1111_set_io(sadev, pin, 0); in pcmcia_jornada720_init()
107 sa1111_set_sleep_io(sadev, pin, 0); in pcmcia_jornada720_init()

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