1/*
2 * arch/arm/mach-dove/irq.c
3 *
4 * Dove IRQ handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2.  This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16#include <asm/mach/arch.h>
17#include <plat/irq.h>
18#include <asm/mach/irq.h>
19#include <mach/pm.h>
20#include <mach/bridge-regs.h>
21#include <plat/orion-gpio.h>
22#include "common.h"
23
24static void pmu_irq_mask(struct irq_data *d)
25{
26	int pin = irq_to_pmu(d->irq);
27	u32 u;
28
29	u = readl(PMU_INTERRUPT_MASK);
30	u &= ~(1 << (pin & 31));
31	writel(u, PMU_INTERRUPT_MASK);
32}
33
34static void pmu_irq_unmask(struct irq_data *d)
35{
36	int pin = irq_to_pmu(d->irq);
37	u32 u;
38
39	u = readl(PMU_INTERRUPT_MASK);
40	u |= 1 << (pin & 31);
41	writel(u, PMU_INTERRUPT_MASK);
42}
43
44static void pmu_irq_ack(struct irq_data *d)
45{
46	int pin = irq_to_pmu(d->irq);
47	u32 u;
48
49	/*
50	 * The PMU mask register is not RW0C: it is RW.  This means that
51	 * the bits take whatever value is written to them; if you write
52	 * a '1', you will set the interrupt.
53	 *
54	 * Unfortunately this means there is NO race free way to clear
55	 * these interrupts.
56	 *
57	 * So, let's structure the code so that the window is as small as
58	 * possible.
59	 */
60	u = ~(1 << (pin & 31));
61	u &= readl_relaxed(PMU_INTERRUPT_CAUSE);
62	writel_relaxed(u, PMU_INTERRUPT_CAUSE);
63}
64
65static struct irq_chip pmu_irq_chip = {
66	.name		= "pmu_irq",
67	.irq_mask	= pmu_irq_mask,
68	.irq_unmask	= pmu_irq_unmask,
69	.irq_ack	= pmu_irq_ack,
70};
71
72static void pmu_irq_handler(struct irq_desc *desc)
73{
74	unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
75	unsigned int irq;
76
77	cause &= readl(PMU_INTERRUPT_MASK);
78	if (cause == 0) {
79		do_bad_IRQ(desc);
80		return;
81	}
82
83	for (irq = 0; irq < NR_PMU_IRQS; irq++) {
84		if (!(cause & (1 << irq)))
85			continue;
86		irq = pmu_to_irq(irq);
87		generic_handle_irq(irq);
88	}
89}
90
91static int __initdata gpio0_irqs[4] = {
92	IRQ_DOVE_GPIO_0_7,
93	IRQ_DOVE_GPIO_8_15,
94	IRQ_DOVE_GPIO_16_23,
95	IRQ_DOVE_GPIO_24_31,
96};
97
98static int __initdata gpio1_irqs[4] = {
99	IRQ_DOVE_HIGH_GPIO,
100	0,
101	0,
102	0,
103};
104
105static int __initdata gpio2_irqs[4] = {
106	0,
107	0,
108	0,
109	0,
110};
111
112#ifdef CONFIG_MULTI_IRQ_HANDLER
113/*
114 * Compiling with both non-DT and DT support enabled, will
115 * break asm irq handler used by non-DT boards. Therefore,
116 * we provide a C-style irq handler even for non-DT boards,
117 * if MULTI_IRQ_HANDLER is set.
118 */
119
120static void __iomem *dove_irq_base = IRQ_VIRT_BASE;
121
122static asmlinkage void
123__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
124{
125	u32 stat;
126
127	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
128	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
129	if (stat) {
130		unsigned int hwirq = 1 + __fls(stat);
131		handle_IRQ(hwirq, regs);
132		return;
133	}
134	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
135	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
136	if (stat) {
137		unsigned int hwirq = 33 + __fls(stat);
138		handle_IRQ(hwirq, regs);
139		return;
140	}
141}
142#endif
143
144void __init dove_init_irq(void)
145{
146	int i;
147
148	orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
149	orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
150
151#ifdef CONFIG_MULTI_IRQ_HANDLER
152	set_handle_irq(dove_legacy_handle_irq);
153#endif
154
155	/*
156	 * Initialize gpiolib for GPIOs 0-71.
157	 */
158	orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
159			IRQ_DOVE_GPIO_START, gpio0_irqs);
160
161	orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
162			IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
163
164	orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
165			IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
166
167	/*
168	 * Mask and clear PMU interrupts
169	 */
170	writel(0, PMU_INTERRUPT_MASK);
171	writel(0, PMU_INTERRUPT_CAUSE);
172
173	for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
174		irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
175		irq_set_status_flags(i, IRQ_LEVEL);
176		irq_clear_status_flags(i, IRQ_NOREQUEST);
177	}
178	irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
179}
180