1/* 2 * Copyright (c) 2015, Sony Mobile Communications AB. 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 and 7 * only version 2 as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15#include <linux/module.h> 16#include <linux/platform_device.h> 17#include <linux/pinctrl/pinctrl.h> 18#include <linux/pinctrl/pinmux.h> 19#include <linux/pinctrl/pinconf.h> 20#include <linux/pinctrl/pinconf-generic.h> 21#include <linux/slab.h> 22#include <linux/regmap.h> 23#include <linux/gpio.h> 24#include <linux/interrupt.h> 25#include <linux/of_device.h> 26 27#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 28 29#include "../core.h" 30#include "../pinctrl-utils.h" 31 32/* mode */ 33#define PM8XXX_GPIO_MODE_ENABLED BIT(0) 34#define PM8XXX_GPIO_MODE_INPUT 0 35#define PM8XXX_GPIO_MODE_OUTPUT 2 36 37/* output buffer */ 38#define PM8XXX_GPIO_PUSH_PULL 0 39#define PM8XXX_GPIO_OPEN_DRAIN 1 40 41/* bias */ 42#define PM8XXX_GPIO_BIAS_PU_30 0 43#define PM8XXX_GPIO_BIAS_PU_1P5 1 44#define PM8XXX_GPIO_BIAS_PU_31P5 2 45#define PM8XXX_GPIO_BIAS_PU_1P5_30 3 46#define PM8XXX_GPIO_BIAS_PD 4 47#define PM8XXX_GPIO_BIAS_NP 5 48 49/* GPIO registers */ 50#define SSBI_REG_ADDR_GPIO_BASE 0x150 51#define SSBI_REG_ADDR_GPIO(n) (SSBI_REG_ADDR_GPIO_BASE + n) 52 53#define PM8XXX_BANK_WRITE BIT(7) 54 55#define PM8XXX_MAX_GPIOS 44 56 57/* custom pinconf parameters */ 58#define PM8XXX_QCOM_DRIVE_STRENGH (PIN_CONFIG_END + 1) 59#define PM8XXX_QCOM_PULL_UP_STRENGTH (PIN_CONFIG_END + 2) 60 61/** 62 * struct pm8xxx_pin_data - dynamic configuration for a pin 63 * @reg: address of the control register 64 * @irq: IRQ from the PMIC interrupt controller 65 * @power_source: logical selected voltage source, mapping in static data 66 * is used translate to register values 67 * @mode: operating mode for the pin (input/output) 68 * @open_drain: output buffer configured as open-drain (vs push-pull) 69 * @output_value: configured output value 70 * @bias: register view of configured bias 71 * @pull_up_strength: placeholder for selected pull up strength 72 * only used to configure bias when pull up is selected 73 * @output_strength: selector of output-strength 74 * @disable: pin disabled / configured as tristate 75 * @function: pinmux selector 76 * @inverted: pin logic is inverted 77 */ 78struct pm8xxx_pin_data { 79 unsigned reg; 80 int irq; 81 u8 power_source; 82 u8 mode; 83 bool open_drain; 84 bool output_value; 85 u8 bias; 86 u8 pull_up_strength; 87 u8 output_strength; 88 bool disable; 89 u8 function; 90 bool inverted; 91}; 92 93struct pm8xxx_gpio { 94 struct device *dev; 95 struct regmap *regmap; 96 struct pinctrl_dev *pctrl; 97 struct gpio_chip chip; 98 99 struct pinctrl_desc desc; 100 unsigned npins; 101}; 102 103static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = { 104 {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0}, 105 {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0}, 106}; 107 108#ifdef CONFIG_DEBUG_FS 109static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = { 110 PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true), 111 PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH, "pull up strength", NULL, true), 112}; 113#endif 114 115static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = { 116 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", 117 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", 118 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", 119 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 120 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", 121 "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", 122 "gpio44", 123}; 124 125static const char * const pm8xxx_gpio_functions[] = { 126 PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED, 127 PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2, 128 PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2, 129 PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4, 130}; 131 132static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl, 133 struct pm8xxx_pin_data *pin, int bank) 134{ 135 unsigned int val = bank << 4; 136 int ret; 137 138 ret = regmap_write(pctrl->regmap, pin->reg, val); 139 if (ret) { 140 dev_err(pctrl->dev, "failed to select bank %d\n", bank); 141 return ret; 142 } 143 144 ret = regmap_read(pctrl->regmap, pin->reg, &val); 145 if (ret) { 146 dev_err(pctrl->dev, "failed to read register %d\n", bank); 147 return ret; 148 } 149 150 return val; 151} 152 153static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl, 154 struct pm8xxx_pin_data *pin, 155 int bank, 156 u8 val) 157{ 158 int ret; 159 160 val |= PM8XXX_BANK_WRITE; 161 val |= bank << 4; 162 163 ret = regmap_write(pctrl->regmap, pin->reg, val); 164 if (ret) 165 dev_err(pctrl->dev, "failed to write register\n"); 166 167 return ret; 168} 169 170static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev) 171{ 172 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 173 174 return pctrl->npins; 175} 176 177static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev, 178 unsigned group) 179{ 180 return pm8xxx_groups[group]; 181} 182 183 184static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev, 185 unsigned group, 186 const unsigned **pins, 187 unsigned *num_pins) 188{ 189 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 190 191 *pins = &pctrl->desc.pins[group].number; 192 *num_pins = 1; 193 194 return 0; 195} 196 197static const struct pinctrl_ops pm8xxx_pinctrl_ops = { 198 .get_groups_count = pm8xxx_get_groups_count, 199 .get_group_name = pm8xxx_get_group_name, 200 .get_group_pins = pm8xxx_get_group_pins, 201 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 202 .dt_free_map = pinctrl_utils_dt_free_map, 203}; 204 205static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev) 206{ 207 return ARRAY_SIZE(pm8xxx_gpio_functions); 208} 209 210static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev, 211 unsigned function) 212{ 213 return pm8xxx_gpio_functions[function]; 214} 215 216static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev, 217 unsigned function, 218 const char * const **groups, 219 unsigned * const num_groups) 220{ 221 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 222 223 *groups = pm8xxx_groups; 224 *num_groups = pctrl->npins; 225 return 0; 226} 227 228static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev, 229 unsigned function, 230 unsigned group) 231{ 232 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 233 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; 234 u8 val; 235 236 pin->function = function; 237 val = pin->function << 1; 238 239 pm8xxx_write_bank(pctrl, pin, 4, val); 240 241 return 0; 242} 243 244static const struct pinmux_ops pm8xxx_pinmux_ops = { 245 .get_functions_count = pm8xxx_get_functions_count, 246 .get_function_name = pm8xxx_get_function_name, 247 .get_function_groups = pm8xxx_get_function_groups, 248 .set_mux = pm8xxx_pinmux_set_mux, 249}; 250 251static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev, 252 unsigned int offset, 253 unsigned long *config) 254{ 255 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 256 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 257 unsigned param = pinconf_to_config_param(*config); 258 unsigned arg; 259 260 switch (param) { 261 case PIN_CONFIG_BIAS_DISABLE: 262 arg = pin->bias == PM8XXX_GPIO_BIAS_NP; 263 break; 264 case PIN_CONFIG_BIAS_PULL_DOWN: 265 arg = pin->bias == PM8XXX_GPIO_BIAS_PD; 266 break; 267 case PIN_CONFIG_BIAS_PULL_UP: 268 arg = pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30; 269 break; 270 case PM8XXX_QCOM_PULL_UP_STRENGTH: 271 arg = pin->pull_up_strength; 272 break; 273 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 274 arg = pin->disable; 275 break; 276 case PIN_CONFIG_INPUT_ENABLE: 277 arg = pin->mode == PM8XXX_GPIO_MODE_INPUT; 278 break; 279 case PIN_CONFIG_OUTPUT: 280 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT) 281 arg = pin->output_value; 282 else 283 arg = 0; 284 break; 285 case PIN_CONFIG_POWER_SOURCE: 286 arg = pin->power_source; 287 break; 288 case PM8XXX_QCOM_DRIVE_STRENGH: 289 arg = pin->output_strength; 290 break; 291 case PIN_CONFIG_DRIVE_PUSH_PULL: 292 arg = !pin->open_drain; 293 break; 294 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 295 arg = pin->open_drain; 296 break; 297 default: 298 return -EINVAL; 299 } 300 301 *config = pinconf_to_config_packed(param, arg); 302 303 return 0; 304} 305 306static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev, 307 unsigned int offset, 308 unsigned long *configs, 309 unsigned num_configs) 310{ 311 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 312 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 313 unsigned param; 314 unsigned arg; 315 unsigned i; 316 u8 banks = 0; 317 u8 val; 318 319 for (i = 0; i < num_configs; i++) { 320 param = pinconf_to_config_param(configs[i]); 321 arg = pinconf_to_config_argument(configs[i]); 322 323 switch (param) { 324 case PIN_CONFIG_BIAS_DISABLE: 325 pin->bias = PM8XXX_GPIO_BIAS_NP; 326 banks |= BIT(2); 327 pin->disable = 0; 328 banks |= BIT(3); 329 break; 330 case PIN_CONFIG_BIAS_PULL_DOWN: 331 pin->bias = PM8XXX_GPIO_BIAS_PD; 332 banks |= BIT(2); 333 pin->disable = 0; 334 banks |= BIT(3); 335 break; 336 case PM8XXX_QCOM_PULL_UP_STRENGTH: 337 if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) { 338 dev_err(pctrl->dev, "invalid pull-up strength\n"); 339 return -EINVAL; 340 } 341 pin->pull_up_strength = arg; 342 /* FALLTHROUGH */ 343 case PIN_CONFIG_BIAS_PULL_UP: 344 pin->bias = pin->pull_up_strength; 345 banks |= BIT(2); 346 pin->disable = 0; 347 banks |= BIT(3); 348 break; 349 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 350 pin->disable = 1; 351 banks |= BIT(3); 352 break; 353 case PIN_CONFIG_INPUT_ENABLE: 354 pin->mode = PM8XXX_GPIO_MODE_INPUT; 355 banks |= BIT(0) | BIT(1); 356 break; 357 case PIN_CONFIG_OUTPUT: 358 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; 359 pin->output_value = !!arg; 360 banks |= BIT(0) | BIT(1); 361 break; 362 case PIN_CONFIG_POWER_SOURCE: 363 pin->power_source = arg; 364 banks |= BIT(0); 365 break; 366 case PM8XXX_QCOM_DRIVE_STRENGH: 367 if (arg > PMIC_GPIO_STRENGTH_LOW) { 368 dev_err(pctrl->dev, "invalid drive strength\n"); 369 return -EINVAL; 370 } 371 pin->output_strength = arg; 372 banks |= BIT(3); 373 break; 374 case PIN_CONFIG_DRIVE_PUSH_PULL: 375 pin->open_drain = 0; 376 banks |= BIT(1); 377 break; 378 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 379 pin->open_drain = 1; 380 banks |= BIT(1); 381 break; 382 default: 383 dev_err(pctrl->dev, 384 "unsupported config parameter: %x\n", 385 param); 386 return -EINVAL; 387 } 388 } 389 390 if (banks & BIT(0)) { 391 val = pin->power_source << 1; 392 val |= PM8XXX_GPIO_MODE_ENABLED; 393 pm8xxx_write_bank(pctrl, pin, 0, val); 394 } 395 396 if (banks & BIT(1)) { 397 val = pin->mode << 2; 398 val |= pin->open_drain << 1; 399 val |= pin->output_value; 400 pm8xxx_write_bank(pctrl, pin, 1, val); 401 } 402 403 if (banks & BIT(2)) { 404 val = pin->bias << 1; 405 pm8xxx_write_bank(pctrl, pin, 2, val); 406 } 407 408 if (banks & BIT(3)) { 409 val = pin->output_strength << 2; 410 val |= pin->disable; 411 pm8xxx_write_bank(pctrl, pin, 3, val); 412 } 413 414 if (banks & BIT(4)) { 415 val = pin->function << 1; 416 pm8xxx_write_bank(pctrl, pin, 4, val); 417 } 418 419 if (banks & BIT(5)) { 420 val = 0; 421 if (!pin->inverted) 422 val |= BIT(3); 423 pm8xxx_write_bank(pctrl, pin, 5, val); 424 } 425 426 return 0; 427} 428 429static const struct pinconf_ops pm8xxx_pinconf_ops = { 430 .is_generic = true, 431 .pin_config_group_get = pm8xxx_pin_config_get, 432 .pin_config_group_set = pm8xxx_pin_config_set, 433}; 434 435static struct pinctrl_desc pm8xxx_pinctrl_desc = { 436 .name = "pm8xxx_gpio", 437 .pctlops = &pm8xxx_pinctrl_ops, 438 .pmxops = &pm8xxx_pinmux_ops, 439 .confops = &pm8xxx_pinconf_ops, 440 .owner = THIS_MODULE, 441}; 442 443static int pm8xxx_gpio_direction_input(struct gpio_chip *chip, 444 unsigned offset) 445{ 446 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip); 447 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 448 u8 val; 449 450 pin->mode = PM8XXX_GPIO_MODE_INPUT; 451 val = pin->mode << 2; 452 453 pm8xxx_write_bank(pctrl, pin, 1, val); 454 455 return 0; 456} 457 458static int pm8xxx_gpio_direction_output(struct gpio_chip *chip, 459 unsigned offset, 460 int value) 461{ 462 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip); 463 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 464 u8 val; 465 466 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; 467 pin->output_value = !!value; 468 469 val = pin->mode << 2; 470 val |= pin->open_drain << 1; 471 val |= pin->output_value; 472 473 pm8xxx_write_bank(pctrl, pin, 1, val); 474 475 return 0; 476} 477 478static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset) 479{ 480 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip); 481 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 482 bool state; 483 int ret; 484 485 if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) { 486 ret = pin->output_value; 487 } else { 488 ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state); 489 if (!ret) 490 ret = !!state; 491 } 492 493 return ret; 494} 495 496static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 497{ 498 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip); 499 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 500 u8 val; 501 502 pin->output_value = !!value; 503 504 val = pin->mode << 2; 505 val |= pin->open_drain << 1; 506 val |= pin->output_value; 507 508 pm8xxx_write_bank(pctrl, pin, 1, val); 509} 510 511static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip, 512 const struct of_phandle_args *gpio_desc, 513 u32 *flags) 514{ 515 if (chip->of_gpio_n_cells < 2) 516 return -EINVAL; 517 518 if (flags) 519 *flags = gpio_desc->args[1]; 520 521 return gpio_desc->args[0] - 1; 522} 523 524 525static int pm8xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 526{ 527 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip); 528 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 529 530 return pin->irq; 531} 532 533#ifdef CONFIG_DEBUG_FS 534#include <linux/seq_file.h> 535 536static void pm8xxx_gpio_dbg_show_one(struct seq_file *s, 537 struct pinctrl_dev *pctldev, 538 struct gpio_chip *chip, 539 unsigned offset, 540 unsigned gpio) 541{ 542 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip); 543 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 544 545 static const char * const modes[] = { 546 "in", "both", "out", "off" 547 }; 548 static const char * const biases[] = { 549 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", 550 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" 551 }; 552 static const char * const buffer_types[] = { 553 "push-pull", "open-drain" 554 }; 555 static const char * const strengths[] = { 556 "no", "high", "medium", "low" 557 }; 558 559 seq_printf(s, " gpio%-2d:", offset + 1); 560 if (pin->disable) { 561 seq_puts(s, " ---"); 562 } else { 563 seq_printf(s, " %-4s", modes[pin->mode]); 564 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]); 565 seq_printf(s, " VIN%d", pin->power_source); 566 seq_printf(s, " %-27s", biases[pin->bias]); 567 seq_printf(s, " %-10s", buffer_types[pin->open_drain]); 568 seq_printf(s, " %-4s", pin->output_value ? "high" : "low"); 569 seq_printf(s, " %-7s", strengths[pin->output_strength]); 570 if (pin->inverted) 571 seq_puts(s, " inverted"); 572 } 573} 574 575static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 576{ 577 unsigned gpio = chip->base; 578 unsigned i; 579 580 for (i = 0; i < chip->ngpio; i++, gpio++) { 581 pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio); 582 seq_puts(s, "\n"); 583 } 584} 585 586#else 587#define pm8xxx_gpio_dbg_show NULL 588#endif 589 590static struct gpio_chip pm8xxx_gpio_template = { 591 .direction_input = pm8xxx_gpio_direction_input, 592 .direction_output = pm8xxx_gpio_direction_output, 593 .get = pm8xxx_gpio_get, 594 .set = pm8xxx_gpio_set, 595 .of_xlate = pm8xxx_gpio_of_xlate, 596 .to_irq = pm8xxx_gpio_to_irq, 597 .dbg_show = pm8xxx_gpio_dbg_show, 598 .owner = THIS_MODULE, 599}; 600 601static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl, 602 struct pm8xxx_pin_data *pin) 603{ 604 int val; 605 606 val = pm8xxx_read_bank(pctrl, pin, 0); 607 if (val < 0) 608 return val; 609 610 pin->power_source = (val >> 1) & 0x7; 611 612 val = pm8xxx_read_bank(pctrl, pin, 1); 613 if (val < 0) 614 return val; 615 616 pin->mode = (val >> 2) & 0x3; 617 pin->open_drain = !!(val & BIT(1)); 618 pin->output_value = val & BIT(0); 619 620 val = pm8xxx_read_bank(pctrl, pin, 2); 621 if (val < 0) 622 return val; 623 624 pin->bias = (val >> 1) & 0x7; 625 if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30) 626 pin->pull_up_strength = pin->bias; 627 else 628 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30; 629 630 val = pm8xxx_read_bank(pctrl, pin, 3); 631 if (val < 0) 632 return val; 633 634 pin->output_strength = (val >> 2) & 0x3; 635 pin->disable = val & BIT(0); 636 637 val = pm8xxx_read_bank(pctrl, pin, 4); 638 if (val < 0) 639 return val; 640 641 pin->function = (val >> 1) & 0x7; 642 643 val = pm8xxx_read_bank(pctrl, pin, 5); 644 if (val < 0) 645 return val; 646 647 pin->inverted = !(val & BIT(3)); 648 649 return 0; 650} 651 652static const struct of_device_id pm8xxx_gpio_of_match[] = { 653 { .compatible = "qcom,pm8018-gpio", .data = (void *)6 }, 654 { .compatible = "qcom,pm8038-gpio", .data = (void *)12 }, 655 { .compatible = "qcom,pm8058-gpio", .data = (void *)40 }, 656 { .compatible = "qcom,pm8917-gpio", .data = (void *)38 }, 657 { .compatible = "qcom,pm8921-gpio", .data = (void *)44 }, 658 { }, 659}; 660MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match); 661 662static int pm8xxx_gpio_probe(struct platform_device *pdev) 663{ 664 struct pm8xxx_pin_data *pin_data; 665 struct pinctrl_pin_desc *pins; 666 struct pm8xxx_gpio *pctrl; 667 int ret; 668 int i; 669 670 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 671 if (!pctrl) 672 return -ENOMEM; 673 674 pctrl->dev = &pdev->dev; 675 pctrl->npins = (unsigned long)of_device_get_match_data(&pdev->dev); 676 677 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); 678 if (!pctrl->regmap) { 679 dev_err(&pdev->dev, "parent regmap unavailable\n"); 680 return -ENXIO; 681 } 682 683 pctrl->desc = pm8xxx_pinctrl_desc; 684 pctrl->desc.npins = pctrl->npins; 685 686 pins = devm_kcalloc(&pdev->dev, 687 pctrl->desc.npins, 688 sizeof(struct pinctrl_pin_desc), 689 GFP_KERNEL); 690 if (!pins) 691 return -ENOMEM; 692 693 pin_data = devm_kcalloc(&pdev->dev, 694 pctrl->desc.npins, 695 sizeof(struct pm8xxx_pin_data), 696 GFP_KERNEL); 697 if (!pin_data) 698 return -ENOMEM; 699 700 for (i = 0; i < pctrl->desc.npins; i++) { 701 pin_data[i].reg = SSBI_REG_ADDR_GPIO(i); 702 pin_data[i].irq = platform_get_irq(pdev, i); 703 if (pin_data[i].irq < 0) { 704 dev_err(&pdev->dev, 705 "missing interrupts for pin %d\n", i); 706 return pin_data[i].irq; 707 } 708 709 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); 710 if (ret) 711 return ret; 712 713 pins[i].number = i; 714 pins[i].name = pm8xxx_groups[i]; 715 pins[i].drv_data = &pin_data[i]; 716 } 717 pctrl->desc.pins = pins; 718 719 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings); 720 pctrl->desc.custom_params = pm8xxx_gpio_bindings; 721#ifdef CONFIG_DEBUG_FS 722 pctrl->desc.custom_conf_items = pm8xxx_conf_items; 723#endif 724 725 pctrl->pctrl = pinctrl_register(&pctrl->desc, &pdev->dev, pctrl); 726 if (IS_ERR(pctrl->pctrl)) { 727 dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n"); 728 return PTR_ERR(pctrl->pctrl); 729 } 730 731 pctrl->chip = pm8xxx_gpio_template; 732 pctrl->chip.base = -1; 733 pctrl->chip.dev = &pdev->dev; 734 pctrl->chip.of_node = pdev->dev.of_node; 735 pctrl->chip.of_gpio_n_cells = 2; 736 pctrl->chip.label = dev_name(pctrl->dev); 737 pctrl->chip.ngpio = pctrl->npins; 738 ret = gpiochip_add(&pctrl->chip); 739 if (ret) { 740 dev_err(&pdev->dev, "failed register gpiochip\n"); 741 goto unregister_pinctrl; 742 } 743 744 ret = gpiochip_add_pin_range(&pctrl->chip, 745 dev_name(pctrl->dev), 746 0, 0, pctrl->chip.ngpio); 747 if (ret) { 748 dev_err(pctrl->dev, "failed to add pin range\n"); 749 goto unregister_gpiochip; 750 } 751 752 platform_set_drvdata(pdev, pctrl); 753 754 dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n"); 755 756 return 0; 757 758unregister_gpiochip: 759 gpiochip_remove(&pctrl->chip); 760 761unregister_pinctrl: 762 pinctrl_unregister(pctrl->pctrl); 763 764 return ret; 765} 766 767static int pm8xxx_gpio_remove(struct platform_device *pdev) 768{ 769 struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev); 770 771 gpiochip_remove(&pctrl->chip); 772 773 pinctrl_unregister(pctrl->pctrl); 774 775 return 0; 776} 777 778static struct platform_driver pm8xxx_gpio_driver = { 779 .driver = { 780 .name = "qcom-ssbi-gpio", 781 .of_match_table = pm8xxx_gpio_of_match, 782 }, 783 .probe = pm8xxx_gpio_probe, 784 .remove = pm8xxx_gpio_remove, 785}; 786 787module_platform_driver(pm8xxx_gpio_driver); 788 789MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); 790MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver"); 791MODULE_LICENSE("GPL v2"); 792