1/* 2 * Cherryview/Braswell pinctrl driver 3 * 4 * Copyright (C) 2014, Intel Corporation 5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 6 * 7 * This driver is based on the original Cherryview GPIO driver by 8 * Ning Li <ning.li@intel.com> 9 * Alan Cox <alan@linux.intel.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16#include <linux/kernel.h> 17#include <linux/module.h> 18#include <linux/init.h> 19#include <linux/types.h> 20#include <linux/gpio.h> 21#include <linux/gpio/driver.h> 22#include <linux/acpi.h> 23#include <linux/pinctrl/pinctrl.h> 24#include <linux/pinctrl/pinmux.h> 25#include <linux/pinctrl/pinconf.h> 26#include <linux/pinctrl/pinconf-generic.h> 27#include <linux/platform_device.h> 28 29#define CHV_INTSTAT 0x300 30#define CHV_INTMASK 0x380 31 32#define FAMILY_PAD_REGS_OFF 0x4400 33#define FAMILY_PAD_REGS_SIZE 0x400 34#define MAX_FAMILY_PAD_GPIO_NO 15 35#define GPIO_REGS_SIZE 8 36 37#define CHV_PADCTRL0 0x000 38#define CHV_PADCTRL0_INTSEL_SHIFT 28 39#define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) 40#define CHV_PADCTRL0_TERM_UP BIT(23) 41#define CHV_PADCTRL0_TERM_SHIFT 20 42#define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) 43#define CHV_PADCTRL0_TERM_20K 1 44#define CHV_PADCTRL0_TERM_5K 2 45#define CHV_PADCTRL0_TERM_1K 4 46#define CHV_PADCTRL0_PMODE_SHIFT 16 47#define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) 48#define CHV_PADCTRL0_GPIOEN BIT(15) 49#define CHV_PADCTRL0_GPIOCFG_SHIFT 8 50#define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) 51#define CHV_PADCTRL0_GPIOCFG_GPIO 0 52#define CHV_PADCTRL0_GPIOCFG_GPO 1 53#define CHV_PADCTRL0_GPIOCFG_GPI 2 54#define CHV_PADCTRL0_GPIOCFG_HIZ 3 55#define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 56#define CHV_PADCTRL0_GPIORXSTATE BIT(0) 57 58#define CHV_PADCTRL1 0x004 59#define CHV_PADCTRL1_CFGLOCK BIT(31) 60#define CHV_PADCTRL1_INVRXTX_SHIFT 4 61#define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) 62#define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) 63#define CHV_PADCTRL1_ODEN BIT(3) 64#define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) 65#define CHV_PADCTRL1_INTWAKECFG_MASK 7 66#define CHV_PADCTRL1_INTWAKECFG_FALLING 1 67#define CHV_PADCTRL1_INTWAKECFG_RISING 2 68#define CHV_PADCTRL1_INTWAKECFG_BOTH 3 69#define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 70 71/** 72 * struct chv_alternate_function - A per group or per pin alternate function 73 * @pin: Pin number (only used in per pin configs) 74 * @mode: Mode the pin should be set in 75 * @invert_oe: Invert OE for this pin 76 */ 77struct chv_alternate_function { 78 unsigned pin; 79 u8 mode; 80 bool invert_oe; 81}; 82 83/** 84 * struct chv_pincgroup - describes a CHV pin group 85 * @name: Name of the group 86 * @pins: An array of pins in this group 87 * @npins: Number of pins in this group 88 * @altfunc: Alternate function applied to all pins in this group 89 * @overrides: Alternate function override per pin or %NULL if not used 90 * @noverrides: Number of per pin alternate function overrides if 91 * @overrides != NULL. 92 */ 93struct chv_pingroup { 94 const char *name; 95 const unsigned *pins; 96 size_t npins; 97 struct chv_alternate_function altfunc; 98 const struct chv_alternate_function *overrides; 99 size_t noverrides; 100}; 101 102/** 103 * struct chv_function - A CHV pinmux function 104 * @name: Name of the function 105 * @groups: An array of groups for this function 106 * @ngroups: Number of groups in @groups 107 */ 108struct chv_function { 109 const char *name; 110 const char * const *groups; 111 size_t ngroups; 112}; 113 114/** 115 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs 116 * @base: Start pin number 117 * @npins: Number of pins in this range 118 */ 119struct chv_gpio_pinrange { 120 unsigned base; 121 unsigned npins; 122}; 123 124/** 125 * struct chv_community - A community specific configuration 126 * @uid: ACPI _UID used to match the community 127 * @pins: All pins in this community 128 * @npins: Number of pins 129 * @groups: All groups in this community 130 * @ngroups: Number of groups 131 * @functions: All functions in this community 132 * @nfunctions: Number of functions 133 * @ngpios: Number of GPIOs in this community 134 * @gpio_ranges: An array of GPIO ranges in this community 135 * @ngpio_ranges: Number of GPIO ranges 136 * @ngpios: Total number of GPIOs in this community 137 */ 138struct chv_community { 139 const char *uid; 140 const struct pinctrl_pin_desc *pins; 141 size_t npins; 142 const struct chv_pingroup *groups; 143 size_t ngroups; 144 const struct chv_function *functions; 145 size_t nfunctions; 146 const struct chv_gpio_pinrange *gpio_ranges; 147 size_t ngpio_ranges; 148 size_t ngpios; 149}; 150 151struct chv_pin_context { 152 u32 padctrl0; 153 u32 padctrl1; 154}; 155 156/** 157 * struct chv_pinctrl - CHV pinctrl private structure 158 * @dev: Pointer to the parent device 159 * @pctldesc: Pin controller description 160 * @pctldev: Pointer to the pin controller device 161 * @chip: GPIO chip in this pin controller 162 * @regs: MMIO registers 163 * @lock: Lock to serialize register accesses 164 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO 165 * offset (in GPIO number space) 166 * @community: Community this pinctrl instance represents 167 * 168 * The first group in @groups is expected to contain all pins that can be 169 * used as GPIOs. 170 */ 171struct chv_pinctrl { 172 struct device *dev; 173 struct pinctrl_desc pctldesc; 174 struct pinctrl_dev *pctldev; 175 struct gpio_chip chip; 176 void __iomem *regs; 177 raw_spinlock_t lock; 178 unsigned intr_lines[16]; 179 const struct chv_community *community; 180 u32 saved_intmask; 181 struct chv_pin_context *saved_pin_context; 182}; 183 184#define gpiochip_to_pinctrl(c) container_of(c, struct chv_pinctrl, chip) 185 186#define ALTERNATE_FUNCTION(p, m, i) \ 187 { \ 188 .pin = (p), \ 189 .mode = (m), \ 190 .invert_oe = (i), \ 191 } 192 193#define PIN_GROUP(n, p, m, i) \ 194 { \ 195 .name = (n), \ 196 .pins = (p), \ 197 .npins = ARRAY_SIZE((p)), \ 198 .altfunc.mode = (m), \ 199 .altfunc.invert_oe = (i), \ 200 } 201 202#define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ 203 { \ 204 .name = (n), \ 205 .pins = (p), \ 206 .npins = ARRAY_SIZE((p)), \ 207 .altfunc.mode = (m), \ 208 .altfunc.invert_oe = (i), \ 209 .overrides = (o), \ 210 .noverrides = ARRAY_SIZE((o)), \ 211 } 212 213#define FUNCTION(n, g) \ 214 { \ 215 .name = (n), \ 216 .groups = (g), \ 217 .ngroups = ARRAY_SIZE((g)), \ 218 } 219 220#define GPIO_PINRANGE(start, end) \ 221 { \ 222 .base = (start), \ 223 .npins = (end) - (start) + 1, \ 224 } 225 226static const struct pinctrl_pin_desc southwest_pins[] = { 227 PINCTRL_PIN(0, "FST_SPI_D2"), 228 PINCTRL_PIN(1, "FST_SPI_D0"), 229 PINCTRL_PIN(2, "FST_SPI_CLK"), 230 PINCTRL_PIN(3, "FST_SPI_D3"), 231 PINCTRL_PIN(4, "FST_SPI_CS1_B"), 232 PINCTRL_PIN(5, "FST_SPI_D1"), 233 PINCTRL_PIN(6, "FST_SPI_CS0_B"), 234 PINCTRL_PIN(7, "FST_SPI_CS2_B"), 235 236 PINCTRL_PIN(15, "UART1_RTS_B"), 237 PINCTRL_PIN(16, "UART1_RXD"), 238 PINCTRL_PIN(17, "UART2_RXD"), 239 PINCTRL_PIN(18, "UART1_CTS_B"), 240 PINCTRL_PIN(19, "UART2_RTS_B"), 241 PINCTRL_PIN(20, "UART1_TXD"), 242 PINCTRL_PIN(21, "UART2_TXD"), 243 PINCTRL_PIN(22, "UART2_CTS_B"), 244 245 PINCTRL_PIN(30, "MF_HDA_CLK"), 246 PINCTRL_PIN(31, "MF_HDA_RSTB"), 247 PINCTRL_PIN(32, "MF_HDA_SDIO"), 248 PINCTRL_PIN(33, "MF_HDA_SDO"), 249 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 250 PINCTRL_PIN(35, "MF_HDA_SYNC"), 251 PINCTRL_PIN(36, "MF_HDA_SDI1"), 252 PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 253 254 PINCTRL_PIN(45, "I2C5_SDA"), 255 PINCTRL_PIN(46, "I2C4_SDA"), 256 PINCTRL_PIN(47, "I2C6_SDA"), 257 PINCTRL_PIN(48, "I2C5_SCL"), 258 PINCTRL_PIN(49, "I2C_NFC_SDA"), 259 PINCTRL_PIN(50, "I2C4_SCL"), 260 PINCTRL_PIN(51, "I2C6_SCL"), 261 PINCTRL_PIN(52, "I2C_NFC_SCL"), 262 263 PINCTRL_PIN(60, "I2C1_SDA"), 264 PINCTRL_PIN(61, "I2C0_SDA"), 265 PINCTRL_PIN(62, "I2C2_SDA"), 266 PINCTRL_PIN(63, "I2C1_SCL"), 267 PINCTRL_PIN(64, "I2C3_SDA"), 268 PINCTRL_PIN(65, "I2C0_SCL"), 269 PINCTRL_PIN(66, "I2C2_SCL"), 270 PINCTRL_PIN(67, "I2C3_SCL"), 271 272 PINCTRL_PIN(75, "SATA_GP0"), 273 PINCTRL_PIN(76, "SATA_GP1"), 274 PINCTRL_PIN(77, "SATA_LEDN"), 275 PINCTRL_PIN(78, "SATA_GP2"), 276 PINCTRL_PIN(79, "MF_SMB_ALERTB"), 277 PINCTRL_PIN(80, "SATA_GP3"), 278 PINCTRL_PIN(81, "MF_SMB_CLK"), 279 PINCTRL_PIN(82, "MF_SMB_DATA"), 280 281 PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 282 PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 283 PINCTRL_PIN(92, "GP_SSP_2_CLK"), 284 PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 285 PINCTRL_PIN(94, "GP_SSP_2_RXD"), 286 PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 287 PINCTRL_PIN(96, "GP_SSP_2_FS"), 288 PINCTRL_PIN(97, "GP_SSP_2_TXD"), 289}; 290 291static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; 292static const unsigned southwest_uart0_pins[] = { 16, 20 }; 293static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 294static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 295static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 296static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 297static const unsigned southwest_lpe_pins[] = { 298 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 299}; 300static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 301static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 302static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 303static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 304static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 305static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 306static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 307static const unsigned southwest_smbus_pins[] = { 79, 81, 82 }; 308static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 309 310/* LPE I2S TXD pins need to have invert_oe set */ 311static const struct chv_alternate_function southwest_lpe_altfuncs[] = { 312 ALTERNATE_FUNCTION(30, 1, true), 313 ALTERNATE_FUNCTION(34, 1, true), 314 ALTERNATE_FUNCTION(97, 1, true), 315}; 316 317/* 318 * Two spi3 chipselects are available in different mode than the main spi3 319 * functionality, which is using mode 1. 320 */ 321static const struct chv_alternate_function southwest_spi3_altfuncs[] = { 322 ALTERNATE_FUNCTION(76, 3, false), 323 ALTERNATE_FUNCTION(80, 3, false), 324}; 325 326static const struct chv_pingroup southwest_groups[] = { 327 PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false), 328 PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false), 329 PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false), 330 PIN_GROUP("hda_grp", southwest_hda_pins, 2, false), 331 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true), 332 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true), 333 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true), 334 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true), 335 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true), 336 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true), 337 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true), 338 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), 339 340 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, 341 southwest_lpe_altfuncs), 342 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, 343 southwest_spi3_altfuncs), 344}; 345 346static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 347static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 348static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 349static const char * const southwest_hda_groups[] = { "hda_grp" }; 350static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 351static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 352static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 353static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 354static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 355static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 356static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 357static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 358static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 359static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 360 361/* 362 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 363 * enabled only as GPIOs. 364 */ 365static const struct chv_function southwest_functions[] = { 366 FUNCTION("uart0", southwest_uart0_groups), 367 FUNCTION("uart1", southwest_uart1_groups), 368 FUNCTION("uart2", southwest_uart2_groups), 369 FUNCTION("hda", southwest_hda_groups), 370 FUNCTION("lpe", southwest_lpe_groups), 371 FUNCTION("i2c0", southwest_i2c0_groups), 372 FUNCTION("i2c1", southwest_i2c1_groups), 373 FUNCTION("i2c2", southwest_i2c2_groups), 374 FUNCTION("i2c3", southwest_i2c3_groups), 375 FUNCTION("i2c4", southwest_i2c4_groups), 376 FUNCTION("i2c5", southwest_i2c5_groups), 377 FUNCTION("i2c6", southwest_i2c6_groups), 378 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 379 FUNCTION("spi3", southwest_spi3_groups), 380}; 381 382static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { 383 GPIO_PINRANGE(0, 7), 384 GPIO_PINRANGE(15, 22), 385 GPIO_PINRANGE(30, 37), 386 GPIO_PINRANGE(45, 52), 387 GPIO_PINRANGE(60, 67), 388 GPIO_PINRANGE(75, 82), 389 GPIO_PINRANGE(90, 97), 390}; 391 392static const struct chv_community southwest_community = { 393 .uid = "1", 394 .pins = southwest_pins, 395 .npins = ARRAY_SIZE(southwest_pins), 396 .groups = southwest_groups, 397 .ngroups = ARRAY_SIZE(southwest_groups), 398 .functions = southwest_functions, 399 .nfunctions = ARRAY_SIZE(southwest_functions), 400 .gpio_ranges = southwest_gpio_ranges, 401 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), 402 .ngpios = ARRAY_SIZE(southwest_pins), 403}; 404 405static const struct pinctrl_pin_desc north_pins[] = { 406 PINCTRL_PIN(0, "GPIO_DFX_0"), 407 PINCTRL_PIN(1, "GPIO_DFX_3"), 408 PINCTRL_PIN(2, "GPIO_DFX_7"), 409 PINCTRL_PIN(3, "GPIO_DFX_1"), 410 PINCTRL_PIN(4, "GPIO_DFX_5"), 411 PINCTRL_PIN(5, "GPIO_DFX_4"), 412 PINCTRL_PIN(6, "GPIO_DFX_8"), 413 PINCTRL_PIN(7, "GPIO_DFX_2"), 414 PINCTRL_PIN(8, "GPIO_DFX_6"), 415 416 PINCTRL_PIN(15, "GPIO_SUS0"), 417 PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 418 PINCTRL_PIN(17, "GPIO_SUS3"), 419 PINCTRL_PIN(18, "GPIO_SUS7"), 420 PINCTRL_PIN(19, "GPIO_SUS1"), 421 PINCTRL_PIN(20, "GPIO_SUS5"), 422 PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 423 PINCTRL_PIN(22, "GPIO_SUS4"), 424 PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 425 PINCTRL_PIN(24, "GPIO_SUS2"), 426 PINCTRL_PIN(25, "GPIO_SUS6"), 427 PINCTRL_PIN(26, "CX_PREQ_B"), 428 PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 429 430 PINCTRL_PIN(30, "TRST_B"), 431 PINCTRL_PIN(31, "TCK"), 432 PINCTRL_PIN(32, "PROCHOT_B"), 433 PINCTRL_PIN(33, "SVIDO_DATA"), 434 PINCTRL_PIN(34, "TMS"), 435 PINCTRL_PIN(35, "CX_PRDY_B_2"), 436 PINCTRL_PIN(36, "TDO_2"), 437 PINCTRL_PIN(37, "CX_PRDY_B"), 438 PINCTRL_PIN(38, "SVIDO_ALERT_B"), 439 PINCTRL_PIN(39, "TDO"), 440 PINCTRL_PIN(40, "SVIDO_CLK"), 441 PINCTRL_PIN(41, "TDI"), 442 443 PINCTRL_PIN(45, "GP_CAMERASB_05"), 444 PINCTRL_PIN(46, "GP_CAMERASB_02"), 445 PINCTRL_PIN(47, "GP_CAMERASB_08"), 446 PINCTRL_PIN(48, "GP_CAMERASB_00"), 447 PINCTRL_PIN(49, "GP_CAMERASB_06"), 448 PINCTRL_PIN(50, "GP_CAMERASB_10"), 449 PINCTRL_PIN(51, "GP_CAMERASB_03"), 450 PINCTRL_PIN(52, "GP_CAMERASB_09"), 451 PINCTRL_PIN(53, "GP_CAMERASB_01"), 452 PINCTRL_PIN(54, "GP_CAMERASB_07"), 453 PINCTRL_PIN(55, "GP_CAMERASB_11"), 454 PINCTRL_PIN(56, "GP_CAMERASB_04"), 455 456 PINCTRL_PIN(60, "PANEL0_BKLTEN"), 457 PINCTRL_PIN(61, "HV_DDI0_HPD"), 458 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 459 PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 460 PINCTRL_PIN(64, "HV_DDI1_HPD"), 461 PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 462 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 463 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 464 PINCTRL_PIN(68, "HV_DDI2_HPD"), 465 PINCTRL_PIN(69, "PANEL1_VDDEN"), 466 PINCTRL_PIN(70, "PANEL1_BKLTEN"), 467 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 468 PINCTRL_PIN(72, "PANEL0_VDDEN"), 469}; 470 471static const struct chv_gpio_pinrange north_gpio_ranges[] = { 472 GPIO_PINRANGE(0, 8), 473 GPIO_PINRANGE(15, 27), 474 GPIO_PINRANGE(30, 41), 475 GPIO_PINRANGE(45, 56), 476 GPIO_PINRANGE(60, 72), 477}; 478 479static const struct chv_community north_community = { 480 .uid = "2", 481 .pins = north_pins, 482 .npins = ARRAY_SIZE(north_pins), 483 .gpio_ranges = north_gpio_ranges, 484 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), 485 .ngpios = ARRAY_SIZE(north_pins), 486}; 487 488static const struct pinctrl_pin_desc east_pins[] = { 489 PINCTRL_PIN(0, "PMU_SLP_S3_B"), 490 PINCTRL_PIN(1, "PMU_BATLOW_B"), 491 PINCTRL_PIN(2, "SUS_STAT_B"), 492 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 493 PINCTRL_PIN(4, "PMU_AC_PRESENT"), 494 PINCTRL_PIN(5, "PMU_PLTRST_B"), 495 PINCTRL_PIN(6, "PMU_SUSCLK"), 496 PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 497 PINCTRL_PIN(8, "PMU_PWRBTN_B"), 498 PINCTRL_PIN(9, "PMU_SLP_S4_B"), 499 PINCTRL_PIN(10, "PMU_WAKE_B"), 500 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 501 502 PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 503 PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 504 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 505 PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 506 PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 507 PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 508 PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 509 PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 510 PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 511 PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 512 PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 513 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 514}; 515 516static const struct chv_gpio_pinrange east_gpio_ranges[] = { 517 GPIO_PINRANGE(0, 11), 518 GPIO_PINRANGE(15, 26), 519}; 520 521static const struct chv_community east_community = { 522 .uid = "3", 523 .pins = east_pins, 524 .npins = ARRAY_SIZE(east_pins), 525 .gpio_ranges = east_gpio_ranges, 526 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), 527 .ngpios = ARRAY_SIZE(east_pins), 528}; 529 530static const struct pinctrl_pin_desc southeast_pins[] = { 531 PINCTRL_PIN(0, "MF_PLT_CLK0"), 532 PINCTRL_PIN(1, "PWM1"), 533 PINCTRL_PIN(2, "MF_PLT_CLK1"), 534 PINCTRL_PIN(3, "MF_PLT_CLK4"), 535 PINCTRL_PIN(4, "MF_PLT_CLK3"), 536 PINCTRL_PIN(5, "PWM0"), 537 PINCTRL_PIN(6, "MF_PLT_CLK5"), 538 PINCTRL_PIN(7, "MF_PLT_CLK2"), 539 540 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 541 PINCTRL_PIN(16, "SDMMC1_CLK"), 542 PINCTRL_PIN(17, "SDMMC1_D0"), 543 PINCTRL_PIN(18, "SDMMC2_D1"), 544 PINCTRL_PIN(19, "SDMMC2_CLK"), 545 PINCTRL_PIN(20, "SDMMC1_D2"), 546 PINCTRL_PIN(21, "SDMMC2_D2"), 547 PINCTRL_PIN(22, "SDMMC2_CMD"), 548 PINCTRL_PIN(23, "SDMMC1_CMD"), 549 PINCTRL_PIN(24, "SDMMC1_D1"), 550 PINCTRL_PIN(25, "SDMMC2_D0"), 551 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 552 553 PINCTRL_PIN(30, "SDMMC3_D1"), 554 PINCTRL_PIN(31, "SDMMC3_CLK"), 555 PINCTRL_PIN(32, "SDMMC3_D3"), 556 PINCTRL_PIN(33, "SDMMC3_D2"), 557 PINCTRL_PIN(34, "SDMMC3_CMD"), 558 PINCTRL_PIN(35, "SDMMC3_D0"), 559 560 PINCTRL_PIN(45, "MF_LPC_AD2"), 561 PINCTRL_PIN(46, "LPC_CLKRUNB"), 562 PINCTRL_PIN(47, "MF_LPC_AD0"), 563 PINCTRL_PIN(48, "LPC_FRAMEB"), 564 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 565 PINCTRL_PIN(50, "MF_LPC_AD3"), 566 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 567 PINCTRL_PIN(52, "MF_LPC_AD1"), 568 569 PINCTRL_PIN(60, "SPI1_MISO"), 570 PINCTRL_PIN(61, "SPI1_CSO_B"), 571 PINCTRL_PIN(62, "SPI1_CLK"), 572 PINCTRL_PIN(63, "MMC1_D6"), 573 PINCTRL_PIN(64, "SPI1_MOSI"), 574 PINCTRL_PIN(65, "MMC1_D5"), 575 PINCTRL_PIN(66, "SPI1_CS1_B"), 576 PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 577 PINCTRL_PIN(68, "MMC1_D7"), 578 PINCTRL_PIN(69, "MMC1_RCLK"), 579 580 PINCTRL_PIN(75, "USB_OC1_B"), 581 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 582 PINCTRL_PIN(77, "GPIO_ALERT"), 583 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 584 PINCTRL_PIN(79, "ILB_SERIRQ"), 585 PINCTRL_PIN(80, "USB_OC0_B"), 586 PINCTRL_PIN(81, "SDMMC3_CD_B"), 587 PINCTRL_PIN(82, "SPKR"), 588 PINCTRL_PIN(83, "SUSPWRDNACK"), 589 PINCTRL_PIN(84, "SPARE_PIN"), 590 PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 591}; 592 593static const unsigned southeast_pwm0_pins[] = { 5 }; 594static const unsigned southeast_pwm1_pins[] = { 1 }; 595static const unsigned southeast_sdmmc1_pins[] = { 596 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 597}; 598static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 599static const unsigned southeast_sdmmc3_pins[] = { 600 30, 31, 32, 33, 34, 35, 78, 81, 85, 601}; 602static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 603static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 604 605static const struct chv_pingroup southeast_groups[] = { 606 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false), 607 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false), 608 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), 609 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), 610 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), 611 PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false), 612 PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false), 613}; 614 615static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 616static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 617static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 618static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 619static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 620static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 621static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 622 623static const struct chv_function southeast_functions[] = { 624 FUNCTION("pwm0", southeast_pwm0_groups), 625 FUNCTION("pwm1", southeast_pwm1_groups), 626 FUNCTION("sdmmc1", southeast_sdmmc1_groups), 627 FUNCTION("sdmmc2", southeast_sdmmc2_groups), 628 FUNCTION("sdmmc3", southeast_sdmmc3_groups), 629 FUNCTION("spi1", southeast_spi1_groups), 630 FUNCTION("spi2", southeast_spi2_groups), 631}; 632 633static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { 634 GPIO_PINRANGE(0, 7), 635 GPIO_PINRANGE(15, 26), 636 GPIO_PINRANGE(30, 35), 637 GPIO_PINRANGE(45, 52), 638 GPIO_PINRANGE(60, 69), 639 GPIO_PINRANGE(75, 85), 640}; 641 642static const struct chv_community southeast_community = { 643 .uid = "4", 644 .pins = southeast_pins, 645 .npins = ARRAY_SIZE(southeast_pins), 646 .groups = southeast_groups, 647 .ngroups = ARRAY_SIZE(southeast_groups), 648 .functions = southeast_functions, 649 .nfunctions = ARRAY_SIZE(southeast_functions), 650 .gpio_ranges = southeast_gpio_ranges, 651 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), 652 .ngpios = ARRAY_SIZE(southeast_pins), 653}; 654 655static const struct chv_community *chv_communities[] = { 656 &southwest_community, 657 &north_community, 658 &east_community, 659 &southeast_community, 660}; 661 662static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset, 663 unsigned reg) 664{ 665 unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 666 unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 667 668 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no + 669 GPIO_REGS_SIZE * pad_no; 670 671 return pctrl->regs + offset + reg; 672} 673 674static void chv_writel(u32 value, void __iomem *reg) 675{ 676 writel(value, reg); 677 /* simple readback to confirm the bus transferring done */ 678 readl(reg); 679} 680 681/* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 682static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset) 683{ 684 void __iomem *reg; 685 686 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 687 return readl(reg) & CHV_PADCTRL1_CFGLOCK; 688} 689 690static int chv_get_groups_count(struct pinctrl_dev *pctldev) 691{ 692 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 693 694 return pctrl->community->ngroups; 695} 696 697static const char *chv_get_group_name(struct pinctrl_dev *pctldev, 698 unsigned group) 699{ 700 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 701 702 return pctrl->community->groups[group].name; 703} 704 705static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 706 const unsigned **pins, unsigned *npins) 707{ 708 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 709 710 *pins = pctrl->community->groups[group].pins; 711 *npins = pctrl->community->groups[group].npins; 712 return 0; 713} 714 715static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 716 unsigned offset) 717{ 718 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 719 unsigned long flags; 720 u32 ctrl0, ctrl1; 721 bool locked; 722 723 raw_spin_lock_irqsave(&pctrl->lock, flags); 724 725 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 726 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); 727 locked = chv_pad_locked(pctrl, offset); 728 729 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 730 731 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 732 seq_puts(s, "GPIO "); 733 } else { 734 u32 mode; 735 736 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 737 mode >>= CHV_PADCTRL0_PMODE_SHIFT; 738 739 seq_printf(s, "mode %d ", mode); 740 } 741 742 seq_printf(s, "ctrl0 0x%08x ctrl1 0x%08x", ctrl0, ctrl1); 743 744 if (locked) 745 seq_puts(s, " [LOCKED]"); 746} 747 748static const struct pinctrl_ops chv_pinctrl_ops = { 749 .get_groups_count = chv_get_groups_count, 750 .get_group_name = chv_get_group_name, 751 .get_group_pins = chv_get_group_pins, 752 .pin_dbg_show = chv_pin_dbg_show, 753}; 754 755static int chv_get_functions_count(struct pinctrl_dev *pctldev) 756{ 757 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 758 759 return pctrl->community->nfunctions; 760} 761 762static const char *chv_get_function_name(struct pinctrl_dev *pctldev, 763 unsigned function) 764{ 765 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 766 767 return pctrl->community->functions[function].name; 768} 769 770static int chv_get_function_groups(struct pinctrl_dev *pctldev, 771 unsigned function, 772 const char * const **groups, 773 unsigned * const ngroups) 774{ 775 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 776 777 *groups = pctrl->community->functions[function].groups; 778 *ngroups = pctrl->community->functions[function].ngroups; 779 return 0; 780} 781 782static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 783 unsigned group) 784{ 785 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 786 const struct chv_pingroup *grp; 787 unsigned long flags; 788 int i; 789 790 grp = &pctrl->community->groups[group]; 791 792 raw_spin_lock_irqsave(&pctrl->lock, flags); 793 794 /* Check first that the pad is not locked */ 795 for (i = 0; i < grp->npins; i++) { 796 if (chv_pad_locked(pctrl, grp->pins[i])) { 797 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", 798 grp->pins[i]); 799 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 800 return -EBUSY; 801 } 802 } 803 804 for (i = 0; i < grp->npins; i++) { 805 const struct chv_alternate_function *altfunc = &grp->altfunc; 806 int pin = grp->pins[i]; 807 void __iomem *reg; 808 u32 value; 809 810 /* Check if there is pin-specific config */ 811 if (grp->overrides) { 812 int j; 813 814 for (j = 0; j < grp->noverrides; j++) { 815 if (grp->overrides[j].pin == pin) { 816 altfunc = &grp->overrides[j]; 817 break; 818 } 819 } 820 } 821 822 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 823 value = readl(reg); 824 /* Disable GPIO mode */ 825 value &= ~CHV_PADCTRL0_GPIOEN; 826 /* Set to desired mode */ 827 value &= ~CHV_PADCTRL0_PMODE_MASK; 828 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; 829 chv_writel(value, reg); 830 831 /* Update for invert_oe */ 832 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 833 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; 834 if (altfunc->invert_oe) 835 value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 836 chv_writel(value, reg); 837 838 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", 839 pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); 840 } 841 842 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 843 844 return 0; 845} 846 847static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 848 struct pinctrl_gpio_range *range, 849 unsigned offset) 850{ 851 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 852 unsigned long flags; 853 void __iomem *reg; 854 u32 value; 855 856 raw_spin_lock_irqsave(&pctrl->lock, flags); 857 858 if (chv_pad_locked(pctrl, offset)) { 859 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 860 if (!(value & CHV_PADCTRL0_GPIOEN)) { 861 /* Locked so cannot enable */ 862 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 863 return -EBUSY; 864 } 865 } else { 866 int i; 867 868 /* Reset the interrupt mapping */ 869 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { 870 if (pctrl->intr_lines[i] == offset) { 871 pctrl->intr_lines[i] = 0; 872 break; 873 } 874 } 875 876 /* Disable interrupt generation */ 877 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 878 value = readl(reg); 879 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 880 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 881 chv_writel(value, reg); 882 883 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 884 value = readl(reg); 885 886 /* 887 * If the pin is in HiZ mode (both TX and RX buffers are 888 * disabled) we turn it to be input now. 889 */ 890 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 891 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 892 value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 893 value |= CHV_PADCTRL0_GPIOCFG_GPI << 894 CHV_PADCTRL0_GPIOCFG_SHIFT; 895 } 896 897 /* Switch to a GPIO mode */ 898 value |= CHV_PADCTRL0_GPIOEN; 899 chv_writel(value, reg); 900 } 901 902 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 903 904 return 0; 905} 906 907static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 908 struct pinctrl_gpio_range *range, 909 unsigned offset) 910{ 911 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 912 unsigned long flags; 913 void __iomem *reg; 914 u32 value; 915 916 raw_spin_lock_irqsave(&pctrl->lock, flags); 917 918 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 919 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN; 920 chv_writel(value, reg); 921 922 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 923} 924 925static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 926 struct pinctrl_gpio_range *range, 927 unsigned offset, bool input) 928{ 929 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 930 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 931 unsigned long flags; 932 u32 ctrl0; 933 934 raw_spin_lock_irqsave(&pctrl->lock, flags); 935 936 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; 937 if (input) 938 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 939 else 940 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 941 chv_writel(ctrl0, reg); 942 943 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 944 945 return 0; 946} 947 948static const struct pinmux_ops chv_pinmux_ops = { 949 .get_functions_count = chv_get_functions_count, 950 .get_function_name = chv_get_function_name, 951 .get_function_groups = chv_get_function_groups, 952 .set_mux = chv_pinmux_set_mux, 953 .gpio_request_enable = chv_gpio_request_enable, 954 .gpio_disable_free = chv_gpio_disable_free, 955 .gpio_set_direction = chv_gpio_set_direction, 956}; 957 958static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, 959 unsigned long *config) 960{ 961 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 962 enum pin_config_param param = pinconf_to_config_param(*config); 963 unsigned long flags; 964 u32 ctrl0, ctrl1; 965 u16 arg = 0; 966 u32 term; 967 968 raw_spin_lock_irqsave(&pctrl->lock, flags); 969 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 970 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 971 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 972 973 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 974 975 switch (param) { 976 case PIN_CONFIG_BIAS_DISABLE: 977 if (term) 978 return -EINVAL; 979 break; 980 981 case PIN_CONFIG_BIAS_PULL_UP: 982 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 983 return -EINVAL; 984 985 switch (term) { 986 case CHV_PADCTRL0_TERM_20K: 987 arg = 20000; 988 break; 989 case CHV_PADCTRL0_TERM_5K: 990 arg = 5000; 991 break; 992 case CHV_PADCTRL0_TERM_1K: 993 arg = 1000; 994 break; 995 } 996 997 break; 998 999 case PIN_CONFIG_BIAS_PULL_DOWN: 1000 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 1001 return -EINVAL; 1002 1003 switch (term) { 1004 case CHV_PADCTRL0_TERM_20K: 1005 arg = 20000; 1006 break; 1007 case CHV_PADCTRL0_TERM_5K: 1008 arg = 5000; 1009 break; 1010 } 1011 1012 break; 1013 1014 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1015 if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 1016 return -EINVAL; 1017 break; 1018 1019 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 1020 u32 cfg; 1021 1022 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1023 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1024 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 1025 return -EINVAL; 1026 1027 break; 1028 } 1029 1030 default: 1031 return -ENOTSUPP; 1032 } 1033 1034 *config = pinconf_to_config_packed(param, arg); 1035 return 0; 1036} 1037 1038static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin, 1039 enum pin_config_param param, u16 arg) 1040{ 1041 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 1042 unsigned long flags; 1043 u32 ctrl0, pull; 1044 1045 raw_spin_lock_irqsave(&pctrl->lock, flags); 1046 ctrl0 = readl(reg); 1047 1048 switch (param) { 1049 case PIN_CONFIG_BIAS_DISABLE: 1050 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1051 break; 1052 1053 case PIN_CONFIG_BIAS_PULL_UP: 1054 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1055 1056 switch (arg) { 1057 case 1000: 1058 /* For 1k there is only pull up */ 1059 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 1060 break; 1061 case 5000: 1062 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1063 break; 1064 case 20000: 1065 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1066 break; 1067 default: 1068 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1069 return -EINVAL; 1070 } 1071 1072 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 1073 break; 1074 1075 case PIN_CONFIG_BIAS_PULL_DOWN: 1076 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1077 1078 switch (arg) { 1079 case 5000: 1080 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1081 break; 1082 case 20000: 1083 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1084 break; 1085 default: 1086 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1087 return -EINVAL; 1088 } 1089 1090 ctrl0 |= pull; 1091 break; 1092 1093 default: 1094 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1095 return -EINVAL; 1096 } 1097 1098 chv_writel(ctrl0, reg); 1099 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1100 1101 return 0; 1102} 1103 1104static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin, 1105 unsigned long *configs, unsigned nconfigs) 1106{ 1107 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1108 enum pin_config_param param; 1109 int i, ret; 1110 u16 arg; 1111 1112 if (chv_pad_locked(pctrl, pin)) 1113 return -EBUSY; 1114 1115 for (i = 0; i < nconfigs; i++) { 1116 param = pinconf_to_config_param(configs[i]); 1117 arg = pinconf_to_config_argument(configs[i]); 1118 1119 switch (param) { 1120 case PIN_CONFIG_BIAS_DISABLE: 1121 case PIN_CONFIG_BIAS_PULL_UP: 1122 case PIN_CONFIG_BIAS_PULL_DOWN: 1123 ret = chv_config_set_pull(pctrl, pin, param, arg); 1124 if (ret) 1125 return ret; 1126 break; 1127 1128 default: 1129 return -ENOTSUPP; 1130 } 1131 1132 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, 1133 param, arg); 1134 } 1135 1136 return 0; 1137} 1138 1139static const struct pinconf_ops chv_pinconf_ops = { 1140 .is_generic = true, 1141 .pin_config_set = chv_config_set, 1142 .pin_config_get = chv_config_get, 1143}; 1144 1145static struct pinctrl_desc chv_pinctrl_desc = { 1146 .pctlops = &chv_pinctrl_ops, 1147 .pmxops = &chv_pinmux_ops, 1148 .confops = &chv_pinconf_ops, 1149 .owner = THIS_MODULE, 1150}; 1151 1152static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl, 1153 unsigned offset) 1154{ 1155 return pctrl->community->pins[offset].number; 1156} 1157 1158static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) 1159{ 1160 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); 1161 int pin = chv_gpio_offset_to_pin(pctrl, offset); 1162 unsigned long flags; 1163 u32 ctrl0, cfg; 1164 1165 raw_spin_lock_irqsave(&pctrl->lock, flags); 1166 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1167 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1168 1169 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1170 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1171 1172 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 1173 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 1174 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 1175} 1176 1177static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1178{ 1179 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); 1180 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); 1181 unsigned long flags; 1182 void __iomem *reg; 1183 u32 ctrl0; 1184 1185 raw_spin_lock_irqsave(&pctrl->lock, flags); 1186 1187 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 1188 ctrl0 = readl(reg); 1189 1190 if (value) 1191 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 1192 else 1193 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 1194 1195 chv_writel(ctrl0, reg); 1196 1197 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1198} 1199 1200static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 1201{ 1202 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); 1203 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); 1204 u32 ctrl0, direction; 1205 unsigned long flags; 1206 1207 raw_spin_lock_irqsave(&pctrl->lock, flags); 1208 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1209 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1210 1211 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1212 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1213 1214 return direction != CHV_PADCTRL0_GPIOCFG_GPO; 1215} 1216 1217static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1218{ 1219 return pinctrl_gpio_direction_input(chip->base + offset); 1220} 1221 1222static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 1223 int value) 1224{ 1225 chv_gpio_set(chip, offset, value); 1226 return pinctrl_gpio_direction_output(chip->base + offset); 1227} 1228 1229static const struct gpio_chip chv_gpio_chip = { 1230 .owner = THIS_MODULE, 1231 .request = gpiochip_generic_request, 1232 .free = gpiochip_generic_free, 1233 .get_direction = chv_gpio_get_direction, 1234 .direction_input = chv_gpio_direction_input, 1235 .direction_output = chv_gpio_direction_output, 1236 .get = chv_gpio_get, 1237 .set = chv_gpio_set, 1238}; 1239 1240static void chv_gpio_irq_ack(struct irq_data *d) 1241{ 1242 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1243 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); 1244 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 1245 u32 intr_line; 1246 1247 raw_spin_lock(&pctrl->lock); 1248 1249 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1250 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1251 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1252 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); 1253 1254 raw_spin_unlock(&pctrl->lock); 1255} 1256 1257static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 1258{ 1259 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1260 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); 1261 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 1262 u32 value, intr_line; 1263 unsigned long flags; 1264 1265 raw_spin_lock_irqsave(&pctrl->lock, flags); 1266 1267 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1268 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1269 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1270 1271 value = readl(pctrl->regs + CHV_INTMASK); 1272 if (mask) 1273 value &= ~BIT(intr_line); 1274 else 1275 value |= BIT(intr_line); 1276 chv_writel(value, pctrl->regs + CHV_INTMASK); 1277 1278 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1279} 1280 1281static void chv_gpio_irq_mask(struct irq_data *d) 1282{ 1283 chv_gpio_irq_mask_unmask(d, true); 1284} 1285 1286static void chv_gpio_irq_unmask(struct irq_data *d) 1287{ 1288 chv_gpio_irq_mask_unmask(d, false); 1289} 1290 1291static unsigned chv_gpio_irq_startup(struct irq_data *d) 1292{ 1293 /* 1294 * Check if the interrupt has been requested with 0 as triggering 1295 * type. In that case it is assumed that the current values 1296 * programmed to the hardware are used (e.g BIOS configured 1297 * defaults). 1298 * 1299 * In that case ->irq_set_type() will never be called so we need to 1300 * read back the values from hardware now, set correct flow handler 1301 * and update mappings before the interrupt is being used. 1302 */ 1303 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { 1304 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1305 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); 1306 unsigned offset = irqd_to_hwirq(d); 1307 int pin = chv_gpio_offset_to_pin(pctrl, offset); 1308 irq_flow_handler_t handler; 1309 unsigned long flags; 1310 u32 intsel, value; 1311 1312 raw_spin_lock_irqsave(&pctrl->lock, flags); 1313 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1314 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1315 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1316 1317 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 1318 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1319 handler = handle_level_irq; 1320 else 1321 handler = handle_edge_irq; 1322 1323 if (!pctrl->intr_lines[intsel]) { 1324 irq_set_handler_locked(d, handler); 1325 pctrl->intr_lines[intsel] = offset; 1326 } 1327 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1328 } 1329 1330 chv_gpio_irq_unmask(d); 1331 return 0; 1332} 1333 1334static int chv_gpio_irq_type(struct irq_data *d, unsigned type) 1335{ 1336 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1337 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); 1338 unsigned offset = irqd_to_hwirq(d); 1339 int pin = chv_gpio_offset_to_pin(pctrl, offset); 1340 unsigned long flags; 1341 u32 value; 1342 1343 raw_spin_lock_irqsave(&pctrl->lock, flags); 1344 1345 /* 1346 * Pins which can be used as shared interrupt are configured in 1347 * BIOS. Driver trusts BIOS configurations and assigns different 1348 * handler according to the irq type. 1349 * 1350 * Driver needs to save the mapping between each pin and 1351 * its interrupt line. 1352 * 1. If the pin cfg is locked in BIOS: 1353 * Trust BIOS has programmed IntWakeCfg bits correctly, 1354 * driver just needs to save the mapping. 1355 * 2. If the pin cfg is not locked in BIOS: 1356 * Driver programs the IntWakeCfg bits and save the mapping. 1357 */ 1358 if (!chv_pad_locked(pctrl, pin)) { 1359 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1360 1361 value = readl(reg); 1362 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 1363 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 1364 1365 if (type & IRQ_TYPE_EDGE_BOTH) { 1366 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1367 value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 1368 else if (type & IRQ_TYPE_EDGE_RISING) 1369 value |= CHV_PADCTRL1_INTWAKECFG_RISING; 1370 else if (type & IRQ_TYPE_EDGE_FALLING) 1371 value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 1372 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1373 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 1374 if (type & IRQ_TYPE_LEVEL_LOW) 1375 value |= CHV_PADCTRL1_INVRXTX_RXDATA; 1376 } 1377 1378 chv_writel(value, reg); 1379 } 1380 1381 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1382 value &= CHV_PADCTRL0_INTSEL_MASK; 1383 value >>= CHV_PADCTRL0_INTSEL_SHIFT; 1384 1385 pctrl->intr_lines[value] = offset; 1386 1387 if (type & IRQ_TYPE_EDGE_BOTH) 1388 irq_set_handler_locked(d, handle_edge_irq); 1389 else if (type & IRQ_TYPE_LEVEL_MASK) 1390 irq_set_handler_locked(d, handle_level_irq); 1391 1392 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1393 1394 return 0; 1395} 1396 1397static struct irq_chip chv_gpio_irqchip = { 1398 .name = "chv-gpio", 1399 .irq_startup = chv_gpio_irq_startup, 1400 .irq_ack = chv_gpio_irq_ack, 1401 .irq_mask = chv_gpio_irq_mask, 1402 .irq_unmask = chv_gpio_irq_unmask, 1403 .irq_set_type = chv_gpio_irq_type, 1404 .flags = IRQCHIP_SKIP_SET_WAKE, 1405}; 1406 1407static void chv_gpio_irq_handler(struct irq_desc *desc) 1408{ 1409 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1410 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); 1411 struct irq_chip *chip = irq_desc_get_chip(desc); 1412 unsigned long pending; 1413 u32 intr_line; 1414 1415 chained_irq_enter(chip, desc); 1416 1417 pending = readl(pctrl->regs + CHV_INTSTAT); 1418 for_each_set_bit(intr_line, &pending, 16) { 1419 unsigned irq, offset; 1420 1421 offset = pctrl->intr_lines[intr_line]; 1422 irq = irq_find_mapping(gc->irqdomain, offset); 1423 generic_handle_irq(irq); 1424 } 1425 1426 chained_irq_exit(chip, desc); 1427} 1428 1429static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 1430{ 1431 const struct chv_gpio_pinrange *range; 1432 struct gpio_chip *chip = &pctrl->chip; 1433 int ret, i, offset; 1434 1435 *chip = chv_gpio_chip; 1436 1437 chip->ngpio = pctrl->community->ngpios; 1438 chip->label = dev_name(pctrl->dev); 1439 chip->dev = pctrl->dev; 1440 chip->base = -1; 1441 1442 ret = gpiochip_add(chip); 1443 if (ret) { 1444 dev_err(pctrl->dev, "Failed to register gpiochip\n"); 1445 return ret; 1446 } 1447 1448 for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) { 1449 range = &pctrl->community->gpio_ranges[i]; 1450 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset, 1451 range->base, range->npins); 1452 if (ret) { 1453 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1454 goto fail; 1455 } 1456 1457 offset += range->npins; 1458 } 1459 1460 /* Mask and clear all interrupts */ 1461 chv_writel(0, pctrl->regs + CHV_INTMASK); 1462 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 1463 1464 ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, 1465 handle_simple_irq, IRQ_TYPE_NONE); 1466 if (ret) { 1467 dev_err(pctrl->dev, "failed to add IRQ chip\n"); 1468 goto fail; 1469 } 1470 1471 gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, 1472 chv_gpio_irq_handler); 1473 return 0; 1474 1475fail: 1476 gpiochip_remove(chip); 1477 1478 return ret; 1479} 1480 1481static int chv_pinctrl_probe(struct platform_device *pdev) 1482{ 1483 struct chv_pinctrl *pctrl; 1484 struct acpi_device *adev; 1485 struct resource *res; 1486 int ret, irq, i; 1487 1488 adev = ACPI_COMPANION(&pdev->dev); 1489 if (!adev) 1490 return -ENODEV; 1491 1492 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1493 if (!pctrl) 1494 return -ENOMEM; 1495 1496 for (i = 0; i < ARRAY_SIZE(chv_communities); i++) 1497 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) { 1498 pctrl->community = chv_communities[i]; 1499 break; 1500 } 1501 if (i == ARRAY_SIZE(chv_communities)) 1502 return -ENODEV; 1503 1504 raw_spin_lock_init(&pctrl->lock); 1505 pctrl->dev = &pdev->dev; 1506 1507#ifdef CONFIG_PM_SLEEP 1508 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev, 1509 pctrl->community->npins, sizeof(*pctrl->saved_pin_context), 1510 GFP_KERNEL); 1511 if (!pctrl->saved_pin_context) 1512 return -ENOMEM; 1513#endif 1514 1515 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1516 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 1517 if (IS_ERR(pctrl->regs)) 1518 return PTR_ERR(pctrl->regs); 1519 1520 irq = platform_get_irq(pdev, 0); 1521 if (irq < 0) { 1522 dev_err(&pdev->dev, "failed to get interrupt number\n"); 1523 return irq; 1524 } 1525 1526 pctrl->pctldesc = chv_pinctrl_desc; 1527 pctrl->pctldesc.name = dev_name(&pdev->dev); 1528 pctrl->pctldesc.pins = pctrl->community->pins; 1529 pctrl->pctldesc.npins = pctrl->community->npins; 1530 1531 pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl); 1532 if (IS_ERR(pctrl->pctldev)) { 1533 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1534 return PTR_ERR(pctrl->pctldev); 1535 } 1536 1537 ret = chv_gpio_probe(pctrl, irq); 1538 if (ret) { 1539 pinctrl_unregister(pctrl->pctldev); 1540 return ret; 1541 } 1542 1543 platform_set_drvdata(pdev, pctrl); 1544 1545 return 0; 1546} 1547 1548static int chv_pinctrl_remove(struct platform_device *pdev) 1549{ 1550 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1551 1552 gpiochip_remove(&pctrl->chip); 1553 pinctrl_unregister(pctrl->pctldev); 1554 1555 return 0; 1556} 1557 1558#ifdef CONFIG_PM_SLEEP 1559static int chv_pinctrl_suspend(struct device *dev) 1560{ 1561 struct platform_device *pdev = to_platform_device(dev); 1562 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1563 int i; 1564 1565 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); 1566 1567 for (i = 0; i < pctrl->community->npins; i++) { 1568 const struct pinctrl_pin_desc *desc; 1569 struct chv_pin_context *ctx; 1570 void __iomem *reg; 1571 1572 desc = &pctrl->community->pins[i]; 1573 if (chv_pad_locked(pctrl, desc->number)) 1574 continue; 1575 1576 ctx = &pctrl->saved_pin_context[i]; 1577 1578 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 1579 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 1580 1581 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 1582 ctx->padctrl1 = readl(reg); 1583 } 1584 1585 return 0; 1586} 1587 1588static int chv_pinctrl_resume(struct device *dev) 1589{ 1590 struct platform_device *pdev = to_platform_device(dev); 1591 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1592 int i; 1593 1594 /* 1595 * Mask all interrupts before restoring per-pin configuration 1596 * registers because we don't know in which state BIOS left them 1597 * upon exiting suspend. 1598 */ 1599 chv_writel(0, pctrl->regs + CHV_INTMASK); 1600 1601 for (i = 0; i < pctrl->community->npins; i++) { 1602 const struct pinctrl_pin_desc *desc; 1603 const struct chv_pin_context *ctx; 1604 void __iomem *reg; 1605 u32 val; 1606 1607 desc = &pctrl->community->pins[i]; 1608 if (chv_pad_locked(pctrl, desc->number)) 1609 continue; 1610 1611 ctx = &pctrl->saved_pin_context[i]; 1612 1613 /* Only restore if our saved state differs from the current */ 1614 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 1615 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 1616 if (ctx->padctrl0 != val) { 1617 chv_writel(ctx->padctrl0, reg); 1618 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", 1619 desc->number, readl(reg)); 1620 } 1621 1622 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 1623 val = readl(reg); 1624 if (ctx->padctrl1 != val) { 1625 chv_writel(ctx->padctrl1, reg); 1626 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", 1627 desc->number, readl(reg)); 1628 } 1629 } 1630 1631 /* 1632 * Now that all pins are restored to known state, we can restore 1633 * the interrupt mask register as well. 1634 */ 1635 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 1636 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); 1637 1638 return 0; 1639} 1640#endif 1641 1642static const struct dev_pm_ops chv_pinctrl_pm_ops = { 1643 SET_LATE_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend, chv_pinctrl_resume) 1644}; 1645 1646static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 1647 { "INT33FF" }, 1648 { } 1649}; 1650MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 1651 1652static struct platform_driver chv_pinctrl_driver = { 1653 .probe = chv_pinctrl_probe, 1654 .remove = chv_pinctrl_remove, 1655 .driver = { 1656 .name = "cherryview-pinctrl", 1657 .pm = &chv_pinctrl_pm_ops, 1658 .acpi_match_table = chv_pinctrl_acpi_match, 1659 }, 1660}; 1661 1662static int __init chv_pinctrl_init(void) 1663{ 1664 return platform_driver_register(&chv_pinctrl_driver); 1665} 1666subsys_initcall(chv_pinctrl_init); 1667 1668static void __exit chv_pinctrl_exit(void) 1669{ 1670 platform_driver_unregister(&chv_pinctrl_driver); 1671} 1672module_exit(chv_pinctrl_exit); 1673 1674MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1675MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 1676MODULE_LICENSE("GPL v2"); 1677