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Searched refs:csr (Results 1 – 161 of 161) sorted by relevance

/linux-4.4.14/arch/alpha/kernel/
Dcore_tsunami.c180 volatile unsigned long *csr; in tsunami_pci_tbi() local
185 csr = &pchip->tlbia.csr; in tsunami_pci_tbi()
187 csr = &pchip->tlbiv.csr; in tsunami_pci_tbi()
193 *csr = value; in tsunami_pci_tbi()
195 *csr; in tsunami_pci_tbi()
226 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write()
230 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write()
231 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; in tsunami_probe_write()
232 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ in tsunami_probe_write()
250 if (tsunami_probe_read(&pchip->pctl.csr) == 0) in tsunami_init_one_pchip()
[all …]
Dcore_wildfire.c118 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; in wildfire_init_hose()
119 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; in wildfire_init_hose()
120 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); in wildfire_init_hose()
122 pci->pci_window[1].wbase.csr = 0x40000000 | 1; in wildfire_init_hose()
123 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
124 pci->pci_window[1].tbase.csr = 0; in wildfire_init_hose()
126 pci->pci_window[2].wbase.csr = 0x80000000 | 1; in wildfire_init_hose()
127 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
128 pci->pci_window[2].tbase.csr = 0x40000000; in wildfire_init_hose()
130 pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3; in wildfire_init_hose()
[all …]
Dcore_titan.c207 volatile unsigned long *csr; in titan_pci_tbi() local
220 csr = &port->port_specific.g.gtlbia.csr; in titan_pci_tbi()
222 csr = &port->port_specific.g.gtlbiv.csr; in titan_pci_tbi()
229 *csr = value; in titan_pci_tbi()
231 *csr; in titan_pci_tbi()
240 pctl.pctl_q_whole = port->pctl.csr; in titan_query_agp()
293 saved_config[index].wsba[0] = port->wsba[0].csr; in titan_init_one_pachip_port()
294 saved_config[index].wsm[0] = port->wsm[0].csr; in titan_init_one_pachip_port()
295 saved_config[index].tba[0] = port->tba[0].csr; in titan_init_one_pachip_port()
297 saved_config[index].wsba[1] = port->wsba[1].csr; in titan_init_one_pachip_port()
[all …]
Dsys_marvel.c96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
98 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; in io7_get_irq_ctl()
174 volatile unsigned long *csr, in io7_redirect_irq() argument
179 val = *csr; in io7_redirect_irq()
183 *csr = val; in io7_redirect_irq()
185 *csr; in io7_redirect_irq()
196 val = io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
200 io7->csrs->PO7_LSI_CTL[which].csr = val; in io7_redirect_one_lsi()
202 io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
213 val = io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
[all …]
Derr_marvel.c817 err_sum |= io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
821 err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr; in marvel_find_io7_with_error()
842 io->io_asic_rev = io7->csrs->IO_ASIC_REV.csr; in marvel_find_io7_with_error()
843 io->io_sys_rev = io7->csrs->IO_SYS_REV.csr; in marvel_find_io7_with_error()
844 io->io7_uph = io7->csrs->IO7_UPH.csr; in marvel_find_io7_with_error()
845 io->hpi_ctl = io7->csrs->HPI_CTL.csr; in marvel_find_io7_with_error()
846 io->crd_ctl = io7->csrs->CRD_CTL.csr; in marvel_find_io7_with_error()
847 io->hei_ctl = io7->csrs->HEI_CTL.csr; in marvel_find_io7_with_error()
848 io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
849 io->po7_uncrr_sym = io7->csrs->PO7_UNCRR_SYM.csr; in marvel_find_io7_with_error()
[all …]
Dcore_marvel.c62 q = ev7csr->csr; in read_ev7_csr()
74 ev7csr->csr = q; in write_ev7_csr()
179 csrs->POx_ERR_SUM.csr = -1UL; in io7_clear_errors()
180 csrs->POx_TLB_ERR.csr = -1UL; in io7_clear_errors()
181 csrs->POx_SPL_COMPLT.csr = -1UL; in io7_clear_errors()
182 csrs->POx_TRANS_SUM.csr = -1UL; in io7_clear_errors()
190 p7csrs->PO7_ERROR_SUM.csr = -1UL; in io7_clear_errors()
191 p7csrs->PO7_UNCRR_SYM.csr = -1UL; in io7_clear_errors()
192 p7csrs->PO7_CRRCT_SYM.csr = -1UL; in io7_clear_errors()
263 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr; in io7_init_hose()
[all …]
Dsys_titan.c83 dim0 = &cchip->dim0.csr; in titan_update_irq_hw()
84 dim1 = &cchip->dim1.csr; in titan_update_irq_hw()
85 dim2 = &cchip->dim2.csr; in titan_update_irq_hw()
86 dim3 = &cchip->dim3.csr; in titan_update_irq_hw()
103 dimB = &cchip->dim0.csr; in titan_update_irq_hw()
104 if (bcpu == 1) dimB = &cchip->dim1.csr; in titan_update_irq_hw()
105 else if (bcpu == 2) dimB = &cchip->dim2.csr; in titan_update_irq_hw()
106 else if (bcpu == 3) dimB = &cchip->dim3.csr; in titan_update_irq_hw()
Dsys_dp264.c68 dim0 = &cchip->dim0.csr; in tsunami_update_irq_hw()
69 dim1 = &cchip->dim1.csr; in tsunami_update_irq_hw()
70 dim2 = &cchip->dim2.csr; in tsunami_update_irq_hw()
71 dim3 = &cchip->dim3.csr; in tsunami_update_irq_hw()
88 if (bcpu == 0) dimB = &cchip->dim0.csr; in tsunami_update_irq_hw()
89 else if (bcpu == 1) dimB = &cchip->dim1.csr; in tsunami_update_irq_hw()
90 else if (bcpu == 2) dimB = &cchip->dim2.csr; in tsunami_update_irq_hw()
91 else dimB = &cchip->dim3.csr; in tsunami_update_irq_hw()
197 pld = TSUNAMI_cchip->dir0.csr; in dp264_device_interrupt()
/linux-4.4.14/drivers/staging/gdm72xx/
Dgdm_qos.c99 qcb->csr[i].qos_buf_count = 0; in gdm_qos_init()
100 qcb->csr[i].enabled = false; in gdm_qos_init()
126 qcb->csr[i].qos_buf_count = 0; in gdm_qos_release_list()
127 qcb->csr[i].enabled = false; in gdm_qos_release_list()
142 static int chk_ipv4_rule(struct gdm_wimax_csr_s *csr, u8 *stream, u8 *port) in chk_ipv4_rule() argument
146 if (csr->classifier_rule_en&IPTYPEOFSERVICE) { in chk_ipv4_rule()
147 if (((stream[1] & csr->ip2s_mask) < csr->ip2s_lo) || in chk_ipv4_rule()
148 ((stream[1] & csr->ip2s_mask) > csr->ip2s_hi)) in chk_ipv4_rule()
152 if (csr->classifier_rule_en&PROTOCOL) { in chk_ipv4_rule()
153 if (stream[9] != csr->protocol) in chk_ipv4_rule()
[all …]
Dgdm_qos.h64 struct gdm_wimax_csr_s csr[QOS_MAX]; member
/linux-4.4.14/arch/sparc/kernel/
Debus.c73 u32 csr = 0; in ebus_dma_irq() local
76 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
77 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq()
80 if (csr & EBDMA_CSR_ERR_PEND) { in ebus_dma_irq()
84 } else if (csr & EBDMA_CSR_INT_PEND) { in ebus_dma_irq()
86 (csr & EBDMA_CSR_TC) ? in ebus_dma_irq()
98 u32 csr; in ebus_dma_register() local
112 csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT; in ebus_dma_register()
115 csr |= EBDMA_CSR_TCI_DIS; in ebus_dma_register()
117 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_register()
[all …]
Dpsycho_common.c254 u64 csr, csr_error_bits; in psycho_pcierr_intr_other() local
257 csr = upa_readq(pbm->pci_csr); in psycho_pcierr_intr_other()
258 csr_error_bits = csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR); in psycho_pcierr_intr_other()
261 upa_writeq(csr, pbm->pci_csr); in psycho_pcierr_intr_other()
Dpci_schizo.c582 unsigned long csr_reg, csr, csr_error_bits; in schizo_pcierr_intr_other() local
587 csr = upa_readq(csr_reg); in schizo_pcierr_intr_other()
589 csr & (SCHIZO_PCICTRL_BUS_UNUS | in schizo_pcierr_intr_other()
597 upa_writeq(csr, csr_reg); in schizo_pcierr_intr_other()
/linux-4.4.14/drivers/crypto/qat/qat_common/
Dicp_qat_hal.h102 #define SET_CAP_CSR(handle, csr, val) \ argument
103 ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)
104 #define GET_CAP_CSR(handle, csr) \ argument
105 ADF_CSR_RD(handle->hal_cap_g_ctl_csr_addr_v, csr)
106 #define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val) argument
107 #define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr) argument
111 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr)) argument
112 #define SET_AE_CSR(handle, ae, csr, val) \ argument
113 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
114 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) argument
Dadf_hw_arbiter.c91 void __iomem *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb() local
99 WRITE_CSR_ARB_SARCONFIG(csr, arb, arb_cfg); in adf_init_arb()
104 WRITE_CSR_ARB_WEIGHT(csr, arb, i, 0xFFFFFFFF); in adf_init_arb()
108 WRITE_CSR_ARB_RESPORDERING(csr, i, 0xFFFFFFFF); in adf_init_arb()
112 WRITE_CSR_ARB_WQCFG(csr, i, i); in adf_init_arb()
121 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, *(thd_2_arb_cfg + i)); in adf_init_arb()
144 void __iomem *csr; in adf_exit_arb() local
150 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb()
154 WRITE_CSR_ARB_SARCONFIG(csr, i, 0); in adf_exit_arb()
158 WRITE_CSR_ARB_WQCFG(csr, i, 0); in adf_exit_arb()
[all …]
Dadf_transport_debug.c89 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show() local
94 head = READ_CSR_RING_HEAD(csr, bank->bank_number, in adf_ring_show()
96 tail = READ_CSR_RING_TAIL(csr, bank->bank_number, in adf_ring_show()
98 empty = READ_CSR_E_STAT(csr, bank->bank_number); in adf_ring_show()
214 void __iomem *csr = bank->csr_addr; in adf_bank_show() local
220 head = READ_CSR_RING_HEAD(csr, bank->bank_number, in adf_bank_show()
222 tail = READ_CSR_RING_TAIL(csr, bank->bank_number, in adf_bank_show()
224 empty = READ_CSR_E_STAT(csr, bank->bank_number); in adf_bank_show()
Dqat_hal.c119 unsigned char ae, unsigned int csr, in qat_hal_rd_ae_csr() argument
125 *value = GET_AE_CSR(handle, ae, csr); in qat_hal_rd_ae_csr()
135 unsigned char ae, unsigned int csr, in qat_hal_wr_ae_csr() argument
141 SET_AE_CSR(handle, ae, csr, value); in qat_hal_wr_ae_csr()
167 unsigned int csr = (1 << ACS_ABO_BITPOS); in qat_hal_wait_cycles() local
175 qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &csr); in qat_hal_wait_cycles()
185 if (elapsed_cycles >= 8 && !(csr & (1 << ACS_ABO_BITPOS))) in qat_hal_wait_cycles()
201 unsigned int csr, new_csr; in qat_hal_set_ae_ctx_mode() local
209 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr); in qat_hal_set_ae_ctx_mode()
210 csr = IGNORE_W1C_MASK & csr; in qat_hal_set_ae_ctx_mode()
[all …]
Dadf_admin.c236 void __iomem *csr = pmisc->virt_addr; in adf_init_admin_comms() local
237 void __iomem *mailbox = csr + ADF_DH895XCC_MAILBOX_BASE_OFFSET; in adf_init_admin_comms()
264 ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGUR_OFFSET, reg_val >> 32); in adf_init_admin_comms()
265 ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGLR_OFFSET, reg_val); in adf_init_admin_comms()
/linux-4.4.14/drivers/usb/musb/
Dmusb_gadget.c262 u16 fifo_count = 0, csr; in txstate() local
281 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
287 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate()
289 musb_ep->end_point.name, csr); in txstate()
293 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate()
295 musb_ep->end_point.name, csr); in txstate()
301 csr); in txstate()
334 csr &= ~(MUSB_TXCSR_AUTOSET in txstate()
336 musb_writew(epio, MUSB_TXCSR, csr in txstate()
338 csr &= ~MUSB_TXCSR_DMAMODE; in txstate()
[all …]
Dmusb_gadget_ep0.c264 u16 csr; in service_zero_data_request() local
287 csr = musb_readw(regs, MUSB_TXCSR); in service_zero_data_request()
288 csr |= MUSB_TXCSR_CLRDATATOG | in service_zero_data_request()
290 csr &= ~(MUSB_TXCSR_P_SENDSTALL | in service_zero_data_request()
293 musb_writew(regs, MUSB_TXCSR, csr); in service_zero_data_request()
295 csr = musb_readw(regs, MUSB_RXCSR); in service_zero_data_request()
296 csr |= MUSB_RXCSR_CLRDATATOG | in service_zero_data_request()
298 csr &= ~(MUSB_RXCSR_P_SENDSTALL | in service_zero_data_request()
300 musb_writew(regs, MUSB_RXCSR, csr); in service_zero_data_request()
428 u16 csr; in service_zero_data_request() local
[all …]
Dmusb_cppi41.c61 u16 csr; in save_rx_toggle() local
69 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR); in save_rx_toggle()
70 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; in save_rx_toggle()
79 u16 csr; in update_rx_toggle() local
88 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in update_rx_toggle()
89 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; in update_rx_toggle()
97 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE; in update_rx_toggle()
98 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr); in update_rx_toggle()
111 u16 csr; in musb_is_tx_fifo_empty() local
114 csr = musb_readw(epio, MUSB_TXCSR); in musb_is_tx_fifo_empty()
[all …]
Dmusb_host.c114 u16 csr; in musb_h_tx_flush_fifo() local
117 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
118 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { in musb_h_tx_flush_fifo()
119 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY; in musb_h_tx_flush_fifo()
120 musb_writew(epio, MUSB_TXCSR, csr); in musb_h_tx_flush_fifo()
121 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
139 ep->epnum, csr)) in musb_h_tx_flush_fifo()
147 u16 csr; in musb_h_ep0_flush_fifo() local
152 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_ep0_flush_fifo()
153 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) in musb_h_ep0_flush_fifo()
[all …]
Dmusbhsdma.c118 u16 csr = 0; in configure_channel() local
124 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; in configure_channel()
127 csr |= MUSB_HSDMA_BURSTMODE_INCR16 in configure_channel()
130 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) in configure_channel()
144 csr); in configure_channel()
202 u16 csr; in dma_channel_abort() local
213 csr = musb_readw(mbase, offset); in dma_channel_abort()
214 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); in dma_channel_abort()
215 musb_writew(mbase, offset, csr); in dma_channel_abort()
216 csr &= ~MUSB_TXCSR_DMAMODE; in dma_channel_abort()
[all …]
Dtusb6010_omap.c193 u16 csr; in tusb_omap_dma_cb() local
198 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); in tusb_omap_dma_cb()
199 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY in tusb_omap_dma_cb()
201 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); in tusb_omap_dma_cb()
222 u16 csr; in tusb_omap_dma_program() local
373 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); in tusb_omap_dma_program()
374 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB in tusb_omap_dma_program()
376 csr &= ~MUSB_TXCSR_P_UNDERRUN; in tusb_omap_dma_program()
377 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); in tusb_omap_dma_program()
380 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in tusb_omap_dma_program()
[all …]
Dcppi_dma.c1088 int csr; in cppi_rx_scan() local
1102 csr = musb_readw(regs, MUSB_RXCSR); in cppi_rx_scan()
1103 if (csr & MUSB_RXCSR_DMAENAB) { in cppi_rx_scan()
1112 csr); in cppi_rx_scan()
1117 int csr; in cppi_rx_scan() local
1124 csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR); in cppi_rx_scan()
1127 && !(csr & MUSB_RXCSR_H_REQPKT)) { in cppi_rx_scan()
1128 csr |= MUSB_RXCSR_H_REQPKT; in cppi_rx_scan()
1130 MUSB_RXCSR_H_WZC_BITS | csr); in cppi_rx_scan()
1131 csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR); in cppi_rx_scan()
[all …]
Dux500_dma.c228 u16 csr; in ux500_dma_channel_abort() local
235 csr = musb_readw(epio, MUSB_TXCSR); in ux500_dma_channel_abort()
236 csr &= ~(MUSB_TXCSR_AUTOSET | in ux500_dma_channel_abort()
239 musb_writew(epio, MUSB_TXCSR, csr); in ux500_dma_channel_abort()
241 csr = musb_readw(epio, MUSB_RXCSR); in ux500_dma_channel_abort()
242 csr &= ~(MUSB_RXCSR_AUTOCLEAR | in ux500_dma_channel_abort()
245 musb_writew(epio, MUSB_RXCSR, csr); in ux500_dma_channel_abort()
/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_csr.c229 state = dev_priv->csr.state; in intel_csr_load_status_get()
246 dev_priv->csr.state = state; in intel_csr_load_status_set()
261 u32 *payload = dev_priv->csr.dmc_payload; in intel_csr_load_program()
279 fw_size = dev_priv->csr.dmc_fw_size; in intel_csr_load_program()
283 for (i = 0; i < dev_priv->csr.mmio_count; i++) { in intel_csr_load_program()
284 I915_WRITE(dev_priv->csr.mmioaddr[i], in intel_csr_load_program()
285 dev_priv->csr.mmiodata[i]); in intel_csr_load_program()
288 dev_priv->csr.state = FW_LOADED; in intel_csr_load_program()
299 struct intel_csr *csr = &dev_priv->csr; in finish_csr_load() local
308 i915_firmware_load_error_print(csr->fw_path, 0); in finish_csr_load()
[all …]
Di915_drv.h1719 struct intel_csr csr; member
Dintel_display.c5818 if (dev_priv->csr.dmc_payload) { in skl_uninit_cdclk()
/linux-4.4.14/arch/sh/kernel/cpu/
Dadc.c15 unsigned char csr; in adc_single() local
21 csr = __raw_readb(ADCSR); in adc_single()
22 csr = channel | ADCSR_ADST | ADCSR_CKS; in adc_single()
23 __raw_writeb(csr, ADCSR); in adc_single()
26 csr = __raw_readb(ADCSR); in adc_single()
27 } while ((csr & ADCSR_ADF) == 0); in adc_single()
29 csr &= ~(ADCSR_ADF | ADCSR_ADST); in adc_single()
30 __raw_writeb(csr, ADCSR); in adc_single()
/linux-4.4.14/drivers/watchdog/
Dshwdt.c89 u8 csr; in sh_wdt_start() local
99 csr = sh_wdt_read_csr(); in sh_wdt_start()
100 csr |= WTCSR_WT | clock_division_ratio; in sh_wdt_start()
101 sh_wdt_write_csr(csr); in sh_wdt_start()
113 csr = sh_wdt_read_csr(); in sh_wdt_start()
114 csr |= WTCSR_TME; in sh_wdt_start()
115 csr &= ~WTCSR_RSTS; in sh_wdt_start()
116 sh_wdt_write_csr(csr); in sh_wdt_start()
119 csr = sh_wdt_read_rstcsr(); in sh_wdt_start()
120 csr &= ~RSTCSR_RSTS; in sh_wdt_start()
[all …]
/linux-4.4.14/drivers/scsi/
Dsun3_scsi.c191 unsigned short csr = dregs->csr; in scsi_sun3_intr() local
195 dregs->csr &= ~CSR_DMA_ENABLE; in scsi_sun3_intr()
198 if(csr & ~CSR_GOOD) { in scsi_sun3_intr()
199 if(csr & CSR_DMA_BUSERR) { in scsi_sun3_intr()
203 if(csr & CSR_DMA_CONFLICT) { in scsi_sun3_intr()
209 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { in scsi_sun3_intr()
259 dregs->csr &= ~CSR_FIFO; in sun3scsi_dma_setup()
260 dregs->csr |= CSR_FIFO; in sun3scsi_dma_setup()
265 dregs->csr |= CSR_SEND; in sun3scsi_dma_setup()
267 dregs->csr &= ~CSR_SEND; in sun3scsi_dma_setup()
[all …]
Dsun3x_esp.c109 u32 csr; in sun3x_esp_dma_drain() local
112 csr = dma_read32(DMA_CSR); in sun3x_esp_dma_drain()
113 if (!(csr & DMA_FIFO_ISDRAIN)) in sun3x_esp_dma_drain()
116 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR); in sun3x_esp_dma_drain()
154 u32 csr; in sun3x_esp_send_dma_cmd() local
160 csr = dma_read32(DMA_CSR); in sun3x_esp_send_dma_cmd()
161 csr |= DMA_ENABLE; in sun3x_esp_send_dma_cmd()
163 csr |= DMA_ST_WRITE; in sun3x_esp_send_dma_cmd()
165 csr &= ~DMA_ST_WRITE; in sun3x_esp_send_dma_cmd()
166 dma_write32(csr, DMA_CSR); in sun3x_esp_send_dma_cmd()
[all …]
Dsun_esp.c356 u32 csr; in sbus_esp_dma_drain() local
362 csr = dma_read32(DMA_CSR); in sbus_esp_dma_drain()
363 if (!(csr & DMA_FIFO_ISDRAIN)) in sbus_esp_dma_drain()
367 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR); in sbus_esp_dma_drain()
422 u32 csr; in sbus_esp_send_dma_cmd() local
434 csr = esp->prev_hme_dmacsr; in sbus_esp_send_dma_cmd()
435 csr |= DMA_SCSI_DISAB | DMA_ENABLE; in sbus_esp_send_dma_cmd()
437 csr |= DMA_ST_WRITE; in sbus_esp_send_dma_cmd()
439 csr &= ~DMA_ST_WRITE; in sbus_esp_send_dma_cmd()
440 esp->prev_hme_dmacsr = csr; in sbus_esp_send_dma_cmd()
[all …]
Dsun3_scsi.h33 unsigned short csr; /* control/status reg */ member
Datari_NCR5380.c1255 dregs->csr |= CSR_DMA_ENABLE; in NCR5380_intr()
1266 dregs->csr |= CSR_DMA_ENABLE; in NCR5380_intr()
1601 dregs->csr |= CSR_INTR; in NCR5380_select()
1864 dregs->csr |= CSR_DMA_ENABLE; in NCR5380_transfer_dma()
1959 dregs->csr |= CSR_INTR; in NCR5380_information_transfer()
1994 dregs->csr |= CSR_INTR; in NCR5380_information_transfer()
2310 dregs->csr |= CSR_DMA_ENABLE; in NCR5380_information_transfer()
/linux-4.4.14/sound/soc/intel/atom/sst/
Dsst_loader.c65 union config_status_reg_mrfld csr; in intel_sst_reset_dsp_mrfld() local
68 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
70 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld()
72 csr.full |= 0x7; in intel_sst_reset_dsp_mrfld()
73 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld()
74 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
76 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld()
78 csr.full &= ~(0x1); in intel_sst_reset_dsp_mrfld()
79 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld()
81 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
[all …]
Dsst.c354 shim_regs->csr = sst_shim_read64(shim, SST_CSR); in sst_save_shim64()
372 sst_shim_write64(shim, SST_CSR, shim_regs->csr); in sst_restore_shim64()
Dsst.h321 u64 csr; member
/linux-4.4.14/drivers/usb/gadget/udc/
Dat91_udc.c115 u32 csr; in proc_ep_show() local
122 csr = __raw_readl(ep->creg); in proc_ep_show()
136 csr, in proc_ep_show()
137 (csr & 0x07ff0000) >> 16, in proc_ep_show()
138 (csr & (1 << 15)) ? "enabled" : "disabled", in proc_ep_show()
139 (csr & (1 << 11)) ? "DATA1" : "DATA0", in proc_ep_show()
140 types[(csr & 0x700) >> 8], in proc_ep_show()
143 (!(csr & 0x700)) in proc_ep_show()
144 ? ((csr & (1 << 7)) ? " IN" : " OUT") in proc_ep_show()
146 (csr & (1 << 6)) ? " rxdatabk1" : "", in proc_ep_show()
[all …]
Ds3c-hsudc.c381 u32 csr, offset; in s3c_hsudc_read_fifo() local
388 csr = readl(hsudc->regs + offset); in s3c_hsudc_read_fifo()
389 if (!(csr & S3C_ESR_RX_SUCCESS)) in s3c_hsudc_read_fifo()
397 rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2); in s3c_hsudc_read_fifo()
434 u32 csr; in s3c_hsudc_epin_intr() local
436 csr = readl(hsudc->regs + S3C_ESR); in s3c_hsudc_epin_intr()
437 if (csr & S3C_ESR_STALL) { in s3c_hsudc_epin_intr()
442 if (csr & S3C_ESR_TX_SUCCESS) { in s3c_hsudc_epin_intr()
450 (csr & S3C_ESR_PSIF_TWO)) in s3c_hsudc_epin_intr()
467 u32 csr; in s3c_hsudc_epout_intr() local
[all …]
Damd5536udc.c440 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); in udc_ep_enable()
443 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); in udc_ep_enable()
456 tmp = readl(&dev->csr->ne[udc_csr_epix]); in udc_ep_enable()
472 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_ep_enable()
1929 tmp = readl(&dev->csr->ne[0]); in activate_control_endpoints()
1936 writel(tmp, &dev->csr->ne[0]); in activate_control_endpoints()
2852 tmp = readl(&dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2857 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2907 tmp = readl(&dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2916 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
[all …]
Damd5536udc.h541 struct udc_csrs __iomem *csr; member
/linux-4.4.14/arch/mips/dec/
Dkn02-irq.c34 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq() local
38 *csr = cached_kn02_csr; in unmask_kn02_irq()
43 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq() local
47 *csr = cached_kn02_csr; in mask_kn02_irq()
66 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs() local
72 *csr = cached_kn02_csr; in init_kn02_irqs()
Dkn01-berr.c53 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_ack() local
58 *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */ in dec_kn01_be_ack()
154 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_interrupt() local
158 if (!(*csr & KN01_CSR_MEMERR)) in dec_kn01_be_interrupt()
181 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); in dec_kn01_be_init() local
187 cached_kn01_csr = *csr; in dec_kn01_be_init()
193 *csr = cached_kn01_csr; in dec_kn01_be_init()
Decc-berr.c231 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in dec_kn02_be_init() local
237 cached_kn02_csr = *csr | KN02_CSR_LEDS; in dec_kn02_be_init()
243 *csr = cached_kn02_csr; in dec_kn02_be_init()
/linux-4.4.14/drivers/pcmcia/
Dpxa2xx_sharpsl.c62 unsigned short cpr, csr; in sharpsl_pcmcia_socket_state() local
70 csr = read_scoop_reg(scoop, SCOOP_CSR); in sharpsl_pcmcia_socket_state()
71 if (csr & 0x0004) { in sharpsl_pcmcia_socket_state()
79 csr |= SCOOP_DEV[skt->nr].keep_vs; in sharpsl_pcmcia_socket_state()
84 SCOOP_DEV[skt->nr].keep_vs = (csr & 0x00C0); in sharpsl_pcmcia_socket_state()
95 state->detect = (csr & 0x0004) ? 0 : 1; in sharpsl_pcmcia_socket_state()
96 state->ready = (csr & 0x0002) ? 1 : 0; in sharpsl_pcmcia_socket_state()
97 state->bvd1 = (csr & 0x0010) ? 1 : 0; in sharpsl_pcmcia_socket_state()
98 state->bvd2 = (csr & 0x0020) ? 1 : 0; in sharpsl_pcmcia_socket_state()
99 state->wrprot = (csr & 0x0008) ? 1 : 0; in sharpsl_pcmcia_socket_state()
[all …]
Dat91_cf.c152 u32 csr; in at91_cf_set_io_map() local
170 csr = AT91_MC_SMC_DBW_8; in at91_cf_set_io_map()
173 csr = AT91_MC_SMC_DBW_16; in at91_cf_set_io_map()
177 AT91_MC_SMC_DBW, csr); in at91_cf_set_io_map()
/linux-4.4.14/arch/mips/cavium-octeon/executive/
Dcvmx-interrupt-rsl.c53 union cvmx_asxx_int_en csr; in __cvmx_interrupt_asxx_enable() local
65 csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block)); in __cvmx_interrupt_asxx_enable()
66 csr.s.txpsh = mask; in __cvmx_interrupt_asxx_enable()
67 csr.s.txpop = mask; in __cvmx_interrupt_asxx_enable()
68 csr.s.ovrflw = mask; in __cvmx_interrupt_asxx_enable()
69 cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64); in __cvmx_interrupt_asxx_enable()
/linux-4.4.14/drivers/crypto/qat/qat_dh895xcc/
Dadf_dh895xcc_hw_data.c179 void __iomem *csr = misc_bar->virt_addr; in adf_enable_error_correction() local
184 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
186 ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
187 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
189 ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
194 val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i)); in adf_enable_error_correction()
196 ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val); in adf_enable_error_correction()
197 val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i)); in adf_enable_error_correction()
199 ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val); in adf_enable_error_correction()
/linux-4.4.14/arch/mips/kernel/
Dsignal.c73 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in copy_fp_to_sigcontext() local
83 err |= __put_user(current->thread.fpu.fcr31, csr); in copy_fp_to_sigcontext()
92 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in copy_fp_from_sigcontext() local
102 err |= __get_user(current->thread.fpu.fcr31, csr); in copy_fp_from_sigcontext()
114 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in save_hw_fp_context() local
116 return _save_fp_context(fpregs, csr); in save_hw_fp_context()
123 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in restore_hw_fp_context() local
125 return _restore_fp_context(fpregs, csr); in restore_hw_fp_context()
170 err = __put_user(read_msa_csr(), &msa->csr); in save_msa_extcontext()
177 err = __put_user(current->thread.fpu.msacsr, &msa->csr); in save_msa_extcontext()
[all …]
Dirq_txx9.c34 u32 csr; member
186 u32 csr = __raw_readl(&txx9_ircptr->csr); in txx9_irq() local
188 if (likely(!(csr & TXx9_IRCSR_IF))) in txx9_irq()
189 return TXX9_IRQ_BASE + (csr & (TXx9_MAX_IR - 1)); in txx9_irq()
Dsignal-common.h36 _save_fp_context(void __user *fpregs, void __user *csr);
38 _restore_fp_context(void __user *fpregs, void __user *csr);
Dmips-r2-to-r6-emul.c200 u32 csr; in movf_func() local
203 csr = current->thread.fpu.fcr31; in movf_func()
206 if (((csr & cond) == 0) && MIPSInst_RD(ir)) in movf_func()
223 u32 csr; in movt_func() local
226 csr = current->thread.fpu.fcr31; in movt_func()
229 if (((csr & cond) != 0) && MIPSInst_RD(ir)) in movt_func()
/linux-4.4.14/arch/sh/boards/mach-hp6xx/
Dpm.c42 u8 stbcr, csr; in pm_enter() local
49 csr = sh_wdt_read_csr(); in pm_enter()
50 csr &= ~WTCSR_TME; in pm_enter()
51 csr |= WTCSR_CKS_4096; in pm_enter()
52 sh_wdt_write_csr(csr); in pm_enter()
53 csr = sh_wdt_read_csr(); in pm_enter()
/linux-4.4.14/arch/arm64/boot/dts/apm/
Dapm-storm.dtsi159 reg-names = "csr-reg";
181 reg-names = "csr-reg";
190 reg-names = "csr-reg";
191 csr-mask = <0x3>;
200 reg-names = "csr-reg";
201 csr-mask = <0xc>;
210 reg-names = "csr-reg";
211 csr-mask = <0x3>;
221 reg-names = "csr-reg";
222 csr-mask = <0x3>;
[all …]
Dapm-shadowcat.dtsi148 reg-names = "csr-reg";
157 reg-names = "csr-reg";
159 csr-mask = <0x3>;
168 reg-names = "csr-reg";
170 csr-mask = <0x3>;
/linux-4.4.14/drivers/net/wireless/rt2x00/
Drt2x00mmio.h36 *value = readl(rt2x00dev->csr.base + offset); in rt2x00mmio_register_read()
43 memcpy_fromio(value, rt2x00dev->csr.base + offset, length); in rt2x00mmio_register_multiread()
50 writel(value, rt2x00dev->csr.base + offset); in rt2x00mmio_register_write()
58 __iowrite32_copy(rt2x00dev->csr.base + offset, value, length >> 2); in rt2x00mmio_register_multiwrite()
Drt2x00pci.c44 if (rt2x00dev->csr.base) { in rt2x00pci_free_reg()
45 iounmap(rt2x00dev->csr.base); in rt2x00pci_free_reg()
46 rt2x00dev->csr.base = NULL; in rt2x00pci_free_reg()
54 rt2x00dev->csr.base = pci_ioremap_bar(pci_dev, 0); in rt2x00pci_alloc_reg()
55 if (!rt2x00dev->csr.base) in rt2x00pci_alloc_reg()
Drt2x00soc.c42 iounmap(rt2x00dev->csr.base); in rt2x00soc_free_reg()
54 rt2x00dev->csr.base = ioremap(res->start, resource_size(res)); in rt2x00soc_alloc_reg()
55 if (!rt2x00dev->csr.base) in rt2x00soc_alloc_reg()
Drt2x00usb.c87 if (unlikely(!rt2x00dev->csr.cache || buffer_length > CSR_CACHE_SIZE)) { in rt2x00usb_vendor_req_buff_lock()
93 memcpy(rt2x00dev->csr.cache, buffer, buffer_length); in rt2x00usb_vendor_req_buff_lock()
96 offset, 0, rt2x00dev->csr.cache, in rt2x00usb_vendor_req_buff_lock()
100 memcpy(buffer, rt2x00dev->csr.cache, buffer_length); in rt2x00usb_vendor_req_buff_lock()
753 kfree(rt2x00dev->csr.cache); in rt2x00usb_free_reg()
754 rt2x00dev->csr.cache = NULL; in rt2x00usb_free_reg()
759 rt2x00dev->csr.cache = kzalloc(CSR_CACHE_SIZE, GFP_KERNEL); in rt2x00usb_alloc_reg()
760 if (!rt2x00dev->csr.cache) in rt2x00usb_alloc_reg()
Drt2x00debug.h62 RT2X00DEBUGFS_REGISTER_ENTRY(csr, u32);
Drt2x00debug.c526 RT2X00DEBUGFS_OPS(csr, "0x%.8x\n", u32);
639 RT2X00DEBUGFS_SPRINTF_REGISTER(csr); in rt2x00debug_create_file_chipset()
723 RT2X00DEBUGFS_CREATE_REGISTER_ENTRY(intf, csr); in rt2x00debug_register()
Drt2x00.h818 union csr { union
821 } csr; member
Drt2400pci.c169 .csr = {
Drt2500usb.c244 .csr = {
Drt2500pci.c169 .csr = {
Drt73usb.c152 .csr = {
Drt61pci.c207 .csr = {
Drt2800lib.c1112 .csr = {
/linux-4.4.14/drivers/power/reset/
Dxgene-reboot.c39 void *csr; member
52 writel(ctx->mask, ctx->csr); in xgene_restart_handler()
71 ctx->csr = of_iomap(dev->of_node, 0); in xgene_reboot_probe()
72 if (!ctx->csr) { in xgene_reboot_probe()
/linux-4.4.14/drivers/net/wireless/ath/wil6210/
Dinterrupt.c208 u32 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx()
269 u32 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx()
326 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX, in wil_cache_mbox_regs()
335 u32 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_misc()
442 u32 icm_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
445 u32 icr_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
450 u32 icm_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
453 u32 icr_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
458 u32 icm_misc = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
461 u32 icr_misc = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
[all …]
Dpcie_bus.c189 wil->csr = pci_ioremap_bar(pdev, 0); in wil_pcie_probe()
190 if (!wil->csr) { in wil_pcie_probe()
196 wil_info(wil, "CSR at %pR -> 0x%p\n", &pdev->resource[0], wil->csr); in wil_pcie_probe()
223 pci_iounmap(pdev, wil->csr); in wil_pcie_probe()
240 void __iomem *csr = wil->csr; in wil_pcie_remove() local
247 pci_iounmap(pdev, csr); in wil_pcie_remove()
Ddebugfs.c205 void __iomem *x = wil->csr + HOSTADDR(r.base) + delta; in wil_print_ring()
244 wil_print_ring(s, "tx", wil->csr + HOST_MBOX + in wil_mbox_debugfs_show()
246 wil_print_ring(s, "rx", wil->csr + HOST_MBOX + in wil_mbox_debugfs_show()
378 wil6210_debugfs_init_offset(wil, d, (void * __force)wil->csr + off, in wil6210_debugfs_create_ISR()
399 wil6210_debugfs_init_offset(wil, d, (void * __force)wil->csr, in wil6210_debugfs_create_pseudo_ISR()
458 wil6210_debugfs_init_offset(wil, d, (void * __force)wil->csr, in wil6210_debugfs_create_ITR_CNT()
461 wil6210_debugfs_init_offset(wil, dtx, (void * __force)wil->csr, in wil6210_debugfs_create_ITR_CNT()
464 wil6210_debugfs_init_offset(wil, drx, (void * __force)wil->csr, in wil6210_debugfs_create_ITR_CNT()
1420 blob->data = (void * __force)wil->csr + HOSTADDR(map->host); in wil6210_debugfs_init_blobs()
1530 wil6210_debugfs_init_offset(wil, dbg, (void * __force)wil->csr, in wil6210_debugfs_init()
Dwil_crash_dump.c77 data = (void * __force)wil->csr + HOSTADDR(map->host); in wil_fw_copy_crash_dump()
Dwil6210.h547 void __iomem *csr; member
664 return readl(wil->csr + HOSTADDR(reg)); in wil_r()
670 writel(val, wil->csr + HOSTADDR(reg)); in wil_w()
Dioctl.c48 off = a - wil->csr; in wil_ioc_addr()
Dwmi.c139 return wil->csr + off; in wmi_buffer()
159 return wil->csr + off; in wmi_addr()
744 wil_memcpy_fromio_32(&d_tail, wil->csr + HOSTADDR(r->tail), in wmi_recv_cmd()
Dmain.c648 wil_memcpy_fromio_32(&bl, wil->csr + HOSTADDR(RGF_USER_BL), in wil_get_bl_info()
/linux-4.4.14/drivers/mtd/devices/
Dms02-nv.c192 mp->resource.csr = csr_res; in ms02nv_init_one()
259 release_resource(mp->resource.csr); in ms02nv_remove_one()
260 kfree(mp->resource.csr); in ms02nv_remove_one()
274 volatile u32 *csr; in ms02nv_init() local
281 csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in ms02nv_init()
282 if (*csr & KN02_CSR_BNK32M) in ms02nv_init()
287 csr = (volatile u32 *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); in ms02nv_init()
288 if (*csr & KN03_MCR_BNK32M) in ms02nv_init()
Dms02-nv.h100 struct resource *csr; member
/linux-4.4.14/drivers/ipack/devices/
Dipoctal.c337 iowrite8(TX_CLK_9600 | RX_CLK_9600, &channel->regs->w.csr); in ipoctal_inst_slot()
486 unsigned char csr = 0; in ipoctal_set_termios() local
559 csr |= TX_CLK_75 | RX_CLK_75; in ipoctal_set_termios()
562 csr |= TX_CLK_110 | RX_CLK_110; in ipoctal_set_termios()
565 csr |= TX_CLK_150 | RX_CLK_150; in ipoctal_set_termios()
568 csr |= TX_CLK_300 | RX_CLK_300; in ipoctal_set_termios()
571 csr |= TX_CLK_600 | RX_CLK_600; in ipoctal_set_termios()
574 csr |= TX_CLK_1200 | RX_CLK_1200; in ipoctal_set_termios()
577 csr |= TX_CLK_1800 | RX_CLK_1800; in ipoctal_set_termios()
580 csr |= TX_CLK_2000 | RX_CLK_2000; in ipoctal_set_termios()
[all …]
Dscc2698.h34 u8 d1, csr; /* Clock select register */ member
/linux-4.4.14/arch/m68k/sun3x/
Dtime.c48 h->csr |= C_WRITE; in sun3x_hwclk()
56 h->csr &= ~C_WRITE; in sun3x_hwclk()
58 h->csr |= C_READ; in sun3x_hwclk()
66 h->csr &= ~C_READ; in sun3x_hwclk()
Dtime.h9 volatile unsigned char csr; member
/linux-4.4.14/Documentation/ABI/testing/
Dsysfs-wusb_cbaf4 Contact: David Vrabel <david.vrabel@csr.com>
55 Contact: David Vrabel <david.vrabel@csr.com>
66 Contact: David Vrabel <david.vrabel@csr.com>
73 Contact: David Vrabel <david.vrabel@csr.com>
81 Contact: David Vrabel <david.vrabel@csr.com>
89 Contact: David Vrabel <david.vrabel@csr.com>
97 Contact: David Vrabel <david.vrabel@csr.com>
Dsysfs-bus-umc4 Contact: David Vrabel <david.vrabel@csr.com>
17 Contact: David Vrabel <david.vrabel@csr.com>
25 Contact: David Vrabel <david.vrabel@csr.com>
Dsysfs-class-uwb_rc-wusbhc4 Contact: David Vrabel <david.vrabel@csr.com>
15 Contact: David Vrabel <david.vrabel@csr.com>
30 Contact: David Vrabel <david.vrabel@csr.com>
Dsysfs-bus-usb24 Contact: David Vrabel <david.vrabel@csr.com>
37 Contact: David Vrabel <david.vrabel@csr.com>
46 Contact: David Vrabel <david.vrabel@csr.com>
57 Contact: David Vrabel <david.vrabel@csr.com>
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dxgene.txt28 may include "csr-reg" and/or "div-reg". If this property
30 only "csr-reg".
37 - csr-offset : Offset to the CSR reset register from the reset address base.
39 - csr-mask : CSR reset mask bit. Default is 0xF.
76 reg-name = "csr-reg";
100 reg-names = "csr-reg", "div-reg";
101 csr-offset = <0x0>;
102 csr-mask = <0x200>;
/linux-4.4.14/drivers/dma/
Dtegra20-apb-dma.c137 unsigned long csr; member
425 u32 csr; in tegra_dma_stop() local
429 csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR); in tegra_dma_stop()
430 csr &= ~TEGRA_APBDMA_CSR_IE_EOC; in tegra_dma_stop()
431 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr); in tegra_dma_stop()
434 csr &= ~TEGRA_APBDMA_CSR_ENB; in tegra_dma_stop()
435 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr); in tegra_dma_stop()
451 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr); in tegra_dma_start()
461 ch_regs->csr | TEGRA_APBDMA_CSR_ENB); in tegra_dma_start()
501 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB); in tegra_dma_configure_for_next()
[all …]
Dtxx9dmac.c505 static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr) in txx9dmac_handle_error() argument
523 errors = csr & (TXX9_DMA_CSR_ABCHC | in txx9dmac_handle_error()
548 u32 csr; in txx9dmac_scan_descriptors() local
552 csr = channel64_readl(dc, CSR); in txx9dmac_scan_descriptors()
553 channel64_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
556 csr = channel32_readl(dc, CSR); in txx9dmac_scan_descriptors()
557 channel32_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
560 if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) { in txx9dmac_scan_descriptors()
565 if (!(csr & TXX9_DMA_CSR_CHNEN)) in txx9dmac_scan_descriptors()
574 if (csr & TXX9_DMA_CSR_ABCHC) in txx9dmac_scan_descriptors()
[all …]
Dfsl-edma.c130 __le16 csr; member
457 edma_writew(edma, le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR(ch)); in fsl_edma_set_tcd_regs()
466 u16 csr = 0; in fsl_edma_fill_tcd() local
491 csr |= EDMA_TCD_CSR_INT_MAJOR; in fsl_edma_fill_tcd()
494 csr |= EDMA_TCD_CSR_D_REQ; in fsl_edma_fill_tcd()
497 csr |= EDMA_TCD_CSR_E_SG; in fsl_edma_fill_tcd()
499 tcd->csr = cpu_to_le16(csr); in fsl_edma_fill_tcd()
Domap-dma.c499 unsigned mask, csr; in omap_dma_irq() local
513 csr = omap_dma_get_csr(c); in omap_dma_irq()
516 omap_dma_callback(channel, csr, c); in omap_dma_irq()
/linux-4.4.14/drivers/edac/
Dedac_mc.c215 struct csrow_info *csr; in _edac_mc_free() local
227 csr = mci->csrows[row]; in _edac_mc_free()
228 if (csr) { in _edac_mc_free()
229 if (csr->channels) { in _edac_mc_free()
231 kfree(csr->channels[chn]); in _edac_mc_free()
232 kfree(csr->channels); in _edac_mc_free()
234 kfree(csr); in _edac_mc_free()
273 struct csrow_info *csr; in edac_mc_alloc() local
357 csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL); in edac_mc_alloc()
358 if (!csr) in edac_mc_alloc()
[all …]
/linux-4.4.14/arch/mips/include/asm/sibyte/
Dsb1250_defs.h255 #define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) argument
256 #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr))) argument
/linux-4.4.14/drivers/isdn/hardware/avm/
Db1dma.c220 card->csr = 0x0; in b1dma_reset()
221 b1dma_writel(card, card->csr, AMCC_INTCSR); in b1dma_reset()
253 card->csr = 0x0; in b1dma_detect()
254 b1dma_writel(card, card->csr, AMCC_INTCSR); in b1dma_detect()
358 if (!(card->csr & EN_TX_TC_INT)) { in b1dma_queue_tx()
360 b1dma_writel(card, card->csr, AMCC_INTCSR); in b1dma_queue_tx()
418 card->csr |= EN_TX_TC_INT; in b1dma_dispatch_tx()
597 newcsr = card->csr | (status & ALL_INT); in b1dma_handle_interrupt()
630 card->csr &= ~EN_TX_TC_INT; in b1dma_handle_interrupt()
634 b1dma_writel(card, card->csr, AMCC_INTCSR); in b1dma_handle_interrupt()
[all …]
Dc4.c420 if (card->csr & DBELL_DOWN_ARM) { /* tx busy */ in c4_dispatch_tx()
471 card->csr |= DBELL_DOWN_ARM; in c4_dispatch_tx()
710 card->csr &= ~DBELL_DOWN_ARM; in c4_handle_interrupt()
712 } else if (card->csr & DBELL_DOWN_HOST) { in c4_handle_interrupt()
714 card->csr &= ~DBELL_DOWN_ARM; in c4_handle_interrupt()
868 card->csr = 0; in c4_load_firmware()
Davmcard.h93 volatile u32 csr; member
/linux-4.4.14/Documentation/devicetree/bindings/net/
Dipq806x-dwmac.txt15 - qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
16 qsgmii-csr registers.
28 qcom,qsgmii-csr = <&qsgmii_csr>;
/linux-4.4.14/arch/powerpc/boot/
Dugecon.c48 u32 csr, data, cr; in ug_io_transaction() local
51 csr = EXI_CSR_CLK_32MHZ | EXI_CSR_CS_0; in ug_io_transaction()
52 out_be32(csr_reg, csr); in ug_io_transaction()
/linux-4.4.14/drivers/net/ethernet/amd/
Dsunlance.c440 u32 csr = sbus_readl(lp->dregs + DMA_CSR); in init_restart_ledma() local
442 if (!(csr & DMA_HNDL_ERROR)) { in init_restart_ledma()
448 csr = sbus_readl(lp->dregs + DMA_CSR); in init_restart_ledma()
449 csr &= ~DMA_E_BURSTS; in init_restart_ledma()
451 csr |= DMA_E_BURST32; in init_restart_ledma()
453 csr |= DMA_E_BURST16; in init_restart_ledma()
455 csr |= (DMA_DSBL_RD_DRN | DMA_DSBL_WR_INV | DMA_FIFO_INV); in init_restart_ledma()
458 csr |= DMA_EN_ENETAUI; in init_restart_ledma()
460 csr &= ~DMA_EN_ENETAUI; in init_restart_ledma()
462 sbus_writel(csr, lp->dregs + DMA_CSR); in init_restart_ledma()
[all …]
/linux-4.4.14/drivers/spi/
Dspi-atmel.c326 u32 csr; member
372 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr); in cs_activate()
376 spi_writel(as, CSR0, asd->csr); in cs_activate()
396 u32 csr; in cs_activate() local
400 csr = spi_readl(as, CSR0 + 4 * i); in cs_activate()
401 if ((csr ^ cpol) & SPI_BIT(CPOL)) in cs_activate()
403 csr ^ SPI_BIT(CPOL)); in cs_activate()
863 u32 scbr, csr; in atmel_spi_set_xfer_speed() local
893 csr = spi_readl(as, CSR0 + 4 * spi->chip_select); in atmel_spi_set_xfer_speed()
894 csr = SPI_BFINS(SCBR, scbr, csr); in atmel_spi_set_xfer_speed()
[all …]
/linux-4.4.14/sound/sparc/
Dcs4231.c1629 u32 csr; in snd_cs4231_sbus_interrupt() local
1637 csr = sbus_readl(chip->port + APCCSR); in snd_cs4231_sbus_interrupt()
1639 sbus_writel(csr, chip->port + APCCSR); in snd_cs4231_sbus_interrupt()
1641 if ((csr & APC_PDMA_READY) && in snd_cs4231_sbus_interrupt()
1642 (csr & APC_PLAY_INT) && in snd_cs4231_sbus_interrupt()
1643 (csr & APC_XINT_PNVA) && in snd_cs4231_sbus_interrupt()
1644 !(csr & APC_XINT_EMPT)) in snd_cs4231_sbus_interrupt()
1647 if ((csr & APC_CDMA_READY) && in snd_cs4231_sbus_interrupt()
1648 (csr & APC_CAPT_INT) && in snd_cs4231_sbus_interrupt()
1649 (csr & APC_XINT_CNVA) && in snd_cs4231_sbus_interrupt()
[all …]
/linux-4.4.14/drivers/net/ethernet/intel/
De100.c288 struct csr { struct
580 struct csr __iomem *csr; member
638 (void)ioread8(&nic->csr->scb.status); in e100_write_flush()
646 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi); in e100_enable_irq()
656 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi); in e100_disable_irq()
665 iowrite32(selective_reset, &nic->csr->port); in e100_hw_reset()
669 iowrite32(software_reset, &nic->csr->port); in e100_hw_reset()
686 iowrite32(selftest | dma_addr, &nic->csr->port); in e100_self_test()
725 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo); in e100_eeprom_write()
731 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo); in e100_eeprom_write()
[all …]
/linux-4.4.14/arch/powerpc/platforms/embedded6xx/
Dusbgecko_udbg.c55 u32 csr, data, cr; in ug_io_transaction() local
58 csr = EXI_CSR_CLK_32MHZ | EXI_CSR_CS_0; in ug_io_transaction()
59 out_be32(csr_reg, csr); in ug_io_transaction()
/linux-4.4.14/Documentation/devicetree/bindings/pci/
Daltera-pcie-msi.txt8 "csr": CSR registers
23 reg-names = "csr", "vector_slave";
Dxgene-pci.txt10 "csr": controller configuration registers.
39 reg-names = "csr", "cfg";
Dxgene-pci-msi.txt55 reg-names = "csr", "cfg";
/linux-4.4.14/arch/mips/txx9/generic/
Dirq_tx4939.c211 u32 csr = __raw_readl(&tx4939_ircptr->cs.r); in tx4939_irq() local
213 if (likely(!(csr & TXx9_IRCSR_IF))) in tx4939_irq()
214 return TXX9_IRQ_BASE + (csr & (TX4939_NUM_IR - 1)); in tx4939_irq()
/linux-4.4.14/arch/c6x/kernel/
Dsetup.c94 unsigned cpu_id, rev_id, csr; in get_cpuinfo() local
117 csr = get_creg(CSR); in get_cpuinfo()
118 cpu_id = csr >> 24; in get_cpuinfo()
119 rev_id = (csr >> 16) & 0xff; in get_cpuinfo()
Dsignal.c58 COPY(csr); COPY(pc); in restore_sigcontext()
123 COPY(csr); COPY(pc); in setup_sigcontext()
Dtraps.c36 pr_err("Status: %08lx ORIG_A4: %08lx\n", regs->csr, regs->orig_a4); in show_regs()
/linux-4.4.14/arch/arm/plat-omap/
Ddma.c1093 u32 csr; in omap1_dma_handle_ch() local
1096 csr = dma_chan[ch].saved_csr; in omap1_dma_handle_ch()
1099 csr = p->dma_read(CSR, ch); in omap1_dma_handle_ch()
1100 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { in omap1_dma_handle_ch()
1101 dma_chan[ch + 6].saved_csr = csr >> 7; in omap1_dma_handle_ch()
1102 csr &= 0x7f; in omap1_dma_handle_ch()
1104 if ((csr & 0x3f) == 0) in omap1_dma_handle_ch()
1108 ch, csr); in omap1_dma_handle_ch()
1111 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) in omap1_dma_handle_ch()
1113 if (unlikely(csr & OMAP_DMA_DROP_IRQ)) in omap1_dma_handle_ch()
[all …]
/linux-4.4.14/drivers/mmc/host/
Dwbsd.c926 u8 csr; in wbsd_get_ro() local
930 csr = inb(host->base + WBSD_CSR); in wbsd_get_ro()
931 csr |= WBSD_MSLED; in wbsd_get_ro()
932 outb(csr, host->base + WBSD_CSR); in wbsd_get_ro()
936 csr = inb(host->base + WBSD_CSR); in wbsd_get_ro()
937 csr &= ~WBSD_MSLED; in wbsd_get_ro()
938 outb(csr, host->base + WBSD_CSR); in wbsd_get_ro()
942 return !!(csr & WBSD_WRPT); in wbsd_get_ro()
1006 u8 csr; in wbsd_tasklet_card() local
1016 csr = inb(host->base + WBSD_CSR); in wbsd_tasklet_card()
[all …]
/linux-4.4.14/drivers/net/ethernet/agere/
Det131x.c738 u32 csr = ET_RXDMA_CSR_FBR1_ENABLE; in et131x_rx_dma_enable() local
742 csr |= ET_RXDMA_CSR_FBR1_SIZE_LO; in et131x_rx_dma_enable()
744 csr |= ET_RXDMA_CSR_FBR1_SIZE_HI; in et131x_rx_dma_enable()
746 csr |= ET_RXDMA_CSR_FBR1_SIZE_LO | ET_RXDMA_CSR_FBR1_SIZE_HI; in et131x_rx_dma_enable()
748 csr |= ET_RXDMA_CSR_FBR0_ENABLE; in et131x_rx_dma_enable()
750 csr |= ET_RXDMA_CSR_FBR0_SIZE_LO; in et131x_rx_dma_enable()
752 csr |= ET_RXDMA_CSR_FBR0_SIZE_HI; in et131x_rx_dma_enable()
754 csr |= ET_RXDMA_CSR_FBR0_SIZE_LO | ET_RXDMA_CSR_FBR0_SIZE_HI; in et131x_rx_dma_enable()
755 writel(csr, &adapter->regs->rxdma.csr); in et131x_rx_dma_enable()
757 csr = readl(&adapter->regs->rxdma.csr); in et131x_rx_dma_enable()
[all …]
Det131x.h241 u32 csr; /* 0x1000 */ member
463 u32 csr; /* 0x2000 */ member
/linux-4.4.14/drivers/tty/serial/
Dsb1250-duart.c127 void __iomem *csr = sport->port.membase + reg; in __read_sbdchn() local
129 return __raw_readq(csr); in __read_sbdchn()
134 void __iomem *csr = sport->memctrl + reg; in __read_sbdshr() local
136 return __raw_readq(csr); in __read_sbdshr()
141 void __iomem *csr = sport->port.membase + reg; in __write_sbdchn() local
143 __raw_writeq(value, csr); in __write_sbdchn()
148 void __iomem *csr = sport->memctrl + reg; in __write_sbdshr() local
150 __raw_writeq(value, csr); in __write_sbdshr()
Dsccnxp.c248 u8 csr; member
289 u8 i, acr = 0, csr = 0, mr0 = 0; in sccnxp_set_baud() local
299 csr = baud_std[i].csr; in sccnxp_set_baud()
314 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); in sccnxp_set_baud()
Ddz.c811 unsigned short csr, tcr, trdy, mask; in dz_console_putchar() local
815 csr = dz_in(dport, DZ_CSR); in dz_console_putchar()
816 dz_out(dport, DZ_CSR, csr & ~DZ_TIE); in dz_console_putchar()
841 dz_out(dport, DZ_CSR, csr); in dz_console_putchar()
/linux-4.4.14/drivers/video/fbdev/via/
Dvia-core.c167 int csr; in viafb_dma_irq() local
171 csr = viafb_mmio_read(VDMA_CSR0); in viafb_dma_irq()
172 if (csr & VDMA_C_DONE) { in viafb_dma_irq()
233 int csr;
253 csr = viafb_mmio_read(VDMA_CSR0);
/linux-4.4.14/drivers/net/wan/lmc/
Dlmc_main.c1241 u32 csr; in lmc_interrupt() local
1256 csr = LMC_CSR_READ (sc, csr_status); in lmc_interrupt()
1261 if ( ! (csr & sc->lmc_intrmask)) { in lmc_interrupt()
1265 firstcsr = csr; in lmc_interrupt()
1268 while (csr & sc->lmc_intrmask) { in lmc_interrupt()
1274 LMC_CSR_WRITE (sc, csr_status, csr); in lmc_interrupt()
1289 if (csr & TULIP_STS_ABNRMLINTR){ in lmc_interrupt()
1294 if (csr & TULIP_STS_RXINTR){ in lmc_interrupt()
1299 if (csr & (TULIP_STS_TXINTR | TULIP_STS_TXNOBUF | TULIP_STS_TXSTOPPED)) { in lmc_interrupt()
1377 if (csr & TULIP_STS_SYSERROR) { in lmc_interrupt()
[all …]
Dlmc_var.h44 #define LMC_CSR_READ(sc, csr) \ argument
45 inl((sc)->lmc_csrs.csr)
/linux-4.4.14/arch/mips/include/uapi/asm/
Ducontext.h39 unsigned int csr; member
/linux-4.4.14/arch/alpha/include/asm/
Dcore_wildfire.h36 volatile unsigned long csr __attribute__((aligned(64))); member
40 volatile unsigned long csr __attribute__((aligned(256))); member
44 volatile unsigned long csr __attribute__((aligned(2048))); member
Dcore_marvel.h29 volatile unsigned long csr __attribute__((aligned(16))); member
64 #define EV7_CSR_OFFSET(name) ((unsigned long)&((ev7_csrs *)NULL)->name.csr)
70 volatile unsigned long csr __attribute__((aligned(64))); member
Dcore_tsunami.h30 volatile unsigned long csr __attribute__((aligned(64))); member
Dcore_titan.h31 volatile unsigned long csr __attribute__((aligned(64))); member
Dcore_apecs.h341 unsigned long csr; /* D-stream fault info. */ member
/linux-4.4.14/drivers/clk/
Dclk-xgene.c44 static inline u32 xgene_clk_read(void __iomem *csr) in xgene_clk_read() argument
46 return readl_relaxed(csr); in xgene_clk_read()
49 static inline void xgene_clk_write(u32 data, void __iomem *csr) in xgene_clk_write() argument
51 return writel_relaxed(data, csr); in xgene_clk_write()
/linux-4.4.14/arch/arm/boot/dts/
Dbcm59056.dtsi53 csr_reg: csr {
/linux-4.4.14/Documentation/devicetree/bindings/mfd/
Dbrcm,bcm59056.txt22 csr, iosr1, iosr2, msr, sdsr1, sdsr2, vsr,
/linux-4.4.14/drivers/ata/
Dahci_xgene.c713 void __iomem *csr = devm_ioremap_resource(dev, res); in xgene_ahci_probe() local
714 if (IS_ERR(csr)) in xgene_ahci_probe()
715 return PTR_ERR(csr); in xgene_ahci_probe()
717 ctx->csr_mux = csr; in xgene_ahci_probe()
/linux-4.4.14/Documentation/devicetree/bindings/dma/
Dapm-xgene-dma.txt29 reg-names = "csr-reg";
/linux-4.4.14/drivers/video/fbdev/
Dleo.c112 u32 csr; member
133 u32 csr; member
235 val = sbus_readl(&par->lc_ss0_usr->csr); in leo_switch_from_graph()
/linux-4.4.14/drivers/hsi/controllers/
Domap_ssi.c208 u32 csr; in ssi_gdd_complete() local
227 csr = readw(omap_ssi->gdd + SSI_GDD_CSR_REG(lch)); in ssi_gdd_complete()
232 if (csr & SSI_CSR_TOUR) { /* Timeout error */ in ssi_gdd_complete()
/linux-4.4.14/drivers/tty/ipwireless/
Dhardware.c538 unsigned short csr = readw(&hw->memregs_CCR->reg_config_and_status); in ipw_setup_hardware() local
540 csr |= 1; in ipw_setup_hardware()
541 writew(csr, &hw->memregs_CCR->reg_config_and_status); in ipw_setup_hardware()
1095 unsigned short csr = readw(&hw->memregs_CCR->reg_config_and_status); in acknowledge_pcmcia_interrupt() local
1097 csr &= 0xfffd; in acknowledge_pcmcia_interrupt()
1098 writew(csr, &hw->memregs_CCR->reg_config_and_status); in acknowledge_pcmcia_interrupt()
/linux-4.4.14/arch/x86/kernel/
Dpci-calgary_64.c833 u32 csr, plssr; in calgary_dump_error_regs() local
836 csr = be32_to_cpu(readl(target)); in calgary_dump_error_regs()
843 tbl->it_busno, csr, plssr); in calgary_dump_error_regs()
849 u32 csr, csmr, plssr, mck, rcstat; in calioc2_dump_error_regs() local
858 csr = be32_to_cpu(readl(target)); in calioc2_dump_error_regs()
872 csr, plssr, csmr, mck); in calioc2_dump_error_regs()
/linux-4.4.14/arch/mips/include/asm/txx9/
Dtx4939.h112 struct tx4939_le_reg csr; member
165 struct tx4939_le_reg csr; member
Dtx3927.h45 volatile unsigned long csr; member
/linux-4.4.14/drivers/regulator/
Dbcm590xx-regulator.c186 BCM590XX_REG_RANGES(csr, dcdc_csr_ranges),
299 BCM590XX_MATCH(csr, CSR),
/linux-4.4.14/arch/mips/include/asm/
Dmsa.h233 __BUILD_MSA_CTL_REG(csr, 1)
/linux-4.4.14/drivers/scsi/be2iscsi/
Dbe.h121 u8 __iomem *csr; member
Dbe_main.c629 phba->ctrl.csr = addr; in beiscsi_map_pci_bars()
949 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET + in be_isr()
/linux-4.4.14/arch/c6x/include/uapi/asm/
Dptrace.h122 REG_PAIR(pc, csr);
/linux-4.4.14/drivers/crypto/ux500/hash/
Dhash_alg.h234 u32 csr[52]; member
Dhash_core.c1179 writel_relaxed(device_state->csr[count], in hash_resume_state()
1232 device_state->csr[count] = in hash_save_state()
/linux-4.4.14/arch/mips/include/asm/octeon/
Dcvmx-pko-defs.h1645 uint64_t csr:1; member
1673 uint64_t csr:1;
1680 uint64_t csr:1; member
1710 uint64_t csr:1;
1727 uint64_t csr:1; member
1763 uint64_t csr:1;
1771 uint64_t csr:1; member
1807 uint64_t csr:1;
Dcvmx-sli-defs.h3303 uint64_t csr:39; member
3305 uint64_t csr:39;
Dcvmx-npei-defs.h4050 uint64_t csr:39; member
4052 uint64_t csr:39;
/linux-4.4.14/drivers/firewire/
Dohci.c1526 struct fw_packet *packet, u32 csr) in handle_local_rom() argument
1537 i = csr - CSR_CONFIG_ROM; in handle_local_rom()
1553 struct fw_packet *packet, u32 csr) in handle_local_lock() argument
1578 sel = (csr - CSR_BUS_MANAGER_ID) / 4; in handle_local_lock()
1602 u64 offset, csr; in handle_local_request() local
1613 csr = offset - CSR_REGISTER_BASE; in handle_local_request()
1616 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) in handle_local_request()
1617 handle_local_rom(ctx->ohci, packet, csr); in handle_local_request()
1618 else switch (csr) { in handle_local_request()
1623 handle_local_lock(ctx->ohci, packet, csr); in handle_local_request()
/linux-4.4.14/drivers/pci/
Dpci.c3483 u16 csr; in pci_pm_reset() local
3488 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); in pci_pm_reset()
3489 if (csr & PCI_PM_CTRL_NO_SOFT_RESET) in pci_pm_reset()
3498 csr &= ~PCI_PM_CTRL_STATE_MASK; in pci_pm_reset()
3499 csr |= PCI_D3hot; in pci_pm_reset()
3500 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
3503 csr &= ~PCI_PM_CTRL_STATE_MASK; in pci_pm_reset()
3504 csr |= PCI_D0; in pci_pm_reset()
3505 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
Dquirks.c1938 u8 __iomem *csr; in quirk_e100_interrupt() local
1984 csr = ioremap(pci_resource_start(dev, 0), 8); in quirk_e100_interrupt()
1985 if (!csr) { in quirk_e100_interrupt()
1990 cmd_hi = readb(csr + 3); in quirk_e100_interrupt()
1993 writeb(1, csr + 3); in quirk_e100_interrupt()
1996 iounmap(csr); in quirk_e100_interrupt()
/linux-4.4.14/drivers/staging/rdma/hfi1/
Dsdma.c1758 csr = read_csr(sde->dd, reg); \
1759 dd_dev_err(sde->dd, "%36s 0x%016llx\n", #reg, csr); \
1763 csr = read_sde_csr(sde, reg); \
1765 #reg, sde->this_idx, csr); \
1769 csr = read_csr(sde->dd, reg + (8 * i)); \
1771 #reg, i, csr); \
1776 u64 csr; in sdma_dumpstate() local
Dchip.c1127 u64 csr; member
1152 #define CNTR_ELEM(name, csr, offset, flags, accessor) \ argument
1155 csr, \
1274 static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr, in read_write_csr() argument
1281 ret = read_csr(dd, csr); in read_write_csr()
1283 write_csr(dd, csr, value); in read_write_csr()
1290 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode); in read_write_csr()
1302 return read_write_csr(dd, entry->csr, mode, data); in dev_access_u32_csr()
1311 u64 csr = entry->csr; in dev_access_u64_csr() local
1316 csr += 8 * vl; in dev_access_u64_csr()
[all …]
/linux-4.4.14/Documentation/DocBook/
Dgpu.xml.db585 API-intel-csr-load-status-get
586 API-intel-csr-load-status-set
587 API-intel-csr-load-program
588 API-intel-csr-ucode-init
589 API-intel-csr-ucode-fini
/linux-4.4.14/drivers/net/wireless/iwlwifi/pcie/
Dtrans.c2083 int csr; in iwl_dbgfs_csr_write() local
2089 if (sscanf(buf, "%d", &csr) != 1) in iwl_dbgfs_csr_write()
2119 DEBUGFS_WRITE_FILE_OPS(csr);
2131 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); in iwl_trans_pcie_dbgfs_register()
/linux-4.4.14/drivers/net/ethernet/sun/
Dsungem.c2092 u32 csr; in gem_stop_phy() local
2102 csr = WOL_WAKECSR_ENABLE; in gem_stop_phy()
2104 csr |= WOL_WAKECSR_MII; in gem_stop_phy()
2105 writel(csr, gp->regs + WOL_WAKECSR); in gem_stop_phy()
/linux-4.4.14/drivers/net/ethernet/emulex/benet/
Dbe.h489 u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ member
Dbe_main.c5519 if (adapter->csr) in be_unmap_pci_bars()
5520 pci_iounmap(adapter->pdev, adapter->csr); in be_unmap_pci_bars()
5557 adapter->csr = pci_iomap(pdev, 2, 0); in be_map_pci_bars()
5558 if (!adapter->csr) in be_map_pci_bars()
Dbe_cmds.c653 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx); in be_POST_stage_get()