115 	u32			csr;  in proc_ep_show()  local
122 	csr = __raw_readl(ep->creg);  in proc_ep_show()
136 		csr,  in proc_ep_show()
137 		(csr & 0x07ff0000) >> 16,  in proc_ep_show()
138 		(csr & (1 << 15)) ? "enabled" : "disabled",  in proc_ep_show()
139 		(csr & (1 << 11)) ? "DATA1" : "DATA0",  in proc_ep_show()
140 		types[(csr & 0x700) >> 8],  in proc_ep_show()
143 		(!(csr & 0x700))  in proc_ep_show()
144 			? ((csr & (1 << 7)) ? " IN" : " OUT")  in proc_ep_show()
146 		(csr & (1 << 6)) ? " rxdatabk1" : "",  in proc_ep_show()
147 		(csr & (1 << 5)) ? " forcestall" : "",  in proc_ep_show()
148 		(csr & (1 << 4)) ? " txpktrdy" : "",  in proc_ep_show()
150 		(csr & (1 << 3)) ? " stallsent" : "",  in proc_ep_show()
151 		(csr & (1 << 2)) ? " rxsetup" : "",  in proc_ep_show()
152 		(csr & (1 << 1)) ? " rxdatabk0" : "",  in proc_ep_show()
153 		(csr & (1 << 0)) ? " txcomp" : "");  in proc_ep_show()
330 	u32		csr;  in read_fifo()  local
342 	csr = __raw_readl(creg);  in read_fifo()
343 	if ((csr & RX_DATA_READY) == 0)  in read_fifo()
346 	count = (csr & AT91_UDP_RXBYTECNT) >> 16;  in read_fifo()
357 	csr |= CLR_FX;  in read_fifo()
360 			csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0);  in read_fifo()
363 			csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK1);  in read_fifo()
367 		csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0);  in read_fifo()
368 	__raw_writel(csr, creg);  in read_fifo()
390 		csr = __raw_readl(creg);  in read_fifo()
404 	u32		csr = __raw_readl(creg);  in write_fifo()  local
421 	if (unlikely(csr & (AT91_UDP_TXCOMP | AT91_UDP_TXPKTRDY))) {  in write_fifo()
422 		if (csr & AT91_UDP_TXCOMP) {  in write_fifo()
423 			csr |= CLR_FX;  in write_fifo()
424 			csr &= ~(SET_FX | AT91_UDP_TXCOMP);  in write_fifo()
425 			__raw_writel(csr, creg);  in write_fifo()
426 			csr = __raw_readl(creg);  in write_fifo()
428 		if (csr & AT91_UDP_TXPKTRDY)  in write_fifo()
457 	csr &= ~SET_FX;  in write_fifo()
458 	csr |= CLR_FX | AT91_UDP_TXPKTRDY;  in write_fifo()
459 	__raw_writel(csr, creg);  in write_fifo()
755 	u32		csr;  in at91_ep_set_halt()  local
765 	csr = __raw_readl(creg);  in at91_ep_set_halt()
772 	if (ep->is_in && (!list_empty(&ep->queue) || (csr >> 16) != 0))  in at91_ep_set_halt()
775 		csr |= CLR_FX;  in at91_ep_set_halt()
776 		csr &= ~SET_FX;  in at91_ep_set_halt()
778 			csr |= AT91_UDP_FORCESTALL;  in at91_ep_set_halt()
783 			csr &= ~AT91_UDP_FORCESTALL;  in at91_ep_set_halt()
785 		__raw_writel(csr, creg);  in at91_ep_set_halt()
1024 	u32			csr = __raw_readl(creg);  in handle_ep()  local
1033 		if (csr & (AT91_UDP_STALLSENT | AT91_UDP_TXCOMP)) {  in handle_ep()
1034 			csr |= CLR_FX;  in handle_ep()
1035 			csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP);  in handle_ep()
1036 			__raw_writel(csr, creg);  in handle_ep()
1042 		if (csr & AT91_UDP_STALLSENT) {  in handle_ep()
1046 			csr |= CLR_FX;  in handle_ep()
1047 			csr &= ~(SET_FX | AT91_UDP_STALLSENT);  in handle_ep()
1048 			__raw_writel(csr, creg);  in handle_ep()
1049 			csr = __raw_readl(creg);  in handle_ep()
1051 		if (req && (csr & RX_DATA_READY))  in handle_ep()
1062 static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr)  in handle_setup()  argument
1072 	rxcount = (csr & AT91_UDP_RXBYTECNT) >> 16;  in handle_setup()
1077 			csr |= AT91_UDP_DIR;  in handle_setup()
1080 			csr &= ~AT91_UDP_DIR;  in handle_setup()
1085 		ERR("SETUP len %d, csr %08x\n", rxcount, csr);  in handle_setup()
1088 	csr |= CLR_FX;  in handle_setup()
1089 	csr &= ~(SET_FX | AT91_UDP_RXSETUP);  in handle_setup()
1090 	__raw_writel(csr, creg);  in handle_setup()
1110 	csr = __raw_readl(creg);  in handle_setup()
1111 	csr |= CLR_FX;  in handle_setup()
1112 	csr &= ~SET_FX;  in handle_setup()
1117 		__raw_writel(csr | AT91_UDP_TXPKTRDY, creg);  in handle_setup()
1273 		csr |= AT91_UDP_FORCESTALL;  in handle_setup()
1274 		__raw_writel(csr, creg);  in handle_setup()
1283 	csr |= AT91_UDP_TXPKTRDY;  in handle_setup()
1284 	__raw_writel(csr, creg);  in handle_setup()
1292 	u32			csr = __raw_readl(creg);  in handle_ep0()  local
1295 	if (unlikely(csr & AT91_UDP_STALLSENT)) {  in handle_ep0()
1298 		csr |= CLR_FX;  in handle_ep0()
1299 		csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_FORCESTALL);  in handle_ep0()
1300 		__raw_writel(csr, creg);  in handle_ep0()
1302 		csr = __raw_readl(creg);  in handle_ep0()
1304 	if (csr & AT91_UDP_RXSETUP) {  in handle_ep0()
1307 		handle_setup(udc, ep0, csr);  in handle_ep0()
1317 	if (csr & AT91_UDP_TXCOMP) {  in handle_ep0()
1318 		csr |= CLR_FX;  in handle_ep0()
1319 		csr &= ~(SET_FX | AT91_UDP_TXCOMP);  in handle_ep0()
1336 			__raw_writel(csr, creg);  in handle_ep0()
1360 	else if (csr & AT91_UDP_RX_DATA_BK0) {  in handle_ep0()
1361 		csr |= CLR_FX;  in handle_ep0()
1362 		csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0);  in handle_ep0()
1370 					csr = __raw_readl(creg);  in handle_ep0()
1371 					csr &= ~SET_FX;  in handle_ep0()
1372 					csr |= CLR_FX | AT91_UDP_TXPKTRDY;  in handle_ep0()
1373 					__raw_writel(csr, creg);  in handle_ep0()
1395 				__raw_writel(csr | AT91_UDP_FORCESTALL, creg);  in handle_ep0()
1402 			__raw_writel(csr, creg);  in handle_ep0()