1/*
2 * Copyright �� 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24#include <linux/firmware.h>
25#include "i915_drv.h"
26#include "i915_reg.h"
27
28/**
29 * DOC: csr support for dmc
30 *
31 * Display Context Save and Restore (CSR) firmware support added from gen9
32 * onwards to drive newly added DMC (Display microcontroller) in display
33 * engine to save and restore the state of display engine when it enter into
34 * low-power state and comes back to normal.
35 *
36 * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
37 * FW_LOADED, FW_FAILED.
38 *
39 * Once the firmware is written into the registers status will be moved from
40 * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
41 * be moved to FW_FAILED.
42 */
43
44#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
45#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
46
47MODULE_FIRMWARE(I915_CSR_SKL);
48MODULE_FIRMWARE(I915_CSR_BXT);
49
50/*
51* SKL CSR registers for DC5 and DC6
52*/
53#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
54#define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
55#define CSR_HTP_ADDR_SKL		0x00500034
56#define CSR_SSP_BASE			0x8F074
57#define CSR_HTP_SKL			0x8F004
58#define CSR_LAST_WRITE			0x8F034
59#define CSR_LAST_WRITE_VALUE		0xc003b400
60/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
61#define CSR_MAX_FW_SIZE			0x2FFF
62#define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
63#define CSR_MMIO_START_RANGE	0x80000
64#define CSR_MMIO_END_RANGE		0x8FFFF
65
66struct intel_css_header {
67	/* 0x09 for DMC */
68	uint32_t module_type;
69
70	/* Includes the DMC specific header in dwords */
71	uint32_t header_len;
72
73	/* always value would be 0x10000 */
74	uint32_t header_ver;
75
76	/* Not used */
77	uint32_t module_id;
78
79	/* Not used */
80	uint32_t module_vendor;
81
82	/* in YYYYMMDD format */
83	uint32_t date;
84
85	/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
86	uint32_t size;
87
88	/* Not used */
89	uint32_t key_size;
90
91	/* Not used */
92	uint32_t modulus_size;
93
94	/* Not used */
95	uint32_t exponent_size;
96
97	/* Not used */
98	uint32_t reserved1[12];
99
100	/* Major Minor */
101	uint32_t version;
102
103	/* Not used */
104	uint32_t reserved2[8];
105
106	/* Not used */
107	uint32_t kernel_header_info;
108} __packed;
109
110struct intel_fw_info {
111	uint16_t reserved1;
112
113	/* Stepping (A, B, C, ..., *). * is a wildcard */
114	char stepping;
115
116	/* Sub-stepping (0, 1, ..., *). * is a wildcard */
117	char substepping;
118
119	uint32_t offset;
120	uint32_t reserved2;
121} __packed;
122
123struct intel_package_header {
124	/* DMC container header length in dwords */
125	unsigned char header_len;
126
127	/* always value would be 0x01 */
128	unsigned char header_ver;
129
130	unsigned char reserved[10];
131
132	/* Number of valid entries in the FWInfo array below */
133	uint32_t num_entries;
134
135	struct intel_fw_info fw_info[20];
136} __packed;
137
138struct intel_dmc_header {
139	/* always value would be 0x40403E3E */
140	uint32_t signature;
141
142	/* DMC binary header length */
143	unsigned char header_len;
144
145	/* 0x01 */
146	unsigned char header_ver;
147
148	/* Reserved */
149	uint16_t dmcc_ver;
150
151	/* Major, Minor */
152	uint32_t	project;
153
154	/* Firmware program size (excluding header) in dwords */
155	uint32_t	fw_size;
156
157	/* Major Minor version */
158	uint32_t fw_version;
159
160	/* Number of valid MMIO cycles present. */
161	uint32_t mmio_count;
162
163	/* MMIO address */
164	uint32_t mmioaddr[8];
165
166	/* MMIO data */
167	uint32_t mmiodata[8];
168
169	/* FW filename  */
170	unsigned char dfile[32];
171
172	uint32_t reserved1[2];
173} __packed;
174
175struct stepping_info {
176	char stepping;
177	char substepping;
178};
179
180static const struct stepping_info skl_stepping_info[] = {
181		{'A', '0'}, {'B', '0'}, {'C', '0'},
182		{'D', '0'}, {'E', '0'}, {'F', '0'},
183		{'G', '0'}, {'H', '0'}, {'I', '0'},
184		{'J', '0'}, {'K', '0'}
185};
186
187static struct stepping_info bxt_stepping_info[] = {
188	{'A', '0'}, {'A', '1'}, {'A', '2'},
189	{'B', '0'}, {'B', '1'}, {'B', '2'}
190};
191
192static char intel_get_stepping(struct drm_device *dev)
193{
194	if (IS_SKYLAKE(dev) && (dev->pdev->revision <
195			ARRAY_SIZE(skl_stepping_info)))
196		return skl_stepping_info[dev->pdev->revision].stepping;
197	else if (IS_BROXTON(dev) && (dev->pdev->revision <
198				ARRAY_SIZE(bxt_stepping_info)))
199		return bxt_stepping_info[dev->pdev->revision].stepping;
200	else
201		return -ENODATA;
202}
203
204static char intel_get_substepping(struct drm_device *dev)
205{
206	if (IS_SKYLAKE(dev) && (dev->pdev->revision <
207			ARRAY_SIZE(skl_stepping_info)))
208		return skl_stepping_info[dev->pdev->revision].substepping;
209	else if (IS_BROXTON(dev) && (dev->pdev->revision <
210			ARRAY_SIZE(bxt_stepping_info)))
211		return bxt_stepping_info[dev->pdev->revision].substepping;
212	else
213		return -ENODATA;
214}
215
216/**
217 * intel_csr_load_status_get() - to get firmware loading status.
218 * @dev_priv: i915 device.
219 *
220 * This function helps to get the firmware loading status.
221 *
222 * Return: Firmware loading status.
223 */
224enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv)
225{
226	enum csr_state state;
227
228	mutex_lock(&dev_priv->csr_lock);
229	state = dev_priv->csr.state;
230	mutex_unlock(&dev_priv->csr_lock);
231
232	return state;
233}
234
235/**
236 * intel_csr_load_status_set() - help to set firmware loading status.
237 * @dev_priv: i915 device.
238 * @state: enumeration of firmware loading status.
239 *
240 * Set the firmware loading status.
241 */
242void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
243			enum csr_state state)
244{
245	mutex_lock(&dev_priv->csr_lock);
246	dev_priv->csr.state = state;
247	mutex_unlock(&dev_priv->csr_lock);
248}
249
250/**
251 * intel_csr_load_program() - write the firmware from memory to register.
252 * @dev: drm device.
253 *
254 * CSR firmware is read from a .bin file and kept in internal memory one time.
255 * Everytime display comes back from low power state this function is called to
256 * copy the firmware from internal memory to registers.
257 */
258void intel_csr_load_program(struct drm_device *dev)
259{
260	struct drm_i915_private *dev_priv = dev->dev_private;
261	u32 *payload = dev_priv->csr.dmc_payload;
262	uint32_t i, fw_size;
263
264	if (!IS_GEN9(dev)) {
265		DRM_ERROR("No CSR support available for this platform\n");
266		return;
267	}
268
269	/*
270	 * FIXME: Firmware gets lost on S3/S4, but not when entering system
271	 * standby or suspend-to-idle (which is just like forced runtime pm).
272	 * Unfortunately the ACPI subsystem doesn't yet give us a way to
273	 * differentiate this, hence figure it out with this hack.
274	 */
275	if (I915_READ(CSR_PROGRAM(0)))
276		return;
277
278	mutex_lock(&dev_priv->csr_lock);
279	fw_size = dev_priv->csr.dmc_fw_size;
280	for (i = 0; i < fw_size; i++)
281		I915_WRITE(CSR_PROGRAM(i), payload[i]);
282
283	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
284		I915_WRITE(dev_priv->csr.mmioaddr[i],
285			dev_priv->csr.mmiodata[i]);
286	}
287
288	dev_priv->csr.state = FW_LOADED;
289	mutex_unlock(&dev_priv->csr_lock);
290}
291
292static void finish_csr_load(const struct firmware *fw, void *context)
293{
294	struct drm_i915_private *dev_priv = context;
295	struct drm_device *dev = dev_priv->dev;
296	struct intel_css_header *css_header;
297	struct intel_package_header *package_header;
298	struct intel_dmc_header *dmc_header;
299	struct intel_csr *csr = &dev_priv->csr;
300	char stepping = intel_get_stepping(dev);
301	char substepping = intel_get_substepping(dev);
302	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
303	uint32_t i;
304	uint32_t *dmc_payload;
305	bool fw_loaded = false;
306
307	if (!fw) {
308		i915_firmware_load_error_print(csr->fw_path, 0);
309		goto out;
310	}
311
312	if ((stepping == -ENODATA) || (substepping == -ENODATA)) {
313		DRM_ERROR("Unknown stepping info, firmware loading failed\n");
314		goto out;
315	}
316
317	/* Extract CSS Header information*/
318	css_header = (struct intel_css_header *)fw->data;
319	if (sizeof(struct intel_css_header) !=
320		(css_header->header_len * 4)) {
321		DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
322			(css_header->header_len * 4));
323		goto out;
324	}
325	readcount += sizeof(struct intel_css_header);
326
327	/* Extract Package Header information*/
328	package_header = (struct intel_package_header *)
329					&fw->data[readcount];
330	if (sizeof(struct intel_package_header) !=
331		(package_header->header_len * 4)) {
332		DRM_ERROR("Firmware has wrong package header length %u bytes\n",
333			(package_header->header_len * 4));
334		goto out;
335	}
336	readcount += sizeof(struct intel_package_header);
337
338	/* Search for dmc_offset to find firware binary. */
339	for (i = 0; i < package_header->num_entries; i++) {
340		if (package_header->fw_info[i].substepping == '*' &&
341			stepping == package_header->fw_info[i].stepping) {
342			dmc_offset = package_header->fw_info[i].offset;
343			break;
344		} else if (stepping == package_header->fw_info[i].stepping &&
345			substepping == package_header->fw_info[i].substepping) {
346			dmc_offset = package_header->fw_info[i].offset;
347			break;
348		} else if (package_header->fw_info[i].stepping == '*' &&
349			package_header->fw_info[i].substepping == '*')
350			dmc_offset = package_header->fw_info[i].offset;
351	}
352	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
353		DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
354		goto out;
355	}
356	readcount += dmc_offset;
357
358	/* Extract dmc_header information. */
359	dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
360	if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
361		DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
362				(dmc_header->header_len));
363		goto out;
364	}
365	readcount += sizeof(struct intel_dmc_header);
366
367	/* Cache the dmc header info. */
368	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
369		DRM_ERROR("Firmware has wrong mmio count %u\n",
370						dmc_header->mmio_count);
371		goto out;
372	}
373	csr->mmio_count = dmc_header->mmio_count;
374	for (i = 0; i < dmc_header->mmio_count; i++) {
375		if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
376			dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
377			DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
378						dmc_header->mmioaddr[i]);
379			goto out;
380		}
381		csr->mmioaddr[i] = dmc_header->mmioaddr[i];
382		csr->mmiodata[i] = dmc_header->mmiodata[i];
383	}
384
385	/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
386	nbytes = dmc_header->fw_size * 4;
387	if (nbytes > CSR_MAX_FW_SIZE) {
388		DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
389		goto out;
390	}
391	csr->dmc_fw_size = dmc_header->fw_size;
392
393	csr->dmc_payload = kmalloc(nbytes, GFP_KERNEL);
394	if (!csr->dmc_payload) {
395		DRM_ERROR("Memory allocation failed for dmc payload\n");
396		goto out;
397	}
398
399	dmc_payload = csr->dmc_payload;
400	memcpy(dmc_payload, &fw->data[readcount], nbytes);
401
402	/* load csr program during system boot, as needed for DC states */
403	intel_csr_load_program(dev);
404	fw_loaded = true;
405
406	DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
407out:
408	if (fw_loaded)
409		intel_runtime_pm_put(dev_priv);
410	else
411		intel_csr_load_status_set(dev_priv, FW_FAILED);
412
413	release_firmware(fw);
414}
415
416/**
417 * intel_csr_ucode_init() - initialize the firmware loading.
418 * @dev: drm device.
419 *
420 * This function is called at the time of loading the display driver to read
421 * firmware from a .bin file and copied into a internal memory.
422 */
423void intel_csr_ucode_init(struct drm_device *dev)
424{
425	struct drm_i915_private *dev_priv = dev->dev_private;
426	struct intel_csr *csr = &dev_priv->csr;
427	int ret;
428
429	if (!HAS_CSR(dev))
430		return;
431
432	if (IS_SKYLAKE(dev))
433		csr->fw_path = I915_CSR_SKL;
434	else if (IS_BROXTON(dev_priv))
435		csr->fw_path = I915_CSR_BXT;
436	else {
437		DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
438		intel_csr_load_status_set(dev_priv, FW_FAILED);
439		return;
440	}
441
442	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
443
444	/*
445	 * Obtain a runtime pm reference, until CSR is loaded,
446	 * to avoid entering runtime-suspend.
447	 */
448	intel_runtime_pm_get(dev_priv);
449
450	/* CSR supported for platform, load firmware */
451	ret = request_firmware_nowait(THIS_MODULE, true, csr->fw_path,
452				&dev_priv->dev->pdev->dev,
453				GFP_KERNEL, dev_priv,
454				finish_csr_load);
455	if (ret) {
456		i915_firmware_load_error_print(csr->fw_path, ret);
457		intel_csr_load_status_set(dev_priv, FW_FAILED);
458	}
459}
460
461/**
462 * intel_csr_ucode_fini() - unload the CSR firmware.
463 * @dev: drm device.
464 *
465 * Firmmware unloading includes freeing the internal momory and reset the
466 * firmware loading status.
467 */
468void intel_csr_ucode_fini(struct drm_device *dev)
469{
470	struct drm_i915_private *dev_priv = dev->dev_private;
471
472	if (!HAS_CSR(dev))
473		return;
474
475	intel_csr_load_status_set(dev_priv, FW_FAILED);
476	kfree(dev_priv->csr.dmc_payload);
477}
478
479void assert_csr_loaded(struct drm_i915_private *dev_priv)
480{
481	WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
482		  "CSR is not loaded.\n");
483	WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
484		  "CSR program storage start is NULL\n");
485	WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
486	WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
487}
488