/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb4vf/ |
H A D | Makefile | 2 # Chelsio T4 SR-IOV Virtual Function Driver
|
H A D | t4vf_defs.h | 2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
|
H A D | t4vf_common.h | 2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
|
H A D | adapter.h | 2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
|
H A D | cxgb4vf_main.c | 2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet 89 * the PCI-E SR-IOV standard). 220 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" t4vf_os_portmod_changed() 2027 * Show PCI-E SR-IOV Virtual Function Resource Limits.
|
/linux-4.4.14/arch/avr32/include/asm/ |
H A D | irqflags.h | 16 return sysreg_read(SR); arch_local_save_flags() 28 sysreg_write(SR, flags); arch_local_irq_restore()
|
H A D | sysreg.h | 67 /* Bitfields in SR */
|
/linux-4.4.14/drivers/media/platform/soc_camera/ |
H A D | atmel-isi.h | 83 /* Also using in SR(ISI_V2) */ 86 /* Also using in SR/IER/IDR/IMR(ISI_V2) */ 90 /* Bitfields in SR */ 92 /* Also using in SR/IER/IDR/IMR */
|
/linux-4.4.14/drivers/media/dvb-frontends/ |
H A D | horus3a.c | 255 * SR <= 4.3 horus3a_set_params() 257 * 4.3 < SR <= 10 horus3a_set_params() 258 * fc_lpf = SR * (1 + rolloff) / 2 + SR / 2 = horus3a_set_params() 259 * SR * 1.175 = SR * (47/40) horus3a_set_params() 260 * 10 < SR horus3a_set_params() 261 * fc_lpf = SR * (1 + rolloff) / 2 + 5 = horus3a_set_params() 262 * SR * 0.675 + 5 = SR * (27/40) + 5 horus3a_set_params() 294 * SR <= 4.5: horus3a_set_params() 296 * 4.5 < SR <= 10: horus3a_set_params() 297 * fc_lpf = SR * (1 + rolloff) / 2 + SR / 2 horus3a_set_params() 298 * 10 < SR: horus3a_set_params() 299 * fc_lpf = SR * (1 + rolloff) / 2 + 5 horus3a_set_params()
|
H A D | stv0900_init.h | 131 u8 car_loop_cut12_2; /* Cut 1.2, SR<=3msps */ 132 u8 car_loop_cut20_2; /* Cut 2.0, SR<3msps */ 133 u8 car_loop_cut12_5; /* Cut 1.2, 3<SR<=7msps */ 134 u8 car_loop_cut20_5; /* Cut 2.0, 3<SR<=7msps */ 135 u8 car_loop_cut12_10; /* Cut 1.2, 7<SR<=15msps */ 136 u8 car_loop_cut20_10; /* Cut 2.0, 7<SR<=15msps */ 137 u8 car_loop_cut12_20; /* Cut 1.2, 10<SR<=25msps */ 138 u8 car_loop_cut20_20; /* Cut 2.0, 10<SR<=25msps */ 139 u8 car_loop_cut12_30; /* Cut 1.2, 25<SR<=45msps */ 140 u8 car_loop_cut20_30; /* Cut 2.0, 10<SR<=45msps */ 146 u8 car_loop_2; /* SR<3msps */ 147 u8 car_loop_5; /* 3<SR<=7msps */ 148 u8 car_loop_10; /* 7<SR<=15msps */ 149 u8 car_loop_20; /* 10<SR<=25msps */ 150 u8 car_loop_30; /* 10<SR<=45msps */
|
H A D | stv090x_priv.h | 216 u8 crl_2; /* SR < 3M */ 217 u8 crl_5; /* 3 < SR <= 7M */ 218 u8 crl_10; /* 7 < SR <= 15M */ 219 u8 crl_20; /* 10 < SR <= 25M */ 220 u8 crl_30; /* 10 < SR <= 45M */
|
H A D | isl6405.h | 40 /* SR = 0 */ 49 /* SR = 1 */
|
H A D | tda826x.c | 89 /* BW = ((1 + RO) * SR/2 + 5) * 1.3 [SR in MSPS, BW in MHz] */ tda826x_set_params()
|
H A D | stv0900_priv.h | 141 STV0900_BLIND_SEARCH,/* offset freq and SR are Unknown */ 142 STV0900_COLD_START,/* only the SR is known */ 143 STV0900_WARM_START/* offset freq and SR are known */
|
H A D | stv090x.c | 823 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/ stv090x_get_lock_tmg() 826 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/ stv090x_get_lock_tmg() 829 } else { /*SR >20Msps*/ stv090x_get_lock_tmg() 839 if (state->srate <= 1000000) { /*SR <=1Msps*/ stv090x_get_lock_tmg() 842 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */ stv090x_get_lock_tmg() 845 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */ stv090x_get_lock_tmg() 848 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */ stv090x_get_lock_tmg() 851 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */ stv090x_get_lock_tmg() 854 } else { /*SR >20Msps*/ stv090x_get_lock_tmg() 870 sym = (srate << 4); /* SR * 2^16 / master_clk */ stv090x_set_srate() 897 sym = (srate << 4); /* SR * 2^16 / master_clk */ stv090x_set_max_srate() 931 sym = (srate << 4); /* SR * 2^16 / master_clk */ stv090x_set_min_srate() 1250 /* Set ACLC BCLC optimised value vs SR */ stv090x_dvbs_track_crl() 1437 /*enlarge the timing bandwidth for Low SR*/ stv090x_start_search() 1445 /*reduce the timing bandwidth for high SR*/ stv090x_start_search() 1452 /* enlarge the timing bandwidth for Low SR */ stv090x_start_search() 1455 /* reduce timing bandwidth for high SR */ stv090x_start_search() 1614 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */ stv090x_get_agc2_min_level() 1618 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */ stv090x_get_agc2_min_level() 3046 msleep(50); /* blind search: wait 50ms for SR stabilization */ stv090x_optimize_track() 3223 /* SR < 2MSPS */ stv090x_algo() 3227 /* SR >= 2Msps */ stv090x_algo()
|
H A D | nxt6000.c | 586 /*.frequency_tolerance = *//* FIXME: 12% of SR */
|
/linux-4.4.14/arch/sh/kernel/ |
H A D | head_64.S | 121 * . SR.FD = 1 (FPU disabled) 122 * . SR.BL = 1 (Exceptions disabled) 123 * . SR.MD = 1 (Privileged Mode) 124 * . SR.MMU = 0 (MMU Disabled) 125 * . SR.CD = 0 (CTC User Visible) 126 * . SR.IMASK = Undefined (Interrupt Mask) 166 * r29 = Initial SR 168 getcon SR, r29 170 putcon r20, SR 257 getcon SR, r21 300 getcon SR, r21 303 putcon r22, SR /* Try to enable */ 304 getcon SR, r22 352 * (r29) Original SR
|
H A D | ptrace_64.c | 46 /* This mask defines the bits of the SR which the user is not allowed to 156 /* PC, SR, SYSCALL */ genregs_get() 189 /* PC, SR, SYSCALL */ genregs_set() 347 * PC, SR, SYSCALL, 422 disallow any changes to certain SR bits or u_fpvalid, since arch_ptrace() 430 /* Ignore change of top 32 bits of SR */ arch_ptrace() 436 /* If lower 32 bits of SR, ignore non-user bits */ arch_ptrace() 551 We need to clear the Single Step setting in SR to avoid do_single_step()
|
H A D | reboot.c | 32 /* Address error with SR.BL=1 first. */ native_machine_restart()
|
H A D | process_32.c | 40 printk("PC : %08lx SP : %08lx SR : %08lx ", show_regs()
|
H A D | ptrace_32.c | 150 /* PC, PR, SR, GBR, MACH, MACL, TRA */ genregs_get() 323 * PC, PR, SR, GBR, MACH, MACL, TRA
|
H A D | kgdb.c | 236 * switch_to() relies on SR.RB toggling, so regs 0->7 are banked sleeping_thread_to_gdb_regs()
|
H A D | process_64.c | 64 printk("SR : %08Lx%08Lx TEA : %08Lx%08Lx KCR0: %08Lx%08Lx\n", show_regs()
|
H A D | signal_64.c | 232 /* Prevent the signal handler manipulating SR in a way that can restore_sigcontext()
|
/linux-4.4.14/drivers/macintosh/ |
H A D | via-cuda.c | 46 #define SR (10*RS) /* Shift register */ macro 187 out_8(&via[IER], IER_SET|SR_INT); /* enable interrupt from SR */ find_via_cuda() 266 out_8(&via[ACR] ,(in_8(&via[ACR]) & ~SR_CTRL) | SR_EXT); /* SR data in */ cuda_init_via() 267 (void)in_8(&via[SR]); /* clear any left-over data */ cuda_init_via() 272 out_8(&via[IER], SR_INT); /* disable SR interrupt from VIA */ cuda_init_via() 277 (void)in_8(&via[SR]); cuda_init_via() 288 (void)in_8(&via[SR]); cuda_init_via() 297 (void)in_8(&via[SR]); cuda_init_via() 428 out_8(&via[SR], req->data[0]); cuda_start() 483 (void)in_8(&via[SR]); cuda_interrupt() 494 (void)in_8(&via[SR]); cuda_interrupt() 505 (void)in_8(&via[SR]); cuda_interrupt() 512 out_8(&via[SR], current_req->data[1]); cuda_interrupt() 523 (void)in_8(&via[SR]); cuda_interrupt() 536 out_8(&via[SR], req->data[data_index++]); cuda_interrupt() 542 *reply_ptr++ = in_8(&via[SR]); cuda_interrupt() 556 (void)in_8(&via[SR]); cuda_interrupt()
|
H A D | via-maciisi.c | 37 #define SR (10*RS) /* Shift register */ macro 163 /* Poll for SR interrupt */ maciisi_stfu() 167 tmp = via[SR]; /* Clear shift register */ maciisi_stfu() 203 tmp = via[SR]; maciisi_init_via() 406 via[SR] = req->data[0]; maciisi_start() 474 tmp = via[SR]; maciisi_interrupt() 489 /* via[SR]; */ maciisi_interrupt() 499 tmp = via[SR]; maciisi_interrupt() 516 tmp = via[SR]; maciisi_interrupt() 543 via[SR] = req->data[data_index++]; maciisi_interrupt() 568 *reply_ptr++ = via[SR]; maciisi_interrupt() 579 tmp = via[SR]; /* That's what happens in 2.2 */ maciisi_interrupt()
|
H A D | via-macii.c | 52 #define SR (10*RS) /* Shift register */ macro 187 x = via[SR]; macii_init_via() 362 via[SR] = req->data[1]; macii_start() 393 /* Clear the SR IRQ flag when polling. */ macii_interrupt() 414 x = via[SR]; macii_interrupt() 456 x = via[SR]; macii_interrupt() 461 via[SR] = req->data[data_index++]; macii_interrupt() 474 x = via[SR]; macii_interrupt() 515 x = via[SR]; macii_interrupt()
|
H A D | via-pmu68k.c | 58 #define SR (10*RS) /* Shift register */ macro 512 via1[SR] = x; send_byte() 522 c = via1[SR]; /* resets SR */ recv_byte() 581 } else if (irq == IRQ_MAC_ADB_SR) { /* SR interrupt */ pmu_interrupt() 587 if ((via1[ACR] & SR_OUT) == 0) bite = via1[SR]; pmu_interrupt()
|
H A D | via-pmu.c | 92 #define SR (10*RS) /* Shift register */ macro 1191 out_8(&v[SR], x); send_byte() 1202 in_8(&v[SR]); /* resets SR */ recv_byte() 1457 printk(KERN_ERR "PMU: spurious SR intr (%x)\n", via[B]); pmu_sr_intr() 1467 bite = in_8(&via[SR]); pmu_sr_intr() 2441 via[SR] = x; eieio(); polled_send_byte() 2451 x = via[SR]; eieio(); polled_recv_byte() 2453 x = via[SR]; eieio(); polled_recv_byte()
|
/linux-4.4.14/arch/avr32/mach-at32ap/ |
H A D | intc.c | 79 status_reg = sysreg_read(SR); do_IRQ() 82 sysreg_write(SR, status_reg); do_IRQ() 134 sysreg_write(SR, (sysreg_read(SR) init_IRQ()
|
/linux-4.4.14/drivers/power/avs/ |
H A D | smartreflex.c | 204 * Currently this function registers interrupt handler for a particular SR 206 * requested for interrupts and the SR interrupt line in present. 245 /* SRCONFIG - disable SR */ sr_v1_disable() 248 /* Disable all other SR interrupts and clear the status as needed */ sr_v1_disable() 257 * Wait for SR to be disabled. sr_v1_disable() 280 /* SRCONFIG - disable SR */ sr_v2_disable() 284 * Disable all other SR interrupts and clear the status sr_v2_disable() 302 * Wait for SR to be disabled. sr_v2_disable() 342 * @sr: SR module to be configured. 346 * SR settings if using the ERROR module inside Smartreflex. 347 * SR CLASS 3 by default uses only the ERROR module where as 348 * SR CLASS 2 can choose between ERROR module and MINMAXAVG 413 * @sr: SR module to be configured. 465 * @sr: SR module to be configured. 469 * SR settings if using the ERROR module inside Smartreflex. 470 * SR CLASS 3 by default uses only the ERROR module where as 471 * SR CLASS 2 can choose between ERROR module and MINMAXAVG 550 * @sr: pointer to which the SR module to be configured belongs to. 582 dev_warn(&sr->pdev->dev, "%s: failure getting SR data for this voltage %ld\n", sr_enable() 592 /* Check if SR is already enabled. If yes do nothing */ sr_enable() 596 /* Configure SR */ sr_enable() 603 /* SRCONFIG - enable SR */ sr_enable() 610 * @sr: pointer to which the SR module to be configured belongs to. 623 /* Check if SR clocks are already disabled. If yes do nothing */ sr_disable() 628 * Disable SR if only it is indeed enabled. Else just sr_disable() 685 * omap_sr_enable() - API to enable SR clocks and to call into the 687 * @voltdm: VDD pointer to which the SR module to be configured belongs to. 716 * omap_sr_disable() - API to disable SR without resetting the voltage 718 * @voltdm: VDD pointer to which the SR module to be configured belongs to. 748 * omap_sr_disable_reset_volt() - API to disable SR and reset the 750 * @voltdm: VDD pointer to which the SR module to be configured belongs to. 860 dev_err(&pdev->dev, "%s: unable to allocate SR instance name\n", omap_sr_probe() 915 pr_warning("%s: Error in SR late init\n", __func__); omap_sr_probe() 1060 pr_err("%s: platform driver register failed for SR\n", sr_init()
|
/linux-4.4.14/arch/arc/kernel/ |
H A D | fpu.c | 15 * To save/restore FPU regs, simplest scheme would use LR/SR insns. 16 * However since SR serializes the pipeline, an alternate "hack" can be used
|
/linux-4.4.14/arch/sh/kernel/cpu/irq/ |
H A D | imask.c | 6 * Simple interrupt handling using IMASK of SR register. 74 .name = "SR.IMASK",
|
/linux-4.4.14/arch/alpha/math-emu/ |
H A D | math.c | 101 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); alpha_fp_emul() 135 FP_SUB_S(SR, SA, SB); alpha_fp_emul() 139 FP_ADD_S(SR, SA, SB); alpha_fp_emul() 143 FP_MUL_S(SR, SA, SB); alpha_fp_emul() 147 FP_DIV_S(SR, SA, SB); alpha_fp_emul() 151 FP_SQRT_S(SR, SB); alpha_fp_emul() 221 FP_CONV(S,D,1,1,SR,DB); alpha_fp_emul() 259 FP_FROM_INT_S(SR, ((long)vb), 64, long); alpha_fp_emul() 271 FP_PACK_SP(&vc, SR); alpha_fp_emul()
|
/linux-4.4.14/arch/sh/kernel/cpu/sh3/ |
H A D | entry.S | 217 ! r8 passes SR bitmask, overwritten with restored data on return 245 mov.l @r15+, k3 ! original SR 259 ! Calculate new SR value 260 mov k3, k2 ! original SR value 264 and k1, k2 ! Mask original SR value 363 mov.l 1f, k4 ! SR bits to clear in k4 390 ! k4 passes SR bitmask 412 mov.l 0f, k3 ! SR bits to set in k3 417 ! - modify SR for bank switch 419 ! k3 passes bits to set in SR 420 ! k4 passes bits to clear in SR 451 mov.l 1f, k4 ! SR bits to clear in k4
|
H A D | swsusp.S | 109 mov.l 2f, r3 ! get new SR value for bank1 117 mov.l 3f, k4 ! SR bits to clear in k4
|
/linux-4.4.14/arch/m68k/include/asm/ |
H A D | macints.h | 65 #define IRQ_VIA1_2 (10) /* ADB SR shifts complete */ 68 #define IRQ_VIA1_3 (11) /* ADB SR CB2 ?? */ 70 #define IRQ_VIA1_4 (12) /* ADB SR ext. clock pulse */
|
H A D | processor.h | 89 unsigned long esp0; /* points to SR of stack frame */
|
/linux-4.4.14/sound/soc/codecs/ |
H A D | wm8523.h | 100 #define WM8523_SR_MASK 0x0007 /* SR - [2:0] */ 101 #define WM8523_SR_SHIFT 0 /* SR - [2:0] */ 102 #define WM8523_SR_WIDTH 3 /* SR - [2:0] */
|
H A D | wm8741.h | 168 #define WM8741_SR_MASK 0x001C /* SR - [4:2] */ 169 #define WM8741_SR_SHIFT 2 /* SR - [4:2] */ 170 #define WM8741_SR_WIDTH 3 /* SR - [4:2] */
|
H A D | wm8737.h | 232 #define WM8737_SR_MASK 0x003E /* SR - [5:1] */ 233 #define WM8737_SR_SHIFT 1 /* SR - [5:1] */ 234 #define WM8737_SR_WIDTH 5 /* SR - [5:1] */
|
H A D | wm8955.h | 140 #define WM8955_SR_MASK 0x003E /* SR - [5:1] */ 141 #define WM8955_SR_SHIFT 1 /* SR - [5:1] */ 142 #define WM8955_SR_WIDTH 5 /* SR - [5:1] */
|
H A D | cs42l52.c | 413 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0), 427 SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL, 442 SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1), 444 SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
|
H A D | cs4349.c | 167 "Immediate", "Zero Cross", "Soft Ramp", "SR on ZC",
|
H A D | wm8983.h | 268 #define WM8983_SR_MASK 0x000E /* SR - [3:1] */ 269 #define WM8983_SR_SHIFT 1 /* SR - [3:1] */ 270 #define WM8983_SR_WIDTH 3 /* SR - [3:1] */
|
H A D | wm8985.h | 270 #define WM8985_SR_MASK 0x000E /* SR - [3:1] */ 271 #define WM8985_SR_SHIFT 1 /* SR - [3:1] */ 272 #define WM8985_SR_WIDTH 3 /* SR - [3:1] */
|
H A D | wm5100.c | 149 dev_dbg(codec->dev, "SR %dHz, slot %d, ref %d\n", wm5100_alloc_sr() 155 dev_err(codec->dev, "All SR slots already in use\n"); wm5100_alloc_sr() 159 dev_dbg(codec->dev, "Allocating SR slot %d for %dHz\n", wm5100_alloc_sr() 170 "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n", wm5100_alloc_sr() 200 dev_dbg(codec->dev, "Dereference SR %dHz, count now %d\n", wm5100_free_sr()
|
/linux-4.4.14/arch/powerpc/include/asm/ |
H A D | pte-fsl-booke.h | 11 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
|
H A D | pte-44x.h | 32 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
|
/linux-4.4.14/arch/arm/mach-omap2/ |
H A D | smartreflex-class3.c | 48 /* SR class3 structure */
|
H A D | vc.c | 755 * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB 760 * the PCB trace, and for setting the SR I2C channel timing parameters.
|
/linux-4.4.14/arch/sparc/math-emu/ |
H A D | math_64.c | 180 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); do_mathemu() 432 case FADDS: FP_ADD_S (SR, SA, SB); break; do_mathemu() 436 case FSUBS: FP_SUB_S (SR, SA, SB); break; do_mathemu() 440 case FMULS: FP_MUL_S (SR, SA, SB); break; do_mathemu() 448 case FDIVS: FP_DIV_S (SR, SA, SB); break; do_mathemu() 452 case FSQRTS: FP_SQRT_S (SR, SB); break; do_mathemu() 470 case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break; do_mathemu() 473 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; do_mathemu() 480 case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break; do_mathemu() 481 case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break; do_mathemu() 508 case 5: FP_PACK_SP (rd, SR); break; do_mathemu()
|
H A D | math_32.c | 285 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); do_one_mathemu() 427 case FADDS: FP_ADD_S (SR, SA, SB); break; do_one_mathemu() 431 case FSUBS: FP_SUB_S (SR, SA, SB); break; do_one_mathemu() 435 case FMULS: FP_MUL_S (SR, SA, SB); break; do_one_mathemu() 443 case FDIVS: FP_DIV_S (SR, SA, SB); break; do_one_mathemu() 447 case FSQRTS: FP_SQRT_S (SR, SB); break; do_one_mathemu() 459 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; do_one_mathemu() 466 case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break; do_one_mathemu() 467 case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break; do_one_mathemu() 506 case 5: FP_PACK_SP (rd, SR); break; do_one_mathemu()
|
/linux-4.4.14/arch/sh/include/cpu-sh5/cpu/ |
H A D | registers.h | 25 #define SR cr0 macro 87 #define __SR __str(SR)
|
/linux-4.4.14/drivers/video/fbdev/omap2/dss/ |
H A D | dispc.c | 283 #define SR(reg) \ macro 294 SR(IRQENABLE); dispc_save_context() 295 SR(CONTROL); dispc_save_context() 296 SR(CONFIG); dispc_save_context() 297 SR(LINE_NUMBER); dispc_save_context() 300 SR(GLOBAL_ALPHA); dispc_save_context() 302 SR(CONTROL2); dispc_save_context() 303 SR(CONFIG2); dispc_save_context() 306 SR(CONTROL3); dispc_save_context() 307 SR(CONFIG3); dispc_save_context() 311 SR(DEFAULT_COLOR(i)); dispc_save_context() 312 SR(TRANS_COLOR(i)); dispc_save_context() 313 SR(SIZE_MGR(i)); dispc_save_context() 316 SR(TIMING_H(i)); dispc_save_context() 317 SR(TIMING_V(i)); dispc_save_context() 318 SR(POL_FREQ(i)); dispc_save_context() 319 SR(DIVISORo(i)); dispc_save_context() 321 SR(DATA_CYCLE1(i)); dispc_save_context() 322 SR(DATA_CYCLE2(i)); dispc_save_context() 323 SR(DATA_CYCLE3(i)); dispc_save_context() 326 SR(CPR_COEF_R(i)); dispc_save_context() 327 SR(CPR_COEF_G(i)); dispc_save_context() 328 SR(CPR_COEF_B(i)); dispc_save_context() 333 SR(OVL_BA0(i)); dispc_save_context() 334 SR(OVL_BA1(i)); dispc_save_context() 335 SR(OVL_POSITION(i)); dispc_save_context() 336 SR(OVL_SIZE(i)); dispc_save_context() 337 SR(OVL_ATTRIBUTES(i)); dispc_save_context() 338 SR(OVL_FIFO_THRESHOLD(i)); dispc_save_context() 339 SR(OVL_ROW_INC(i)); dispc_save_context() 340 SR(OVL_PIXEL_INC(i)); dispc_save_context() 342 SR(OVL_PRELOAD(i)); dispc_save_context() 344 SR(OVL_WINDOW_SKIP(i)); dispc_save_context() 345 SR(OVL_TABLE_BA(i)); dispc_save_context() 348 SR(OVL_FIR(i)); dispc_save_context() 349 SR(OVL_PICTURE_SIZE(i)); dispc_save_context() 350 SR(OVL_ACCU0(i)); dispc_save_context() 351 SR(OVL_ACCU1(i)); dispc_save_context() 354 SR(OVL_FIR_COEF_H(i, j)); dispc_save_context() 357 SR(OVL_FIR_COEF_HV(i, j)); dispc_save_context() 360 SR(OVL_CONV_COEF(i, j)); dispc_save_context() 364 SR(OVL_FIR_COEF_V(i, j)); dispc_save_context() 368 SR(OVL_BA0_UV(i)); dispc_save_context() 369 SR(OVL_BA1_UV(i)); dispc_save_context() 370 SR(OVL_FIR2(i)); dispc_save_context() 371 SR(OVL_ACCU2_0(i)); dispc_save_context() 372 SR(OVL_ACCU2_1(i)); dispc_save_context() 375 SR(OVL_FIR_COEF_H2(i, j)); dispc_save_context() 378 SR(OVL_FIR_COEF_HV2(i, j)); dispc_save_context() 381 SR(OVL_FIR_COEF_V2(i, j)); dispc_save_context() 384 SR(OVL_ATTRIBUTES2(i)); dispc_save_context() 388 SR(DIVISOR); dispc_save_context() 514 #undef SR macro
|
H A D | dss.c | 133 #define SR(reg) \ macro 142 SR(CONTROL); dss_save_context() 146 SR(SDI_CONTROL); dss_save_context() 147 SR(PLL_CONTROL); dss_save_context() 173 #undef SR macro
|
H A D | hdmi4_core.c | 623 * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as hdmi_core_audio_config()
|
/linux-4.4.14/include/linux/power/ |
H A D | smartreflex.h | 204 * @sensor_voltdm_name: Name of voltdomain of SR instance 212 * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR. 227 * @notify: API to notify the class driver about an event in SR. 231 * Can be used by the SR driver to take any class 275 * @voltdm: Pointer to the voltage domain associated with the SR
|
/linux-4.4.14/arch/sh/kernel/cpu/sh2/ |
H A D | entry.S | 51 mov.l @(5*4,r15),r3 ! previous SR 55 mov.l r3,@(5*4,r15) ! update SR 71 mov.l r0,@-r15 ! original SR 115 mov.l @r2+,r0 ! old SR 121 mov.l r0,@-r2 ! save old SR
|
/linux-4.4.14/arch/sh/kernel/cpu/sh2a/ |
H A D | entry.S | 49 bld.b #6,@(0,r2) !previus SR.MD 50 bst.b #6,@(4*4,r15) !set cpu mode to SR.MD 53 bset.b #6,@(0,r2) !set SR.MD 66 mov.l r0,@-r15 ! original SR 94 mov.l @r8+,r11 ! old SR
|
/linux-4.4.14/arch/sh/include/asm/ |
H A D | processor_32.h | 45 * Bit of SR register 151 /* Set FD flag in SR */ disable_fpu() 163 /* Clear out FD flag in SR */ enable_fpu()
|
H A D | mmu_context_64.h | 41 /* Set ASID into SR */ set_asid()
|
H A D | processor_64.h | 53 * Bit of SR register 185 /* Set FD flag in SR */ disable_fpu() 197 /* Clear out FD flag in SR */ enable_fpu()
|
/linux-4.4.14/drivers/rtc/ |
H A D | rtc-isl1208.c | 246 dev_err(&client->dev, "%s: reading SR failed\n", __func__); isl1208_rtc_proc() 285 dev_err(&client->dev, "%s: reading SR failed\n", __func__); isl1208_i2c_read_time() 328 dev_err(&client->dev, "%s: reading SR failed\n", __func__); isl1208_i2c_read_alarm() 443 dev_err(&client->dev, "%s: reading SR failed\n", __func__); isl1208_i2c_set_time() 451 dev_err(&client->dev, "%s: writing SR failed\n", __func__); isl1208_i2c_set_time() 467 dev_err(&client->dev, "%s: writing SR failed\n", __func__); isl1208_i2c_set_time() 512 dev_err(&client->dev, "%s: reading SR failed\n", isl1208_rtc_interrupt() 527 dev_err(&client->dev, "%s: writing SR failed\n", isl1208_rtc_interrupt()
|
H A D | rtc-rv3029c2.c | 150 dev_err(&client->dev, "%s: reading SR failed\n", __func__); rv3029c2_i2c_read_time() 199 dev_err(&client->dev, "%s: reading SR failed\n", __func__); rv3029c2_i2c_read_alarm() 272 dev_err(&client->dev, "%s: reading SR failed\n", __func__); rv3029c2_rtc_i2c_set_alarm() 357 dev_err(&client->dev, "%s: reading SR failed\n", __func__); rv3029c2_i2c_set_time() 363 dev_err(&client->dev, "%s: reading SR failed\n", __func__); rv3029c2_i2c_set_time()
|
H A D | rtc-at91sam9.c | 283 * SR clears it, so we must only read it in this irq handler! at91_rtc_cache_events() 286 sr = rtt_readl(rtc, SR) & (mr >> 16); at91_rtc_cache_events()
|
/linux-4.4.14/drivers/net/ethernet/intel/fm10k/ |
H A D | fm10k_iov.c | 325 "Unable to initialize SR-IOV mailbox\n"); fm10k_iov_alloc_data() 344 "Cannot disable SR-IOV while VFs are assigned\n"); fm10k_iov_disable() 372 "Cannot modify SR-IOV while VFs are assigned\n"); fm10k_iov_configure() 395 "Enable PCI SR-IOV failed: %d\n", err); fm10k_iov_configure() 430 /* verify SR-IOV is active and that vf idx is valid */ fm10k_ndo_set_vf_mac() 455 /* verify SR-IOV is active and that vf idx is valid */ fm10k_ndo_set_vf_vlan() 487 /* verify SR-IOV is active and that vf idx is valid */ fm10k_ndo_set_vf_bw() 511 /* verify SR-IOV is active and that vf idx is valid */ fm10k_ndo_get_vf_config()
|
H A D | fm10k.h | 310 /* SR-IOV information management structure */
|
H A D | fm10k_type.h | 75 /* PCIe SR-IOV Info */
|
H A D | fm10k_pci.c | 1957 /* enable SR-IOV after registering netdev to enforce PF/VF ordering */ fm10k_probe() 2107 /* restore SR-IOV interface */ fm10k_resume()
|
/linux-4.4.14/drivers/video/fbdev/via/ |
H A D | viamode.h | 29 unsigned char SR[StdSR]; member in struct:VPITTable
|
H A D | viamode.c | 248 unsigned char SR[StdSR];
|
/linux-4.4.14/drivers/cpuidle/ |
H A D | cpuidle-kirkwood.c | 49 .name = "DDR SR",
|
/linux-4.4.14/arch/arm/mach-davinci/ |
H A D | cpuidle.c | 68 .name = "DDR SR",
|
/linux-4.4.14/arch/m68k/ifpsp060/ |
H A D | iskeleton.S | 72 btst #0x5,%sp@ | supervisor bit set in saved SR? 107 | * SR * * SR * 147 | * SR * * SR *
|
/linux-4.4.14/drivers/media/pci/ngene/ |
H A D | ngene-core.c | 97 while (Cur->ngeneBuffer.SR.Flags & 0x80) { demux_tasklet() 100 if (Cur->ngeneBuffer.SR.Flags & 0x20) demux_tasklet() 106 Cur->ngeneBuffer.SR. demux_tasklet() 120 Cur->ngeneBuffer.SR.Flags &= demux_tasklet() 133 Cur->ngeneBuffer.SR.Flags &= ~0x40; demux_tasklet() 141 Cur->ngeneBuffer.SR.DTOUpdate = demux_tasklet() 150 if (Cur->ngeneBuffer.SR.Flags & 0x01) demux_tasklet() 152 if (Cur->ngeneBuffer.SR.Flags & 0x20) demux_tasklet() 158 Cur->ngeneBuffer.SR.Clock, demux_tasklet() 163 Cur->ngeneBuffer.SR.Clock, demux_tasklet() 169 Cur->ngeneBuffer.SR.Flags = 0x00; demux_tasklet() 235 ngeneBuffer.SR.Flags & 0xC0) == 0x80) { irq_handler() 237 ngeneBuffer.SR.Flags |= 0x40; irq_handler() 521 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80; flush_buffers() 531 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR)); clear_buffers() 540 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate = clear_buffers() 547 memset(&Cur->ngeneBuffer.SR, 0, clear_buffers() 548 sizeof(Cur->ngeneBuffer.SR)); clear_buffers()
|
H A D | ngene.h | 188 struct BUFFER_STREAM_RESULTS SR; member in struct:BUFFER_HEADER
|
/linux-4.4.14/drivers/pci/ |
H A D | iov.c | 39 * Per SR-IOV spec sec 3.3.10 and 3.3.11, First VF Offset and VF Stride may 273 dev_err(&dev->dev, "not enough MMIO resources for SR-IOV\n"); sriov_enable() 285 dev_err(&dev->dev, "SR-IOV: IOV BARS not allocated\n"); sriov_enable() 558 * pci_iov_resource_bar - get position of the SR-IOV BAR 562 * Returns position of the BAR encapsulated in the SR-IOV capability. 586 * Returns the alignment of the VF BAR found in the SR-IOV capability. 629 * pci_enable_sriov - enable the SR-IOV capability 647 * pci_disable_sriov - disable the SR-IOV capability 665 * Returns number of VFs, or 0 if SR-IOV is not enabled.
|
H A D | remove.c | 68 * Stopping an SR-IOV PF device removes all the associated VFs, pci_stop_bus_device()
|
H A D | pci.h | 251 u32 cap; /* SR-IOV Capabilities */ 252 u16 ctrl; /* SR-IOV Control */
|
H A D | probe.c | 689 * created by an SR-IOV device. Walk up to the first bridge device pci_set_bus_msi_domain() 2037 /* Reserve buses for SR-IOV capability. */ pci_scan_child_bus()
|
/linux-4.4.14/arch/powerpc/math-emu/ |
H A D | math_efp.c | 219 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); do_spe_mathemu() 250 FP_ADD_S(SR, SA, SB); do_spe_mathemu() 254 FP_SUB_S(SR, SA, SB); do_spe_mathemu() 258 FP_MUL_S(SR, SA, SB); do_spe_mathemu() 262 FP_DIV_S(SR, SA, SB); do_spe_mathemu() 297 FP_CONV(S, D, 1, 2, SR, DB); do_spe_mathemu() 329 pr_debug("SR: %ld %08lx %ld (%ld)\n", SR_s, SR_f, SR_e, SR_c); do_spe_mathemu() 331 FP_PACK_SP(vc.wp + 1, SR); do_spe_mathemu()
|
/linux-4.4.14/arch/openrisc/kernel/ |
H A D | ptrace.c | 49 * SR (Supervision register) 100 * Skip SR and padding... userspace isn't allowed to changes bits in genregs_set()
|
H A D | traps.c | 119 " PC: %08lx SR: %08lx SP: %08lx\n", show_registers() 181 " PC: %08lx SR: %08lx SP: %08lx\n", nommu_dump_state()
|
H A D | head.S | 143 * r13 - temp it actually contains new SR, not needed anymore 545 * SR[5] = 0, SR[6] = 0, 6th and 7th bit of SR set to 0 853 l.rfe // SR <- ESR, PC <- EPC 946 l.rfe // SR <- ESR, PC <- EPC
|
H A D | entry.S | 254 l.mfspr r6,r0,SPR_SR // SR 986 /* We don't store SR as _switch only gets called in a context where 987 * the SR will be the same going in and coming out... */
|
/linux-4.4.14/arch/sh/kernel/cpu/sh5/ |
H A D | entry.S | 22 * SR fields. 83 getcon SR, r6; \ 85 putcon r6, SR; 88 getcon SR, r6; \ 90 putcon r6, SR; 606 ! construct useful SR for handle_exception 613 ! SSR is now the current SR with the MD and MMU bits set 818 /* We are in a safe position to turn SR.BL off, but set IMASK=0xf 831 getcon SR, r6 834 putcon r6, SR 837 putcon r6, SR 909 getcon SR, r7 1039 getcon SR, r59 1042 putcon r59, SR /* SR.BL = 1, keep nesting out */ 1331 shlli r2, 16, r2 /* align new ASID against SR.ASID */ 1332 andc r0, r4, r0 /* efface old ASID from SR */ 1382 getcon sr, r0 /* r0 = saved original SR */ 1431 getcon sr, r0 /* r0 = saved original SR */ 1994 /* Now that exception vectors are set up reset SR.BL */ 1995 getcon SR, r22 1998 putcon r22, SR
|
/linux-4.4.14/drivers/crypto/qat/qat_dh895xcc/ |
H A D | adf_isr.c | 70 /* If SR-IOV is disabled, add entries for each bank */ adf_enable_msix() 110 /* If SR-IOV is enabled (vf_info is non-NULL), check for VF->PF ints */ adf_msix_isr_ae() 172 /* Request msix irq for all banks unless SR-IOV enabled */ adf_request_irqs() 237 /* If SR-IOV is disabled (vf_info is NULL), add entries for each bank */ adf_isr_alloc_msix_entry_table()
|
/linux-4.4.14/include/linux/mmc/ |
H A D | dw_mmc.h | 74 * @cmd_status: Snapshot of SR taken upon completion of the current 76 * @data_status: Snapshot of SR taken upon completion of the current 138 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 140 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
|
/linux-4.4.14/arch/avr32/kernel/ |
H A D | ptrace.c | 33 pr_debug("user_enable_single_step: pid=%u, PC=0x%08lx, SR=0x%08lx\n", user_enable_single_step() 246 pr_debug("do_debug: status=0x%08x PC=0x%08lx SR=0x%08lx tif=0x%08lx\n", do_debug() 271 "PC=0x%08lx SR=0x%08lx\n", do_debug() 349 pr_debug("Sending SIGTRAP: code=%d PC=0x%08lx SR=0x%08lx\n", do_debug()
|
H A D | entry-avr32b.S | 314 1: pushm r11, r12 /* PC and SR */ 436 1: pushm r8, r9 /* PC and SR */ 703 * not schedule since that involves the D bit in SR getting
|
H A D | kprobes.c | 73 BUG_ON(!(sysreg_read(SR) & SYSREG_BIT(SR_D))); prepare_singlestep()
|
H A D | signal.c | 278 if ((sysreg_read(SR) & MODE_MASK) == MODE_SUPERVISOR) do_notify_resume()
|
/linux-4.4.14/drivers/net/ethernet/intel/ixgbe/ |
H A D | ixgbe_lib.c | 34 * ixgbe_cache_ring_dcb_sriov - Descriptor ring to register mapping for SR-IOV 37 * Cache the descriptor ring offsets for SR-IOV to the assigned rings. It 60 /* start at VMDq register offset for SR-IOV enabled setups */ ixgbe_cache_ring_dcb_sriov() 199 * SR-IOV doesn't use any descriptor rings but changes the default if 217 /* start at VMDq register offset for SR-IOV enabled setups */ ixgbe_cache_ring_sriov() 318 * ixgbe_set_dcb_sriov_queues: Allocate queues for SR-IOV devices w/ DCB 321 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues 487 * ixgbe_set_sriov_queues - Allocate queues for SR-IOV devices 490 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues 506 /* only proceed if SR-IOV is enabled */ ixgbe_set_sriov_queues() 1123 /* Disable SR-IOV support */ ixgbe_set_interrupt_capability() 1124 e_dev_warn("Disabling SR-IOV support\n"); ixgbe_set_interrupt_capability()
|
H A D | ixgbe_sriov.c | 56 e_info(probe, "SR-IOV enabled with %d VFs\n", adapter->num_vfs); __ixgbe_enable_sriov() 105 /* Disable RSC when in SR-IOV mode */ __ixgbe_enable_sriov() 133 /* Note this function is called when the user wants to enable SR-IOV 148 * have been created via the new PCI SR-IOV sysfs interface. ixgbe_enable_sriov() 203 /* if SR-IOV is already disabled then there is nothing to do */ ixgbe_disable_sriov() 209 * If our VFs are assigned we cannot shut down SR-IOV ixgbe_disable_sriov() 267 /* While the SR-IOV capability structure reports total VFs to be 64, ixgbe_pci_sriov_enable() 270 * Second, VMDQ also uses the same pools that SR-IOV does. We need to ixgbe_pci_sriov_enable()
|
H A D | ixgbe.h | 304 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 762 /* SR-IOV */
|
H A D | ixgbe_main.c | 3269 * SR-IOV is enabled ixgbe_set_rx_drop_en() 3408 /* Program table for at least 2 queues w/ SR-IOV so that VFs can ixgbe_setup_reta() 3709 * i.e. 32 or 64 VFs for SR-IOV ixgbe_configure_virtualization() 4221 * if SR-IOV and VMDQ are disabled - otherwise ensure ixgbe_set_rx_mode() 5021 * If SR-IOV enabled then wait a bit before bringing the adapter ixgbe_reinit_locked() 5434 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); ixgbe_sw_init() 5436 /* assign number of SR-IOV VFs */ ixgbe_sw_init() 5440 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); ixgbe_sw_init() 8043 /* We cannot enable ATR if SR-IOV is enabled */ ixgbe_set_features() 8208 /* disable Rx switching replication unless we have SR-IOV ixgbe_configure_bridge_mode() 8609 * the PCIe SR-IOV capability. ixgbe_probe() 8759 /* SR-IOV not supported on the 82598 */ ixgbe_probe()
|
H A D | ixgbe_ethtool.c | 2937 /*Allow at least 2 queues w/ SR-IOV.*/ ixgbe_set_rxfh() 3008 /* SR-IOV currently only allows one queue on the PF */ ixgbe_max_channels() 3054 /* we do not support ATR queueing if SR-IOV is enabled */ ixgbe_get_channels()
|
/linux-4.4.14/drivers/crypto/qat/qat_common/ |
H A D | adf_sriov.c | 155 * Due to the hardware design, when SR-IOV and the ring arbiter adf_enable_sriov() 158 * When SR-IOV is enabled, each of the VFs will own one bundle. adf_enable_sriov() 238 dev_warn(&pdev->dev, "IOMMU should be enabled for SR-IOV to work correctly\n"); adf_sriov_configure()
|
H A D | adf_accel_devices.h | 229 /* vf_info is non-zero when SR-IOV is init'ed */
|
/linux-4.4.14/arch/sh/kernel/cpu/ |
H A D | init.c | 237 /* Clear SR.DSP bit */ release_dsp() 252 * Set the SR.DSP bit, wait for one instruction, and then read dsp_init() 253 * back the SR value. dsp_init()
|
/linux-4.4.14/drivers/i2c/busses/ |
H A D | i2c-iop3xx.c | 88 /* NB SR bits not same position as CR IE bits :-( */ iop3xx_i2c_enable() 112 * Then it passes the SR flags of interest to BH via adap data 158 * sleep until interrupted, then recover and analyse the SR
|
H A D | i2c-at91.c | 495 * TXCOMP and TXRDY bits all together in the Status Register (SR). atmel_twi_interrupt() 505 * By setting the TXRDY bit in the SR, the I2C controller also triggers atmel_twi_interrupt() 516 * sets once again the NACK bit into the SR. atmel_twi_interrupt() 519 * Hence, the NACK bit is pending into the SR. This is why we should atmel_twi_interrupt() 520 * read the SR to clear all pending interrupts at the beginning of atmel_twi_interrupt() 526 * THR (and sets the LOCK bit in the SR): even though the DMA controller atmel_twi_interrupt()
|
H A D | i2c-xiic.c | 308 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", xiic_read_rx() 379 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", xiic_process() 676 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, xiic_xfer()
|
H A D | i2c-nomadik.c | 71 /* Status register (SR) */
|
/linux-4.4.14/arch/powerpc/kvm/ |
H A D | book3s_32_mmu_host.c | 102 dprintk_sr("SR: Searching 0x%llx -> 0x%llx\n", find_sid_vsid() 109 dprintk_sr("SR: Searching 0x%llx -> 0x%llx\n", find_sid_vsid() 114 dprintk_sr("SR: Searching 0x%llx -> not found\n", gvsid); find_sid_vsid()
|
H A D | book3s_32_mmu.c | 213 dprintk_pte("SR 0x%lx: vsid=0x%x, raw=0x%x\n", eaddr >> 28, kvmppc_mmu_book3s_32_xlate_pte()
|
/linux-4.4.14/arch/s390/kernel/ |
H A D | sysinfo.c | 418 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); s390_adjust_jiffies() 443 FP_DIV_S(SR, SA, SB); s390_adjust_jiffies() 444 FP_TO_INT_S(capability, SR, 32, 0); s390_adjust_jiffies()
|
H A D | early.c | 120 "DEFSYS %s 00000-%.5X EW %.5X-%.5X SR %.5X-%.5X", create_kernel_nss()
|
/linux-4.4.14/drivers/pci/hotplug/ |
H A D | pciehp_pci.c | 93 * Stopping an SR-IOV PF device removes all the associated VFs, pciehp_unconfigure_device()
|
/linux-4.4.14/drivers/net/ethernet/sfc/ |
H A D | siena_sriov.h | 31 /* Base VI to use for SR-IOV. Must be aligned to (1 << EFX_VI_SCALE_MAX),
|
H A D | filter.h | 67 * networking and SR-IOV)
|
H A D | ef10_sriov.c | 390 "please detach them before disabling SR-IOV\n"); efx_ef10_pci_sriov_disable()
|
H A D | siena_sriov.c | 1062 netif_info(efx, probe, efx->net_dev, "no SR-IOV VFs probed\n"); efx_siena_sriov_probe() 1348 "enabled SR-IOV for %d VFs, %d VI per VF\n", efx_siena_sriov_init()
|
/linux-4.4.14/arch/openrisc/include/asm/ |
H A D | processor.h | 28 /* Kernel and user SR register setting */
|
/linux-4.4.14/arch/h8300/include/asm/ |
H A D | processor.h | 60 unsigned long esp0; /* points to SR of stack frame */
|
/linux-4.4.14/arch/blackfin/include/asm/ |
H A D | processor.h | 57 unsigned long esp0; /* points to SR of stack frame pt_regs */
|
/linux-4.4.14/arch/m68k/ifpsp060/src/ |
H A D | isp.S | 612 # * SR * * Next * 615 # from link -->* A6 * * SR * 641 # * SR * * Next * 644 # * SR * 656 mov.w EXC_ISR(%a6),(%a6) # put new SR on stack 674 # * SR * * Next * 677 # * SR * 690 mov.w EXC_ISR(%a6),(%a6) # put new SR on stack 711 # * SR * * SR * 747 # * SR * * SR * 782 # * Current * * SR * 785 # * SR * 794 mov.w EXC_ISR(%a6),0x8(%a6) # put SR on stack 3193 # (2) Save current SR; Then mask off all maskable interrupts. # 3280 mov.w %sr,%d7 # save current SR 3334 # D7 = old SR 3415 mov.w %d7,%sr # restore old SR 3427 mov.w %d7,%sr # restore old SR 3582 mov.w %sr,%d7 # save current SR 3634 # D7 = old SR 3715 mov.w %d7,%sr # restore old SR 3727 mov.w %d7,%sr # restore old SR 3813 # (2) Save current SR; Then mask off all maskable interrupts. # 3891 mov.w %sr,%d7 # save current SR 3925 # D7 = old SR 4014 mov.w %d7,%sr # restore old SR 4026 mov.w %d7,%sr # restore old SR 4049 mov.w %sr,%d7 # save current SR 4081 # D7 = old SR 4170 mov.w %d7,%sr # restore old SR 4182 mov.w %d7,%sr # restore old SR 4195 mov.w %sr,%d7 # save current SR 4229 # D7 = old SR
|
/linux-4.4.14/drivers/spi/ |
H A D | spi-atmel.c | 103 /* Bitfields in SR */ 609 while (spi_readl(as, SR) & SPI_BIT(RDRF)) { atmel_spi_next_xfer_single() 664 (void)spi_readl(as, SR); atmel_spi_next_xfer_fifo() 1115 status = spi_readl(as, SR); atmel_spi_pio_interrupt() 1136 spi_readl(as, SR); atmel_spi_pio_interrupt() 1172 status = spi_readl(as, SR); atmel_spi_pdc_interrupt() 1183 spi_readl(as, SR); atmel_spi_pdc_interrupt() 1371 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) atmel_spi_one_transfer() 1376 while (spi_readl(as, SR) & SPI_BIT(RDRF)) atmel_spi_one_transfer() 1380 spi_readl(as, SR); atmel_spi_one_transfer() 1680 spi_readl(as, SR); atmel_spi_remove()
|
H A D | spi-dw.h | 59 /* Bit fields in SR, 7 bits */
|
H A D | spi-dw.c | 82 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR)); dw_spi_show_regs()
|
H A D | spi-rockchip.c | 118 /* Bit fields in SR, 5bit */
|
/linux-4.4.14/drivers/input/serio/ |
H A D | at32psif.c | 113 status = psif_readl(psif, SR); psif_interrupt() 140 while (!(psif_readl(psif, SR) & PSIF_BIT(TXEMPTY)) && timeout--) psif_write()
|
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
H A D | vga.c | 38 port == 0x03c4 || port == 0x03c5 || /* SR */ nvkm_rdport() 60 port == 0x03c4 || port == 0x03c5 || /* SR */ nvkm_wrport()
|
/linux-4.4.14/arch/powerpc/sysdev/ |
H A D | ppc4xx_cpm.c | 298 * CPM registers in the following order (ER,FR,SR). The cpm_init() 299 * others have them in the following order (SR,ER,FR). cpm_init()
|
H A D | uic.c | 109 /* On the UIC, acking (i.e. clearing the SR bit) uic_mask_ack_irq()
|
/linux-4.4.14/drivers/net/ethernet/intel/i40e/ |
H A D | i40e_nvm.c | 36 * in this file) as an equivalent of the FLASH part mapped into the SR. 46 /* The SR size is stored regardless of the nvm programming mode i40e_init_nvm() 234 /* Here we are checking the SR limit only for the flat memory model. i40e_read_nvm_aq() 314 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() 345 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq() 402 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() 445 /* Here we are checking the SR limit only for the flat memory model. i40e_write_nvm_aq() 520 /* Read SR page */ i40e_calc_nvm_checksum() 563 * This function will commit SR to NVM.
|
H A D | i40e_virtchnl_pf.c | 893 dev_warn(&pf->pdev->dev, "VFs are assigned - not disabling SR-IOV\n"); i40e_free_vfs() 916 * work correctly when SR-IOV gets re-enabled. i40e_free_vfs() 1001 "Cannot enable SR-IOV virtual functions while the device is undergoing diagnostic testing\n"); i40e_pci_sriov_enable() 1021 dev_warn(&pdev->dev, "Failed to enable SR-IOV: %d\n", err); i40e_pci_sriov_enable()
|
/linux-4.4.14/drivers/usb/misc/sisusbvga/ |
H A D | sisusb_struct.h | 71 unsigned char SR[4]; member in struct:SiS_StandTable
|
H A D | sisusb_init.c | 355 SRdata = SiS_Pr->SiS_StandTable[StandTableIndex].SR[0] | 0x20; SiS_SetSeqRegs() 359 SRdata = SiS_Pr->SiS_StandTable[StandTableIndex].SR[i - 1]; SiS_SetSeqRegs()
|
/linux-4.4.14/drivers/misc/ |
H A D | atmel-ssc.c | 188 ssc_readl(ssc->regs, SR); ssc_probe()
|
/linux-4.4.14/arch/sh/mm/ |
H A D | tlbex_64.c | 18 * has to run with SR.BL==1, i.e. no interrupts taken inside it and panic
|
/linux-4.4.14/arch/frv/kernel/ |
H A D | cmode.S | 117 # (7) Set '1' to the DRCN.SR bit, and change SDRAM to the
|
/linux-4.4.14/drivers/net/ethernet/qlogic/qlcnic/ |
H A D | qlcnic_sriov_pf.c | 461 "SR-IOV is disabled successfully on port %d\n", qlcnic_sriov_pf_disable() 471 "SR-IOV VFs belonging to port %d are assigned to VMs. SR-IOV can not be disabled on this port\n", qlcnic_pci_sriov_disable() 474 "Please detach SR-IOV VFs belonging to port %d from VMs, and then try to disable SR-IOV on this port\n", qlcnic_pci_sriov_disable() 624 "SR-IOV cannot be enabled, when legacy interrupts are enabled\n"); qlcnic_pci_sriov_enable() 643 "SR-IOV is enabled successfully on port %d\n", qlcnic_pci_sriov_enable() 660 netdev_info(netdev, "Failed to enable SR-IOV on port %d\n", qlcnic_pci_sriov_enable()
|
H A D | qlcnic_83xx_init.c | 2292 * If SR-IOV capability is detected, SR-IOV physical function qlcnic_83xx_get_nic_configuration() 2294 * SR-IOV virtual function initialization follows a qlcnic_83xx_get_nic_configuration() 2534 /* Configure default, SR-IOV or Virtual NIC mode of operation */ qlcnic_83xx_init()
|
/linux-4.4.14/include/uapi/linux/ |
H A D | if_link.h | 132 IFLA_NUM_VF, /* Number of VFs if device is SR-IOV PF */ 532 /* SR-IOV virtual function management section */
|
H A D | mdio.h | 135 #define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */ 162 #define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */
|
H A D | pci_regs.h | 868 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 871 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ 877 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
|
/linux-4.4.14/drivers/xen/xen-pciback/ |
H A D | pciback_ops.c | 57 * SR-IOV devices in all use MSI-X and have no legacy xen_pcibk_control_isr() 291 * SR-IOV devices (which don't have any legacy IRQ) have xen_pcibk_disable_msix()
|
/linux-4.4.14/drivers/scsi/megaraid/ |
H A D | megaraid_sas_base.c | 79 MODULE_PARM_DESC(allow_vf_ioctls, "Allow ioctls in SR-IOV VF mode. Default: 0"); 2007 dev_warn(&instance->pdev->dev, "SR-IOV: Couldn't get LD/VF " megasas_get_ld_vf_affiliation_111() 2022 dev_printk(KERN_DEBUG, &instance->pdev->dev, "SR-IOV: Couldn't allocate " megasas_get_ld_vf_affiliation_111() 2054 dev_warn(&instance->pdev->dev, "SR-IOV: Getting LD/VF affiliation for " megasas_get_ld_vf_affiliation_111() 2060 dev_warn(&instance->pdev->dev, "SR-IOV: LD/VF affiliation DCMD" megasas_get_ld_vf_affiliation_111() 2072 dev_warn(&instance->pdev->dev, "SR-IOV: " megasas_get_ld_vf_affiliation_111() 2118 dev_warn(&instance->pdev->dev, "SR-IOV: Couldn't get LD/VF " megasas_get_ld_vf_affiliation_12() 2134 dev_printk(KERN_DEBUG, &instance->pdev->dev, "SR-IOV: Couldn't allocate " megasas_get_ld_vf_affiliation_12() 2166 dev_warn(&instance->pdev->dev, "SR-IOV: Getting LD/VF affiliation for " megasas_get_ld_vf_affiliation_12() 2172 dev_warn(&instance->pdev->dev, "SR-IOV: LD/VF affiliation DCMD" megasas_get_ld_vf_affiliation_12() 2181 dev_warn(&instance->pdev->dev, "SR-IOV: Got new LD/VF " megasas_get_ld_vf_affiliation_12() 2247 dev_warn(&instance->pdev->dev, "SR-IOV: Got new LD/VF " megasas_get_ld_vf_affiliation_12() 2264 /* This function will get the current SR-IOV LD/VF affiliation */ megasas_get_ld_vf_affiliation() 2277 /* This function will tell FW to start the SR-IOV heartbeat */ megasas_sriov_start_heartbeat() 2302 dev_printk(KERN_DEBUG, &instance->pdev->dev, "SR-IOV: Couldn't allocate" megasas_sriov_start_heartbeat() 2324 dev_warn(&instance->pdev->dev, "SR-IOV: Starting heartbeat for scsi%d\n", megasas_sriov_start_heartbeat() 2334 dev_warn(&instance->pdev->dev, "SR-IOV: MR_DCMD_CTRL_SHARED_HOST" megasas_sriov_start_heartbeat() 2347 /* Handler for SR-IOV heartbeat */ megasas_sriov_heartbeat_handler() 2360 dev_warn(&instance->pdev->dev, "SR-IOV: Heartbeat never " megasas_sriov_heartbeat_handler() 4876 dev_info(&instance->pdev->dev, "SR-IOV: firmware type: %s\n", megasas_init_fw() 4936 /* Launch SR-IOV heartbeat timer */ megasas_init_fw() 5567 /* Get current SR-IOV LD/VF affiliation */ megasas_probe_one() 5713 /* Shutdown SR-IOV heartbeat timer */ megasas_suspend() 5819 /* Re-launch SR-IOV heartbeat timer */ megasas_resume() 5888 /* Shutdown SR-IOV heartbeat timer */ megasas_detach_one()
|
H A D | megaraid_sas_fusion.c | 2602 /* If SR-IOV VF mode & heartbeat timeout, don't wait */ megasas_wait_for_outstanding_fusion() 2608 /* If SR-IOV VF mode & I/O timeout, check for HB timeout */ megasas_wait_for_outstanding_fusion() 2619 dev_warn(&instance->pdev->dev, "SR-IOV:" megasas_wait_for_outstanding_fusion() 2839 /* Let SR-IOV VF & PF sync up if there was a HB failure */ megasas_reset_fusion() 2848 dev_warn(&instance->pdev->dev, "SR-IOV:" megasas_reset_fusion() 2865 "SR-IOV: FW was found" megasas_reset_fusion() 2874 dev_warn(&instance->pdev->dev, "SR-IOV: " megasas_reset_fusion() 2940 /* Restart SR-IOV heartbeat */ megasas_reset_fusion()
|
H A D | megaraid_sas_fusion.h | 503 #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/
|
/linux-4.4.14/drivers/net/ethernet/broadcom/bnx2x/ |
H A D | bnx2x_sriov.h | 49 u32 cap; /* SR-IOV Capabilities */ 50 u16 ctrl; /* SR-IOV Control */ 327 /* SR-IOV information */
|
H A D | bnx2x_sriov.c | 1241 /* SR-IOV capability was enabled but there are no VFs*/ bnx2x_iov_init_one() 2402 BNX2X_ERR("failed to configure SR-IOV since vfdb was not allocated. Check dmesg for errors in probe stage\n"); bnx2x_sriov_configure() 2578 BNX2X_ERR("vfqs struct is null. Was this invoked before dynamically enabling SR-IOV? vfidx was %d\n", bnx2x_vf_op_prep()
|
/linux-4.4.14/sound/arm/ |
H A D | aaci.c | 378 * 4 -> FL(3), FR(4), SL(7), SR(8) 379 * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required) 380 * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
|
/linux-4.4.14/include/linux/i2c/ |
H A D | twl.h | 319 /*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */ 832 /* EXTERNAL dc-to-dc buck convertor controllable via SR */ 837 /* Non SR compliant dc-to-dc buck convertors */
|
/linux-4.4.14/drivers/usb/gadget/udc/bdc/ |
H A D | bdc_core.c | 278 /* Disable any unwanted SR's on SRR */ bdc_mem_init() 280 /* We don't want Microframe counter wrap SR */ bdc_mem_init()
|
H A D | bdc_udc.c | 341 dev_warn(bdc->dev, "SR:%d not handled\n", sr_type); bdc_udc_interrupt() 384 * Host then driver will receive a USPC SR with VBUS present bdc_udc_start()
|
H A D | bdc_ep.c | 1068 * started SR 1617 /* Helper function to update ep0 upon SR with xsf_succ or xsf_short */ ep0_xsf_complete()
|
/linux-4.4.14/drivers/gpu/drm/i915/ |
H A D | intel_pm.c | 636 /* Display SR */ pineview_update_wm() 642 reg |= FW_WM(wm, SR); pineview_update_wm() 646 /* cursor SR */ pineview_update_wm() 655 /* Display HPLL off SR */ pineview_update_wm() 664 /* cursor HPLL off SR */ pineview_update_wm() 745 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", g4x_check_srwm() 761 DRM_DEBUG_KMS("SR latency is 0, disabling\n"); g4x_check_srwm() 832 FW_WM(wm->sr.plane, SR) | vlv_write_wm_values() 1335 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n", vlv_update_wm() 1392 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", g4x_update_wm() 1398 FW_WM(plane_sr, SR) | g4x_update_wm() 1405 /* HPLL off in SR has some issues on G4x... disable it */ g4x_update_wm() 1469 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", i965_update_wm() 1473 I915_WRITE(DSPFW1, FW_WM(srwm, SR) | i965_update_wm() 1479 /* update cursor SR watermark */ i965_update_wm() 1601 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", i9xx_update_wm() 3939 wm->sr.plane = _FW_WM(tmp, SR); 4063 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", 4105 * - self-refresh (SR) mode 4115 * The SR calculation is: 4127 * to set the non-SR watermarks to 8.
|
/linux-4.4.14/drivers/video/fbdev/ |
H A D | bw2.c | 264 printk(KERN_ERR "bw2: can't handle SR %02x\n", bw2_do_default_mode()
|
H A D | cg3.c | 328 printk(KERN_ERR "cgthree: can't handle SR %02x\n", cg3_do_default_mode()
|
/linux-4.4.14/drivers/media/pci/cobalt/ |
H A D | cobalt-i2c.c | 72 /* SR[7:0] - Status register */
|
/linux-4.4.14/drivers/net/fddi/skfp/ |
H A D | srf.c | 418 DB_SMT("SRF: state SR%d Threshold %d\n", smt_send_srf()
|
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb4/ |
H A D | t4_pci_id_tbl.h | 48 * -- "8" for drivers attaching to SR-IOV Virtual Functions, etc.
|
/linux-4.4.14/arch/alpha/kernel/ |
H A D | sys_noritake.c | 164 * 0 OR of all unmasked ints in SR #2
|
/linux-4.4.14/include/linux/mtd/ |
H A D | spi-nor.h | 87 #define SR_SRWD BIT(7) /* SR write protect */
|
/linux-4.4.14/arch/mips/include/asm/emma/ |
H A D | emma2rh.h | 232 #define SR 0x000000ff macro
|
/linux-4.4.14/arch/sh/kernel/cpu/sh4a/ |
H A D | perf_event.c | 66 * 0x0280 number of elapsed cycles while SR.BL is asserted
|
/linux-4.4.14/arch/m68k/kernel/ |
H A D | ptrace.c | 33 /* determines which bits in the SR the user has access to. */
|
H A D | entry.S | 263 bclr #7,%sp@(PT_OFF_SR) | clear trace bit in SR
|
/linux-4.4.14/arch/m68k/mac/ |
H A D | macints.c | 12 * - slot 2: ADB data ready (SR full)
|
/linux-4.4.14/arch/nios2/kernel/ |
H A D | process.c | 170 pr_emerg("SR: %08lx SP: %08lx\n", dump()
|
/linux-4.4.14/sound/pci/ctxfi/ |
H A D | cthardware.h | 212 #define DAI_INT (1 << 3) /* DAI (SR-tracker or SPDIF-receiver) */
|
/linux-4.4.14/sound/ppc/ |
H A D | daca.c | 55 /* SR: no swap, 1bit delay, 32-48kHz */ daca_init_client()
|
H A D | snd_ps3_reg.h | 624 The SR must have the same setting as the a0_3wmctrl reg.
|
/linux-4.4.14/sound/soc/atmel/ |
H A D | atmel_ssc_dai.c | 163 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR) atmel_ssc_interrupt() 294 ssc_readl(ssc_p->ssc->regs, SR)); atmel_ssc_startup() 791 ssc_readl(ssc_p->ssc->regs, SR)); atmel_ssc_prepare() 834 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR); atmel_ssc_suspend()
|
/linux-4.4.14/drivers/mtd/nand/ |
H A D | atmel_nand.c | 937 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) { atmel_nand_pmecc_read_page() 971 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) { atmel_nand_pmecc_write_page() 1421 ecc_status = ecc_readl(host->ecc, SR); atmel_nand_correct() 1647 u32 nfc_status = nfc_readl(host->nfc->hsmc_regs, SR); nfc_read_status() 1757 while (nfc_readl(host->nfc->hsmc_regs, SR) & NFC_SR_BUSY) { nfc_send_command() 2358 nfc_readl(nfc->hsmc_regs, SR); /* clear the NFC_SR */ atmel_nand_nfc_probe()
|
/linux-4.4.14/drivers/net/can/sja1000/ |
H A D | peak_pcmcia.c | 117 #define PCC_EEP_SR_WEN 0x02 /* EEPROM SR Write Enable bit */ 118 #define PCC_EEP_SR_WIP 0x01 /* EEPROM SR Write In Progress bit */
|
/linux-4.4.14/arch/m68k/fpsp040/ |
H A D | gen_except.S | 383 btstb #7,(%a7) |test T1 in SR 385 btstb #6,(%a7) |test T0 in SR
|
H A D | skeleton.S | 377 btst #0x5,%sp@ | supervisor bit set in saved SR?
|
/linux-4.4.14/sound/soc/fsl/ |
H A D | fsl_sai.c | 522 /* Clear SR bit to finish the reset */ fsl_sai_trigger() 586 /* Clear SR bit to finish the reset */ fsl_sai_dai_probe()
|
/linux-4.4.14/drivers/pwm/ |
H A D | pwm-atmel.c | 27 /* Bit field in SR */
|
/linux-4.4.14/drivers/scsi/fnic/ |
H A D | vnic_devcmd.h | 238 * or SR-IOV virtual vnic
|
/linux-4.4.14/drivers/ide/ |
H A D | ide-cd.c | 1469 { "MATSHITADVD-ROM SR-8187", NULL, IDE_AFLAG_PLAY_AUDIO_OK }, 1470 { "MATSHITADVD-ROM SR-8186", NULL, IDE_AFLAG_PLAY_AUDIO_OK }, 1471 { "MATSHITADVD-ROM SR-8176", NULL, IDE_AFLAG_PLAY_AUDIO_OK }, 1472 { "MATSHITADVD-ROM SR-8174", NULL, IDE_AFLAG_PLAY_AUDIO_OK },
|
/linux-4.4.14/drivers/misc/genwqe/ |
H A D | card_debugfs.c | 330 "Physical" : "Virtual or no SR-IOV", genwqe_info_show()
|
/linux-4.4.14/drivers/clocksource/ |
H A D | tcb_clksrc.c | 182 sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR)); ch2_irq()
|
/linux-4.4.14/arch/parisc/kernel/ |
H A D | head.S | 215 /* PARANOID: clear user scratch/user space SR's */
|
/linux-4.4.14/drivers/mtd/spi-nor/ |
H A D | spi-nor.c | 89 pr_err("error %d reading SR\n", (int) ret); read_sr() 439 * (SR). Does not support these features found in newer SR bitfields:
|
H A D | fsl-quadspi.c | 515 "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n", fsl_qspi_runcmd()
|
/linux-4.4.14/drivers/mmc/host/ |
H A D | atmel-mci.c | 119 * @cmd_status: Snapshot of SR taken upon completion of the current 121 * @data_status: Snapshot of SR taken upon completion of the current 174 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 176 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 397 * not disabling interrupts, so IMR and SR may not be atmci_regs_show() 430 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]); atmci_regs_show()
|
/linux-4.4.14/drivers/vfio/pci/ |
H A D | vfio_pci_config.c | 480 /* Mask in virtual memory enable for SR-IOV devices */ vfio_basic_config_read() 527 * SR-IOV devices will trigger this, but we catch them later vfio_basic_config_write() 580 /* Virtualized for SR-IOV functions, which just have FFFF */ init_pci_cap_basic_perm()
|
/linux-4.4.14/drivers/video/fbdev/sis/ |
H A D | vstruct.h | 134 unsigned char SR[4]; member in struct:SiS_StandTable_S
|
/linux-4.4.14/drivers/input/tablet/ |
H A D | wacom_serial4.c | 138 #define COMMAND_ENABLE_CONTINUOUS_MODE "SR\r"
|
/linux-4.4.14/drivers/net/wireless/iwlwifi/mvm/ |
H A D | rs.c | 1530 "SR %d high. Find rate exceeding EXPECTED_CURRENT %d\n", rs_get_best_rate() 1535 "SR %d not that good. Find rate exceeding ACTUAL_TPT %d\n", rs_get_best_rate() 1884 "Decrease rate because of low SR\n"); rs_get_rate_action() 1943 "SR is above NO DECREASE. Avoid downscale\n"); rs_get_rate_action() 2037 IWL_DEBUG_RATE(mvm, "increase txp because of weak SR\n"); rs_get_tpc_action() 2136 "(TPC: %d): cur_tpt %d SR %d weak %d strong %d weak_tpt %d strong_tpt %d\n", rs_tpc_perform() 2282 "SWITCHING TO NEW TABLE SR: %d " rs_rate_scale_perform() 2294 "GOING BACK TO THE OLD TABLE: SR %d " rs_rate_scale_perform() 2340 "%s: cur_tpt %d SR %d low %d high %d low_tpt %d high_tpt %d\n", rs_rate_scale_perform()
|
/linux-4.4.14/arch/powerpc/kernel/ |
H A D | pci_dn.c | 223 * when re-enabling SR-IOV. remove_dev_pci_data()
|
/linux-4.4.14/arch/mips/include/asm/sn/sn0/ |
H A D | hubpi.h | 62 #define PI_HARDRESET_BIT 0x020068 /* Bit cleared by s/w on SR */
|
/linux-4.4.14/drivers/net/ethernet/intel/ixgb/ |
H A D | ixgb_hw.c | 177 * Identifies the vendor of the optics module on the adapter. The SR adapters 241 /* The SR adapters carry two different types of XPAK optics ixgb_identify_phy()
|
/linux-4.4.14/drivers/net/ethernet/mellanox/mlx4/ |
H A D | main.c | 2950 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", mlx4_enable_sriov() 2969 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); mlx4_enable_sriov() 2973 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", mlx4_enable_sriov() 3699 /* Disabling SR-IOV is not allowed while there are active vf's */ mlx4_remove_one() 3704 pr_warn("Will not disable SR-IOV.\n"); mlx4_remove_one() 3717 mlx4_warn(dev, "Disabling SR-IOV\n"); mlx4_remove_one()
|
/linux-4.4.14/drivers/scsi/lpfc/ |
H A D | lpfc_crtn.h | 464 /* functions to support SR-IOV */
|
/linux-4.4.14/drivers/mtd/chips/ |
H A D | cfi_cmdset_0001.c | 1709 /* ยง4.8 of the 28FxxxJ3A datasheet says "Any time SR.4 and/or SR.5 is set do_write_buffer() 1720 printk(KERN_WARNING "SR.4 or SR.5 bits set in buffer write (status %lx). Clearing.\n", status.x[0]); do_write_buffer()
|
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb3/ |
H A D | ael1002.c | 243 "10GBASE-SR"); t3_ael1006_phy_prep()
|
/linux-4.4.14/drivers/net/ethernet/cisco/enic/ |
H A D | vnic_devcmd.h | 270 * or SR-IOV virtual vnic
|
/linux-4.4.14/drivers/net/ethernet/amd/xgbe/ |
H A D | xgbe-dev.c | 2609 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); xgbe_enable_rx() 2645 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); xgbe_disable_rx() 2705 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); xgbe_powerup_rx() 2720 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); xgbe_powerdown_rx()
|
/linux-4.4.14/arch/s390/mm/ |
H A D | extmem.c | 95 static char *segtype_string[] = { "SW", "EW", "SR", "ER", "SN", "EN", "SC",
|
/linux-4.4.14/arch/blackfin/mach-bf518/include/mach/ |
H A D | defBF512.h | 1199 #define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */ 1200 #define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */ 1201 #define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */ 1202 #define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */
|
/linux-4.4.14/drivers/net/ethernet/intel/igb/ |
H A D | igb_main.c | 1147 /* disable SR-IOV for non MSI-X configurations */ igb_set_interrupt_capability() 2244 * the PCIe SR-IOV capability. igb_probe() 2683 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); igb_disable_sriov() 2730 /* if allocation failed then we do not support SR-IOV */ igb_enable_sriov() 2846 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2880 /* I350 cannot do RSS and SR-IOV at the same time */ igb_init_queue_configuration() 2982 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); igb_sw_init() 3395 /* 82576 supports 2 RSS queues for SR-IOV */ igb_setup_mrqc() 3499 /* Attention!!! For SR-IOV PF driver operations you must enable igb_setup_rctl() 3563 /* If we're in VMDQ or SR-IOV mode, then set global RLPML igb_rlpml_set() 4058 /* In order to support SR-IOV and eventually VMDq it is necessary to set igb_set_rx_mode()
|
/linux-4.4.14/drivers/gpu/drm/gma500/ |
H A D | psb_intel_reg.h | 1128 * defines the Start Row (SR) and the second the End Row (ER). SR and ER
|
/linux-4.4.14/drivers/staging/unisys/visorbus/ |
H A D | visorchipset.c | 2107 * when an SR-IOV device has been shut down. The ID is passed to the script 2124 * when an SR-IOV device has been recovered. The ID is passed to the script
|
/linux-4.4.14/drivers/mtd/devices/ |
H A D | spear_smi.c | 82 #define SR_SRWD 0x80 /* SR write protect */
|