1/*
2 * Register definitions for the Atmel Image Sensor Interface.
3 *
4 * Copyright (C) 2011 Atmel Corporation
5 * Josh Wu, <josh.wu@atmel.com>
6 *
7 * Based on previous work by Lars Haring, <lars.haring@atmel.com>
8 * and Sedji Gaouaou
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#ifndef __ATMEL_ISI_H__
15#define __ATMEL_ISI_H__
16
17#include <linux/types.h>
18
19/* ISI_V2 register offsets */
20#define ISI_CFG1				0x0000
21#define ISI_CFG2				0x0004
22#define ISI_PSIZE				0x0008
23#define ISI_PDECF				0x000c
24#define ISI_Y2R_SET0				0x0010
25#define ISI_Y2R_SET1				0x0014
26#define ISI_R2Y_SET0				0x0018
27#define ISI_R2Y_SET1				0x001C
28#define ISI_R2Y_SET2				0x0020
29#define ISI_CTRL				0x0024
30#define ISI_STATUS				0x0028
31#define ISI_INTEN				0x002C
32#define ISI_INTDIS				0x0030
33#define ISI_INTMASK				0x0034
34#define ISI_DMA_CHER				0x0038
35#define ISI_DMA_CHDR				0x003C
36#define ISI_DMA_CHSR				0x0040
37#define ISI_DMA_P_ADDR				0x0044
38#define ISI_DMA_P_CTRL				0x0048
39#define ISI_DMA_P_DSCR				0x004C
40#define ISI_DMA_C_ADDR				0x0050
41#define ISI_DMA_C_CTRL				0x0054
42#define ISI_DMA_C_DSCR				0x0058
43
44/* Bitfields in CFG1 */
45#define ISI_CFG1_HSYNC_POL_ACTIVE_LOW		(1 << 2)
46#define ISI_CFG1_VSYNC_POL_ACTIVE_LOW		(1 << 3)
47#define ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING	(1 << 4)
48#define ISI_CFG1_EMB_SYNC			(1 << 6)
49#define ISI_CFG1_CRC_SYNC			(1 << 7)
50/* Constants for FRATE(ISI_V2) */
51#define		ISI_CFG1_FRATE_CAPTURE_ALL	(0 << 8)
52#define		ISI_CFG1_FRATE_DIV_2		(1 << 8)
53#define		ISI_CFG1_FRATE_DIV_3		(2 << 8)
54#define		ISI_CFG1_FRATE_DIV_4		(3 << 8)
55#define		ISI_CFG1_FRATE_DIV_5		(4 << 8)
56#define		ISI_CFG1_FRATE_DIV_6		(5 << 8)
57#define		ISI_CFG1_FRATE_DIV_7		(6 << 8)
58#define		ISI_CFG1_FRATE_DIV_8		(7 << 8)
59#define		ISI_CFG1_FRATE_DIV_MASK		(7 << 8)
60#define ISI_CFG1_DISCR				(1 << 11)
61#define ISI_CFG1_FULL_MODE			(1 << 12)
62/* Definition for THMASK(ISI_V2) */
63#define		ISI_CFG1_THMASK_BEATS_4		(0 << 13)
64#define		ISI_CFG1_THMASK_BEATS_8		(1 << 13)
65#define		ISI_CFG1_THMASK_BEATS_16	(2 << 13)
66
67/* Bitfields in CFG2 */
68#define ISI_CFG2_GRAYSCALE			(1 << 13)
69/* Constants for YCC_SWAP(ISI_V2) */
70#define		ISI_CFG2_YCC_SWAP_DEFAULT	(0 << 28)
71#define		ISI_CFG2_YCC_SWAP_MODE_1	(1 << 28)
72#define		ISI_CFG2_YCC_SWAP_MODE_2	(2 << 28)
73#define		ISI_CFG2_YCC_SWAP_MODE_3	(3 << 28)
74#define		ISI_CFG2_YCC_SWAP_MODE_MASK	(3 << 28)
75#define ISI_CFG2_IM_VSIZE_OFFSET		0
76#define ISI_CFG2_IM_HSIZE_OFFSET		16
77#define ISI_CFG2_IM_VSIZE_MASK		(0x7FF << ISI_CFG2_IM_VSIZE_OFFSET)
78#define ISI_CFG2_IM_HSIZE_MASK		(0x7FF << ISI_CFG2_IM_HSIZE_OFFSET)
79
80/* Bitfields in CTRL */
81/* Also using in SR(ISI_V2) */
82#define ISI_CTRL_EN				(1 << 0)
83#define ISI_CTRL_CDC				(1 << 8)
84/* Also using in SR/IER/IDR/IMR(ISI_V2) */
85#define ISI_CTRL_DIS				(1 << 1)
86#define ISI_CTRL_SRST				(1 << 2)
87
88/* Bitfields in SR */
89#define ISI_SR_SIP				(1 << 19)
90/* Also using in SR/IER/IDR/IMR */
91#define ISI_SR_VSYNC				(1 << 10)
92#define ISI_SR_PXFR_DONE			(1 << 16)
93#define ISI_SR_CXFR_DONE			(1 << 17)
94#define ISI_SR_P_OVR				(1 << 24)
95#define ISI_SR_C_OVR				(1 << 25)
96#define ISI_SR_CRC_ERR				(1 << 26)
97#define ISI_SR_FR_OVR				(1 << 27)
98
99/* Bitfields in DMA_C_CTRL & in DMA_P_CTRL */
100#define ISI_DMA_CTRL_FETCH			(1 << 0)
101#define ISI_DMA_CTRL_WB				(1 << 1)
102#define ISI_DMA_CTRL_IEN			(1 << 2)
103#define ISI_DMA_CTRL_DONE			(1 << 3)
104
105/* Bitfields in DMA_CHSR/CHER/CHDR */
106#define ISI_DMA_CHSR_P_CH			(1 << 0)
107#define ISI_DMA_CHSR_C_CH			(1 << 1)
108
109/* Definition for isi_platform_data */
110#define ISI_DATAWIDTH_8				0x01
111#define ISI_DATAWIDTH_10			0x02
112
113struct v4l2_async_subdev;
114
115struct isi_platform_data {
116	u8 has_emb_sync;
117	u8 emb_crc_sync;
118	u8 hsync_act_low;
119	u8 vsync_act_low;
120	u8 pclk_act_falling;
121	u8 full_mode;
122	u32 data_width_flags;
123	/* Using for ISI_CFG1 */
124	u32 frate;
125	/* Using for ISI_MCK */
126	u32 mck_hz;
127	struct v4l2_async_subdev **asd;	/* Flat array, arranged in groups */
128	int *asd_sizes;		/* 0-terminated array of asd group sizes */
129};
130
131#endif /* __ATMEL_ISI_H__ */
132