/linux-4.4.14/arch/arm/mach-omap2/ |
H A D | l3_2xxx.h | 2 * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions 16 /* L3 CONNIDs */
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H A D | l3_3xxx.h | 2 * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions 16 /* L3 Initiator IDs */
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H A D | opp3xxx_data.c | 102 * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is 110 /* L3 OPP2 */ 112 /* L3 OPP3 */ 137 /* L3 OPP1 - OPP50 */ 139 /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
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H A D | opp4xxx_data.c | 76 /* L3 OPP1 - OPP50 */ 78 /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */ 142 /* L3 OPP1 - OPP50 */ 144 /* L3 OPP2 - OPP100 */
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H A D | iomap.h | 34 #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */ 40 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ 57 /* We map both L3 and L4 on OMAP2 */ 103 /* We map both L3 and L4 on OMAP3 */ 159 /* We map both L3 and L4 on OMAP4 */
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H A D | omap_hwmod_2xxx_interconnect_data.c | 11 * XXX handle crossbar/shared link difference for L3? 27 /* L3 -> L4_CORE interface */ 34 /* MPU -> L3 interface */
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H A D | omap_hwmod_2420_data.c | 12 * XXX handle crossbar/shared link difference for L3? 297 /* IVA <- L3 interface */ 305 /* DSP <- L3 interface */ 361 /* dma_system -> L3 */
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H A D | omap_hwmod_2xxx_3xxx_interconnect_data.c | 11 * XXX handle crossbar/shared link difference for L3?
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H A D | omap_hwmod_2430_data.c | 12 * XXX handle crossbar/shared link difference for L3? 441 /* L3 -> L4_CORE interface */ 498 /* IVA2 <- L3 interface */ 562 /* dma_system -> L3 */
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H A D | omap4-common.c | 66 * paths between the MPU to EMIF, and the MPU to L3 interconnects. 100 * Async bridges can be found on paths between MPU to EMIF and MPU to L3 112 * In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
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H A D | omap-pm.h | 26 * initiators -- it represents the device's L3 interconnect 114 * code will also need to add an minimum L3 interconnect speed
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H A D | omap_hwmod_81xx_data.c | 110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */ 162 /* L3 slow -> L4 ls peripheral interface running at 125MHz */ 169 /* L3 med -> L4 fast peripheral interface running at 250MHz */ 197 /* L3 med peripheral interface running at 200MHz */ 224 /* L3 med peripheral interface running at 250MHz */
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H A D | sram242x.S | 100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks 194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks 310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
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H A D | sram243x.S | 100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks 194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks 310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
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H A D | opp2xxx.h | 264 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz 304 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
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H A D | omap_hwmod_3xxx_data.c | 56 /* L3 */ 2161 /* L3 -> L4_CORE interface */ 2168 /* L3 -> L4_PER interface */ 2184 /* MPU -> L3 interface */ 2558 /* IVA2 <- L3 interface */ 3101 /* dma_system -> L3 */ 3414 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 3455 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 4004 * which sometimes leads to unrecoverable L3 error. XXX The omap3xxx_hwmod_init()
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H A D | clkt2xxx_virt_prcm_set.c | 71 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
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H A D | powerdomains44xx_data.c | 264 /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
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H A D | powerdomains54xx_data.c | 222 /* l3init_54xx_pwrdm: L3 initators pheripherals power domain */
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H A D | powerdomains7xx_data.c | 258 /* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
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H A D | omap_hwmod_2xxx_ipblock_data.c | 195 /* L3 */
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H A D | omap_hwmod_44xx_data.c | 967 * The lowest frequency at the moment for L3 bus is 100 MHz, so 1450 * The lowest frequency at the moment for L3 bus is 100 MHz, so
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H A D | omap_hwmod.c | 30 * interconnects such as the L3 and L4 buses; but there are other
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/linux-4.4.14/include/net/netfilter/ipv4/ |
H A D | nf_conntrack_ipv4.h | 5 * - move L3 protocol dependent part from include/linux/netfilter_ipv4/
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/linux-4.4.14/arch/blackfin/kernel/cplb-mpu/ |
H A D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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/linux-4.4.14/arch/blackfin/kernel/cplb-nompu/ |
H A D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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/linux-4.4.14/tools/testing/selftests/powerpc/pmu/ |
H A D | l3_bank_test.c | 15 * Tests that the L3 bank handling is correct. We fixed it in commit e9aaac1.
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/linux-4.4.14/arch/ia64/lib/ |
H A D | clear_page.S | 16 # define L3_LINE_SIZE 64 // Itanium L3 line size 19 # define L3_LINE_SIZE 128 // McKinley L3 line size 50 mov ar.lc = r16 // one L3 line per iteration
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/linux-4.4.14/net/l3mdev/ |
H A D | l3mdev.c | 2 * net/l3mdev/l3mdev.c - L3 master device implementation 16 * l3mdev_master_ifindex - get index of L3 master device 42 * l3mdev_fib_table - get FIB table id associated with an L3
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/linux-4.4.14/sound/soc/codecs/ |
H A D | l3.c | 2 * L3 code 13 * L3 bus algorithm module. 89 MODULE_DESCRIPTION("L3 bit-banging driver");
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H A D | wm8350.c | 548 SOC_DAPM_SINGLE_TLV("L3 Capture Volume", 558 SOC_DAPM_SINGLE_TLV("L3 Capture Volume", 722 {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"}, 728 {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"}, 732 /* L3 Inputs */
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H A D | uda134x.c | 549 dev_err(&pdev->dev, "Missing L3 bitbang function\n"); uda134x_codec_probe()
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H A D | rt5670.c | 1590 SND_SOC_DAPM_INPUT("DMIC L3"), 1939 { "DMIC3", NULL, "DMIC L3" }, 1974 { "DMIC L3", NULL, "DMIC CLK" }, 1975 { "DMIC L3", NULL, "DMIC3 Power" }, 1989 { "Mono DMIC L Mux", "DMIC3", "DMIC L3" },
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H A D | rt5677.c | 2672 SND_SOC_DAPM_INPUT("DMIC L3"), 3211 { "DMIC3", NULL, "DMIC L3" }, 3220 { "DMIC L3", NULL, "DMIC CLK" }, 3227 { "DMIC L3", NULL, "DMIC3 power" }, 3985 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
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/linux-4.4.14/drivers/bus/ |
H A D | omap_l3_noc.c | 2 * OMAP L3 Interconnect error handling driver 43 * 1) Custom errors in L3 : 45 * 2) Standard L3 error: 47 * L3 tries to access target while it is idle 142 "%s:L3 %s Error: MASTER %s TARGET %s (%s)%s%s\n", l3_handle_target() 161 * Interrupt Handler for L3 error detection. 162 * 1) Identify the L3 clockdomain partition to which the error belongs to. 207 "L3 %s error: target %d mod:%d %s\n", l3_interrupt_handler() 229 dev_err(l3->dev, "L3 %s IRQ not handled!!\n", l3_interrupt_handler()
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H A D | omap_l3_noc.h | 2 * OMAP L3 Interconnect error handling driver header 30 /* L3 TARG register offsets */ 58 * struct l3_masters_data - L3 Master information 59 * @id: ID of the L3 Master 68 * struct l3_target_data - L3 Target information 69 * @offset: Offset from base for L3 Target 99 * struct omap_l3 - Description of data relevant for L3 bus.
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H A D | omap_l3_smx.h | 2 * OMAP3XXX L3 Interconnect Driver header 125 /* L3 error log bit fields. Common for IA and TA */ 130 /* L3 agent status bit fields. */
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H A D | omap_l3_smx.c | 2 * OMAP3XXX L3 Interconnect Driver
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/linux-4.4.14/include/linux/ |
H A D | cache.h | 47 * These could be inter-node cacheline sizes/L3 cacheline
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H A D | mISDNif.h | 54 Layer = 04 L3 -> L2 55 Layer = 08 L2 -> L3
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H A D | skbuff.h | 82 * hardware doesn't need to parse L3/L4 headers to implement this. 923 * layer-2 (L2), layer-3 (L3), or layer-4 (L4). 934 * was computed. For instance an L3 hash cannot be set as an L4 hash. 938 * at L4 may be considered an L3 hash. This should only be done if the
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H A D | netdevice.h | 1271 * @IFF_L3MDEV_MASTER: device is an L3 master device 1274 * @IFF_L3MDEV_SLAVE: device is enslaved to an L3 master device
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/linux-4.4.14/arch/powerpc/include/asm/ |
H A D | fsl_pamu_stash.h | 36 u32 cache; /* cache to stash to: L1,L2,L3 */
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H A D | reg.h | 553 #define L3CR_L3E 0x80000000 /* L3 enable */ 554 #define L3CR_L3PE 0x40000000 /* L3 data parity enable */ 555 #define L3CR_L3APE 0x20000000 /* L3 addr parity enable */ 556 #define L3CR_L3SIZ 0x10000000 /* L3 size */ 557 #define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */ 558 #define L3CR_L3RES 0x04000000 /* L3 special reserved bit */ 559 #define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */ 560 #define L3CR_L3IO 0x00400000 /* L3 instruction only */ 561 #define L3CR_L3SPO 0x00040000 /* L3 sample point override */ 562 #define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */ 563 #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */ 564 #define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */ 565 #define L3CR_L3HWF 0x00000800 /* L3 hardware flush */ 566 #define L3CR_L3I 0x00000400 /* L3 global invalidate */ 567 #define L3CR_L3RT 0x00000300 /* L3 SRAM type */ 568 #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */ 569 #define L3CR_L3DO 0x00000040 /* L3 data only mode */ 570 #define L3CR_PMEN 0x00000004 /* L3 private memory enable */ 571 #define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
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H A D | pmac_feature.h | 95 #define PMAC_TYPE_TITANIUM2 0x48 /* Titanium II PowerBook (no L3, M6) */ 96 #define PMAC_TYPE_TITANIUM3 0x49 /* Titanium III PowerBook (with L3 & M7) */ 97 #define PMAC_TYPE_TITANIUM4 0x50 /* Titanium IV PowerBook (with L3 & M9) */
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/linux-4.4.14/include/net/netfilter/ |
H A D | nf_conntrack_l3proto.h | 4 * Header for use in defining a given L3 protocol for connection tracking. 20 /* L3 Protocol Family number. ex) PF_INET */
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H A D | nf_conntrack_l4proto.h | 5 * - generalized L3 protocol dependent part. 20 /* L3 Protocol number. */
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H A D | nf_conntrack_core.h | 7 * - generalize L3 protocol dependent part.
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H A D | nf_conntrack_helper.h | 5 * - generalize L3 protocol dependent part.
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H A D | nf_conntrack_tuple.h | 5 * - generalize L3 protocol dependent part.
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H A D | nf_conntrack.h | 7 * - generalize L3 protocol dependent part.
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/linux-4.4.14/arch/metag/lib/ |
H A D | div64.S | 13 BNE $L3 18 $L3:
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/linux-4.4.14/arch/x86/kernel/ |
H A D | amd_nb.c | 96 * Check for L3 cache presence. amd_cache_northbridges() 102 * Some CPU families support L3 Cache Index Disable. There are some amd_cache_northbridges() 114 /* L3 cache partitioning is supported on family 0x15 */ amd_cache_northbridges() 194 /* if necessary, collect reset state of L3 partitioning and BAN mode */ amd_set_subcaches() 213 /* reset BAN mode if L3 partitioning returned to reset state */ amd_set_subcaches()
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/linux-4.4.14/arch/x86/kernel/cpu/ |
H A D | perf_event_intel_ds.c | 56 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */ 60 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */ 61 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */ 62 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */ 63 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */ 64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */ 65 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/ 66 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */ 67 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */ 68 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */ 69 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */ 77 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | P(SNOOP, HIT); intel_pmu_pebs_data_source_nhm() 78 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | P(SNOOP, HITM); intel_pmu_pebs_data_source_nhm() 79 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | P(SNOOP, HITM); intel_pmu_pebs_data_source_nhm()
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H A D | intel_cacheinfo.c | 297 * L3 cache descriptors 323 * check whether a slot used for disabling an L3 index is occupied. 324 * @l3: L3 cache descriptor 385 * We need to WBINVD on a core on the node containing the L3 amd_l3_disable_index() 397 * disable a L3 cache index by using a disable-slot 399 * @l3: L3 cache descriptor 400 * @cpu: A CPU on the node containing the L3 cache 447 pr_warning("L3 slot %d in use/index already disabled!\n", store_cache_disable() 572 /* only for L3, and not in virtualized environments */ amd_init_l3_cache()
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H A D | perf_event_amd.c | 260 * NB events are events measuring L3 cache, Hypertransport
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/linux-4.4.14/arch/metag/tbx/ |
H A D | tbidspram.S | 111 $L3: 118 BR $L3
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/linux-4.4.14/drivers/isdn/pcbit/ |
H A D | edss1.c | 148 {EV_USR_SETUP_REQ, "CC->L3: Setup Request"}, 149 {EV_USR_SETUP_RESP, "CC->L3: Setup Response"}, 150 {EV_USR_PROCED_REQ, "CC->L3: Proceeding Request"}, 151 {EV_USR_RELEASE_REQ, "CC->L3: Release Request"},
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H A D | drv.c | 282 printk(KERN_DEBUG "L3 protocol unknown\n"); pcbit_command()
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/linux-4.4.14/include/linux/i2c/ |
H A D | adp5588.h | 63 #define CMP1_LVL2_HYS 0x34 /* L3 Light Sensor Reference Level, Output Falling For Sensor 1 */ 64 #define CMP1_LVL3_TRIP 0x35 /* L3 Light Sensor Hysteresis (Active when Output Rising) For Sensor 1 */ 68 #define CMP2_LVL3_TRIP 0x39 /* L3 Light Sensor Reference Level, Output Falling For Sensor 2 */ 69 #define CMP2_LVL3_HYS 0x3A /* L3 Light Sensor Hysteresis (Active when Output Rising) For Sensor 2 */
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H A D | adp8860.h | 97 * L3 comparator current 0..138uA
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H A D | adp8870.h | 94 * L3 comparator current 0..551uA
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/linux-4.4.14/arch/xtensa/lib/ |
H A D | memset.S | 91 bbci.l a4, 2, .L3 95 .L3:
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H A D | usercopy.S | 187 bbci.l a4, 2, .L3 193 .L3:
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H A D | memcopy.S | 177 bbsi.l a4, 2, .L3 181 .L3:
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/linux-4.4.14/include/net/ |
H A D | l3mdev.h | 2 * include/net/l3mdev.h - L3 master device API 55 * enslaved to an L3 master device FIB lookups are based on the
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/linux-4.4.14/arch/powerpc/perf/ |
H A D | power8-pmu.c | 47 /* The data cache was reloaded from local core's L3 due to a demand load */ 49 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ 55 /* Total HW L3 prefetches(Load+store) */ 79 * | | *- L1/L2/L3 cache_sel | 109 * if cache_sel[0] == 0: # L3 bank 144 #define EVENT_CACHE_SEL_SHIFT 20 /* L2/L3 cache select */ 329 * L2/L3 events contain a cache selector field, which is power8_get_constraint()
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/linux-4.4.14/arch/m68k/lib/ |
H A D | divsi3.S | 115 jpl L3 118 L3: movel sp@+, d2 label
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H A D | udivsi3.S | 95 jcc L3 /* then try next algorithm */ 107 L3: movel d1, d2 /* use d2 as divisor backup */ label
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/linux-4.4.14/arch/powerpc/platforms/powermac/ |
H A D | cache.S | 22 * Flush and disable all data caches (dL1, L2, L3). This is used 322 /* Flush the L3 cache using the hardware assist */ 329 mtspr SPRN_L3CR,r0 /* lock the L3 cache */ 340 mtspr SPRN_L3CR,r3 /* disable the L3 cache */
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H A D | smp.c | 666 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ 845 /* Setup L2/L3 */ smp_core99_setup_cpu()
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/linux-4.4.14/arch/mips/include/asm/sn/ |
H A D | intr.h | 57 * L3 = INT_PEND1
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/linux-4.4.14/drivers/cpufreq/ |
H A D | s5pv210-cpufreq.c | 111 L0, L1, L2, L3, L4, enumerator in enum:perf_level 129 {0, L3, 200*1000}, 158 [L3] = { 185 /* L3 : [200/200/100][166/83][133/66][200/200] */ 373 if (index >= L3) s5pv210_target()
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H A D | pmac32-cpufreq.c | 271 /* Save & disable L2 and L3 caches */ pmu_set_cpu_speed() 296 /* Restore L3 cache */ pmu_set_cpu_speed()
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H A D | exynos5440-cpufreq.c | 93 L0, L1, L2, L3, L4, enumerator in enum:cpufreq_level_index
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/linux-4.4.14/arch/alpha/kernel/ |
H A D | setup.c | 1283 show_cache_size (f, "L3 cache", alpha_l3_cacheshape); show_cpuinfo() 1354 int L1I, L1D, L2, L3; determine_cpu_caches() local 1365 L3 = -1; determine_cpu_caches() 1386 L3 = -1; determine_cpu_caches() 1413 L3 = (bc_control & 1 ? CSHAPE (size, width, 1) : -1); determine_cpu_caches() 1417 L3 = external_cache_probe(1024*1024, width); determine_cpu_caches() 1431 L3 = -1; determine_cpu_caches() 1454 L3 = -1; determine_cpu_caches() 1461 L3 = -1; determine_cpu_caches() 1466 L1I = L1D = L2 = L3 = 0; determine_cpu_caches() 1473 alpha_l3_cacheshape = L3; determine_cpu_caches()
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/linux-4.4.14/arch/blackfin/include/uapi/asm/ |
H A D | ptrace.h | 15 * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
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/linux-4.4.14/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/ |
H A D | EventClass.py | 79 # in L1/L2/L3 or IO operations
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/linux-4.4.14/arch/tile/include/hv/ |
H A D | netio_intf.h | 110 /** The L3 checksum has not been calculated. */ 116 /** The L3 checksum is incorrect (or perhaps has not been calculated). */ 282 /** Whether we should balance on L3, if available */ 362 /** To ensure that the L3 header is aligned mod 4, the L2 header should be 392 /** The offset of the L3 header from the start of the packet data. */ 837 /** Retrieve the length of the packet, starting with the L3 (generally, 843 * @return Length of the packet's L3 header and data, in bytes. 853 /** Return a pointer to the packet's L3 (generally, the IP) header. 856 * Note that we guarantee word alignment of the L3 header. 860 * @return A pointer to the packet's L3 header. 1097 /** Determine whether the L3 (IP) checksum was calculated. 1102 * @return Nonzero if the L3 (IP) checksum was calculated. 1111 /** Determine whether the L3 (IP) checksum was calculated and found to be 1127 /** Determine whether the ethertype was recognized and L3 packet data was 1133 * @return Nonzero if the ethertype was recognized and L3 packet data was 1168 * Note that this function does not verify L3 or L4 checksums. 1212 /** Return the length of the packet, starting with the L3 (IP) header. 1217 * @return Length of the packet's L3 header and data, in bytes. 1227 /** Return a pointer to the packet's L3 (generally, the IP) header. 1230 * Note that we guarantee word alignment of the L3 header. 1234 * @return A pointer to the packet's L3 header. 1283 * Note that this function does not verify L3 or L4 checksums. 1426 /** Retrieve the length of the packet, starting with the L3 (generally, the IP) 1431 * @return Length of the packet's L3 header and data, in bytes. 1451 /** Return a pointer to the packet's L3 (generally, the IP) header. 1454 * Note that we guarantee word alignment of the L3 header. 1457 * @return A pointer to the packet's L3 header. 1684 /** Determine whether the L3 (IP) checksum was calculated. 1688 * @return Nonzero if the L3 (IP) checksum was calculated. 1699 /** Determine whether the L3 (IP) checksum was calculated and found to be 1715 /** Determine whether the Ethertype was recognized and L3 packet data was 1720 * @return Nonzero if the Ethertype was recognized and L3 packet data was 1770 * functions like @ref NETIO_PKT_L3_DATA() to get a pointer to the L3 payload. 1790 * functions like @ref NETIO_PKT_L3_DATA() to get a pointer to the L3 payload.
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H A D | hypervisor.h | 2048 #define HV_PTE_INDEX_NC 4 /**< L1$/L2$ incoherent with L3$ */ 2092 * or store misses there, it goes to an L3 cache in a designated tile; 2096 * when the copy in the remote L3$ is changed. Otherwise, such 2100 * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is 2106 * or store misses there, it goes to an L3 cache in one of a set of 2113 * when the copy in the remote L3$ is changed. Otherwise, such 2117 * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is 2240 * to tag pages whose L3 cache is being migrated from one cpu to another. 2268 * (also known as non-inclusive). This means that changes to the L3 2481 * Specifies the remote tile which is providing the L3 cache for this page.
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/linux-4.4.14/arch/hexagon/lib/ |
H A D | memset.S | 177 if (p0.new) jump:nt .L3 189 .L3:
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/linux-4.4.14/drivers/devfreq/exynos/ |
H A D | exynos4_bus.c | 196 /* ACLK_GDL/R L3: 133MHz */ 214 /* DMC L3: 133MHz */ 231 /* DMC L3: 133MHz */ 249 /* ACLK_GDL/R L3: 133MHz */ 266 /* ACLK_GDL/R L3: 133MHz */
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/linux-4.4.14/drivers/edac/ |
H A D | mce_amd.c | 44 static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" }; 114 "Protocol error (link, L3, probe filter)", 118 "L3 data cache ECC error", /* xec = 0x1c */ 119 "L3 cache tag error", 120 "L3 LRU parity bits error",
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H A D | edac_core.h | 115 * cache could be composed of L1, L2 and L3 levels of cache. 117 * L2 and maybe L3 caches.
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H A D | xgene_edac.c | 1002 /* L3 Error device */ 1041 * Version 1 of the L3 controller has broken single bit correctable logic for 1144 /* Enable/disable L3 error top level interrupt */ xgene_edac_l3_hw_init() 1211 dev_err(edac->dev, "no L3 resource address\n"); xgene_edac_l3_add() 1217 "devm_ioremap_resource failed for L3 resource address\n"); xgene_edac_l3_add() 1265 dev_info(edac->dev, "X-Gene EDAC L3 registered\n"); xgene_edac_l3_add()
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H A D | amd64_edac.c | 161 * F10, this is extended to L3 cache scrubbing on CPU models sporting that 730 edac_dbg(1, " x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n", debug_dump_dramcfg_low()
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/linux-4.4.14/drivers/isdn/hisax/ |
H A D | isdnl3.c | 222 HiSax_putstatus(st->l1.hardware, "L3", "no D protocol"); no_l3_proto() 311 printk(KERN_ERR "HiSax internal L3 error CR(%d) not in list\n", p->callref); release_l3_process() 312 l3_debug(p->st, "HiSax internal L3 error CR(%d) not in list", p->callref); release_l3_process()
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H A D | callc.c | 1002 "%d L3->L4 unknown primitiv %#x", dchan_l3l4()
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/linux-4.4.14/drivers/bcma/ |
H A D | driver_pci.c | 219 /* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
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/linux-4.4.14/arch/blackfin/mach-bf561/ |
H A D | secondary.S | 50 L3 = r6; define
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/linux-4.4.14/arch/blackfin/mach-common/ |
H A D | head.S | 59 L3 = r6; define
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/linux-4.4.14/include/uapi/linux/ |
H A D | atmsap.h | 44 #define ATM_L3_NONE 0 /* L3 not specified */
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H A D | perf_event.h | 908 #define PERF_MEM_LVL_L3 0x40 /* L3 */
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H A D | ethtool.h | 1383 /* L3-L4 network traffic flow hash options */
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/linux-4.4.14/arch/parisc/include/asm/ |
H A D | pgalloc.h | 14 * Here (for 64 bit kernels) we implement a Hybrid L2/L3 scheme: we
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/linux-4.4.14/arch/frv/include/asm/ |
H A D | atomic_defs.h | 147 " "#op" %L1,%L3,%L2 \n" \
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/linux-4.4.14/arch/blackfin/kernel/ |
H A D | pseudodbg.c | 16 "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3",
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H A D | trace.c | 977 pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n", show_regs()
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/linux-4.4.14/drivers/net/ |
H A D | veth.c | 26 #define MIN_MTU 68 /* Min L3 MTU */ 27 #define MAX_MTU 65535 /* Max L3 MTU (arbitrary) */
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/linux-4.4.14/drivers/net/ethernet/samsung/sxgbe/ |
H A D | sxgbe_desc.c | 349 /* L3/L4 Pkt type */ sxgbe_rx_wbstatus() 379 pr_err("Invalid L3/L4 Packet type\n"); sxgbe_rx_wbstatus()
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H A D | sxgbe_ethtool.c | 102 /* L3/L4 Pkt type */
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H A D | sxgbe_common.h | 278 /* L3/L4 Pkt type */
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H A D | sxgbe_reg.h | 189 /* L3/L4 function registers */
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/linux-4.4.14/arch/blackfin/mm/ |
H A D | isram-driver.c | 165 /* src is in L2 or L3 - so just dereference*/ isram_memcpy() 183 /* dest in L2 or L3 - so just dereference */ isram_memcpy()
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/linux-4.4.14/drivers/iommu/ |
H A D | fsl_pamu.c | 60 * L3 cache controller node. 513 * @stash_dest_hint: L1, L2 or L3 527 /* Fastpath, exit early if L3/CPC cache is target for stashing */ get_stash_id() 607 /* setup QMAN Private data stashing for the L3 cache */ setup_qbman_paace() 615 /* Set DQRR and Frame stashing for the L3 cache */ setup_qbman_paace()
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/linux-4.4.14/drivers/net/wireless/ath/wil6210/ |
H A D | txrx.h | 380 * bit 4 : L3:1 IPv4 checksum 388 * bit 4 : L3I:1 L3 identified and checksum calculated
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/linux-4.4.14/arch/tile/include/gxio/ |
H A D | trio.h | 262 /* Do not fill L3 when writing, and invalidate lines upon egress. */ 265 /* L3 cache fills should only populate IO cache ways. */
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H A D | mpipe.h | 204 /* Do not fill L3 when writing, and invalidate lines upon egress. */ 207 /* L3 cache fills should only populate IO cache ways. */ 895 * The L3 analysis handles IPv4 and IPv6, dropping packets with bad 904 * The L3 analysis handles other packets too, hashing the dMAC
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/linux-4.4.14/arch/powerpc/kernel/ |
H A D | l2cr_6xx.S | 287 * Here is a similar routine for dealing with the L3 cache 337 /* Set up the L3CR configuration bits (and switch L3 off) */
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H A D | cpu_setup_6xx.S | 219 /* We check for the presence of an L3 cache setup by
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H A D | cacheinfo.c | 115 * (e.g. L1d -> L1i -> L2 -> L3).
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/linux-4.4.14/arch/arm/mach-sa1100/ |
H A D | assabet.c | 152 GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */ adv7171_write() 165 /* Restore GPIO state for L3 bus */ adv7171_write()
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/linux-4.4.14/arch/arm/include/asm/hardware/ |
H A D | sa1111.h | 148 * L3_CAR L3 Control Bus Address Register 149 * L3_CDR L3 Control Bus Data Register
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/linux-4.4.14/drivers/uio/ |
H A D | uio_pruss.c | 4 * This driver exports PRUSS host event out interrupts and PRUSS, L3 RAM,
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/linux-4.4.14/drivers/pinctrl/mediatek/ |
H A D | pinctrl-mtk-mt6397.h | 69 "L3", "mt6397",
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H A D | pinctrl-mtk-mt8127.h | 1008 "L3", "mt8127",
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H A D | pinctrl-mtk-mt8135.h | 1788 "L3", "mt8135",
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/linux-4.4.14/arch/tile/lib/ |
H A D | cacheflush.c | 152 * data we just loaded into our own cache and the old home L3. finv_buffer_remote()
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/linux-4.4.14/arch/x86/include/asm/ |
H A D | mce.h | 59 #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
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/linux-4.4.14/include/xen/interface/ |
H A D | elfnote.h | 115 * indicate 'extended-cr3' support allowing L3 page tables to be
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H A D | xen.h | 166 * 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD 173 * been set to RO, make sure to set RO the PUD (L3). Do the same 174 * operation on PGD (L4) pagetable entries that have a PUD (L3) entry. 182 * instead use L3.
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H A D | xen-mca.h | 142 /* L3 cache disable Action */
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/linux-4.4.14/net/netfilter/ |
H A D | xt_HMARK.c | 322 pr_info("xt_HMARK: proto mask must be zero with L3 mode\n"); hmark_tg_check()
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H A D | nf_conntrack_proto.c | 0 /* L3/L4 protocol support for nf_conntrack. */
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H A D | xt_CT.c | 155 pr_info("Timeout policy `%s' can only be used by L3 protocol " xt_ct_set_timeout()
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H A D | nf_nat_core.c | 795 /* Make sure that L3 NAT is there by when we call nf_nat_setup_info to nfnetlink_parse_nat_setup()
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H A D | nf_conntrack_netlink.c | 853 /* Dump entries of a given L3 protocol number. ctnetlink_dump_table()
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/linux-4.4.14/include/linux/mfd/ |
H A D | adp5520.h | 250 * L3 comparator current 0..127uA
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/linux-4.4.14/drivers/video/backlight/ |
H A D | adp8860_bl.c | 56 #define ADP8860_L3_TRP 0x1F /* L3 comparator reference */ 57 #define ADP8860_L3_HYS 0x20 /* L3 hysteresis */
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H A D | adp8870_bl.c | 69 #define ADP8870_L3TRP 0x34 /* L3 comparator reference */ 70 #define ADP8870_L3HYS 0x35 /* L3 hysteresis */
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/linux-4.4.14/arch/blackfin/mach-bf561/include/mach/ |
H A D | anomaly.h | 102 /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ 234 /* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
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/linux-4.4.14/net/openvswitch/ |
H A D | flow.c | 604 * header and the beginning of the L3 header differ. key_extract() 606 * Advance network_header to the beginning of the L3 key_extract()
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H A D | conntrack.c | 502 /* The conntrack module expects to be working at L3. */ ovs_ct_execute()
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/linux-4.4.14/drivers/media/platform/davinci/ |
H A D | vpif.c | 276 * As per the standard in the channel, configure the values of L1, L3,
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/linux-4.4.14/drivers/media/platform/omap3isp/ |
H A D | isp.h | 161 * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
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H A D | ispresizer.c | 489 * max intermediate rate <= L3 clock * input height / output height 490 * max intermediate rate <= L3 clock / 2 538 * The number of cycles per second is controlled by the L3 clock, leading to 540 * cycles per request = L3 frequency / 2 * 256 / data rate
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H A D | ispccdc.c | 948 * should be 90% form L3/2 clock, otherwise just L3/2. omap3isp_ccdc_max_rate()
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H A D | isp.c | 139 * omap3isp_flush - Post pending L3 bus writes by doing a register readback
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/linux-4.4.14/drivers/net/usb/ |
H A D | lg-vl600.c | 208 * for some reason. Peek at the L3 header to check vl600_rx_fixup()
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/linux-4.4.14/drivers/gpu/drm/i915/ |
H A D | intel_mocs.c | 62 /* L3 caching options */
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H A D | i915_gem_context.c | 186 * Try to make the context utilize L3 as well as LLC. i915_gem_alloc_context_obj() 188 * On VLV we don't have L3 controls in the PTEs so we i915_gem_alloc_context_obj() 759 DRM_DEBUG_DRIVER("L3 remapping failed\n"); do_switch()
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H A D | i915_cmd_parser.c | 1219 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. i915_cmd_parser_get_version()
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H A D | i915_gpu_error.c | 1378 case I915_CACHE_L3_LLC: return " L3+LLC"; i915_cache_level_str()
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H A D | i915_drv.h | 822 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 825 the CPU, but L3 is only visible to the GPU. */
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H A D | i915_irq.c | 1176 /* We must turn off DOP level clock gating to access the L3 registers. ivybridge_parity_work() 3387 /* L3 parity interrupt is always unmasked. */ gen5_gt_irq_postinstall()
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H A D | intel_pm.c | 6649 /* L3 caching of data atomics doesn't work -- disable it. */ haswell_init_clock_gating() 6855 * Disabling L3 clock gating- MMIO 940c[25] = 1 valleyview_init_clock_gating()
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H A D | i915_reg.h | 1543 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 8150 #define GEN9_LNCFCMOCS0 0xb020 /* L3 Cache Control base */
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/linux-4.4.14/arch/tile/mm/ |
H A D | homecache.c | 302 /* Upgrade "force any cpu" to "No L3" for immutable. */ pte_set_home()
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/linux-4.4.14/net/ax25/ |
H A D | ax25_in.c | 227 /* Also match on any registered callsign from L3/4 */ ax25_rcv()
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/linux-4.4.14/arch/mips/kernel/ |
H A D | mips-cm.c | 110 [0x6] = "L3",
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/linux-4.4.14/arch/sh/boards/ |
H A D | board-magicpanelr2.c | 151 * L3 TCK; L2 (x); L1 (x); L0 (x); setup_port_multiplexing()
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/linux-4.4.14/drivers/net/ethernet/qlogic/qlcnic/ |
H A D | qlcnic.h | 171 __le16 encap_descr; /* 15:10 offset of outer L3 header, 172 * 9:6 number of 32bit words in outer L3 header, 174 * 4 offload outer L3 checksum, 176 * 2 Inner L3 type, IPv4=0, IPv6=1, 177 * 1 Outer L3 type,IPv4=0, IPv6=1,
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/linux-4.4.14/drivers/net/ethernet/marvell/ |
H A D | mvpp2.c | 389 /* IPv6 max L3 address size */ 591 /* L3 cast enum */ 1986 /* IPv4 L3 multicast or broadcast */ mvpp2_prs_ip4_cast() 2078 /* IPv6 L3 multicast entry */ mvpp2_prs_ip6_cast() 2325 /* Set L3 offset */ mvpp2_prs_etype_init() 2357 /* Set L3 offset */ mvpp2_prs_etype_init() 2394 /* Set L3 offset */ mvpp2_prs_etype_init() 2456 /* Set L3 offset */ mvpp2_prs_etype_init() 2481 /* Set L3 offset even it's unknown L3 */ mvpp2_prs_etype_init() 2602 /* Set L3 offset */ mvpp2_prs_pppoe_init() 2652 /* Set L3 offset */ mvpp2_prs_pppoe_init() 2677 /* Set L3 offset even if it's unknown L3 */ mvpp2_prs_pppoe_init()
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/linux-4.4.14/arch/tile/kernel/ |
H A D | pci-dma.c | 106 * On tilegx, data is delivered to hash-for-home L3; on tilepro, __dma_prep_page()
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/linux-4.4.14/arch/x86/include/asm/xen/ |
H A D | interface.h | 170 * of a L3 or L4 page table.
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/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/ |
H A D | anomaly.h | 30 /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
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/linux-4.4.14/net/ethernet/ |
H A D | eth.c | 133 /* parse any remaining L2/L3 headers, check for L4 */ eth_get_headlen()
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/linux-4.4.14/include/uapi/linux/wimax/ |
H A D | i2400m.h | 328 * L3/L4 control protocol
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/linux-4.4.14/arch/ia64/kernel/ |
H A D | ivt.S | 536 * up the physical address of the L3 PTE and then continue at label 1 below. 541 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE 608 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE 662 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
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/linux-4.4.14/arch/blackfin/mach-bf527/include/mach/ |
H A D | anomaly.h | 90 /* Data Read From L3 Memory by USB DMA May be Corrupted */
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/linux-4.4.14/arch/arm/mm/ |
H A D | cache-uniphier.c | 532 * error on L3 or outer because they are optional. uniphier_cache_init()
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/linux-4.4.14/crypto/ |
H A D | jitterentropy.c | 246 * L3 and real memory accesses have even a wider range of wait states. However, 247 * to reliably access either L3 or memory, the ec->mem memory must be quite
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/linux-4.4.14/drivers/video/fbdev/omap2/dss/ |
H A D | hdmi5_core.c | 53 const unsigned long long iclk = 266000000; /* DSS L3 ICLK */ hdmi_core_ddc_init()
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/linux-4.4.14/drivers/isdn/act2000/ |
H A D | module.c | 407 printk(KERN_WARNING "L3 protocol unknown\n"); act2000_command()
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/linux-4.4.14/drivers/isdn/gigaset/ |
H A D | i4l.c | 392 case ISDN_CMD_SETL3: /* Set L3 to given protocol */ command_from_LL()
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/linux-4.4.14/drivers/net/ipvlan/ |
H A D | ipvlan_main.c | 800 MODULE_DESCRIPTION("Driver for L3 (IPv6/IPv4) based VLANs");
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/linux-4.4.14/arch/parisc/mm/ |
H A D | init.c | 40 /* NOTE: This layout exactly conforms to the hybrid L2/L3 page table layout
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/linux-4.4.14/arch/arm/mach-ixp4xx/ |
H A D | ixp4xx_npe.c | 226 /* set CCTXT at ECS DEBUG L3 to specify in which context to execute npe_debug_instr()
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/linux-4.4.14/net/ipv4/ |
H A D | ip_fragment.c | 81 int vif; /* L3 master device index */
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H A D | fib_frontend.c | 1206 * an L3 master device (e.g., VRF)
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/linux-4.4.14/drivers/media/dvb-core/ |
H A D | dvb_net.c | 831 skb_reserve(skb, 2); /* longword align L3 header */ 834 /* copy L3 payload */
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/linux-4.4.14/drivers/net/ethernet/neterion/vxge/ |
H A D | vxge-traffic.h | 433 * fields, etc. L3/L4 checksums are not offloaded, but the packet 876 * fields, etc. L3/L4 checksums are not offloaded, but the packet 1817 * @l3_cksum: in L3 checksum is valid
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H A D | vxge-config.h | 1318 * Bit 9 - L3 Checksum Correct
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/linux-4.4.14/arch/x86/xen/ |
H A D | mmu.c | 2007 /* We can't that easily rip out L3 and L2, as the Xen pagetables are xen_setup_kernel_pagetable() 2008 * set out this way: [L4], [L1], [L2], [L3], [L1], [L1] ... for xen_setup_kernel_pagetable() 2010 * [L4], [L3], [L2], [L1], [L1], order .. So for dom0 we can only xen_setup_kernel_pagetable()
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/linux-4.4.14/drivers/macintosh/ |
H A D | via-pmu.c | 1897 /* Save the state of the L2 and L3 caches */ powerbook_sleep_Core99() 1937 /* Restore L3 cache */ powerbook_sleep_Core99()
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/linux-4.4.14/drivers/net/ethernet/cirrus/ |
H A D | cs89x0.c | 447 skb_reserve(skb, 2); /* longword align L3 header */ dma_rx() 690 skb_reserve(skb, 2); /* longword align L3 header */ net_rx()
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/linux-4.4.14/drivers/staging/media/omap4iss/ |
H A D | iss.c | 55 * omap4iss_flush - Post pending L3 bus writes by doing a register readback
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/linux-4.4.14/drivers/net/ethernet/rocker/ |
H A D | rocker.c | 3002 /* For each active neighbor, we have an L3 unicast group and rocker_port_ipv4_neigh() 3003 * a /32 route to the neighbor, which uses the L3 unicast rocker_port_ipv4_neigh() 3004 * group. The L3 unicast group can also be referred to by rocker_port_ipv4_neigh() 3017 "Error (%d) L3 unicast group index %d\n", rocker_port_ipv4_neigh()
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/linux-4.4.14/drivers/net/ethernet/freescale/ |
H A D | ucc_geth.h | 985 by L3
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/linux-4.4.14/drivers/net/ethernet/amd/xgbe/ |
H A D | xgbe.h | 746 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
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/linux-4.4.14/arch/sparc/kernel/ |
H A D | mdesc.c | 749 * Otherwise fallback to use shared L3 or L2 caches. set_sock_ids()
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/linux-4.4.14/arch/arm/plat-omap/ |
H A D | dma.c | 1252 * As the DSP may be using IRQENABLE_L2 and L3, let's not
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/linux-4.4.14/drivers/infiniband/ulp/ipoib/ |
H A D | ipoib_main.c | 436 /* Couldn't find a unique device with L2 parameters only. Use L3 ipoib_get_net_dev_by_params()
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/linux-4.4.14/drivers/net/ethernet/intel/i40e/ |
H A D | i40e_fcoe.c | 1342 /* set header to L3 of FC */ i40e_fcoe_set_skb_header()
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/linux-4.4.14/drivers/net/ethernet/hisilicon/hns/ |
H A D | hns_enet.c | 251 /* handle L3 protocols */ hns_nic_get_headlen()
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/linux-4.4.14/sound/usb/ |
H A D | pcm.c | 1357 * L1 L2 0x05 R1 R2 0x05 L3 L4 0xfa R3 R4 0xfa fill_playback_urb_dsd_dop()
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/linux-4.4.14/tools/perf/util/ |
H A D | sort.c | 845 "L3",
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/linux-4.4.14/drivers/net/ethernet/neterion/ |
H A D | s2io.c | 2443 * up into by the NIC. The frame is split into L3 header, L4 Header, 2591 * Buffer2 will have L3/L4 header plus fill_rx_buffers() 7467 * L3/L4 aggregatable rx_osm_handler() 8319 /* Update L3 header */ update_L3L4_header() 8471 * check if the pkt is L3/L4 aggregatable. If not s2io_club_tcp_session()
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/linux-4.4.14/drivers/isdn/hardware/eicon/ |
H A D | message.c | 1385 if (noCh) add_p(plci, ESC, "\x02\x18\xfd"); /* D-channel, no B-L3 */ connect_req() 8557 /* L2 and L3 B-Chan protocol. */ 8559 /* Enabled L2 and L3 Configurations: */ 8564 /* L3 == Modem or L3 == Transparent are allowed */ 8642 llc[2] = 4; /* pass L3 always transparent */ add_modem_b23()
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/linux-4.4.14/drivers/isdn/capi/ |
H A D | capidrv.c | 2003 printk(KERN_DEBUG "capidrv-%d: set L3 on chan %ld to %ld\n", capidrv_command()
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/linux-4.4.14/drivers/isdn/i4l/ |
H A D | isdn_common.c | 1867 * given L2- and L3-protocols.
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H A D | isdn_net.c | 750 /* Got incoming Call, setup L2 and L3 protocols, isdn_net_dial()
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/linux-4.4.14/arch/parisc/kernel/ |
H A D | entry.S | 430 * Here we implement a Hybrid L2/L3 scheme: we allocate the
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/linux-4.4.14/kernel/locking/ |
H A D | lockdep.c | 1874 * e.g. the L1 -> L2 -> L3 -> L4 and the L5 -> L1 -> L2 -> L3 check_prev_add()
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/linux-4.4.14/drivers/usb/dwc2/ |
H A D | hcd.c | 3130 /* Initiate lx_state to L3 disconnected state */ dwc2_hcd_init()
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/linux-4.4.14/drivers/hid/ |
H A D | hid-sony.c | 874 [0x02] = BTN_THUMBL, /* L3 */
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/linux-4.4.14/include/rdma/ |
H A D | ib_verbs.h | 1406 /* L3 header*/
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/linux-4.4.14/drivers/net/ethernet/sun/ |
H A D | cassini.h | 1167 #define HP_STATUS0_L3_OFF_MASK 0x0000FE00 /* L3 offset */
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/linux-4.4.14/net/ipv6/ |
H A D | addrconf.c | 3041 /* no link local addresses on L3 master devices */ addrconf_addr_gen()
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