Searched refs:L3 (Results 1 - 199 of 199) sorted by relevance

/linux-4.4.14/arch/arm/mach-omap2/
H A Dl3_2xxx.h2 * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
16 /* L3 CONNIDs */
H A Dl3_3xxx.h2 * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
16 /* L3 Initiator IDs */
H A Dopp3xxx_data.c102 * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
110 /* L3 OPP2 */
112 /* L3 OPP3 */
137 /* L3 OPP1 - OPP50 */
139 /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
H A Dopp4xxx_data.c76 /* L3 OPP1 - OPP50 */
78 /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
142 /* L3 OPP1 - OPP50 */
144 /* L3 OPP2 - OPP100 */
H A Diomap.h34 #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
40 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
57 /* We map both L3 and L4 on OMAP2 */
103 /* We map both L3 and L4 on OMAP3 */
159 /* We map both L3 and L4 on OMAP4 */
H A Domap_hwmod_2xxx_interconnect_data.c11 * XXX handle crossbar/shared link difference for L3?
27 /* L3 -> L4_CORE interface */
34 /* MPU -> L3 interface */
H A Domap_hwmod_2420_data.c12 * XXX handle crossbar/shared link difference for L3?
297 /* IVA <- L3 interface */
305 /* DSP <- L3 interface */
361 /* dma_system -> L3 */
H A Domap_hwmod_2xxx_3xxx_interconnect_data.c11 * XXX handle crossbar/shared link difference for L3?
H A Domap_hwmod_2430_data.c12 * XXX handle crossbar/shared link difference for L3?
441 /* L3 -> L4_CORE interface */
498 /* IVA2 <- L3 interface */
562 /* dma_system -> L3 */
H A Domap4-common.c66 * paths between the MPU to EMIF, and the MPU to L3 interconnects.
100 * Async bridges can be found on paths between MPU to EMIF and MPU to L3
112 * In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
H A Domap-pm.h26 * initiators -- it represents the device's L3 interconnect
114 * code will also need to add an minimum L3 interconnect speed
H A Domap_hwmod_81xx_data.c110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
162 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
169 /* L3 med -> L4 fast peripheral interface running at 250MHz */
197 /* L3 med peripheral interface running at 200MHz */
224 /* L3 med peripheral interface running at 250MHz */
H A Dsram242x.S100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
H A Dsram243x.S100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
H A Dopp2xxx.h264 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
304 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
H A Domap_hwmod_3xxx_data.c56 /* L3 */
2161 /* L3 -> L4_CORE interface */
2168 /* L3 -> L4_PER interface */
2184 /* MPU -> L3 interface */
2558 /* IVA2 <- L3 interface */
3101 /* dma_system -> L3 */
3414 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3455 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
4004 * which sometimes leads to unrecoverable L3 error. XXX The omap3xxx_hwmod_init()
H A Dclkt2xxx_virt_prcm_set.c71 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
H A Dpowerdomains44xx_data.c264 /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
H A Dpowerdomains54xx_data.c222 /* l3init_54xx_pwrdm: L3 initators pheripherals power domain */
H A Dpowerdomains7xx_data.c258 /* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
H A Domap_hwmod_2xxx_ipblock_data.c195 /* L3 */
H A Domap_hwmod_44xx_data.c967 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1450 * The lowest frequency at the moment for L3 bus is 100 MHz, so
H A Domap_hwmod.c30 * interconnects such as the L3 and L4 buses; but there are other
/linux-4.4.14/include/net/netfilter/ipv4/
H A Dnf_conntrack_ipv4.h5 * - move L3 protocol dependent part from include/linux/netfilter_ipv4/
/linux-4.4.14/arch/blackfin/kernel/cplb-mpu/
H A DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
/linux-4.4.14/arch/blackfin/kernel/cplb-nompu/
H A DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
/linux-4.4.14/tools/testing/selftests/powerpc/pmu/
H A Dl3_bank_test.c15 * Tests that the L3 bank handling is correct. We fixed it in commit e9aaac1.
/linux-4.4.14/arch/ia64/lib/
H A Dclear_page.S16 # define L3_LINE_SIZE 64 // Itanium L3 line size
19 # define L3_LINE_SIZE 128 // McKinley L3 line size
50 mov ar.lc = r16 // one L3 line per iteration
/linux-4.4.14/net/l3mdev/
H A Dl3mdev.c2 * net/l3mdev/l3mdev.c - L3 master device implementation
16 * l3mdev_master_ifindex - get index of L3 master device
42 * l3mdev_fib_table - get FIB table id associated with an L3
/linux-4.4.14/sound/soc/codecs/
H A Dl3.c2 * L3 code
13 * L3 bus algorithm module.
89 MODULE_DESCRIPTION("L3 bit-banging driver");
H A Dwm8350.c548 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
558 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
722 {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
728 {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
732 /* L3 Inputs */
H A Duda134x.c549 dev_err(&pdev->dev, "Missing L3 bitbang function\n"); uda134x_codec_probe()
H A Drt5670.c1590 SND_SOC_DAPM_INPUT("DMIC L3"),
1939 { "DMIC3", NULL, "DMIC L3" },
1974 { "DMIC L3", NULL, "DMIC CLK" },
1975 { "DMIC L3", NULL, "DMIC3 Power" },
1989 { "Mono DMIC L Mux", "DMIC3", "DMIC L3" },
H A Drt5677.c2672 SND_SOC_DAPM_INPUT("DMIC L3"),
3211 { "DMIC3", NULL, "DMIC L3" },
3220 { "DMIC L3", NULL, "DMIC CLK" },
3227 { "DMIC L3", NULL, "DMIC3 power" },
3985 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
/linux-4.4.14/drivers/bus/
H A Domap_l3_noc.c2 * OMAP L3 Interconnect error handling driver
43 * 1) Custom errors in L3 :
45 * 2) Standard L3 error:
47 * L3 tries to access target while it is idle
142 "%s:L3 %s Error: MASTER %s TARGET %s (%s)%s%s\n", l3_handle_target()
161 * Interrupt Handler for L3 error detection.
162 * 1) Identify the L3 clockdomain partition to which the error belongs to.
207 "L3 %s error: target %d mod:%d %s\n", l3_interrupt_handler()
229 dev_err(l3->dev, "L3 %s IRQ not handled!!\n", l3_interrupt_handler()
H A Domap_l3_noc.h2 * OMAP L3 Interconnect error handling driver header
30 /* L3 TARG register offsets */
58 * struct l3_masters_data - L3 Master information
59 * @id: ID of the L3 Master
68 * struct l3_target_data - L3 Target information
69 * @offset: Offset from base for L3 Target
99 * struct omap_l3 - Description of data relevant for L3 bus.
H A Domap_l3_smx.h2 * OMAP3XXX L3 Interconnect Driver header
125 /* L3 error log bit fields. Common for IA and TA */
130 /* L3 agent status bit fields. */
H A Domap_l3_smx.c2 * OMAP3XXX L3 Interconnect Driver
/linux-4.4.14/include/linux/
H A Dcache.h47 * These could be inter-node cacheline sizes/L3 cacheline
H A DmISDNif.h54 Layer = 04 L3 -> L2
55 Layer = 08 L2 -> L3
H A Dskbuff.h82 * hardware doesn't need to parse L3/L4 headers to implement this.
923 * layer-2 (L2), layer-3 (L3), or layer-4 (L4).
934 * was computed. For instance an L3 hash cannot be set as an L4 hash.
938 * at L4 may be considered an L3 hash. This should only be done if the
H A Dnetdevice.h1271 * @IFF_L3MDEV_MASTER: device is an L3 master device
1274 * @IFF_L3MDEV_SLAVE: device is enslaved to an L3 master device
/linux-4.4.14/arch/powerpc/include/asm/
H A Dfsl_pamu_stash.h36 u32 cache; /* cache to stash to: L1,L2,L3 */
H A Dreg.h553 #define L3CR_L3E 0x80000000 /* L3 enable */
554 #define L3CR_L3PE 0x40000000 /* L3 data parity enable */
555 #define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
556 #define L3CR_L3SIZ 0x10000000 /* L3 size */
557 #define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
558 #define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
559 #define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
560 #define L3CR_L3IO 0x00400000 /* L3 instruction only */
561 #define L3CR_L3SPO 0x00040000 /* L3 sample point override */
562 #define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
563 #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
564 #define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
565 #define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
566 #define L3CR_L3I 0x00000400 /* L3 global invalidate */
567 #define L3CR_L3RT 0x00000300 /* L3 SRAM type */
568 #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
569 #define L3CR_L3DO 0x00000040 /* L3 data only mode */
570 #define L3CR_PMEN 0x00000004 /* L3 private memory enable */
571 #define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
H A Dpmac_feature.h95 #define PMAC_TYPE_TITANIUM2 0x48 /* Titanium II PowerBook (no L3, M6) */
96 #define PMAC_TYPE_TITANIUM3 0x49 /* Titanium III PowerBook (with L3 & M7) */
97 #define PMAC_TYPE_TITANIUM4 0x50 /* Titanium IV PowerBook (with L3 & M9) */
/linux-4.4.14/include/net/netfilter/
H A Dnf_conntrack_l3proto.h4 * Header for use in defining a given L3 protocol for connection tracking.
20 /* L3 Protocol Family number. ex) PF_INET */
H A Dnf_conntrack_l4proto.h5 * - generalized L3 protocol dependent part.
20 /* L3 Protocol number. */
H A Dnf_conntrack_core.h7 * - generalize L3 protocol dependent part.
H A Dnf_conntrack_helper.h5 * - generalize L3 protocol dependent part.
H A Dnf_conntrack_tuple.h5 * - generalize L3 protocol dependent part.
H A Dnf_conntrack.h7 * - generalize L3 protocol dependent part.
/linux-4.4.14/arch/metag/lib/
H A Ddiv64.S13 BNE $L3
18 $L3:
/linux-4.4.14/arch/x86/kernel/
H A Damd_nb.c96 * Check for L3 cache presence. amd_cache_northbridges()
102 * Some CPU families support L3 Cache Index Disable. There are some amd_cache_northbridges()
114 /* L3 cache partitioning is supported on family 0x15 */ amd_cache_northbridges()
194 /* if necessary, collect reset state of L3 partitioning and BAN mode */ amd_set_subcaches()
213 /* reset BAN mode if L3 partitioning returned to reset state */ amd_set_subcaches()
/linux-4.4.14/arch/x86/kernel/cpu/
H A Dperf_event_intel_ds.c56 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
60 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
61 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
62 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
63 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
65 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
66 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
67 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
68 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
69 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
77 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | P(SNOOP, HIT); intel_pmu_pebs_data_source_nhm()
78 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | P(SNOOP, HITM); intel_pmu_pebs_data_source_nhm()
79 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | P(SNOOP, HITM); intel_pmu_pebs_data_source_nhm()
H A Dintel_cacheinfo.c297 * L3 cache descriptors
323 * check whether a slot used for disabling an L3 index is occupied.
324 * @l3: L3 cache descriptor
385 * We need to WBINVD on a core on the node containing the L3 amd_l3_disable_index()
397 * disable a L3 cache index by using a disable-slot
399 * @l3: L3 cache descriptor
400 * @cpu: A CPU on the node containing the L3 cache
447 pr_warning("L3 slot %d in use/index already disabled!\n", store_cache_disable()
572 /* only for L3, and not in virtualized environments */ amd_init_l3_cache()
H A Dperf_event_amd.c260 * NB events are events measuring L3 cache, Hypertransport
/linux-4.4.14/arch/metag/tbx/
H A Dtbidspram.S111 $L3:
118 BR $L3
/linux-4.4.14/drivers/isdn/pcbit/
H A Dedss1.c148 {EV_USR_SETUP_REQ, "CC->L3: Setup Request"},
149 {EV_USR_SETUP_RESP, "CC->L3: Setup Response"},
150 {EV_USR_PROCED_REQ, "CC->L3: Proceeding Request"},
151 {EV_USR_RELEASE_REQ, "CC->L3: Release Request"},
H A Ddrv.c282 printk(KERN_DEBUG "L3 protocol unknown\n"); pcbit_command()
/linux-4.4.14/include/linux/i2c/
H A Dadp5588.h63 #define CMP1_LVL2_HYS 0x34 /* L3 Light Sensor Reference Level, Output Falling For Sensor 1 */
64 #define CMP1_LVL3_TRIP 0x35 /* L3 Light Sensor Hysteresis (Active when Output Rising) For Sensor 1 */
68 #define CMP2_LVL3_TRIP 0x39 /* L3 Light Sensor Reference Level, Output Falling For Sensor 2 */
69 #define CMP2_LVL3_HYS 0x3A /* L3 Light Sensor Hysteresis (Active when Output Rising) For Sensor 2 */
H A Dadp8860.h97 * L3 comparator current 0..138uA
H A Dadp8870.h94 * L3 comparator current 0..551uA
/linux-4.4.14/arch/xtensa/lib/
H A Dmemset.S91 bbci.l a4, 2, .L3
95 .L3:
H A Dusercopy.S187 bbci.l a4, 2, .L3
193 .L3:
H A Dmemcopy.S177 bbsi.l a4, 2, .L3
181 .L3:
/linux-4.4.14/include/net/
H A Dl3mdev.h2 * include/net/l3mdev.h - L3 master device API
55 * enslaved to an L3 master device FIB lookups are based on the
/linux-4.4.14/arch/powerpc/perf/
H A Dpower8-pmu.c47 /* The data cache was reloaded from local core's L3 due to a demand load */
49 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
55 /* Total HW L3 prefetches(Load+store) */
79 * | | *- L1/L2/L3 cache_sel |
109 * if cache_sel[0] == 0: # L3 bank
144 #define EVENT_CACHE_SEL_SHIFT 20 /* L2/L3 cache select */
329 * L2/L3 events contain a cache selector field, which is power8_get_constraint()
/linux-4.4.14/arch/m68k/lib/
H A Ddivsi3.S115 jpl L3
118 L3: movel sp@+, d2 label
H A Dudivsi3.S95 jcc L3 /* then try next algorithm */
107 L3: movel d1, d2 /* use d2 as divisor backup */ label
/linux-4.4.14/arch/powerpc/platforms/powermac/
H A Dcache.S22 * Flush and disable all data caches (dL1, L2, L3). This is used
322 /* Flush the L3 cache using the hardware assist */
329 mtspr SPRN_L3CR,r0 /* lock the L3 cache */
340 mtspr SPRN_L3CR,r3 /* disable the L3 cache */
H A Dsmp.c666 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
845 /* Setup L2/L3 */ smp_core99_setup_cpu()
/linux-4.4.14/arch/mips/include/asm/sn/
H A Dintr.h57 * L3 = INT_PEND1
/linux-4.4.14/drivers/cpufreq/
H A Ds5pv210-cpufreq.c111 L0, L1, L2, L3, L4, enumerator in enum:perf_level
129 {0, L3, 200*1000},
158 [L3] = {
185 /* L3 : [200/200/100][166/83][133/66][200/200] */
373 if (index >= L3) s5pv210_target()
H A Dpmac32-cpufreq.c271 /* Save & disable L2 and L3 caches */ pmu_set_cpu_speed()
296 /* Restore L3 cache */ pmu_set_cpu_speed()
H A Dexynos5440-cpufreq.c93 L0, L1, L2, L3, L4, enumerator in enum:cpufreq_level_index
/linux-4.4.14/arch/alpha/kernel/
H A Dsetup.c1283 show_cache_size (f, "L3 cache", alpha_l3_cacheshape); show_cpuinfo()
1354 int L1I, L1D, L2, L3; determine_cpu_caches() local
1365 L3 = -1; determine_cpu_caches()
1386 L3 = -1; determine_cpu_caches()
1413 L3 = (bc_control & 1 ? CSHAPE (size, width, 1) : -1); determine_cpu_caches()
1417 L3 = external_cache_probe(1024*1024, width); determine_cpu_caches()
1431 L3 = -1; determine_cpu_caches()
1454 L3 = -1; determine_cpu_caches()
1461 L3 = -1; determine_cpu_caches()
1466 L1I = L1D = L2 = L3 = 0; determine_cpu_caches()
1473 alpha_l3_cacheshape = L3; determine_cpu_caches()
/linux-4.4.14/arch/blackfin/include/uapi/asm/
H A Dptrace.h15 * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
/linux-4.4.14/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/
H A DEventClass.py79 # in L1/L2/L3 or IO operations
/linux-4.4.14/arch/tile/include/hv/
H A Dnetio_intf.h110 /** The L3 checksum has not been calculated. */
116 /** The L3 checksum is incorrect (or perhaps has not been calculated). */
282 /** Whether we should balance on L3, if available */
362 /** To ensure that the L3 header is aligned mod 4, the L2 header should be
392 /** The offset of the L3 header from the start of the packet data. */
837 /** Retrieve the length of the packet, starting with the L3 (generally,
843 * @return Length of the packet's L3 header and data, in bytes.
853 /** Return a pointer to the packet's L3 (generally, the IP) header.
856 * Note that we guarantee word alignment of the L3 header.
860 * @return A pointer to the packet's L3 header.
1097 /** Determine whether the L3 (IP) checksum was calculated.
1102 * @return Nonzero if the L3 (IP) checksum was calculated.
1111 /** Determine whether the L3 (IP) checksum was calculated and found to be
1127 /** Determine whether the ethertype was recognized and L3 packet data was
1133 * @return Nonzero if the ethertype was recognized and L3 packet data was
1168 * Note that this function does not verify L3 or L4 checksums.
1212 /** Return the length of the packet, starting with the L3 (IP) header.
1217 * @return Length of the packet's L3 header and data, in bytes.
1227 /** Return a pointer to the packet's L3 (generally, the IP) header.
1230 * Note that we guarantee word alignment of the L3 header.
1234 * @return A pointer to the packet's L3 header.
1283 * Note that this function does not verify L3 or L4 checksums.
1426 /** Retrieve the length of the packet, starting with the L3 (generally, the IP)
1431 * @return Length of the packet's L3 header and data, in bytes.
1451 /** Return a pointer to the packet's L3 (generally, the IP) header.
1454 * Note that we guarantee word alignment of the L3 header.
1457 * @return A pointer to the packet's L3 header.
1684 /** Determine whether the L3 (IP) checksum was calculated.
1688 * @return Nonzero if the L3 (IP) checksum was calculated.
1699 /** Determine whether the L3 (IP) checksum was calculated and found to be
1715 /** Determine whether the Ethertype was recognized and L3 packet data was
1720 * @return Nonzero if the Ethertype was recognized and L3 packet data was
1770 * functions like @ref NETIO_PKT_L3_DATA() to get a pointer to the L3 payload.
1790 * functions like @ref NETIO_PKT_L3_DATA() to get a pointer to the L3 payload.
H A Dhypervisor.h2048 #define HV_PTE_INDEX_NC 4 /**< L1$/L2$ incoherent with L3$ */
2092 * or store misses there, it goes to an L3 cache in a designated tile;
2096 * when the copy in the remote L3$ is changed. Otherwise, such
2100 * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is
2106 * or store misses there, it goes to an L3 cache in one of a set of
2113 * when the copy in the remote L3$ is changed. Otherwise, such
2117 * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is
2240 * to tag pages whose L3 cache is being migrated from one cpu to another.
2268 * (also known as non-inclusive). This means that changes to the L3
2481 * Specifies the remote tile which is providing the L3 cache for this page.
/linux-4.4.14/arch/hexagon/lib/
H A Dmemset.S177 if (p0.new) jump:nt .L3
189 .L3:
/linux-4.4.14/drivers/devfreq/exynos/
H A Dexynos4_bus.c196 /* ACLK_GDL/R L3: 133MHz */
214 /* DMC L3: 133MHz */
231 /* DMC L3: 133MHz */
249 /* ACLK_GDL/R L3: 133MHz */
266 /* ACLK_GDL/R L3: 133MHz */
/linux-4.4.14/drivers/edac/
H A Dmce_amd.c44 static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
114 "Protocol error (link, L3, probe filter)",
118 "L3 data cache ECC error", /* xec = 0x1c */
119 "L3 cache tag error",
120 "L3 LRU parity bits error",
H A Dedac_core.h115 * cache could be composed of L1, L2 and L3 levels of cache.
117 * L2 and maybe L3 caches.
H A Dxgene_edac.c1002 /* L3 Error device */
1041 * Version 1 of the L3 controller has broken single bit correctable logic for
1144 /* Enable/disable L3 error top level interrupt */ xgene_edac_l3_hw_init()
1211 dev_err(edac->dev, "no L3 resource address\n"); xgene_edac_l3_add()
1217 "devm_ioremap_resource failed for L3 resource address\n"); xgene_edac_l3_add()
1265 dev_info(edac->dev, "X-Gene EDAC L3 registered\n"); xgene_edac_l3_add()
H A Damd64_edac.c161 * F10, this is extended to L3 cache scrubbing on CPU models sporting that
730 edac_dbg(1, " x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n", debug_dump_dramcfg_low()
/linux-4.4.14/drivers/isdn/hisax/
H A Disdnl3.c222 HiSax_putstatus(st->l1.hardware, "L3", "no D protocol"); no_l3_proto()
311 printk(KERN_ERR "HiSax internal L3 error CR(%d) not in list\n", p->callref); release_l3_process()
312 l3_debug(p->st, "HiSax internal L3 error CR(%d) not in list", p->callref); release_l3_process()
H A Dcallc.c1002 "%d L3->L4 unknown primitiv %#x", dchan_l3l4()
/linux-4.4.14/drivers/bcma/
H A Ddriver_pci.c219 /* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
/linux-4.4.14/arch/blackfin/mach-bf561/
H A Dsecondary.S50 L3 = r6; define
/linux-4.4.14/arch/blackfin/mach-common/
H A Dhead.S59 L3 = r6; define
/linux-4.4.14/include/uapi/linux/
H A Datmsap.h44 #define ATM_L3_NONE 0 /* L3 not specified */
H A Dperf_event.h908 #define PERF_MEM_LVL_L3 0x40 /* L3 */
H A Dethtool.h1383 /* L3-L4 network traffic flow hash options */
/linux-4.4.14/arch/parisc/include/asm/
H A Dpgalloc.h14 * Here (for 64 bit kernels) we implement a Hybrid L2/L3 scheme: we
/linux-4.4.14/arch/frv/include/asm/
H A Datomic_defs.h147 " "#op" %L1,%L3,%L2 \n" \
/linux-4.4.14/arch/blackfin/kernel/
H A Dpseudodbg.c16 "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3",
H A Dtrace.c977 pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n", show_regs()
/linux-4.4.14/drivers/net/
H A Dveth.c26 #define MIN_MTU 68 /* Min L3 MTU */
27 #define MAX_MTU 65535 /* Max L3 MTU (arbitrary) */
/linux-4.4.14/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_desc.c349 /* L3/L4 Pkt type */ sxgbe_rx_wbstatus()
379 pr_err("Invalid L3/L4 Packet type\n"); sxgbe_rx_wbstatus()
H A Dsxgbe_ethtool.c102 /* L3/L4 Pkt type */
H A Dsxgbe_common.h278 /* L3/L4 Pkt type */
H A Dsxgbe_reg.h189 /* L3/L4 function registers */
/linux-4.4.14/arch/blackfin/mm/
H A Disram-driver.c165 /* src is in L2 or L3 - so just dereference*/ isram_memcpy()
183 /* dest in L2 or L3 - so just dereference */ isram_memcpy()
/linux-4.4.14/drivers/iommu/
H A Dfsl_pamu.c60 * L3 cache controller node.
513 * @stash_dest_hint: L1, L2 or L3
527 /* Fastpath, exit early if L3/CPC cache is target for stashing */ get_stash_id()
607 /* setup QMAN Private data stashing for the L3 cache */ setup_qbman_paace()
615 /* Set DQRR and Frame stashing for the L3 cache */ setup_qbman_paace()
/linux-4.4.14/drivers/net/wireless/ath/wil6210/
H A Dtxrx.h380 * bit 4 : L3:1 IPv4 checksum
388 * bit 4 : L3I:1 L3 identified and checksum calculated
/linux-4.4.14/arch/tile/include/gxio/
H A Dtrio.h262 /* Do not fill L3 when writing, and invalidate lines upon egress. */
265 /* L3 cache fills should only populate IO cache ways. */
H A Dmpipe.h204 /* Do not fill L3 when writing, and invalidate lines upon egress. */
207 /* L3 cache fills should only populate IO cache ways. */
895 * The L3 analysis handles IPv4 and IPv6, dropping packets with bad
904 * The L3 analysis handles other packets too, hashing the dMAC
/linux-4.4.14/arch/powerpc/kernel/
H A Dl2cr_6xx.S287 * Here is a similar routine for dealing with the L3 cache
337 /* Set up the L3CR configuration bits (and switch L3 off) */
H A Dcpu_setup_6xx.S219 /* We check for the presence of an L3 cache setup by
H A Dcacheinfo.c115 * (e.g. L1d -> L1i -> L2 -> L3).
/linux-4.4.14/arch/arm/mach-sa1100/
H A Dassabet.c152 GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */ adv7171_write()
165 /* Restore GPIO state for L3 bus */ adv7171_write()
/linux-4.4.14/arch/arm/include/asm/hardware/
H A Dsa1111.h148 * L3_CAR L3 Control Bus Address Register
149 * L3_CDR L3 Control Bus Data Register
/linux-4.4.14/drivers/uio/
H A Duio_pruss.c4 * This driver exports PRUSS host event out interrupts and PRUSS, L3 RAM,
/linux-4.4.14/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-mt6397.h69 "L3", "mt6397",
H A Dpinctrl-mtk-mt8127.h1008 "L3", "mt8127",
H A Dpinctrl-mtk-mt8135.h1788 "L3", "mt8135",
/linux-4.4.14/arch/tile/lib/
H A Dcacheflush.c152 * data we just loaded into our own cache and the old home L3. finv_buffer_remote()
/linux-4.4.14/arch/x86/include/asm/
H A Dmce.h59 #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
/linux-4.4.14/include/xen/interface/
H A Delfnote.h115 * indicate 'extended-cr3' support allowing L3 page tables to be
H A Dxen.h166 * 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD
173 * been set to RO, make sure to set RO the PUD (L3). Do the same
174 * operation on PGD (L4) pagetable entries that have a PUD (L3) entry.
182 * instead use L3.
H A Dxen-mca.h142 /* L3 cache disable Action */
/linux-4.4.14/net/netfilter/
H A Dxt_HMARK.c322 pr_info("xt_HMARK: proto mask must be zero with L3 mode\n"); hmark_tg_check()
H A Dnf_conntrack_proto.c0 /* L3/L4 protocol support for nf_conntrack. */
H A Dxt_CT.c155 pr_info("Timeout policy `%s' can only be used by L3 protocol " xt_ct_set_timeout()
H A Dnf_nat_core.c795 /* Make sure that L3 NAT is there by when we call nf_nat_setup_info to nfnetlink_parse_nat_setup()
H A Dnf_conntrack_netlink.c853 /* Dump entries of a given L3 protocol number. ctnetlink_dump_table()
/linux-4.4.14/include/linux/mfd/
H A Dadp5520.h250 * L3 comparator current 0..127uA
/linux-4.4.14/drivers/video/backlight/
H A Dadp8860_bl.c56 #define ADP8860_L3_TRP 0x1F /* L3 comparator reference */
57 #define ADP8860_L3_HYS 0x20 /* L3 hysteresis */
H A Dadp8870_bl.c69 #define ADP8870_L3TRP 0x34 /* L3 comparator reference */
70 #define ADP8870_L3HYS 0x35 /* L3 hysteresis */
/linux-4.4.14/arch/blackfin/mach-bf561/include/mach/
H A Danomaly.h102 /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
234 /* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
/linux-4.4.14/net/openvswitch/
H A Dflow.c604 * header and the beginning of the L3 header differ. key_extract()
606 * Advance network_header to the beginning of the L3 key_extract()
H A Dconntrack.c502 /* The conntrack module expects to be working at L3. */ ovs_ct_execute()
/linux-4.4.14/drivers/media/platform/davinci/
H A Dvpif.c276 * As per the standard in the channel, configure the values of L1, L3,
/linux-4.4.14/drivers/media/platform/omap3isp/
H A Disp.h161 * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
H A Dispresizer.c489 * max intermediate rate <= L3 clock * input height / output height
490 * max intermediate rate <= L3 clock / 2
538 * The number of cycles per second is controlled by the L3 clock, leading to
540 * cycles per request = L3 frequency / 2 * 256 / data rate
H A Dispccdc.c948 * should be 90% form L3/2 clock, otherwise just L3/2. omap3isp_ccdc_max_rate()
H A Disp.c139 * omap3isp_flush - Post pending L3 bus writes by doing a register readback
/linux-4.4.14/drivers/net/usb/
H A Dlg-vl600.c208 * for some reason. Peek at the L3 header to check vl600_rx_fixup()
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_mocs.c62 /* L3 caching options */
H A Di915_gem_context.c186 * Try to make the context utilize L3 as well as LLC. i915_gem_alloc_context_obj()
188 * On VLV we don't have L3 controls in the PTEs so we i915_gem_alloc_context_obj()
759 DRM_DEBUG_DRIVER("L3 remapping failed\n"); do_switch()
H A Di915_cmd_parser.c1219 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. i915_cmd_parser_get_version()
H A Di915_gpu_error.c1378 case I915_CACHE_L3_LLC: return " L3+LLC"; i915_cache_level_str()
H A Di915_drv.h822 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
825 the CPU, but L3 is only visible to the GPU. */
H A Di915_irq.c1176 /* We must turn off DOP level clock gating to access the L3 registers. ivybridge_parity_work()
3387 /* L3 parity interrupt is always unmasked. */ gen5_gt_irq_postinstall()
H A Dintel_pm.c6649 /* L3 caching of data atomics doesn't work -- disable it. */ haswell_init_clock_gating()
6855 * Disabling L3 clock gating- MMIO 940c[25] = 1 valleyview_init_clock_gating()
H A Di915_reg.h1543 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
8150 #define GEN9_LNCFCMOCS0 0xb020 /* L3 Cache Control base */
/linux-4.4.14/arch/tile/mm/
H A Dhomecache.c302 /* Upgrade "force any cpu" to "No L3" for immutable. */ pte_set_home()
/linux-4.4.14/net/ax25/
H A Dax25_in.c227 /* Also match on any registered callsign from L3/4 */ ax25_rcv()
/linux-4.4.14/arch/mips/kernel/
H A Dmips-cm.c110 [0x6] = "L3",
/linux-4.4.14/arch/sh/boards/
H A Dboard-magicpanelr2.c151 * L3 TCK; L2 (x); L1 (x); L0 (x); setup_port_multiplexing()
/linux-4.4.14/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic.h171 __le16 encap_descr; /* 15:10 offset of outer L3 header,
172 * 9:6 number of 32bit words in outer L3 header,
174 * 4 offload outer L3 checksum,
176 * 2 Inner L3 type, IPv4=0, IPv6=1,
177 * 1 Outer L3 type,IPv4=0, IPv6=1,
/linux-4.4.14/drivers/net/ethernet/marvell/
H A Dmvpp2.c389 /* IPv6 max L3 address size */
591 /* L3 cast enum */
1986 /* IPv4 L3 multicast or broadcast */ mvpp2_prs_ip4_cast()
2078 /* IPv6 L3 multicast entry */ mvpp2_prs_ip6_cast()
2325 /* Set L3 offset */ mvpp2_prs_etype_init()
2357 /* Set L3 offset */ mvpp2_prs_etype_init()
2394 /* Set L3 offset */ mvpp2_prs_etype_init()
2456 /* Set L3 offset */ mvpp2_prs_etype_init()
2481 /* Set L3 offset even it's unknown L3 */ mvpp2_prs_etype_init()
2602 /* Set L3 offset */ mvpp2_prs_pppoe_init()
2652 /* Set L3 offset */ mvpp2_prs_pppoe_init()
2677 /* Set L3 offset even if it's unknown L3 */ mvpp2_prs_pppoe_init()
/linux-4.4.14/arch/tile/kernel/
H A Dpci-dma.c106 * On tilegx, data is delivered to hash-for-home L3; on tilepro, __dma_prep_page()
/linux-4.4.14/arch/x86/include/asm/xen/
H A Dinterface.h170 * of a L3 or L4 page table.
/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/
H A Danomaly.h30 /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
/linux-4.4.14/net/ethernet/
H A Deth.c133 /* parse any remaining L2/L3 headers, check for L4 */ eth_get_headlen()
/linux-4.4.14/include/uapi/linux/wimax/
H A Di2400m.h328 * L3/L4 control protocol
/linux-4.4.14/arch/ia64/kernel/
H A Divt.S536 * up the physical address of the L3 PTE and then continue at label 1 below.
541 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
608 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
662 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
/linux-4.4.14/arch/blackfin/mach-bf527/include/mach/
H A Danomaly.h90 /* Data Read From L3 Memory by USB DMA May be Corrupted */
/linux-4.4.14/arch/arm/mm/
H A Dcache-uniphier.c532 * error on L3 or outer because they are optional. uniphier_cache_init()
/linux-4.4.14/crypto/
H A Djitterentropy.c246 * L3 and real memory accesses have even a wider range of wait states. However,
247 * to reliably access either L3 or memory, the ec->mem memory must be quite
/linux-4.4.14/drivers/video/fbdev/omap2/dss/
H A Dhdmi5_core.c53 const unsigned long long iclk = 266000000; /* DSS L3 ICLK */ hdmi_core_ddc_init()
/linux-4.4.14/drivers/isdn/act2000/
H A Dmodule.c407 printk(KERN_WARNING "L3 protocol unknown\n"); act2000_command()
/linux-4.4.14/drivers/isdn/gigaset/
H A Di4l.c392 case ISDN_CMD_SETL3: /* Set L3 to given protocol */ command_from_LL()
/linux-4.4.14/drivers/net/ipvlan/
H A Dipvlan_main.c800 MODULE_DESCRIPTION("Driver for L3 (IPv6/IPv4) based VLANs");
/linux-4.4.14/arch/parisc/mm/
H A Dinit.c40 /* NOTE: This layout exactly conforms to the hybrid L2/L3 page table layout
/linux-4.4.14/arch/arm/mach-ixp4xx/
H A Dixp4xx_npe.c226 /* set CCTXT at ECS DEBUG L3 to specify in which context to execute npe_debug_instr()
/linux-4.4.14/net/ipv4/
H A Dip_fragment.c81 int vif; /* L3 master device index */
H A Dfib_frontend.c1206 * an L3 master device (e.g., VRF)
/linux-4.4.14/drivers/media/dvb-core/
H A Ddvb_net.c831 skb_reserve(skb, 2); /* longword align L3 header */
834 /* copy L3 payload */
/linux-4.4.14/drivers/net/ethernet/neterion/vxge/
H A Dvxge-traffic.h433 * fields, etc. L3/L4 checksums are not offloaded, but the packet
876 * fields, etc. L3/L4 checksums are not offloaded, but the packet
1817 * @l3_cksum: in L3 checksum is valid
H A Dvxge-config.h1318 * Bit 9 - L3 Checksum Correct
/linux-4.4.14/arch/x86/xen/
H A Dmmu.c2007 /* We can't that easily rip out L3 and L2, as the Xen pagetables are xen_setup_kernel_pagetable()
2008 * set out this way: [L4], [L1], [L2], [L3], [L1], [L1] ... for xen_setup_kernel_pagetable()
2010 * [L4], [L3], [L2], [L1], [L1], order .. So for dom0 we can only xen_setup_kernel_pagetable()
/linux-4.4.14/drivers/macintosh/
H A Dvia-pmu.c1897 /* Save the state of the L2 and L3 caches */ powerbook_sleep_Core99()
1937 /* Restore L3 cache */ powerbook_sleep_Core99()
/linux-4.4.14/drivers/net/ethernet/cirrus/
H A Dcs89x0.c447 skb_reserve(skb, 2); /* longword align L3 header */ dma_rx()
690 skb_reserve(skb, 2); /* longword align L3 header */ net_rx()
/linux-4.4.14/drivers/staging/media/omap4iss/
H A Diss.c55 * omap4iss_flush - Post pending L3 bus writes by doing a register readback
/linux-4.4.14/drivers/net/ethernet/rocker/
H A Drocker.c3002 /* For each active neighbor, we have an L3 unicast group and rocker_port_ipv4_neigh()
3003 * a /32 route to the neighbor, which uses the L3 unicast rocker_port_ipv4_neigh()
3004 * group. The L3 unicast group can also be referred to by rocker_port_ipv4_neigh()
3017 "Error (%d) L3 unicast group index %d\n", rocker_port_ipv4_neigh()
/linux-4.4.14/drivers/net/ethernet/freescale/
H A Ducc_geth.h985 by L3
/linux-4.4.14/drivers/net/ethernet/amd/xgbe/
H A Dxgbe.h746 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
/linux-4.4.14/arch/sparc/kernel/
H A Dmdesc.c749 * Otherwise fallback to use shared L3 or L2 caches. set_sock_ids()
/linux-4.4.14/arch/arm/plat-omap/
H A Ddma.c1252 * As the DSP may be using IRQENABLE_L2 and L3, let's not
/linux-4.4.14/drivers/infiniband/ulp/ipoib/
H A Dipoib_main.c436 /* Couldn't find a unique device with L2 parameters only. Use L3 ipoib_get_net_dev_by_params()
/linux-4.4.14/drivers/net/ethernet/intel/i40e/
H A Di40e_fcoe.c1342 /* set header to L3 of FC */ i40e_fcoe_set_skb_header()
/linux-4.4.14/drivers/net/ethernet/hisilicon/hns/
H A Dhns_enet.c251 /* handle L3 protocols */ hns_nic_get_headlen()
/linux-4.4.14/sound/usb/
H A Dpcm.c1357 * L1 L2 0x05 R1 R2 0x05 L3 L4 0xfa R3 R4 0xfa fill_playback_urb_dsd_dop()
/linux-4.4.14/tools/perf/util/
H A Dsort.c845 "L3",
/linux-4.4.14/drivers/net/ethernet/neterion/
H A Ds2io.c2443 * up into by the NIC. The frame is split into L3 header, L4 Header,
2591 * Buffer2 will have L3/L4 header plus fill_rx_buffers()
7467 * L3/L4 aggregatable rx_osm_handler()
8319 /* Update L3 header */ update_L3L4_header()
8471 * check if the pkt is L3/L4 aggregatable. If not s2io_club_tcp_session()
/linux-4.4.14/drivers/isdn/hardware/eicon/
H A Dmessage.c1385 if (noCh) add_p(plci, ESC, "\x02\x18\xfd"); /* D-channel, no B-L3 */ connect_req()
8557 /* L2 and L3 B-Chan protocol. */
8559 /* Enabled L2 and L3 Configurations: */
8564 /* L3 == Modem or L3 == Transparent are allowed */
8642 llc[2] = 4; /* pass L3 always transparent */ add_modem_b23()
/linux-4.4.14/drivers/isdn/capi/
H A Dcapidrv.c2003 printk(KERN_DEBUG "capidrv-%d: set L3 on chan %ld to %ld\n", capidrv_command()
/linux-4.4.14/drivers/isdn/i4l/
H A Disdn_common.c1867 * given L2- and L3-protocols.
H A Disdn_net.c750 /* Got incoming Call, setup L2 and L3 protocols, isdn_net_dial()
/linux-4.4.14/arch/parisc/kernel/
H A Dentry.S430 * Here we implement a Hybrid L2/L3 scheme: we allocate the
/linux-4.4.14/kernel/locking/
H A Dlockdep.c1874 * e.g. the L1 -> L2 -> L3 -> L4 and the L5 -> L1 -> L2 -> L3 check_prev_add()
/linux-4.4.14/drivers/usb/dwc2/
H A Dhcd.c3130 /* Initiate lx_state to L3 disconnected state */ dwc2_hcd_init()
/linux-4.4.14/drivers/hid/
H A Dhid-sony.c874 [0x02] = BTN_THUMBL, /* L3 */
/linux-4.4.14/include/rdma/
H A Dib_verbs.h1406 /* L3 header*/
/linux-4.4.14/drivers/net/ethernet/sun/
H A Dcassini.h1167 #define HP_STATUS0_L3_OFF_MASK 0x0000FE00 /* L3 offset */
/linux-4.4.14/net/ipv6/
H A Daddrconf.c3041 /* no link local addresses on L3 master devices */ addrconf_addr_gen()

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