1/* 2 * DM81xx hwmod data. 3 * 4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ 5 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18#include <linux/platform_data/gpio-omap.h> 19#include <linux/platform_data/hsmmc-omap.h> 20#include <linux/platform_data/spi-omap2-mcspi.h> 21#include <plat/dmtimer.h> 22 23#include "omap_hwmod_common_data.h" 24#include "cm81xx.h" 25#include "ti81xx.h" 26#include "wd_timer.h" 27 28/* 29 * DM816X hardware modules integration data 30 * 31 * Note: This is incomplete and at present, not generated from h/w database. 32 */ 33 34/* 35 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS" 36 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400. 37 */ 38#define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140 39#define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144 40#define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148 41#define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c 42#define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150 43#define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154 44#define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158 45#define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c 46#define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160 47#define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164 48#define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168 49#define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c 50#define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190 51#define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194 52#define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198 53#define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c 54#define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8 55#define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4 56#define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0 57#define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4 58#define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4 59#define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8 60#define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec 61#define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0 62#define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4 63#define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8 64#define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc 65#define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200 66#define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204 67 68/* Registers specific to dm814x */ 69#define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c 70#define DM814X_CM_ALWON_ATL_CLKCTRL 0x170 71#define DM814X_CM_ALWON_MLB_CLKCTRL 0x174 72#define DM814X_CM_ALWON_PATA_CLKCTRL 0x178 73#define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180 74#define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184 75#define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188 76#define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4 77#define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8 78#define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc 79#define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0 80#define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218 81#define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c 82#define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220 83#define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224 84#define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228 85 86/* Registers specific to dm816x */ 87#define DM816X_DM_ALWON_BASE 0x1400 88#define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) 89#define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) 90#define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) 91#define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE) 92#define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) 93#define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) 94#define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE) 95#define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE) 96#define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE) 97#define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE) 98#define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE) 99#define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE) 100#define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE) 101#define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE) 102 103/* 104 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's 105 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500 106 */ 107#define DM816X_CM_DEFAULT_OFFSET 0x500 108#define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET) 109 110/* L3 Interconnect entries clocked at 125, 250 and 500MHz */ 111static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { 112 .name = "alwon_l3_slow", 113 .clkdm_name = "alwon_l3s_clkdm", 114 .class = &l3_hwmod_class, 115 .flags = HWMOD_NO_IDLEST, 116}; 117 118static struct omap_hwmod dm81xx_default_l3_slow_hwmod = { 119 .name = "default_l3_slow", 120 .clkdm_name = "default_l3_slow_clkdm", 121 .class = &l3_hwmod_class, 122 .flags = HWMOD_NO_IDLEST, 123}; 124 125static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = { 126 .name = "l3_med", 127 .clkdm_name = "alwon_l3_med_clkdm", 128 .class = &l3_hwmod_class, 129 .flags = HWMOD_NO_IDLEST, 130}; 131 132static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = { 133 .name = "l3_fast", 134 .clkdm_name = "alwon_l3_fast_clkdm", 135 .class = &l3_hwmod_class, 136 .flags = HWMOD_NO_IDLEST, 137}; 138 139/* 140 * L4 standard peripherals, see TRM table 1-12 for devices using this. 141 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. 142 */ 143static struct omap_hwmod dm81xx_l4_ls_hwmod = { 144 .name = "l4_ls", 145 .clkdm_name = "alwon_l3s_clkdm", 146 .class = &l4_hwmod_class, 147 .flags = HWMOD_NO_IDLEST, 148}; 149 150/* 151 * L4 high-speed peripherals. For devices using this, please see the TRM 152 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM 153 * table 1-73 for devices using 250MHz SYSCLK5 clock. 154 */ 155static struct omap_hwmod dm81xx_l4_hs_hwmod = { 156 .name = "l4_hs", 157 .clkdm_name = "alwon_l3_med_clkdm", 158 .class = &l4_hwmod_class, 159 .flags = HWMOD_NO_IDLEST, 160}; 161 162/* L3 slow -> L4 ls peripheral interface running at 125MHz */ 163static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = { 164 .master = &dm81xx_alwon_l3_slow_hwmod, 165 .slave = &dm81xx_l4_ls_hwmod, 166 .user = OCP_USER_MPU, 167}; 168 169/* L3 med -> L4 fast peripheral interface running at 250MHz */ 170static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = { 171 .master = &dm81xx_alwon_l3_med_hwmod, 172 .slave = &dm81xx_l4_hs_hwmod, 173 .user = OCP_USER_MPU, 174}; 175 176/* MPU */ 177static struct omap_hwmod dm814x_mpu_hwmod = { 178 .name = "mpu", 179 .clkdm_name = "alwon_l3s_clkdm", 180 .class = &mpu_hwmod_class, 181 .flags = HWMOD_INIT_NO_IDLE, 182 .main_clk = "mpu_ck", 183 .prcm = { 184 .omap4 = { 185 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL, 186 .modulemode = MODULEMODE_SWCTRL, 187 }, 188 }, 189}; 190 191static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = { 192 .master = &dm814x_mpu_hwmod, 193 .slave = &dm81xx_alwon_l3_slow_hwmod, 194 .user = OCP_USER_MPU, 195}; 196 197/* L3 med peripheral interface running at 200MHz */ 198static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = { 199 .master = &dm814x_mpu_hwmod, 200 .slave = &dm81xx_alwon_l3_med_hwmod, 201 .user = OCP_USER_MPU, 202}; 203 204static struct omap_hwmod dm816x_mpu_hwmod = { 205 .name = "mpu", 206 .clkdm_name = "alwon_mpu_clkdm", 207 .class = &mpu_hwmod_class, 208 .flags = HWMOD_INIT_NO_IDLE, 209 .main_clk = "mpu_ck", 210 .prcm = { 211 .omap4 = { 212 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL, 213 .modulemode = MODULEMODE_SWCTRL, 214 }, 215 }, 216}; 217 218static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = { 219 .master = &dm816x_mpu_hwmod, 220 .slave = &dm81xx_alwon_l3_slow_hwmod, 221 .user = OCP_USER_MPU, 222}; 223 224/* L3 med peripheral interface running at 250MHz */ 225static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = { 226 .master = &dm816x_mpu_hwmod, 227 .slave = &dm81xx_alwon_l3_med_hwmod, 228 .user = OCP_USER_MPU, 229}; 230 231/* UART common */ 232static struct omap_hwmod_class_sysconfig uart_sysc = { 233 .rev_offs = 0x50, 234 .sysc_offs = 0x54, 235 .syss_offs = 0x58, 236 .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 237 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 238 SYSS_HAS_RESET_STATUS, 239 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 240 MSTANDBY_SMART_WKUP, 241 .sysc_fields = &omap_hwmod_sysc_type1, 242}; 243 244static struct omap_hwmod_class uart_class = { 245 .name = "uart", 246 .sysc = &uart_sysc, 247}; 248 249static struct omap_hwmod dm81xx_uart1_hwmod = { 250 .name = "uart1", 251 .clkdm_name = "alwon_l3s_clkdm", 252 .main_clk = "sysclk10_ck", 253 .prcm = { 254 .omap4 = { 255 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL, 256 .modulemode = MODULEMODE_SWCTRL, 257 }, 258 }, 259 .class = &uart_class, 260 .flags = DEBUG_TI81XXUART1_FLAGS, 261}; 262 263static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = { 264 .master = &dm81xx_l4_ls_hwmod, 265 .slave = &dm81xx_uart1_hwmod, 266 .clk = "sysclk6_ck", 267 .user = OCP_USER_MPU, 268}; 269 270static struct omap_hwmod dm81xx_uart2_hwmod = { 271 .name = "uart2", 272 .clkdm_name = "alwon_l3s_clkdm", 273 .main_clk = "sysclk10_ck", 274 .prcm = { 275 .omap4 = { 276 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL, 277 .modulemode = MODULEMODE_SWCTRL, 278 }, 279 }, 280 .class = &uart_class, 281 .flags = DEBUG_TI81XXUART2_FLAGS, 282}; 283 284static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = { 285 .master = &dm81xx_l4_ls_hwmod, 286 .slave = &dm81xx_uart2_hwmod, 287 .clk = "sysclk6_ck", 288 .user = OCP_USER_MPU, 289}; 290 291static struct omap_hwmod dm81xx_uart3_hwmod = { 292 .name = "uart3", 293 .clkdm_name = "alwon_l3s_clkdm", 294 .main_clk = "sysclk10_ck", 295 .prcm = { 296 .omap4 = { 297 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL, 298 .modulemode = MODULEMODE_SWCTRL, 299 }, 300 }, 301 .class = &uart_class, 302 .flags = DEBUG_TI81XXUART3_FLAGS, 303}; 304 305static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = { 306 .master = &dm81xx_l4_ls_hwmod, 307 .slave = &dm81xx_uart3_hwmod, 308 .clk = "sysclk6_ck", 309 .user = OCP_USER_MPU, 310}; 311 312static struct omap_hwmod_class_sysconfig wd_timer_sysc = { 313 .rev_offs = 0x0, 314 .sysc_offs = 0x10, 315 .syss_offs = 0x14, 316 .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | 317 SYSS_HAS_RESET_STATUS, 318 .sysc_fields = &omap_hwmod_sysc_type1, 319}; 320 321static struct omap_hwmod_class wd_timer_class = { 322 .name = "wd_timer", 323 .sysc = &wd_timer_sysc, 324 .pre_shutdown = &omap2_wd_timer_disable, 325 .reset = &omap2_wd_timer_reset, 326}; 327 328static struct omap_hwmod dm81xx_wd_timer_hwmod = { 329 .name = "wd_timer", 330 .clkdm_name = "alwon_l3s_clkdm", 331 .main_clk = "sysclk18_ck", 332 .flags = HWMOD_NO_IDLEST, 333 .prcm = { 334 .omap4 = { 335 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL, 336 .modulemode = MODULEMODE_SWCTRL, 337 }, 338 }, 339 .class = &wd_timer_class, 340}; 341 342static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = { 343 .master = &dm81xx_l4_ls_hwmod, 344 .slave = &dm81xx_wd_timer_hwmod, 345 .clk = "sysclk6_ck", 346 .user = OCP_USER_MPU, 347}; 348 349/* I2C common */ 350static struct omap_hwmod_class_sysconfig i2c_sysc = { 351 .rev_offs = 0x0, 352 .sysc_offs = 0x10, 353 .syss_offs = 0x90, 354 .sysc_flags = SYSC_HAS_SIDLEMODE | 355 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 356 SYSC_HAS_AUTOIDLE, 357 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 358 .sysc_fields = &omap_hwmod_sysc_type1, 359}; 360 361static struct omap_hwmod_class i2c_class = { 362 .name = "i2c", 363 .sysc = &i2c_sysc, 364}; 365 366static struct omap_hwmod dm81xx_i2c1_hwmod = { 367 .name = "i2c1", 368 .clkdm_name = "alwon_l3s_clkdm", 369 .main_clk = "sysclk10_ck", 370 .prcm = { 371 .omap4 = { 372 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL, 373 .modulemode = MODULEMODE_SWCTRL, 374 }, 375 }, 376 .class = &i2c_class, 377}; 378 379static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = { 380 .master = &dm81xx_l4_ls_hwmod, 381 .slave = &dm81xx_i2c1_hwmod, 382 .clk = "sysclk6_ck", 383 .user = OCP_USER_MPU, 384}; 385 386static struct omap_hwmod dm81xx_i2c2_hwmod = { 387 .name = "i2c2", 388 .clkdm_name = "alwon_l3s_clkdm", 389 .main_clk = "sysclk10_ck", 390 .prcm = { 391 .omap4 = { 392 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL, 393 .modulemode = MODULEMODE_SWCTRL, 394 }, 395 }, 396 .class = &i2c_class, 397}; 398 399static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { 400 .rev_offs = 0x0000, 401 .sysc_offs = 0x0010, 402 .syss_offs = 0x0014, 403 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 404 SYSC_HAS_SOFTRESET | 405 SYSS_HAS_RESET_STATUS, 406 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 407 .sysc_fields = &omap_hwmod_sysc_type1, 408}; 409 410static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = { 411 .master = &dm81xx_l4_ls_hwmod, 412 .slave = &dm81xx_i2c2_hwmod, 413 .clk = "sysclk6_ck", 414 .user = OCP_USER_MPU, 415}; 416 417static struct omap_hwmod_class dm81xx_elm_hwmod_class = { 418 .name = "elm", 419 .sysc = &dm81xx_elm_sysc, 420}; 421 422static struct omap_hwmod dm81xx_elm_hwmod = { 423 .name = "elm", 424 .clkdm_name = "alwon_l3s_clkdm", 425 .class = &dm81xx_elm_hwmod_class, 426 .main_clk = "sysclk6_ck", 427}; 428 429static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { 430 .master = &dm81xx_l4_ls_hwmod, 431 .slave = &dm81xx_elm_hwmod, 432 .user = OCP_USER_MPU, 433}; 434 435static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = { 436 .rev_offs = 0x0000, 437 .sysc_offs = 0x0010, 438 .syss_offs = 0x0114, 439 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 440 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 441 SYSS_HAS_RESET_STATUS, 442 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 443 SIDLE_SMART_WKUP, 444 .sysc_fields = &omap_hwmod_sysc_type1, 445}; 446 447static struct omap_hwmod_class dm81xx_gpio_hwmod_class = { 448 .name = "gpio", 449 .sysc = &dm81xx_gpio_sysc, 450 .rev = 2, 451}; 452 453static struct omap_gpio_dev_attr gpio_dev_attr = { 454 .bank_width = 32, 455 .dbck_flag = true, 456}; 457 458static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 459 { .role = "dbclk", .clk = "sysclk18_ck" }, 460}; 461 462static struct omap_hwmod dm81xx_gpio1_hwmod = { 463 .name = "gpio1", 464 .clkdm_name = "alwon_l3s_clkdm", 465 .class = &dm81xx_gpio_hwmod_class, 466 .main_clk = "sysclk6_ck", 467 .prcm = { 468 .omap4 = { 469 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL, 470 .modulemode = MODULEMODE_SWCTRL, 471 }, 472 }, 473 .opt_clks = gpio1_opt_clks, 474 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 475 .dev_attr = &gpio_dev_attr, 476}; 477 478static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { 479 .master = &dm81xx_l4_ls_hwmod, 480 .slave = &dm81xx_gpio1_hwmod, 481 .user = OCP_USER_MPU, 482}; 483 484static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 485 { .role = "dbclk", .clk = "sysclk18_ck" }, 486}; 487 488static struct omap_hwmod dm81xx_gpio2_hwmod = { 489 .name = "gpio2", 490 .clkdm_name = "alwon_l3s_clkdm", 491 .class = &dm81xx_gpio_hwmod_class, 492 .main_clk = "sysclk6_ck", 493 .prcm = { 494 .omap4 = { 495 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, 496 .modulemode = MODULEMODE_SWCTRL, 497 }, 498 }, 499 .opt_clks = gpio2_opt_clks, 500 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 501 .dev_attr = &gpio_dev_attr, 502}; 503 504static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { 505 .master = &dm81xx_l4_ls_hwmod, 506 .slave = &dm81xx_gpio2_hwmod, 507 .user = OCP_USER_MPU, 508}; 509 510static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = { 511 .rev_offs = 0x0, 512 .sysc_offs = 0x10, 513 .syss_offs = 0x14, 514 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 515 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 516 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 517 .sysc_fields = &omap_hwmod_sysc_type1, 518}; 519 520static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = { 521 .name = "gpmc", 522 .sysc = &dm81xx_gpmc_sysc, 523}; 524 525static struct omap_hwmod dm81xx_gpmc_hwmod = { 526 .name = "gpmc", 527 .clkdm_name = "alwon_l3s_clkdm", 528 .class = &dm81xx_gpmc_hwmod_class, 529 .main_clk = "sysclk6_ck", 530 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 531 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, 532 .prcm = { 533 .omap4 = { 534 .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL, 535 .modulemode = MODULEMODE_SWCTRL, 536 }, 537 }, 538}; 539 540static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { 541 .master = &dm81xx_alwon_l3_slow_hwmod, 542 .slave = &dm81xx_gpmc_hwmod, 543 .user = OCP_USER_MPU, 544}; 545 546static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = { 547 .rev_offs = 0x0, 548 .sysc_offs = 0x10, 549 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 550 SYSC_HAS_SOFTRESET, 551 .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART, 552 .sysc_fields = &omap_hwmod_sysc_type2, 553}; 554 555static struct omap_hwmod_class dm81xx_usbotg_class = { 556 .name = "usbotg", 557 .sysc = &dm81xx_usbhsotg_sysc, 558}; 559 560static struct omap_hwmod dm81xx_usbss_hwmod = { 561 .name = "usb_otg_hs", 562 .clkdm_name = "default_l3_slow_clkdm", 563 .main_clk = "sysclk6_ck", 564 .prcm = { 565 .omap4 = { 566 .clkctrl_offs = DM816X_CM_DEFAULT_USB_CLKCTRL, 567 .modulemode = MODULEMODE_SWCTRL, 568 }, 569 }, 570 .class = &dm81xx_usbotg_class, 571}; 572 573static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = { 574 .master = &dm81xx_default_l3_slow_hwmod, 575 .slave = &dm81xx_usbss_hwmod, 576 .clk = "sysclk6_ck", 577 .user = OCP_USER_MPU, 578}; 579 580static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = { 581 .rev_offs = 0x0000, 582 .sysc_offs = 0x0010, 583 .syss_offs = 0x0014, 584 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, 585 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 586 SIDLE_SMART_WKUP, 587 .sysc_fields = &omap_hwmod_sysc_type2, 588}; 589 590static struct omap_hwmod_class dm816x_timer_hwmod_class = { 591 .name = "timer", 592 .sysc = &dm816x_timer_sysc, 593}; 594 595static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 596 .timer_capability = OMAP_TIMER_ALWON, 597}; 598 599static struct omap_hwmod dm814x_timer1_hwmod = { 600 .name = "timer1", 601 .clkdm_name = "alwon_l3s_clkdm", 602 .main_clk = "timer_sys_ck", 603 .dev_attr = &capability_alwon_dev_attr, 604 .class = &dm816x_timer_hwmod_class, 605 .flags = HWMOD_NO_IDLEST, 606}; 607 608static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { 609 .master = &dm81xx_l4_ls_hwmod, 610 .slave = &dm814x_timer1_hwmod, 611 .clk = "timer_sys_ck", 612 .user = OCP_USER_MPU, 613}; 614 615static struct omap_hwmod dm816x_timer1_hwmod = { 616 .name = "timer1", 617 .clkdm_name = "alwon_l3s_clkdm", 618 .main_clk = "timer1_fck", 619 .prcm = { 620 .omap4 = { 621 .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL, 622 .modulemode = MODULEMODE_SWCTRL, 623 }, 624 }, 625 .dev_attr = &capability_alwon_dev_attr, 626 .class = &dm816x_timer_hwmod_class, 627}; 628 629static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { 630 .master = &dm81xx_l4_ls_hwmod, 631 .slave = &dm816x_timer1_hwmod, 632 .clk = "sysclk6_ck", 633 .user = OCP_USER_MPU, 634}; 635 636static struct omap_hwmod dm814x_timer2_hwmod = { 637 .name = "timer2", 638 .clkdm_name = "alwon_l3s_clkdm", 639 .main_clk = "timer_sys_ck", 640 .dev_attr = &capability_alwon_dev_attr, 641 .class = &dm816x_timer_hwmod_class, 642 .flags = HWMOD_NO_IDLEST, 643}; 644 645static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { 646 .master = &dm81xx_l4_ls_hwmod, 647 .slave = &dm814x_timer2_hwmod, 648 .clk = "timer_sys_ck", 649 .user = OCP_USER_MPU, 650}; 651 652static struct omap_hwmod dm816x_timer2_hwmod = { 653 .name = "timer2", 654 .clkdm_name = "alwon_l3s_clkdm", 655 .main_clk = "timer2_fck", 656 .prcm = { 657 .omap4 = { 658 .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL, 659 .modulemode = MODULEMODE_SWCTRL, 660 }, 661 }, 662 .dev_attr = &capability_alwon_dev_attr, 663 .class = &dm816x_timer_hwmod_class, 664}; 665 666static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { 667 .master = &dm81xx_l4_ls_hwmod, 668 .slave = &dm816x_timer2_hwmod, 669 .clk = "sysclk6_ck", 670 .user = OCP_USER_MPU, 671}; 672 673static struct omap_hwmod dm816x_timer3_hwmod = { 674 .name = "timer3", 675 .clkdm_name = "alwon_l3s_clkdm", 676 .main_clk = "timer3_fck", 677 .prcm = { 678 .omap4 = { 679 .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL, 680 .modulemode = MODULEMODE_SWCTRL, 681 }, 682 }, 683 .dev_attr = &capability_alwon_dev_attr, 684 .class = &dm816x_timer_hwmod_class, 685}; 686 687static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = { 688 .master = &dm81xx_l4_ls_hwmod, 689 .slave = &dm816x_timer3_hwmod, 690 .clk = "sysclk6_ck", 691 .user = OCP_USER_MPU, 692}; 693 694static struct omap_hwmod dm816x_timer4_hwmod = { 695 .name = "timer4", 696 .clkdm_name = "alwon_l3s_clkdm", 697 .main_clk = "timer4_fck", 698 .prcm = { 699 .omap4 = { 700 .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL, 701 .modulemode = MODULEMODE_SWCTRL, 702 }, 703 }, 704 .dev_attr = &capability_alwon_dev_attr, 705 .class = &dm816x_timer_hwmod_class, 706}; 707 708static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = { 709 .master = &dm81xx_l4_ls_hwmod, 710 .slave = &dm816x_timer4_hwmod, 711 .clk = "sysclk6_ck", 712 .user = OCP_USER_MPU, 713}; 714 715static struct omap_hwmod dm816x_timer5_hwmod = { 716 .name = "timer5", 717 .clkdm_name = "alwon_l3s_clkdm", 718 .main_clk = "timer5_fck", 719 .prcm = { 720 .omap4 = { 721 .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL, 722 .modulemode = MODULEMODE_SWCTRL, 723 }, 724 }, 725 .dev_attr = &capability_alwon_dev_attr, 726 .class = &dm816x_timer_hwmod_class, 727}; 728 729static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = { 730 .master = &dm81xx_l4_ls_hwmod, 731 .slave = &dm816x_timer5_hwmod, 732 .clk = "sysclk6_ck", 733 .user = OCP_USER_MPU, 734}; 735 736static struct omap_hwmod dm816x_timer6_hwmod = { 737 .name = "timer6", 738 .clkdm_name = "alwon_l3s_clkdm", 739 .main_clk = "timer6_fck", 740 .prcm = { 741 .omap4 = { 742 .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL, 743 .modulemode = MODULEMODE_SWCTRL, 744 }, 745 }, 746 .dev_attr = &capability_alwon_dev_attr, 747 .class = &dm816x_timer_hwmod_class, 748}; 749 750static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = { 751 .master = &dm81xx_l4_ls_hwmod, 752 .slave = &dm816x_timer6_hwmod, 753 .clk = "sysclk6_ck", 754 .user = OCP_USER_MPU, 755}; 756 757static struct omap_hwmod dm816x_timer7_hwmod = { 758 .name = "timer7", 759 .clkdm_name = "alwon_l3s_clkdm", 760 .main_clk = "timer7_fck", 761 .prcm = { 762 .omap4 = { 763 .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL, 764 .modulemode = MODULEMODE_SWCTRL, 765 }, 766 }, 767 .dev_attr = &capability_alwon_dev_attr, 768 .class = &dm816x_timer_hwmod_class, 769}; 770 771static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { 772 .master = &dm81xx_l4_ls_hwmod, 773 .slave = &dm816x_timer7_hwmod, 774 .clk = "sysclk6_ck", 775 .user = OCP_USER_MPU, 776}; 777 778/* CPSW on dm814x */ 779static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = { 780 .rev_offs = 0x0, 781 .sysc_offs = 0x8, 782 .syss_offs = 0x4, 783 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 784 SYSS_HAS_RESET_STATUS, 785 .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | 786 MSTANDBY_NO, 787 .sysc_fields = &omap_hwmod_sysc_type3, 788}; 789 790static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = { 791 .name = "cpgmac0", 792 .sysc = &dm814x_cpgmac_sysc, 793}; 794 795static struct omap_hwmod dm814x_cpgmac0_hwmod = { 796 .name = "cpgmac0", 797 .class = &dm814x_cpgmac0_hwmod_class, 798 .clkdm_name = "alwon_ethernet_clkdm", 799 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 800 .main_clk = "cpsw_125mhz_gclk", 801 .prcm = { 802 .omap4 = { 803 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, 804 .modulemode = MODULEMODE_SWCTRL, 805 }, 806 }, 807}; 808 809static struct omap_hwmod_class dm814x_mdio_hwmod_class = { 810 .name = "davinci_mdio", 811}; 812 813static struct omap_hwmod dm814x_mdio_hwmod = { 814 .name = "davinci_mdio", 815 .class = &dm814x_mdio_hwmod_class, 816 .clkdm_name = "alwon_ethernet_clkdm", 817 .main_clk = "cpsw_125mhz_gclk", 818}; 819 820static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = { 821 .master = &dm81xx_l4_hs_hwmod, 822 .slave = &dm814x_cpgmac0_hwmod, 823 .clk = "cpsw_125mhz_gclk", 824 .user = OCP_USER_MPU, 825}; 826 827static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = { 828 .master = &dm814x_cpgmac0_hwmod, 829 .slave = &dm814x_mdio_hwmod, 830 .user = OCP_USER_MPU, 831 .flags = HWMOD_NO_IDLEST, 832}; 833 834/* EMAC Ethernet */ 835static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { 836 .rev_offs = 0x0, 837 .sysc_offs = 0x4, 838 .sysc_flags = SYSC_HAS_SOFTRESET, 839 .sysc_fields = &omap_hwmod_sysc_type2, 840}; 841 842static struct omap_hwmod_class dm816x_emac_hwmod_class = { 843 .name = "emac", 844 .sysc = &dm816x_emac_sysc, 845}; 846 847/* 848 * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate 849 * driver probed before EMAC0, we let MDIO do the clock idling. 850 */ 851static struct omap_hwmod dm816x_emac0_hwmod = { 852 .name = "emac0", 853 .clkdm_name = "alwon_ethernet_clkdm", 854 .class = &dm816x_emac_hwmod_class, 855 .flags = HWMOD_NO_IDLEST, 856}; 857 858static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = { 859 .master = &dm81xx_l4_hs_hwmod, 860 .slave = &dm816x_emac0_hwmod, 861 .clk = "sysclk5_ck", 862 .user = OCP_USER_MPU, 863}; 864 865static struct omap_hwmod_class dm81xx_mdio_hwmod_class = { 866 .name = "davinci_mdio", 867 .sysc = &dm816x_emac_sysc, 868}; 869 870static struct omap_hwmod dm81xx_emac0_mdio_hwmod = { 871 .name = "davinci_mdio", 872 .class = &dm81xx_mdio_hwmod_class, 873 .clkdm_name = "alwon_ethernet_clkdm", 874 .main_clk = "sysclk24_ck", 875 .flags = HWMOD_NO_IDLEST, 876 /* 877 * REVISIT: This should be moved to the emac0_hwmod 878 * once we have a better way to handle device slaves. 879 */ 880 .prcm = { 881 .omap4 = { 882 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, 883 .modulemode = MODULEMODE_SWCTRL, 884 }, 885 }, 886}; 887 888static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = { 889 .master = &dm81xx_l4_hs_hwmod, 890 .slave = &dm81xx_emac0_mdio_hwmod, 891 .user = OCP_USER_MPU, 892}; 893 894static struct omap_hwmod dm816x_emac1_hwmod = { 895 .name = "emac1", 896 .clkdm_name = "alwon_ethernet_clkdm", 897 .main_clk = "sysclk24_ck", 898 .flags = HWMOD_NO_IDLEST, 899 .prcm = { 900 .omap4 = { 901 .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL, 902 .modulemode = MODULEMODE_SWCTRL, 903 }, 904 }, 905 .class = &dm816x_emac_hwmod_class, 906}; 907 908static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { 909 .master = &dm81xx_l4_hs_hwmod, 910 .slave = &dm816x_emac1_hwmod, 911 .clk = "sysclk5_ck", 912 .user = OCP_USER_MPU, 913}; 914 915static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = { 916 .rev_offs = 0x0, 917 .sysc_offs = 0x110, 918 .syss_offs = 0x114, 919 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 920 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 921 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 922 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 923 .sysc_fields = &omap_hwmod_sysc_type1, 924}; 925 926static struct omap_hwmod_class dm816x_mmc_class = { 927 .name = "mmc", 928 .sysc = &dm816x_mmc_sysc, 929}; 930 931static struct omap_hwmod_opt_clk dm816x_mmc1_opt_clks[] = { 932 { .role = "dbck", .clk = "sysclk18_ck", }, 933}; 934 935static struct omap_hsmmc_dev_attr mmc1_dev_attr = { 936 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 937}; 938 939static struct omap_hwmod dm816x_mmc1_hwmod = { 940 .name = "mmc1", 941 .clkdm_name = "alwon_l3s_clkdm", 942 .opt_clks = dm816x_mmc1_opt_clks, 943 .opt_clks_cnt = ARRAY_SIZE(dm816x_mmc1_opt_clks), 944 .main_clk = "sysclk10_ck", 945 .prcm = { 946 .omap4 = { 947 .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL, 948 .modulemode = MODULEMODE_SWCTRL, 949 }, 950 }, 951 .dev_attr = &mmc1_dev_attr, 952 .class = &dm816x_mmc_class, 953}; 954 955static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { 956 .master = &dm81xx_l4_ls_hwmod, 957 .slave = &dm816x_mmc1_hwmod, 958 .clk = "sysclk6_ck", 959 .user = OCP_USER_MPU, 960 .flags = OMAP_FIREWALL_L4 961}; 962 963static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = { 964 .rev_offs = 0x0, 965 .sysc_offs = 0x110, 966 .syss_offs = 0x114, 967 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 968 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 969 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 970 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 971 .sysc_fields = &omap_hwmod_sysc_type1, 972}; 973 974static struct omap_hwmod_class dm816x_mcspi_class = { 975 .name = "mcspi", 976 .sysc = &dm816x_mcspi_sysc, 977 .rev = OMAP3_MCSPI_REV, 978}; 979 980static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = { 981 .num_chipselect = 4, 982}; 983 984static struct omap_hwmod dm81xx_mcspi1_hwmod = { 985 .name = "mcspi1", 986 .clkdm_name = "alwon_l3s_clkdm", 987 .main_clk = "sysclk10_ck", 988 .prcm = { 989 .omap4 = { 990 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, 991 .modulemode = MODULEMODE_SWCTRL, 992 }, 993 }, 994 .class = &dm816x_mcspi_class, 995 .dev_attr = &dm816x_mcspi1_dev_attr, 996}; 997 998static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { 999 .master = &dm81xx_l4_ls_hwmod, 1000 .slave = &dm81xx_mcspi1_hwmod, 1001 .clk = "sysclk6_ck", 1002 .user = OCP_USER_MPU, 1003}; 1004 1005static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = { 1006 .rev_offs = 0x000, 1007 .sysc_offs = 0x010, 1008 .syss_offs = 0x014, 1009 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1010 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, 1011 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1012 .sysc_fields = &omap_hwmod_sysc_type1, 1013}; 1014 1015static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = { 1016 .name = "mailbox", 1017 .sysc = &dm81xx_mailbox_sysc, 1018}; 1019 1020static struct omap_hwmod dm81xx_mailbox_hwmod = { 1021 .name = "mailbox", 1022 .clkdm_name = "alwon_l3s_clkdm", 1023 .class = &dm81xx_mailbox_hwmod_class, 1024 .main_clk = "sysclk6_ck", 1025 .prcm = { 1026 .omap4 = { 1027 .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL, 1028 .modulemode = MODULEMODE_SWCTRL, 1029 }, 1030 }, 1031}; 1032 1033static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = { 1034 .master = &dm81xx_l4_ls_hwmod, 1035 .slave = &dm81xx_mailbox_hwmod, 1036 .user = OCP_USER_MPU, 1037}; 1038 1039static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = { 1040 .name = "tpcc", 1041}; 1042 1043static struct omap_hwmod dm81xx_tpcc_hwmod = { 1044 .name = "tpcc", 1045 .class = &dm81xx_tpcc_hwmod_class, 1046 .clkdm_name = "alwon_l3s_clkdm", 1047 .main_clk = "sysclk4_ck", 1048 .prcm = { 1049 .omap4 = { 1050 .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL, 1051 .modulemode = MODULEMODE_SWCTRL, 1052 }, 1053 }, 1054}; 1055 1056static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = { 1057 .master = &dm81xx_alwon_l3_fast_hwmod, 1058 .slave = &dm81xx_tpcc_hwmod, 1059 .clk = "sysclk4_ck", 1060 .user = OCP_USER_MPU, 1061}; 1062 1063static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = { 1064 { 1065 .pa_start = 0x49800000, 1066 .pa_end = 0x49800000 + SZ_8K - 1, 1067 .flags = ADDR_TYPE_RT, 1068 }, 1069 { }, 1070}; 1071 1072static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = { 1073 .name = "tptc0", 1074}; 1075 1076static struct omap_hwmod dm81xx_tptc0_hwmod = { 1077 .name = "tptc0", 1078 .class = &dm81xx_tptc0_hwmod_class, 1079 .clkdm_name = "alwon_l3s_clkdm", 1080 .main_clk = "sysclk4_ck", 1081 .prcm = { 1082 .omap4 = { 1083 .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL, 1084 .modulemode = MODULEMODE_SWCTRL, 1085 }, 1086 }, 1087}; 1088 1089static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = { 1090 .master = &dm81xx_alwon_l3_fast_hwmod, 1091 .slave = &dm81xx_tptc0_hwmod, 1092 .clk = "sysclk4_ck", 1093 .addr = dm81xx_tptc0_addr_space, 1094 .user = OCP_USER_MPU, 1095}; 1096 1097static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = { 1098 .master = &dm81xx_tptc0_hwmod, 1099 .slave = &dm81xx_alwon_l3_fast_hwmod, 1100 .clk = "sysclk4_ck", 1101 .addr = dm81xx_tptc0_addr_space, 1102 .user = OCP_USER_MPU, 1103}; 1104 1105static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = { 1106 { 1107 .pa_start = 0x49900000, 1108 .pa_end = 0x49900000 + SZ_8K - 1, 1109 .flags = ADDR_TYPE_RT, 1110 }, 1111 { }, 1112}; 1113 1114static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = { 1115 .name = "tptc1", 1116}; 1117 1118static struct omap_hwmod dm81xx_tptc1_hwmod = { 1119 .name = "tptc1", 1120 .class = &dm81xx_tptc1_hwmod_class, 1121 .clkdm_name = "alwon_l3s_clkdm", 1122 .main_clk = "sysclk4_ck", 1123 .prcm = { 1124 .omap4 = { 1125 .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL, 1126 .modulemode = MODULEMODE_SWCTRL, 1127 }, 1128 }, 1129}; 1130 1131static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = { 1132 .master = &dm81xx_alwon_l3_fast_hwmod, 1133 .slave = &dm81xx_tptc1_hwmod, 1134 .clk = "sysclk4_ck", 1135 .addr = dm81xx_tptc1_addr_space, 1136 .user = OCP_USER_MPU, 1137}; 1138 1139static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = { 1140 .master = &dm81xx_tptc1_hwmod, 1141 .slave = &dm81xx_alwon_l3_fast_hwmod, 1142 .clk = "sysclk4_ck", 1143 .addr = dm81xx_tptc1_addr_space, 1144 .user = OCP_USER_MPU, 1145}; 1146 1147static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = { 1148 { 1149 .pa_start = 0x49a00000, 1150 .pa_end = 0x49a00000 + SZ_8K - 1, 1151 .flags = ADDR_TYPE_RT, 1152 }, 1153 { }, 1154}; 1155 1156static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = { 1157 .name = "tptc2", 1158}; 1159 1160static struct omap_hwmod dm81xx_tptc2_hwmod = { 1161 .name = "tptc2", 1162 .class = &dm81xx_tptc2_hwmod_class, 1163 .clkdm_name = "alwon_l3s_clkdm", 1164 .main_clk = "sysclk4_ck", 1165 .prcm = { 1166 .omap4 = { 1167 .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL, 1168 .modulemode = MODULEMODE_SWCTRL, 1169 }, 1170 }, 1171}; 1172 1173static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = { 1174 .master = &dm81xx_alwon_l3_fast_hwmod, 1175 .slave = &dm81xx_tptc2_hwmod, 1176 .clk = "sysclk4_ck", 1177 .addr = dm81xx_tptc2_addr_space, 1178 .user = OCP_USER_MPU, 1179}; 1180 1181static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = { 1182 .master = &dm81xx_tptc2_hwmod, 1183 .slave = &dm81xx_alwon_l3_fast_hwmod, 1184 .clk = "sysclk4_ck", 1185 .addr = dm81xx_tptc2_addr_space, 1186 .user = OCP_USER_MPU, 1187}; 1188 1189static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = { 1190 { 1191 .pa_start = 0x49b00000, 1192 .pa_end = 0x49b00000 + SZ_8K - 1, 1193 .flags = ADDR_TYPE_RT, 1194 }, 1195 { }, 1196}; 1197 1198static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = { 1199 .name = "tptc3", 1200}; 1201 1202static struct omap_hwmod dm81xx_tptc3_hwmod = { 1203 .name = "tptc3", 1204 .class = &dm81xx_tptc3_hwmod_class, 1205 .clkdm_name = "alwon_l3s_clkdm", 1206 .main_clk = "sysclk4_ck", 1207 .prcm = { 1208 .omap4 = { 1209 .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL, 1210 .modulemode = MODULEMODE_SWCTRL, 1211 }, 1212 }, 1213}; 1214 1215static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = { 1216 .master = &dm81xx_alwon_l3_fast_hwmod, 1217 .slave = &dm81xx_tptc3_hwmod, 1218 .clk = "sysclk4_ck", 1219 .addr = dm81xx_tptc3_addr_space, 1220 .user = OCP_USER_MPU, 1221}; 1222 1223static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = { 1224 .master = &dm81xx_tptc3_hwmod, 1225 .slave = &dm81xx_alwon_l3_fast_hwmod, 1226 .clk = "sysclk4_ck", 1227 .addr = dm81xx_tptc3_addr_space, 1228 .user = OCP_USER_MPU, 1229}; 1230 1231/* 1232 * REVISIT: Test and enable the following once clocks work: 1233 * dm81xx_l4_ls__gpio1 1234 * dm81xx_l4_ls__gpio2 1235 * dm81xx_l4_ls__mailbox 1236 * dm81xx_alwon_l3_slow__gpmc 1237 * dm81xx_default_l3_slow__usbss 1238 * 1239 * Also note that some devices share a single clkctrl_offs.. 1240 * For example, i2c1 and 3 share one, and i2c2 and 4 share one. 1241 */ 1242static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { 1243 &dm814x_mpu__alwon_l3_slow, 1244 &dm814x_mpu__alwon_l3_med, 1245 &dm81xx_alwon_l3_slow__l4_ls, 1246 &dm81xx_alwon_l3_slow__l4_hs, 1247 &dm81xx_l4_ls__uart1, 1248 &dm81xx_l4_ls__uart2, 1249 &dm81xx_l4_ls__uart3, 1250 &dm81xx_l4_ls__wd_timer1, 1251 &dm81xx_l4_ls__i2c1, 1252 &dm81xx_l4_ls__i2c2, 1253 &dm81xx_l4_ls__elm, 1254 &dm81xx_l4_ls__mcspi1, 1255 &dm81xx_alwon_l3_fast__tpcc, 1256 &dm81xx_alwon_l3_fast__tptc0, 1257 &dm81xx_alwon_l3_fast__tptc1, 1258 &dm81xx_alwon_l3_fast__tptc2, 1259 &dm81xx_alwon_l3_fast__tptc3, 1260 &dm81xx_tptc0__alwon_l3_fast, 1261 &dm81xx_tptc1__alwon_l3_fast, 1262 &dm81xx_tptc2__alwon_l3_fast, 1263 &dm81xx_tptc3__alwon_l3_fast, 1264 &dm814x_l4_ls__timer1, 1265 &dm814x_l4_ls__timer2, 1266 &dm814x_l4_hs__cpgmac0, 1267 &dm814x_cpgmac0__mdio, 1268 NULL, 1269}; 1270 1271int __init dm814x_hwmod_init(void) 1272{ 1273 omap_hwmod_init(); 1274 return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs); 1275} 1276 1277static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { 1278 &dm816x_mpu__alwon_l3_slow, 1279 &dm816x_mpu__alwon_l3_med, 1280 &dm81xx_alwon_l3_slow__l4_ls, 1281 &dm81xx_alwon_l3_slow__l4_hs, 1282 &dm81xx_l4_ls__uart1, 1283 &dm81xx_l4_ls__uart2, 1284 &dm81xx_l4_ls__uart3, 1285 &dm81xx_l4_ls__wd_timer1, 1286 &dm81xx_l4_ls__i2c1, 1287 &dm81xx_l4_ls__i2c2, 1288 &dm81xx_l4_ls__gpio1, 1289 &dm81xx_l4_ls__gpio2, 1290 &dm81xx_l4_ls__elm, 1291 &dm816x_l4_ls__mmc1, 1292 &dm816x_l4_ls__timer1, 1293 &dm816x_l4_ls__timer2, 1294 &dm816x_l4_ls__timer3, 1295 &dm816x_l4_ls__timer4, 1296 &dm816x_l4_ls__timer5, 1297 &dm816x_l4_ls__timer6, 1298 &dm816x_l4_ls__timer7, 1299 &dm81xx_l4_ls__mcspi1, 1300 &dm81xx_l4_ls__mailbox, 1301 &dm81xx_l4_hs__emac0, 1302 &dm81xx_emac0__mdio, 1303 &dm816x_l4_hs__emac1, 1304 &dm81xx_alwon_l3_fast__tpcc, 1305 &dm81xx_alwon_l3_fast__tptc0, 1306 &dm81xx_alwon_l3_fast__tptc1, 1307 &dm81xx_alwon_l3_fast__tptc2, 1308 &dm81xx_alwon_l3_fast__tptc3, 1309 &dm81xx_tptc0__alwon_l3_fast, 1310 &dm81xx_tptc1__alwon_l3_fast, 1311 &dm81xx_tptc2__alwon_l3_fast, 1312 &dm81xx_tptc3__alwon_l3_fast, 1313 &dm81xx_alwon_l3_slow__gpmc, 1314 &dm81xx_default_l3_slow__usbss, 1315 NULL, 1316}; 1317 1318int __init dm816x_hwmod_init(void) 1319{ 1320 omap_hwmod_init(); 1321 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs); 1322} 1323