1/* 2 * Copyright �� 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28#include <linux/cpufreq.h> 29#include "i915_drv.h" 30#include "intel_drv.h" 31#include "../../../platform/x86/intel_ips.h" 32#include <linux/module.h> 33 34/** 35 * RC6 is a special power stage which allows the GPU to enter an very 36 * low-voltage mode when idle, using down to 0V while at this stage. This 37 * stage is entered automatically when the GPU is idle when RC6 support is 38 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 39 * 40 * There are different RC6 modes available in Intel GPU, which differentiate 41 * among each other with the latency required to enter and leave RC6 and 42 * voltage consumed by the GPU in different states. 43 * 44 * The combination of the following flags define which states GPU is allowed 45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 46 * RC6pp is deepest RC6. Their support by hardware varies according to the 47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 48 * which brings the most power savings; deeper states save more power, but 49 * require higher latency to switch to and wake up. 50 */ 51#define INTEL_RC6_ENABLE (1<<0) 52#define INTEL_RC6p_ENABLE (1<<1) 53#define INTEL_RC6pp_ENABLE (1<<2) 54 55static void bxt_init_clock_gating(struct drm_device *dev) 56{ 57 struct drm_i915_private *dev_priv = dev->dev_private; 58 59 /* WaDisableSDEUnitClockGating:bxt */ 60 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 61 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 62 63 /* 64 * FIXME: 65 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. 66 */ 67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 68 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); 69} 70 71static void i915_pineview_get_mem_freq(struct drm_device *dev) 72{ 73 struct drm_i915_private *dev_priv = dev->dev_private; 74 u32 tmp; 75 76 tmp = I915_READ(CLKCFG); 77 78 switch (tmp & CLKCFG_FSB_MASK) { 79 case CLKCFG_FSB_533: 80 dev_priv->fsb_freq = 533; /* 133*4 */ 81 break; 82 case CLKCFG_FSB_800: 83 dev_priv->fsb_freq = 800; /* 200*4 */ 84 break; 85 case CLKCFG_FSB_667: 86 dev_priv->fsb_freq = 667; /* 167*4 */ 87 break; 88 case CLKCFG_FSB_400: 89 dev_priv->fsb_freq = 400; /* 100*4 */ 90 break; 91 } 92 93 switch (tmp & CLKCFG_MEM_MASK) { 94 case CLKCFG_MEM_533: 95 dev_priv->mem_freq = 533; 96 break; 97 case CLKCFG_MEM_667: 98 dev_priv->mem_freq = 667; 99 break; 100 case CLKCFG_MEM_800: 101 dev_priv->mem_freq = 800; 102 break; 103 } 104 105 /* detect pineview DDR3 setting */ 106 tmp = I915_READ(CSHRDDR3CTL); 107 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 108} 109 110static void i915_ironlake_get_mem_freq(struct drm_device *dev) 111{ 112 struct drm_i915_private *dev_priv = dev->dev_private; 113 u16 ddrpll, csipll; 114 115 ddrpll = I915_READ16(DDRMPLL1); 116 csipll = I915_READ16(CSIPLL0); 117 118 switch (ddrpll & 0xff) { 119 case 0xc: 120 dev_priv->mem_freq = 800; 121 break; 122 case 0x10: 123 dev_priv->mem_freq = 1066; 124 break; 125 case 0x14: 126 dev_priv->mem_freq = 1333; 127 break; 128 case 0x18: 129 dev_priv->mem_freq = 1600; 130 break; 131 default: 132 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", 133 ddrpll & 0xff); 134 dev_priv->mem_freq = 0; 135 break; 136 } 137 138 dev_priv->ips.r_t = dev_priv->mem_freq; 139 140 switch (csipll & 0x3ff) { 141 case 0x00c: 142 dev_priv->fsb_freq = 3200; 143 break; 144 case 0x00e: 145 dev_priv->fsb_freq = 3733; 146 break; 147 case 0x010: 148 dev_priv->fsb_freq = 4266; 149 break; 150 case 0x012: 151 dev_priv->fsb_freq = 4800; 152 break; 153 case 0x014: 154 dev_priv->fsb_freq = 5333; 155 break; 156 case 0x016: 157 dev_priv->fsb_freq = 5866; 158 break; 159 case 0x018: 160 dev_priv->fsb_freq = 6400; 161 break; 162 default: 163 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", 164 csipll & 0x3ff); 165 dev_priv->fsb_freq = 0; 166 break; 167 } 168 169 if (dev_priv->fsb_freq == 3200) { 170 dev_priv->ips.c_m = 0; 171 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 172 dev_priv->ips.c_m = 1; 173 } else { 174 dev_priv->ips.c_m = 2; 175 } 176} 177 178static const struct cxsr_latency cxsr_latency_table[] = { 179 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 180 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 181 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 182 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ 183 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ 184 185 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ 186 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ 187 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ 188 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ 189 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ 190 191 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ 192 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ 193 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ 194 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ 195 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ 196 197 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ 198 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ 199 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ 200 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ 201 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ 202 203 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ 204 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ 205 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ 206 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ 207 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ 208 209 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ 210 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ 211 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ 212 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ 213 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 214}; 215 216static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 217 int is_ddr3, 218 int fsb, 219 int mem) 220{ 221 const struct cxsr_latency *latency; 222 int i; 223 224 if (fsb == 0 || mem == 0) 225 return NULL; 226 227 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { 228 latency = &cxsr_latency_table[i]; 229 if (is_desktop == latency->is_desktop && 230 is_ddr3 == latency->is_ddr3 && 231 fsb == latency->fsb_freq && mem == latency->mem_freq) 232 return latency; 233 } 234 235 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 236 237 return NULL; 238} 239 240static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) 241{ 242 u32 val; 243 244 mutex_lock(&dev_priv->rps.hw_lock); 245 246 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 247 if (enable) 248 val &= ~FORCE_DDR_HIGH_FREQ; 249 else 250 val |= FORCE_DDR_HIGH_FREQ; 251 val &= ~FORCE_DDR_LOW_FREQ; 252 val |= FORCE_DDR_FREQ_REQ_ACK; 253 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); 254 255 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & 256 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) 257 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); 258 259 mutex_unlock(&dev_priv->rps.hw_lock); 260} 261 262static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) 263{ 264 u32 val; 265 266 mutex_lock(&dev_priv->rps.hw_lock); 267 268 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 269 if (enable) 270 val |= DSP_MAXFIFO_PM5_ENABLE; 271 else 272 val &= ~DSP_MAXFIFO_PM5_ENABLE; 273 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); 274 275 mutex_unlock(&dev_priv->rps.hw_lock); 276} 277 278#define FW_WM(value, plane) \ 279 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) 280 281void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) 282{ 283 struct drm_device *dev = dev_priv->dev; 284 u32 val; 285 286 if (IS_VALLEYVIEW(dev)) { 287 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); 288 POSTING_READ(FW_BLC_SELF_VLV); 289 dev_priv->wm.vlv.cxsr = enable; 290 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { 291 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); 292 POSTING_READ(FW_BLC_SELF); 293 } else if (IS_PINEVIEW(dev)) { 294 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; 295 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; 296 I915_WRITE(DSPFW3, val); 297 POSTING_READ(DSPFW3); 298 } else if (IS_I945G(dev) || IS_I945GM(dev)) { 299 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : 300 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); 301 I915_WRITE(FW_BLC_SELF, val); 302 POSTING_READ(FW_BLC_SELF); 303 } else if (IS_I915GM(dev)) { 304 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : 305 _MASKED_BIT_DISABLE(INSTPM_SELF_EN); 306 I915_WRITE(INSTPM, val); 307 POSTING_READ(INSTPM); 308 } else { 309 return; 310 } 311 312 DRM_DEBUG_KMS("memory self-refresh is %s\n", 313 enable ? "enabled" : "disabled"); 314} 315 316 317/* 318 * Latency for FIFO fetches is dependent on several factors: 319 * - memory configuration (speed, channels) 320 * - chipset 321 * - current MCH state 322 * It can be fairly high in some situations, so here we assume a fairly 323 * pessimal value. It's a tradeoff between extra memory fetches (if we 324 * set this value too high, the FIFO will fetch frequently to stay full) 325 * and power consumption (set it too low to save power and we might see 326 * FIFO underruns and display "flicker"). 327 * 328 * A value of 5us seems to be a good balance; safe for very low end 329 * platforms but not overly aggressive on lower latency configs. 330 */ 331static const int pessimal_latency_ns = 5000; 332 333#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ 334 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) 335 336static int vlv_get_fifo_size(struct drm_device *dev, 337 enum pipe pipe, int plane) 338{ 339 struct drm_i915_private *dev_priv = dev->dev_private; 340 int sprite0_start, sprite1_start, size; 341 342 switch (pipe) { 343 uint32_t dsparb, dsparb2, dsparb3; 344 case PIPE_A: 345 dsparb = I915_READ(DSPARB); 346 dsparb2 = I915_READ(DSPARB2); 347 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); 348 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); 349 break; 350 case PIPE_B: 351 dsparb = I915_READ(DSPARB); 352 dsparb2 = I915_READ(DSPARB2); 353 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); 354 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); 355 break; 356 case PIPE_C: 357 dsparb2 = I915_READ(DSPARB2); 358 dsparb3 = I915_READ(DSPARB3); 359 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); 360 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); 361 break; 362 default: 363 return 0; 364 } 365 366 switch (plane) { 367 case 0: 368 size = sprite0_start; 369 break; 370 case 1: 371 size = sprite1_start - sprite0_start; 372 break; 373 case 2: 374 size = 512 - 1 - sprite1_start; 375 break; 376 default: 377 return 0; 378 } 379 380 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n", 381 pipe_name(pipe), plane == 0 ? "primary" : "sprite", 382 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), 383 size); 384 385 return size; 386} 387 388static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 389{ 390 struct drm_i915_private *dev_priv = dev->dev_private; 391 uint32_t dsparb = I915_READ(DSPARB); 392 int size; 393 394 size = dsparb & 0x7f; 395 if (plane) 396 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; 397 398 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 399 plane ? "B" : "A", size); 400 401 return size; 402} 403 404static int i830_get_fifo_size(struct drm_device *dev, int plane) 405{ 406 struct drm_i915_private *dev_priv = dev->dev_private; 407 uint32_t dsparb = I915_READ(DSPARB); 408 int size; 409 410 size = dsparb & 0x1ff; 411 if (plane) 412 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; 413 size >>= 1; /* Convert to cachelines */ 414 415 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 416 plane ? "B" : "A", size); 417 418 return size; 419} 420 421static int i845_get_fifo_size(struct drm_device *dev, int plane) 422{ 423 struct drm_i915_private *dev_priv = dev->dev_private; 424 uint32_t dsparb = I915_READ(DSPARB); 425 int size; 426 427 size = dsparb & 0x7f; 428 size >>= 2; /* Convert to cachelines */ 429 430 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 431 plane ? "B" : "A", 432 size); 433 434 return size; 435} 436 437/* Pineview has different values for various configs */ 438static const struct intel_watermark_params pineview_display_wm = { 439 .fifo_size = PINEVIEW_DISPLAY_FIFO, 440 .max_wm = PINEVIEW_MAX_WM, 441 .default_wm = PINEVIEW_DFT_WM, 442 .guard_size = PINEVIEW_GUARD_WM, 443 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 444}; 445static const struct intel_watermark_params pineview_display_hplloff_wm = { 446 .fifo_size = PINEVIEW_DISPLAY_FIFO, 447 .max_wm = PINEVIEW_MAX_WM, 448 .default_wm = PINEVIEW_DFT_HPLLOFF_WM, 449 .guard_size = PINEVIEW_GUARD_WM, 450 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 451}; 452static const struct intel_watermark_params pineview_cursor_wm = { 453 .fifo_size = PINEVIEW_CURSOR_FIFO, 454 .max_wm = PINEVIEW_CURSOR_MAX_WM, 455 .default_wm = PINEVIEW_CURSOR_DFT_WM, 456 .guard_size = PINEVIEW_CURSOR_GUARD_WM, 457 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 458}; 459static const struct intel_watermark_params pineview_cursor_hplloff_wm = { 460 .fifo_size = PINEVIEW_CURSOR_FIFO, 461 .max_wm = PINEVIEW_CURSOR_MAX_WM, 462 .default_wm = PINEVIEW_CURSOR_DFT_WM, 463 .guard_size = PINEVIEW_CURSOR_GUARD_WM, 464 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 465}; 466static const struct intel_watermark_params g4x_wm_info = { 467 .fifo_size = G4X_FIFO_SIZE, 468 .max_wm = G4X_MAX_WM, 469 .default_wm = G4X_MAX_WM, 470 .guard_size = 2, 471 .cacheline_size = G4X_FIFO_LINE_SIZE, 472}; 473static const struct intel_watermark_params g4x_cursor_wm_info = { 474 .fifo_size = I965_CURSOR_FIFO, 475 .max_wm = I965_CURSOR_MAX_WM, 476 .default_wm = I965_CURSOR_DFT_WM, 477 .guard_size = 2, 478 .cacheline_size = G4X_FIFO_LINE_SIZE, 479}; 480static const struct intel_watermark_params valleyview_wm_info = { 481 .fifo_size = VALLEYVIEW_FIFO_SIZE, 482 .max_wm = VALLEYVIEW_MAX_WM, 483 .default_wm = VALLEYVIEW_MAX_WM, 484 .guard_size = 2, 485 .cacheline_size = G4X_FIFO_LINE_SIZE, 486}; 487static const struct intel_watermark_params valleyview_cursor_wm_info = { 488 .fifo_size = I965_CURSOR_FIFO, 489 .max_wm = VALLEYVIEW_CURSOR_MAX_WM, 490 .default_wm = I965_CURSOR_DFT_WM, 491 .guard_size = 2, 492 .cacheline_size = G4X_FIFO_LINE_SIZE, 493}; 494static const struct intel_watermark_params i965_cursor_wm_info = { 495 .fifo_size = I965_CURSOR_FIFO, 496 .max_wm = I965_CURSOR_MAX_WM, 497 .default_wm = I965_CURSOR_DFT_WM, 498 .guard_size = 2, 499 .cacheline_size = I915_FIFO_LINE_SIZE, 500}; 501static const struct intel_watermark_params i945_wm_info = { 502 .fifo_size = I945_FIFO_SIZE, 503 .max_wm = I915_MAX_WM, 504 .default_wm = 1, 505 .guard_size = 2, 506 .cacheline_size = I915_FIFO_LINE_SIZE, 507}; 508static const struct intel_watermark_params i915_wm_info = { 509 .fifo_size = I915_FIFO_SIZE, 510 .max_wm = I915_MAX_WM, 511 .default_wm = 1, 512 .guard_size = 2, 513 .cacheline_size = I915_FIFO_LINE_SIZE, 514}; 515static const struct intel_watermark_params i830_a_wm_info = { 516 .fifo_size = I855GM_FIFO_SIZE, 517 .max_wm = I915_MAX_WM, 518 .default_wm = 1, 519 .guard_size = 2, 520 .cacheline_size = I830_FIFO_LINE_SIZE, 521}; 522static const struct intel_watermark_params i830_bc_wm_info = { 523 .fifo_size = I855GM_FIFO_SIZE, 524 .max_wm = I915_MAX_WM/2, 525 .default_wm = 1, 526 .guard_size = 2, 527 .cacheline_size = I830_FIFO_LINE_SIZE, 528}; 529static const struct intel_watermark_params i845_wm_info = { 530 .fifo_size = I830_FIFO_SIZE, 531 .max_wm = I915_MAX_WM, 532 .default_wm = 1, 533 .guard_size = 2, 534 .cacheline_size = I830_FIFO_LINE_SIZE, 535}; 536 537/** 538 * intel_calculate_wm - calculate watermark level 539 * @clock_in_khz: pixel clock 540 * @wm: chip FIFO params 541 * @pixel_size: display pixel size 542 * @latency_ns: memory latency for the platform 543 * 544 * Calculate the watermark level (the level at which the display plane will 545 * start fetching from memory again). Each chip has a different display 546 * FIFO size and allocation, so the caller needs to figure that out and pass 547 * in the correct intel_watermark_params structure. 548 * 549 * As the pixel clock runs, the FIFO will be drained at a rate that depends 550 * on the pixel size. When it reaches the watermark level, it'll start 551 * fetching FIFO line sized based chunks from memory until the FIFO fills 552 * past the watermark point. If the FIFO drains completely, a FIFO underrun 553 * will occur, and a display engine hang could result. 554 */ 555static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 556 const struct intel_watermark_params *wm, 557 int fifo_size, 558 int pixel_size, 559 unsigned long latency_ns) 560{ 561 long entries_required, wm_size; 562 563 /* 564 * Note: we need to make sure we don't overflow for various clock & 565 * latency values. 566 * clocks go from a few thousand to several hundred thousand. 567 * latency is usually a few thousand 568 */ 569 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / 570 1000; 571 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); 572 573 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); 574 575 wm_size = fifo_size - (entries_required + wm->guard_size); 576 577 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); 578 579 /* Don't promote wm_size to unsigned... */ 580 if (wm_size > (long)wm->max_wm) 581 wm_size = wm->max_wm; 582 if (wm_size <= 0) 583 wm_size = wm->default_wm; 584 585 /* 586 * Bspec seems to indicate that the value shouldn't be lower than 587 * 'burst size + 1'. Certainly 830 is quite unhappy with low values. 588 * Lets go for 8 which is the burst size since certain platforms 589 * already use a hardcoded 8 (which is what the spec says should be 590 * done). 591 */ 592 if (wm_size <= 8) 593 wm_size = 8; 594 595 return wm_size; 596} 597 598static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) 599{ 600 struct drm_crtc *crtc, *enabled = NULL; 601 602 for_each_crtc(dev, crtc) { 603 if (intel_crtc_active(crtc)) { 604 if (enabled) 605 return NULL; 606 enabled = crtc; 607 } 608 } 609 610 return enabled; 611} 612 613static void pineview_update_wm(struct drm_crtc *unused_crtc) 614{ 615 struct drm_device *dev = unused_crtc->dev; 616 struct drm_i915_private *dev_priv = dev->dev_private; 617 struct drm_crtc *crtc; 618 const struct cxsr_latency *latency; 619 u32 reg; 620 unsigned long wm; 621 622 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 623 dev_priv->fsb_freq, dev_priv->mem_freq); 624 if (!latency) { 625 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 626 intel_set_memory_cxsr(dev_priv, false); 627 return; 628 } 629 630 crtc = single_enabled_crtc(dev); 631 if (crtc) { 632 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 633 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 634 int clock = adjusted_mode->crtc_clock; 635 636 /* Display SR */ 637 wm = intel_calculate_wm(clock, &pineview_display_wm, 638 pineview_display_wm.fifo_size, 639 pixel_size, latency->display_sr); 640 reg = I915_READ(DSPFW1); 641 reg &= ~DSPFW_SR_MASK; 642 reg |= FW_WM(wm, SR); 643 I915_WRITE(DSPFW1, reg); 644 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 645 646 /* cursor SR */ 647 wm = intel_calculate_wm(clock, &pineview_cursor_wm, 648 pineview_display_wm.fifo_size, 649 pixel_size, latency->cursor_sr); 650 reg = I915_READ(DSPFW3); 651 reg &= ~DSPFW_CURSOR_SR_MASK; 652 reg |= FW_WM(wm, CURSOR_SR); 653 I915_WRITE(DSPFW3, reg); 654 655 /* Display HPLL off SR */ 656 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, 657 pineview_display_hplloff_wm.fifo_size, 658 pixel_size, latency->display_hpll_disable); 659 reg = I915_READ(DSPFW3); 660 reg &= ~DSPFW_HPLL_SR_MASK; 661 reg |= FW_WM(wm, HPLL_SR); 662 I915_WRITE(DSPFW3, reg); 663 664 /* cursor HPLL off SR */ 665 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, 666 pineview_display_hplloff_wm.fifo_size, 667 pixel_size, latency->cursor_hpll_disable); 668 reg = I915_READ(DSPFW3); 669 reg &= ~DSPFW_HPLL_CURSOR_MASK; 670 reg |= FW_WM(wm, HPLL_CURSOR); 671 I915_WRITE(DSPFW3, reg); 672 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 673 674 intel_set_memory_cxsr(dev_priv, true); 675 } else { 676 intel_set_memory_cxsr(dev_priv, false); 677 } 678} 679 680static bool g4x_compute_wm0(struct drm_device *dev, 681 int plane, 682 const struct intel_watermark_params *display, 683 int display_latency_ns, 684 const struct intel_watermark_params *cursor, 685 int cursor_latency_ns, 686 int *plane_wm, 687 int *cursor_wm) 688{ 689 struct drm_crtc *crtc; 690 const struct drm_display_mode *adjusted_mode; 691 int htotal, hdisplay, clock, pixel_size; 692 int line_time_us, line_count; 693 int entries, tlb_miss; 694 695 crtc = intel_get_crtc_for_plane(dev, plane); 696 if (!intel_crtc_active(crtc)) { 697 *cursor_wm = cursor->guard_size; 698 *plane_wm = display->guard_size; 699 return false; 700 } 701 702 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 703 clock = adjusted_mode->crtc_clock; 704 htotal = adjusted_mode->crtc_htotal; 705 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 706 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 707 708 /* Use the small buffer method to calculate plane watermark */ 709 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 710 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; 711 if (tlb_miss > 0) 712 entries += tlb_miss; 713 entries = DIV_ROUND_UP(entries, display->cacheline_size); 714 *plane_wm = entries + display->guard_size; 715 if (*plane_wm > (int)display->max_wm) 716 *plane_wm = display->max_wm; 717 718 /* Use the large buffer method to calculate cursor watermark */ 719 line_time_us = max(htotal * 1000 / clock, 1); 720 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 721 entries = line_count * crtc->cursor->state->crtc_w * pixel_size; 722 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 723 if (tlb_miss > 0) 724 entries += tlb_miss; 725 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 726 *cursor_wm = entries + cursor->guard_size; 727 if (*cursor_wm > (int)cursor->max_wm) 728 *cursor_wm = (int)cursor->max_wm; 729 730 return true; 731} 732 733/* 734 * Check the wm result. 735 * 736 * If any calculated watermark values is larger than the maximum value that 737 * can be programmed into the associated watermark register, that watermark 738 * must be disabled. 739 */ 740static bool g4x_check_srwm(struct drm_device *dev, 741 int display_wm, int cursor_wm, 742 const struct intel_watermark_params *display, 743 const struct intel_watermark_params *cursor) 744{ 745 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", 746 display_wm, cursor_wm); 747 748 if (display_wm > display->max_wm) { 749 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", 750 display_wm, display->max_wm); 751 return false; 752 } 753 754 if (cursor_wm > cursor->max_wm) { 755 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", 756 cursor_wm, cursor->max_wm); 757 return false; 758 } 759 760 if (!(display_wm || cursor_wm)) { 761 DRM_DEBUG_KMS("SR latency is 0, disabling\n"); 762 return false; 763 } 764 765 return true; 766} 767 768static bool g4x_compute_srwm(struct drm_device *dev, 769 int plane, 770 int latency_ns, 771 const struct intel_watermark_params *display, 772 const struct intel_watermark_params *cursor, 773 int *display_wm, int *cursor_wm) 774{ 775 struct drm_crtc *crtc; 776 const struct drm_display_mode *adjusted_mode; 777 int hdisplay, htotal, pixel_size, clock; 778 unsigned long line_time_us; 779 int line_count, line_size; 780 int small, large; 781 int entries; 782 783 if (!latency_ns) { 784 *display_wm = *cursor_wm = 0; 785 return false; 786 } 787 788 crtc = intel_get_crtc_for_plane(dev, plane); 789 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 790 clock = adjusted_mode->crtc_clock; 791 htotal = adjusted_mode->crtc_htotal; 792 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 793 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 794 795 line_time_us = max(htotal * 1000 / clock, 1); 796 line_count = (latency_ns / line_time_us + 1000) / 1000; 797 line_size = hdisplay * pixel_size; 798 799 /* Use the minimum of the small and large buffer method for primary */ 800 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 801 large = line_count * line_size; 802 803 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 804 *display_wm = entries + display->guard_size; 805 806 /* calculate the self-refresh watermark for display cursor */ 807 entries = line_count * pixel_size * crtc->cursor->state->crtc_w; 808 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 809 *cursor_wm = entries + cursor->guard_size; 810 811 return g4x_check_srwm(dev, 812 *display_wm, *cursor_wm, 813 display, cursor); 814} 815 816#define FW_WM_VLV(value, plane) \ 817 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) 818 819static void vlv_write_wm_values(struct intel_crtc *crtc, 820 const struct vlv_wm_values *wm) 821{ 822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 823 enum pipe pipe = crtc->pipe; 824 825 I915_WRITE(VLV_DDL(pipe), 826 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | 827 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | 828 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | 829 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); 830 831 I915_WRITE(DSPFW1, 832 FW_WM(wm->sr.plane, SR) | 833 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | 834 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | 835 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); 836 I915_WRITE(DSPFW2, 837 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | 838 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | 839 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); 840 I915_WRITE(DSPFW3, 841 FW_WM(wm->sr.cursor, CURSOR_SR)); 842 843 if (IS_CHERRYVIEW(dev_priv)) { 844 I915_WRITE(DSPFW7_CHV, 845 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | 846 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); 847 I915_WRITE(DSPFW8_CHV, 848 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | 849 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); 850 I915_WRITE(DSPFW9_CHV, 851 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | 852 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); 853 I915_WRITE(DSPHOWM, 854 FW_WM(wm->sr.plane >> 9, SR_HI) | 855 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | 856 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | 857 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | 858 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | 859 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | 860 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | 861 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | 862 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | 863 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); 864 } else { 865 I915_WRITE(DSPFW7, 866 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | 867 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); 868 I915_WRITE(DSPHOWM, 869 FW_WM(wm->sr.plane >> 9, SR_HI) | 870 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | 871 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | 872 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | 873 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | 874 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | 875 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); 876 } 877 878 /* zero (unused) WM1 watermarks */ 879 I915_WRITE(DSPFW4, 0); 880 I915_WRITE(DSPFW5, 0); 881 I915_WRITE(DSPFW6, 0); 882 I915_WRITE(DSPHOWM1, 0); 883 884 POSTING_READ(DSPFW1); 885} 886 887#undef FW_WM_VLV 888 889enum vlv_wm_level { 890 VLV_WM_LEVEL_PM2, 891 VLV_WM_LEVEL_PM5, 892 VLV_WM_LEVEL_DDR_DVFS, 893}; 894 895/* latency must be in 0.1us units. */ 896static unsigned int vlv_wm_method2(unsigned int pixel_rate, 897 unsigned int pipe_htotal, 898 unsigned int horiz_pixels, 899 unsigned int bytes_per_pixel, 900 unsigned int latency) 901{ 902 unsigned int ret; 903 904 ret = (latency * pixel_rate) / (pipe_htotal * 10000); 905 ret = (ret + 1) * horiz_pixels * bytes_per_pixel; 906 ret = DIV_ROUND_UP(ret, 64); 907 908 return ret; 909} 910 911static void vlv_setup_wm_latency(struct drm_device *dev) 912{ 913 struct drm_i915_private *dev_priv = dev->dev_private; 914 915 /* all latencies in usec */ 916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; 917 918 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; 919 920 if (IS_CHERRYVIEW(dev_priv)) { 921 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; 922 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; 923 924 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; 925 } 926} 927 928static uint16_t vlv_compute_wm_level(struct intel_plane *plane, 929 struct intel_crtc *crtc, 930 const struct intel_plane_state *state, 931 int level) 932{ 933 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 934 int clock, htotal, pixel_size, width, wm; 935 936 if (dev_priv->wm.pri_latency[level] == 0) 937 return USHRT_MAX; 938 939 if (!state->visible) 940 return 0; 941 942 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0); 943 clock = crtc->config->base.adjusted_mode.crtc_clock; 944 htotal = crtc->config->base.adjusted_mode.crtc_htotal; 945 width = crtc->config->pipe_src_w; 946 if (WARN_ON(htotal == 0)) 947 htotal = 1; 948 949 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 950 /* 951 * FIXME the formula gives values that are 952 * too big for the cursor FIFO, and hence we 953 * would never be able to use cursors. For 954 * now just hardcode the watermark. 955 */ 956 wm = 63; 957 } else { 958 wm = vlv_wm_method2(clock, htotal, width, pixel_size, 959 dev_priv->wm.pri_latency[level] * 10); 960 } 961 962 return min_t(int, wm, USHRT_MAX); 963} 964 965static void vlv_compute_fifo(struct intel_crtc *crtc) 966{ 967 struct drm_device *dev = crtc->base.dev; 968 struct vlv_wm_state *wm_state = &crtc->wm_state; 969 struct intel_plane *plane; 970 unsigned int total_rate = 0; 971 const int fifo_size = 512 - 1; 972 int fifo_extra, fifo_left = fifo_size; 973 974 for_each_intel_plane_on_crtc(dev, crtc, plane) { 975 struct intel_plane_state *state = 976 to_intel_plane_state(plane->base.state); 977 978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) 979 continue; 980 981 if (state->visible) { 982 wm_state->num_active_planes++; 983 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0); 984 } 985 } 986 987 for_each_intel_plane_on_crtc(dev, crtc, plane) { 988 struct intel_plane_state *state = 989 to_intel_plane_state(plane->base.state); 990 unsigned int rate; 991 992 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 993 plane->wm.fifo_size = 63; 994 continue; 995 } 996 997 if (!state->visible) { 998 plane->wm.fifo_size = 0; 999 continue; 1000 } 1001 1002 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0); 1003 plane->wm.fifo_size = fifo_size * rate / total_rate; 1004 fifo_left -= plane->wm.fifo_size; 1005 } 1006 1007 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1); 1008 1009 /* spread the remainder evenly */ 1010 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1011 int plane_extra; 1012 1013 if (fifo_left == 0) 1014 break; 1015 1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) 1017 continue; 1018 1019 /* give it all to the first plane if none are active */ 1020 if (plane->wm.fifo_size == 0 && 1021 wm_state->num_active_planes) 1022 continue; 1023 1024 plane_extra = min(fifo_extra, fifo_left); 1025 plane->wm.fifo_size += plane_extra; 1026 fifo_left -= plane_extra; 1027 } 1028 1029 WARN_ON(fifo_left != 0); 1030} 1031 1032static void vlv_invert_wms(struct intel_crtc *crtc) 1033{ 1034 struct vlv_wm_state *wm_state = &crtc->wm_state; 1035 int level; 1036 1037 for (level = 0; level < wm_state->num_levels; level++) { 1038 struct drm_device *dev = crtc->base.dev; 1039 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; 1040 struct intel_plane *plane; 1041 1042 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; 1043 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor; 1044 1045 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1046 switch (plane->base.type) { 1047 int sprite; 1048 case DRM_PLANE_TYPE_CURSOR: 1049 wm_state->wm[level].cursor = plane->wm.fifo_size - 1050 wm_state->wm[level].cursor; 1051 break; 1052 case DRM_PLANE_TYPE_PRIMARY: 1053 wm_state->wm[level].primary = plane->wm.fifo_size - 1054 wm_state->wm[level].primary; 1055 break; 1056 case DRM_PLANE_TYPE_OVERLAY: 1057 sprite = plane->plane; 1058 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - 1059 wm_state->wm[level].sprite[sprite]; 1060 break; 1061 } 1062 } 1063 } 1064} 1065 1066static void vlv_compute_wm(struct intel_crtc *crtc) 1067{ 1068 struct drm_device *dev = crtc->base.dev; 1069 struct vlv_wm_state *wm_state = &crtc->wm_state; 1070 struct intel_plane *plane; 1071 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; 1072 int level; 1073 1074 memset(wm_state, 0, sizeof(*wm_state)); 1075 1076 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; 1077 wm_state->num_levels = to_i915(dev)->wm.max_level + 1; 1078 1079 wm_state->num_active_planes = 0; 1080 1081 vlv_compute_fifo(crtc); 1082 1083 if (wm_state->num_active_planes != 1) 1084 wm_state->cxsr = false; 1085 1086 if (wm_state->cxsr) { 1087 for (level = 0; level < wm_state->num_levels; level++) { 1088 wm_state->sr[level].plane = sr_fifo_size; 1089 wm_state->sr[level].cursor = 63; 1090 } 1091 } 1092 1093 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1094 struct intel_plane_state *state = 1095 to_intel_plane_state(plane->base.state); 1096 1097 if (!state->visible) 1098 continue; 1099 1100 /* normal watermarks */ 1101 for (level = 0; level < wm_state->num_levels; level++) { 1102 int wm = vlv_compute_wm_level(plane, crtc, state, level); 1103 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511; 1104 1105 /* hack */ 1106 if (WARN_ON(level == 0 && wm > max_wm)) 1107 wm = max_wm; 1108 1109 if (wm > plane->wm.fifo_size) 1110 break; 1111 1112 switch (plane->base.type) { 1113 int sprite; 1114 case DRM_PLANE_TYPE_CURSOR: 1115 wm_state->wm[level].cursor = wm; 1116 break; 1117 case DRM_PLANE_TYPE_PRIMARY: 1118 wm_state->wm[level].primary = wm; 1119 break; 1120 case DRM_PLANE_TYPE_OVERLAY: 1121 sprite = plane->plane; 1122 wm_state->wm[level].sprite[sprite] = wm; 1123 break; 1124 } 1125 } 1126 1127 wm_state->num_levels = level; 1128 1129 if (!wm_state->cxsr) 1130 continue; 1131 1132 /* maxfifo watermarks */ 1133 switch (plane->base.type) { 1134 int sprite, level; 1135 case DRM_PLANE_TYPE_CURSOR: 1136 for (level = 0; level < wm_state->num_levels; level++) 1137 wm_state->sr[level].cursor = 1138 wm_state->wm[level].cursor; 1139 break; 1140 case DRM_PLANE_TYPE_PRIMARY: 1141 for (level = 0; level < wm_state->num_levels; level++) 1142 wm_state->sr[level].plane = 1143 min(wm_state->sr[level].plane, 1144 wm_state->wm[level].primary); 1145 break; 1146 case DRM_PLANE_TYPE_OVERLAY: 1147 sprite = plane->plane; 1148 for (level = 0; level < wm_state->num_levels; level++) 1149 wm_state->sr[level].plane = 1150 min(wm_state->sr[level].plane, 1151 wm_state->wm[level].sprite[sprite]); 1152 break; 1153 } 1154 } 1155 1156 /* clear any (partially) filled invalid levels */ 1157 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { 1158 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); 1159 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level])); 1160 } 1161 1162 vlv_invert_wms(crtc); 1163} 1164 1165#define VLV_FIFO(plane, value) \ 1166 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) 1167 1168static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc) 1169{ 1170 struct drm_device *dev = crtc->base.dev; 1171 struct drm_i915_private *dev_priv = to_i915(dev); 1172 struct intel_plane *plane; 1173 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0; 1174 1175 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1176 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 1177 WARN_ON(plane->wm.fifo_size != 63); 1178 continue; 1179 } 1180 1181 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) 1182 sprite0_start = plane->wm.fifo_size; 1183 else if (plane->plane == 0) 1184 sprite1_start = sprite0_start + plane->wm.fifo_size; 1185 else 1186 fifo_size = sprite1_start + plane->wm.fifo_size; 1187 } 1188 1189 WARN_ON(fifo_size != 512 - 1); 1190 1191 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n", 1192 pipe_name(crtc->pipe), sprite0_start, 1193 sprite1_start, fifo_size); 1194 1195 switch (crtc->pipe) { 1196 uint32_t dsparb, dsparb2, dsparb3; 1197 case PIPE_A: 1198 dsparb = I915_READ(DSPARB); 1199 dsparb2 = I915_READ(DSPARB2); 1200 1201 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | 1202 VLV_FIFO(SPRITEB, 0xff)); 1203 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | 1204 VLV_FIFO(SPRITEB, sprite1_start)); 1205 1206 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | 1207 VLV_FIFO(SPRITEB_HI, 0x1)); 1208 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | 1209 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); 1210 1211 I915_WRITE(DSPARB, dsparb); 1212 I915_WRITE(DSPARB2, dsparb2); 1213 break; 1214 case PIPE_B: 1215 dsparb = I915_READ(DSPARB); 1216 dsparb2 = I915_READ(DSPARB2); 1217 1218 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | 1219 VLV_FIFO(SPRITED, 0xff)); 1220 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | 1221 VLV_FIFO(SPRITED, sprite1_start)); 1222 1223 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | 1224 VLV_FIFO(SPRITED_HI, 0xff)); 1225 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | 1226 VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); 1227 1228 I915_WRITE(DSPARB, dsparb); 1229 I915_WRITE(DSPARB2, dsparb2); 1230 break; 1231 case PIPE_C: 1232 dsparb3 = I915_READ(DSPARB3); 1233 dsparb2 = I915_READ(DSPARB2); 1234 1235 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | 1236 VLV_FIFO(SPRITEF, 0xff)); 1237 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | 1238 VLV_FIFO(SPRITEF, sprite1_start)); 1239 1240 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | 1241 VLV_FIFO(SPRITEF_HI, 0xff)); 1242 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | 1243 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); 1244 1245 I915_WRITE(DSPARB3, dsparb3); 1246 I915_WRITE(DSPARB2, dsparb2); 1247 break; 1248 default: 1249 break; 1250 } 1251} 1252 1253#undef VLV_FIFO 1254 1255static void vlv_merge_wm(struct drm_device *dev, 1256 struct vlv_wm_values *wm) 1257{ 1258 struct intel_crtc *crtc; 1259 int num_active_crtcs = 0; 1260 1261 wm->level = to_i915(dev)->wm.max_level; 1262 wm->cxsr = true; 1263 1264 for_each_intel_crtc(dev, crtc) { 1265 const struct vlv_wm_state *wm_state = &crtc->wm_state; 1266 1267 if (!crtc->active) 1268 continue; 1269 1270 if (!wm_state->cxsr) 1271 wm->cxsr = false; 1272 1273 num_active_crtcs++; 1274 wm->level = min_t(int, wm->level, wm_state->num_levels - 1); 1275 } 1276 1277 if (num_active_crtcs != 1) 1278 wm->cxsr = false; 1279 1280 if (num_active_crtcs > 1) 1281 wm->level = VLV_WM_LEVEL_PM2; 1282 1283 for_each_intel_crtc(dev, crtc) { 1284 struct vlv_wm_state *wm_state = &crtc->wm_state; 1285 enum pipe pipe = crtc->pipe; 1286 1287 if (!crtc->active) 1288 continue; 1289 1290 wm->pipe[pipe] = wm_state->wm[wm->level]; 1291 if (wm->cxsr) 1292 wm->sr = wm_state->sr[wm->level]; 1293 1294 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; 1295 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; 1296 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; 1297 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; 1298 } 1299} 1300 1301static void vlv_update_wm(struct drm_crtc *crtc) 1302{ 1303 struct drm_device *dev = crtc->dev; 1304 struct drm_i915_private *dev_priv = dev->dev_private; 1305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1306 enum pipe pipe = intel_crtc->pipe; 1307 struct vlv_wm_values wm = {}; 1308 1309 vlv_compute_wm(intel_crtc); 1310 vlv_merge_wm(dev, &wm); 1311 1312 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) { 1313 /* FIXME should be part of crtc atomic commit */ 1314 vlv_pipe_set_fifo_size(intel_crtc); 1315 return; 1316 } 1317 1318 if (wm.level < VLV_WM_LEVEL_DDR_DVFS && 1319 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) 1320 chv_set_memory_dvfs(dev_priv, false); 1321 1322 if (wm.level < VLV_WM_LEVEL_PM5 && 1323 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) 1324 chv_set_memory_pm5(dev_priv, false); 1325 1326 if (!wm.cxsr && dev_priv->wm.vlv.cxsr) 1327 intel_set_memory_cxsr(dev_priv, false); 1328 1329 /* FIXME should be part of crtc atomic commit */ 1330 vlv_pipe_set_fifo_size(intel_crtc); 1331 1332 vlv_write_wm_values(intel_crtc, &wm); 1333 1334 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, " 1335 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n", 1336 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor, 1337 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], 1338 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); 1339 1340 if (wm.cxsr && !dev_priv->wm.vlv.cxsr) 1341 intel_set_memory_cxsr(dev_priv, true); 1342 1343 if (wm.level >= VLV_WM_LEVEL_PM5 && 1344 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) 1345 chv_set_memory_pm5(dev_priv, true); 1346 1347 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS && 1348 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) 1349 chv_set_memory_dvfs(dev_priv, true); 1350 1351 dev_priv->wm.vlv = wm; 1352} 1353 1354#define single_plane_enabled(mask) is_power_of_2(mask) 1355 1356static void g4x_update_wm(struct drm_crtc *crtc) 1357{ 1358 struct drm_device *dev = crtc->dev; 1359 static const int sr_latency_ns = 12000; 1360 struct drm_i915_private *dev_priv = dev->dev_private; 1361 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1362 int plane_sr, cursor_sr; 1363 unsigned int enabled = 0; 1364 bool cxsr_enabled; 1365 1366 if (g4x_compute_wm0(dev, PIPE_A, 1367 &g4x_wm_info, pessimal_latency_ns, 1368 &g4x_cursor_wm_info, pessimal_latency_ns, 1369 &planea_wm, &cursora_wm)) 1370 enabled |= 1 << PIPE_A; 1371 1372 if (g4x_compute_wm0(dev, PIPE_B, 1373 &g4x_wm_info, pessimal_latency_ns, 1374 &g4x_cursor_wm_info, pessimal_latency_ns, 1375 &planeb_wm, &cursorb_wm)) 1376 enabled |= 1 << PIPE_B; 1377 1378 if (single_plane_enabled(enabled) && 1379 g4x_compute_srwm(dev, ffs(enabled) - 1, 1380 sr_latency_ns, 1381 &g4x_wm_info, 1382 &g4x_cursor_wm_info, 1383 &plane_sr, &cursor_sr)) { 1384 cxsr_enabled = true; 1385 } else { 1386 cxsr_enabled = false; 1387 intel_set_memory_cxsr(dev_priv, false); 1388 plane_sr = cursor_sr = 0; 1389 } 1390 1391 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " 1392 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1393 planea_wm, cursora_wm, 1394 planeb_wm, cursorb_wm, 1395 plane_sr, cursor_sr); 1396 1397 I915_WRITE(DSPFW1, 1398 FW_WM(plane_sr, SR) | 1399 FW_WM(cursorb_wm, CURSORB) | 1400 FW_WM(planeb_wm, PLANEB) | 1401 FW_WM(planea_wm, PLANEA)); 1402 I915_WRITE(DSPFW2, 1403 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1404 FW_WM(cursora_wm, CURSORA)); 1405 /* HPLL off in SR has some issues on G4x... disable it */ 1406 I915_WRITE(DSPFW3, 1407 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | 1408 FW_WM(cursor_sr, CURSOR_SR)); 1409 1410 if (cxsr_enabled) 1411 intel_set_memory_cxsr(dev_priv, true); 1412} 1413 1414static void i965_update_wm(struct drm_crtc *unused_crtc) 1415{ 1416 struct drm_device *dev = unused_crtc->dev; 1417 struct drm_i915_private *dev_priv = dev->dev_private; 1418 struct drm_crtc *crtc; 1419 int srwm = 1; 1420 int cursor_sr = 16; 1421 bool cxsr_enabled; 1422 1423 /* Calc sr entries for one plane configs */ 1424 crtc = single_enabled_crtc(dev); 1425 if (crtc) { 1426 /* self-refresh has much higher latency */ 1427 static const int sr_latency_ns = 12000; 1428 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1429 int clock = adjusted_mode->crtc_clock; 1430 int htotal = adjusted_mode->crtc_htotal; 1431 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 1432 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 1433 unsigned long line_time_us; 1434 int entries; 1435 1436 line_time_us = max(htotal * 1000 / clock, 1); 1437 1438 /* Use ns/us then divide to preserve precision */ 1439 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1440 pixel_size * hdisplay; 1441 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); 1442 srwm = I965_FIFO_SIZE - entries; 1443 if (srwm < 0) 1444 srwm = 1; 1445 srwm &= 0x1ff; 1446 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", 1447 entries, srwm); 1448 1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1450 pixel_size * crtc->cursor->state->crtc_w; 1451 entries = DIV_ROUND_UP(entries, 1452 i965_cursor_wm_info.cacheline_size); 1453 cursor_sr = i965_cursor_wm_info.fifo_size - 1454 (entries + i965_cursor_wm_info.guard_size); 1455 1456 if (cursor_sr > i965_cursor_wm_info.max_wm) 1457 cursor_sr = i965_cursor_wm_info.max_wm; 1458 1459 DRM_DEBUG_KMS("self-refresh watermark: display plane %d " 1460 "cursor %d\n", srwm, cursor_sr); 1461 1462 cxsr_enabled = true; 1463 } else { 1464 cxsr_enabled = false; 1465 /* Turn off self refresh if both pipes are enabled */ 1466 intel_set_memory_cxsr(dev_priv, false); 1467 } 1468 1469 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 1470 srwm); 1471 1472 /* 965 has limitations... */ 1473 I915_WRITE(DSPFW1, FW_WM(srwm, SR) | 1474 FW_WM(8, CURSORB) | 1475 FW_WM(8, PLANEB) | 1476 FW_WM(8, PLANEA)); 1477 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | 1478 FW_WM(8, PLANEC_OLD)); 1479 /* update cursor SR watermark */ 1480 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); 1481 1482 if (cxsr_enabled) 1483 intel_set_memory_cxsr(dev_priv, true); 1484} 1485 1486#undef FW_WM 1487 1488static void i9xx_update_wm(struct drm_crtc *unused_crtc) 1489{ 1490 struct drm_device *dev = unused_crtc->dev; 1491 struct drm_i915_private *dev_priv = dev->dev_private; 1492 const struct intel_watermark_params *wm_info; 1493 uint32_t fwater_lo; 1494 uint32_t fwater_hi; 1495 int cwm, srwm = 1; 1496 int fifo_size; 1497 int planea_wm, planeb_wm; 1498 struct drm_crtc *crtc, *enabled = NULL; 1499 1500 if (IS_I945GM(dev)) 1501 wm_info = &i945_wm_info; 1502 else if (!IS_GEN2(dev)) 1503 wm_info = &i915_wm_info; 1504 else 1505 wm_info = &i830_a_wm_info; 1506 1507 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1508 crtc = intel_get_crtc_for_plane(dev, 0); 1509 if (intel_crtc_active(crtc)) { 1510 const struct drm_display_mode *adjusted_mode; 1511 int cpp = crtc->primary->state->fb->bits_per_pixel / 8; 1512 if (IS_GEN2(dev)) 1513 cpp = 4; 1514 1515 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1516 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1517 wm_info, fifo_size, cpp, 1518 pessimal_latency_ns); 1519 enabled = crtc; 1520 } else { 1521 planea_wm = fifo_size - wm_info->guard_size; 1522 if (planea_wm > (long)wm_info->max_wm) 1523 planea_wm = wm_info->max_wm; 1524 } 1525 1526 if (IS_GEN2(dev)) 1527 wm_info = &i830_bc_wm_info; 1528 1529 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1530 crtc = intel_get_crtc_for_plane(dev, 1); 1531 if (intel_crtc_active(crtc)) { 1532 const struct drm_display_mode *adjusted_mode; 1533 int cpp = crtc->primary->state->fb->bits_per_pixel / 8; 1534 if (IS_GEN2(dev)) 1535 cpp = 4; 1536 1537 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1538 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1539 wm_info, fifo_size, cpp, 1540 pessimal_latency_ns); 1541 if (enabled == NULL) 1542 enabled = crtc; 1543 else 1544 enabled = NULL; 1545 } else { 1546 planeb_wm = fifo_size - wm_info->guard_size; 1547 if (planeb_wm > (long)wm_info->max_wm) 1548 planeb_wm = wm_info->max_wm; 1549 } 1550 1551 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 1552 1553 if (IS_I915GM(dev) && enabled) { 1554 struct drm_i915_gem_object *obj; 1555 1556 obj = intel_fb_obj(enabled->primary->state->fb); 1557 1558 /* self-refresh seems busted with untiled */ 1559 if (obj->tiling_mode == I915_TILING_NONE) 1560 enabled = NULL; 1561 } 1562 1563 /* 1564 * Overlay gets an aggressive default since video jitter is bad. 1565 */ 1566 cwm = 2; 1567 1568 /* Play safe and disable self-refresh before adjusting watermarks. */ 1569 intel_set_memory_cxsr(dev_priv, false); 1570 1571 /* Calc sr entries for one plane configs */ 1572 if (HAS_FW_BLC(dev) && enabled) { 1573 /* self-refresh has much higher latency */ 1574 static const int sr_latency_ns = 6000; 1575 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode; 1576 int clock = adjusted_mode->crtc_clock; 1577 int htotal = adjusted_mode->crtc_htotal; 1578 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; 1579 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; 1580 unsigned long line_time_us; 1581 int entries; 1582 1583 line_time_us = max(htotal * 1000 / clock, 1); 1584 1585 /* Use ns/us then divide to preserve precision */ 1586 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1587 pixel_size * hdisplay; 1588 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); 1589 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); 1590 srwm = wm_info->fifo_size - entries; 1591 if (srwm < 0) 1592 srwm = 1; 1593 1594 if (IS_I945G(dev) || IS_I945GM(dev)) 1595 I915_WRITE(FW_BLC_SELF, 1596 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); 1597 else if (IS_I915GM(dev)) 1598 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); 1599 } 1600 1601 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 1602 planea_wm, planeb_wm, cwm, srwm); 1603 1604 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 1605 fwater_hi = (cwm & 0x1f); 1606 1607 /* Set request length to 8 cachelines per fetch */ 1608 fwater_lo = fwater_lo | (1 << 24) | (1 << 8); 1609 fwater_hi = fwater_hi | (1 << 8); 1610 1611 I915_WRITE(FW_BLC, fwater_lo); 1612 I915_WRITE(FW_BLC2, fwater_hi); 1613 1614 if (enabled) 1615 intel_set_memory_cxsr(dev_priv, true); 1616} 1617 1618static void i845_update_wm(struct drm_crtc *unused_crtc) 1619{ 1620 struct drm_device *dev = unused_crtc->dev; 1621 struct drm_i915_private *dev_priv = dev->dev_private; 1622 struct drm_crtc *crtc; 1623 const struct drm_display_mode *adjusted_mode; 1624 uint32_t fwater_lo; 1625 int planea_wm; 1626 1627 crtc = single_enabled_crtc(dev); 1628 if (crtc == NULL) 1629 return; 1630 1631 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1632 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1633 &i845_wm_info, 1634 dev_priv->display.get_fifo_size(dev, 0), 1635 4, pessimal_latency_ns); 1636 fwater_lo = I915_READ(FW_BLC) & ~0xfff; 1637 fwater_lo |= (3<<8) | planea_wm; 1638 1639 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); 1640 1641 I915_WRITE(FW_BLC, fwater_lo); 1642} 1643 1644uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) 1645{ 1646 uint32_t pixel_rate; 1647 1648 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; 1649 1650 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to 1651 * adjust the pixel_rate here. */ 1652 1653 if (pipe_config->pch_pfit.enabled) { 1654 uint64_t pipe_w, pipe_h, pfit_w, pfit_h; 1655 uint32_t pfit_size = pipe_config->pch_pfit.size; 1656 1657 pipe_w = pipe_config->pipe_src_w; 1658 pipe_h = pipe_config->pipe_src_h; 1659 1660 pfit_w = (pfit_size >> 16) & 0xFFFF; 1661 pfit_h = pfit_size & 0xFFFF; 1662 if (pipe_w < pfit_w) 1663 pipe_w = pfit_w; 1664 if (pipe_h < pfit_h) 1665 pipe_h = pfit_h; 1666 1667 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, 1668 pfit_w * pfit_h); 1669 } 1670 1671 return pixel_rate; 1672} 1673 1674/* latency must be in 0.1us units. */ 1675static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, 1676 uint32_t latency) 1677{ 1678 uint64_t ret; 1679 1680 if (WARN(latency == 0, "Latency value missing\n")) 1681 return UINT_MAX; 1682 1683 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; 1684 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; 1685 1686 return ret; 1687} 1688 1689/* latency must be in 0.1us units. */ 1690static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 1691 uint32_t horiz_pixels, uint8_t bytes_per_pixel, 1692 uint32_t latency) 1693{ 1694 uint32_t ret; 1695 1696 if (WARN(latency == 0, "Latency value missing\n")) 1697 return UINT_MAX; 1698 1699 ret = (latency * pixel_rate) / (pipe_htotal * 10000); 1700 ret = (ret + 1) * horiz_pixels * bytes_per_pixel; 1701 ret = DIV_ROUND_UP(ret, 64) + 2; 1702 return ret; 1703} 1704 1705static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, 1706 uint8_t bytes_per_pixel) 1707{ 1708 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; 1709} 1710 1711struct skl_pipe_wm_parameters { 1712 bool active; 1713 uint32_t pipe_htotal; 1714 uint32_t pixel_rate; /* in KHz */ 1715 struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; 1716}; 1717 1718struct ilk_wm_maximums { 1719 uint16_t pri; 1720 uint16_t spr; 1721 uint16_t cur; 1722 uint16_t fbc; 1723}; 1724 1725/* used in computing the new watermarks state */ 1726struct intel_wm_config { 1727 unsigned int num_pipes_active; 1728 bool sprites_enabled; 1729 bool sprites_scaled; 1730}; 1731 1732/* 1733 * For both WM_PIPE and WM_LP. 1734 * mem_value must be in 0.1us units. 1735 */ 1736static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, 1737 const struct intel_plane_state *pstate, 1738 uint32_t mem_value, 1739 bool is_lp) 1740{ 1741 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; 1742 uint32_t method1, method2; 1743 1744 if (!cstate->base.active || !pstate->visible) 1745 return 0; 1746 1747 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); 1748 1749 if (!is_lp) 1750 return method1; 1751 1752 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1753 cstate->base.adjusted_mode.crtc_htotal, 1754 drm_rect_width(&pstate->dst), 1755 bpp, 1756 mem_value); 1757 1758 return min(method1, method2); 1759} 1760 1761/* 1762 * For both WM_PIPE and WM_LP. 1763 * mem_value must be in 0.1us units. 1764 */ 1765static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, 1766 const struct intel_plane_state *pstate, 1767 uint32_t mem_value) 1768{ 1769 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; 1770 uint32_t method1, method2; 1771 1772 if (!cstate->base.active || !pstate->visible) 1773 return 0; 1774 1775 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); 1776 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1777 cstate->base.adjusted_mode.crtc_htotal, 1778 drm_rect_width(&pstate->dst), 1779 bpp, 1780 mem_value); 1781 return min(method1, method2); 1782} 1783 1784/* 1785 * For both WM_PIPE and WM_LP. 1786 * mem_value must be in 0.1us units. 1787 */ 1788static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, 1789 const struct intel_plane_state *pstate, 1790 uint32_t mem_value) 1791{ 1792 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; 1793 1794 if (!cstate->base.active || !pstate->visible) 1795 return 0; 1796 1797 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1798 cstate->base.adjusted_mode.crtc_htotal, 1799 drm_rect_width(&pstate->dst), 1800 bpp, 1801 mem_value); 1802} 1803 1804/* Only for WM_LP. */ 1805static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, 1806 const struct intel_plane_state *pstate, 1807 uint32_t pri_val) 1808{ 1809 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; 1810 1811 if (!cstate->base.active || !pstate->visible) 1812 return 0; 1813 1814 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp); 1815} 1816 1817static unsigned int ilk_display_fifo_size(const struct drm_device *dev) 1818{ 1819 if (INTEL_INFO(dev)->gen >= 8) 1820 return 3072; 1821 else if (INTEL_INFO(dev)->gen >= 7) 1822 return 768; 1823 else 1824 return 512; 1825} 1826 1827static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, 1828 int level, bool is_sprite) 1829{ 1830 if (INTEL_INFO(dev)->gen >= 8) 1831 /* BDW primary/sprite plane watermarks */ 1832 return level == 0 ? 255 : 2047; 1833 else if (INTEL_INFO(dev)->gen >= 7) 1834 /* IVB/HSW primary/sprite plane watermarks */ 1835 return level == 0 ? 127 : 1023; 1836 else if (!is_sprite) 1837 /* ILK/SNB primary plane watermarks */ 1838 return level == 0 ? 127 : 511; 1839 else 1840 /* ILK/SNB sprite plane watermarks */ 1841 return level == 0 ? 63 : 255; 1842} 1843 1844static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, 1845 int level) 1846{ 1847 if (INTEL_INFO(dev)->gen >= 7) 1848 return level == 0 ? 63 : 255; 1849 else 1850 return level == 0 ? 31 : 63; 1851} 1852 1853static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) 1854{ 1855 if (INTEL_INFO(dev)->gen >= 8) 1856 return 31; 1857 else 1858 return 15; 1859} 1860 1861/* Calculate the maximum primary/sprite plane watermark */ 1862static unsigned int ilk_plane_wm_max(const struct drm_device *dev, 1863 int level, 1864 const struct intel_wm_config *config, 1865 enum intel_ddb_partitioning ddb_partitioning, 1866 bool is_sprite) 1867{ 1868 unsigned int fifo_size = ilk_display_fifo_size(dev); 1869 1870 /* if sprites aren't enabled, sprites get nothing */ 1871 if (is_sprite && !config->sprites_enabled) 1872 return 0; 1873 1874 /* HSW allows LP1+ watermarks even with multiple pipes */ 1875 if (level == 0 || config->num_pipes_active > 1) { 1876 fifo_size /= INTEL_INFO(dev)->num_pipes; 1877 1878 /* 1879 * For some reason the non self refresh 1880 * FIFO size is only half of the self 1881 * refresh FIFO size on ILK/SNB. 1882 */ 1883 if (INTEL_INFO(dev)->gen <= 6) 1884 fifo_size /= 2; 1885 } 1886 1887 if (config->sprites_enabled) { 1888 /* level 0 is always calculated with 1:1 split */ 1889 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { 1890 if (is_sprite) 1891 fifo_size *= 5; 1892 fifo_size /= 6; 1893 } else { 1894 fifo_size /= 2; 1895 } 1896 } 1897 1898 /* clamp to max that the registers can hold */ 1899 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); 1900} 1901 1902/* Calculate the maximum cursor plane watermark */ 1903static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, 1904 int level, 1905 const struct intel_wm_config *config) 1906{ 1907 /* HSW LP1+ watermarks w/ multiple pipes */ 1908 if (level > 0 && config->num_pipes_active > 1) 1909 return 64; 1910 1911 /* otherwise just report max that registers can hold */ 1912 return ilk_cursor_wm_reg_max(dev, level); 1913} 1914 1915static void ilk_compute_wm_maximums(const struct drm_device *dev, 1916 int level, 1917 const struct intel_wm_config *config, 1918 enum intel_ddb_partitioning ddb_partitioning, 1919 struct ilk_wm_maximums *max) 1920{ 1921 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); 1922 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); 1923 max->cur = ilk_cursor_wm_max(dev, level, config); 1924 max->fbc = ilk_fbc_wm_reg_max(dev); 1925} 1926 1927static void ilk_compute_wm_reg_maximums(struct drm_device *dev, 1928 int level, 1929 struct ilk_wm_maximums *max) 1930{ 1931 max->pri = ilk_plane_wm_reg_max(dev, level, false); 1932 max->spr = ilk_plane_wm_reg_max(dev, level, true); 1933 max->cur = ilk_cursor_wm_reg_max(dev, level); 1934 max->fbc = ilk_fbc_wm_reg_max(dev); 1935} 1936 1937static bool ilk_validate_wm_level(int level, 1938 const struct ilk_wm_maximums *max, 1939 struct intel_wm_level *result) 1940{ 1941 bool ret; 1942 1943 /* already determined to be invalid? */ 1944 if (!result->enable) 1945 return false; 1946 1947 result->enable = result->pri_val <= max->pri && 1948 result->spr_val <= max->spr && 1949 result->cur_val <= max->cur; 1950 1951 ret = result->enable; 1952 1953 /* 1954 * HACK until we can pre-compute everything, 1955 * and thus fail gracefully if LP0 watermarks 1956 * are exceeded... 1957 */ 1958 if (level == 0 && !result->enable) { 1959 if (result->pri_val > max->pri) 1960 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", 1961 level, result->pri_val, max->pri); 1962 if (result->spr_val > max->spr) 1963 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", 1964 level, result->spr_val, max->spr); 1965 if (result->cur_val > max->cur) 1966 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", 1967 level, result->cur_val, max->cur); 1968 1969 result->pri_val = min_t(uint32_t, result->pri_val, max->pri); 1970 result->spr_val = min_t(uint32_t, result->spr_val, max->spr); 1971 result->cur_val = min_t(uint32_t, result->cur_val, max->cur); 1972 result->enable = true; 1973 } 1974 1975 return ret; 1976} 1977 1978static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, 1979 const struct intel_crtc *intel_crtc, 1980 int level, 1981 struct intel_crtc_state *cstate, 1982 struct intel_wm_level *result) 1983{ 1984 struct intel_plane *intel_plane; 1985 uint16_t pri_latency = dev_priv->wm.pri_latency[level]; 1986 uint16_t spr_latency = dev_priv->wm.spr_latency[level]; 1987 uint16_t cur_latency = dev_priv->wm.cur_latency[level]; 1988 1989 /* WM1+ latency values stored in 0.5us units */ 1990 if (level > 0) { 1991 pri_latency *= 5; 1992 spr_latency *= 5; 1993 cur_latency *= 5; 1994 } 1995 1996 for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) { 1997 struct intel_plane_state *pstate = 1998 to_intel_plane_state(intel_plane->base.state); 1999 2000 switch (intel_plane->base.type) { 2001 case DRM_PLANE_TYPE_PRIMARY: 2002 result->pri_val = ilk_compute_pri_wm(cstate, pstate, 2003 pri_latency, 2004 level); 2005 result->fbc_val = ilk_compute_fbc_wm(cstate, pstate, 2006 result->pri_val); 2007 break; 2008 case DRM_PLANE_TYPE_OVERLAY: 2009 result->spr_val = ilk_compute_spr_wm(cstate, pstate, 2010 spr_latency); 2011 break; 2012 case DRM_PLANE_TYPE_CURSOR: 2013 result->cur_val = ilk_compute_cur_wm(cstate, pstate, 2014 cur_latency); 2015 break; 2016 } 2017 } 2018 2019 result->enable = true; 2020} 2021 2022static uint32_t 2023hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) 2024{ 2025 struct drm_i915_private *dev_priv = dev->dev_private; 2026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2027 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; 2028 u32 linetime, ips_linetime; 2029 2030 if (!intel_crtc->active) 2031 return 0; 2032 2033 /* The WM are computed with base on how long it takes to fill a single 2034 * row at the given clock rate, multiplied by 8. 2035 * */ 2036 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, 2037 adjusted_mode->crtc_clock); 2038 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, 2039 dev_priv->cdclk_freq); 2040 2041 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | 2042 PIPE_WM_LINETIME_TIME(linetime); 2043} 2044 2045static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) 2046{ 2047 struct drm_i915_private *dev_priv = dev->dev_private; 2048 2049 if (IS_GEN9(dev)) { 2050 uint32_t val; 2051 int ret, i; 2052 int level, max_level = ilk_wm_max_level(dev); 2053 2054 /* read the first set of memory latencies[0:3] */ 2055 val = 0; /* data0 to be programmed to 0 for first set */ 2056 mutex_lock(&dev_priv->rps.hw_lock); 2057 ret = sandybridge_pcode_read(dev_priv, 2058 GEN9_PCODE_READ_MEM_LATENCY, 2059 &val); 2060 mutex_unlock(&dev_priv->rps.hw_lock); 2061 2062 if (ret) { 2063 DRM_ERROR("SKL Mailbox read error = %d\n", ret); 2064 return; 2065 } 2066 2067 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; 2068 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & 2069 GEN9_MEM_LATENCY_LEVEL_MASK; 2070 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & 2071 GEN9_MEM_LATENCY_LEVEL_MASK; 2072 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & 2073 GEN9_MEM_LATENCY_LEVEL_MASK; 2074 2075 /* read the second set of memory latencies[4:7] */ 2076 val = 1; /* data0 to be programmed to 1 for second set */ 2077 mutex_lock(&dev_priv->rps.hw_lock); 2078 ret = sandybridge_pcode_read(dev_priv, 2079 GEN9_PCODE_READ_MEM_LATENCY, 2080 &val); 2081 mutex_unlock(&dev_priv->rps.hw_lock); 2082 if (ret) { 2083 DRM_ERROR("SKL Mailbox read error = %d\n", ret); 2084 return; 2085 } 2086 2087 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; 2088 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & 2089 GEN9_MEM_LATENCY_LEVEL_MASK; 2090 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & 2091 GEN9_MEM_LATENCY_LEVEL_MASK; 2092 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & 2093 GEN9_MEM_LATENCY_LEVEL_MASK; 2094 2095 /* 2096 * WaWmMemoryReadLatency:skl 2097 * 2098 * punit doesn't take into account the read latency so we need 2099 * to add 2us to the various latency levels we retrieve from 2100 * the punit. 2101 * - W0 is a bit special in that it's the only level that 2102 * can't be disabled if we want to have display working, so 2103 * we always add 2us there. 2104 * - For levels >=1, punit returns 0us latency when they are 2105 * disabled, so we respect that and don't add 2us then 2106 * 2107 * Additionally, if a level n (n > 1) has a 0us latency, all 2108 * levels m (m >= n) need to be disabled. We make sure to 2109 * sanitize the values out of the punit to satisfy this 2110 * requirement. 2111 */ 2112 wm[0] += 2; 2113 for (level = 1; level <= max_level; level++) 2114 if (wm[level] != 0) 2115 wm[level] += 2; 2116 else { 2117 for (i = level + 1; i <= max_level; i++) 2118 wm[i] = 0; 2119 2120 break; 2121 } 2122 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2123 uint64_t sskpd = I915_READ64(MCH_SSKPD); 2124 2125 wm[0] = (sskpd >> 56) & 0xFF; 2126 if (wm[0] == 0) 2127 wm[0] = sskpd & 0xF; 2128 wm[1] = (sskpd >> 4) & 0xFF; 2129 wm[2] = (sskpd >> 12) & 0xFF; 2130 wm[3] = (sskpd >> 20) & 0x1FF; 2131 wm[4] = (sskpd >> 32) & 0x1FF; 2132 } else if (INTEL_INFO(dev)->gen >= 6) { 2133 uint32_t sskpd = I915_READ(MCH_SSKPD); 2134 2135 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; 2136 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; 2137 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; 2138 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; 2139 } else if (INTEL_INFO(dev)->gen >= 5) { 2140 uint32_t mltr = I915_READ(MLTR_ILK); 2141 2142 /* ILK primary LP0 latency is 700 ns */ 2143 wm[0] = 7; 2144 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; 2145 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; 2146 } 2147} 2148 2149static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2150{ 2151 /* ILK sprite LP0 latency is 1300 ns */ 2152 if (INTEL_INFO(dev)->gen == 5) 2153 wm[0] = 13; 2154} 2155 2156static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2157{ 2158 /* ILK cursor LP0 latency is 1300 ns */ 2159 if (INTEL_INFO(dev)->gen == 5) 2160 wm[0] = 13; 2161 2162 /* WaDoubleCursorLP3Latency:ivb */ 2163 if (IS_IVYBRIDGE(dev)) 2164 wm[3] *= 2; 2165} 2166 2167int ilk_wm_max_level(const struct drm_device *dev) 2168{ 2169 /* how many WM levels are we expecting */ 2170 if (INTEL_INFO(dev)->gen >= 9) 2171 return 7; 2172 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2173 return 4; 2174 else if (INTEL_INFO(dev)->gen >= 6) 2175 return 3; 2176 else 2177 return 2; 2178} 2179 2180static void intel_print_wm_latency(struct drm_device *dev, 2181 const char *name, 2182 const uint16_t wm[8]) 2183{ 2184 int level, max_level = ilk_wm_max_level(dev); 2185 2186 for (level = 0; level <= max_level; level++) { 2187 unsigned int latency = wm[level]; 2188 2189 if (latency == 0) { 2190 DRM_ERROR("%s WM%d latency not provided\n", 2191 name, level); 2192 continue; 2193 } 2194 2195 /* 2196 * - latencies are in us on gen9. 2197 * - before then, WM1+ latency values are in 0.5us units 2198 */ 2199 if (IS_GEN9(dev)) 2200 latency *= 10; 2201 else if (level > 0) 2202 latency *= 5; 2203 2204 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", 2205 name, level, wm[level], 2206 latency / 10, latency % 10); 2207 } 2208} 2209 2210static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, 2211 uint16_t wm[5], uint16_t min) 2212{ 2213 int level, max_level = ilk_wm_max_level(dev_priv->dev); 2214 2215 if (wm[0] >= min) 2216 return false; 2217 2218 wm[0] = max(wm[0], min); 2219 for (level = 1; level <= max_level; level++) 2220 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); 2221 2222 return true; 2223} 2224 2225static void snb_wm_latency_quirk(struct drm_device *dev) 2226{ 2227 struct drm_i915_private *dev_priv = dev->dev_private; 2228 bool changed; 2229 2230 /* 2231 * The BIOS provided WM memory latency values are often 2232 * inadequate for high resolution displays. Adjust them. 2233 */ 2234 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | 2235 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | 2236 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); 2237 2238 if (!changed) 2239 return; 2240 2241 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); 2242 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2243 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2244 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2245} 2246 2247static void ilk_setup_wm_latency(struct drm_device *dev) 2248{ 2249 struct drm_i915_private *dev_priv = dev->dev_private; 2250 2251 intel_read_wm_latency(dev, dev_priv->wm.pri_latency); 2252 2253 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, 2254 sizeof(dev_priv->wm.pri_latency)); 2255 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, 2256 sizeof(dev_priv->wm.pri_latency)); 2257 2258 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); 2259 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); 2260 2261 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2262 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2263 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2264 2265 if (IS_GEN6(dev)) 2266 snb_wm_latency_quirk(dev); 2267} 2268 2269static void skl_setup_wm_latency(struct drm_device *dev) 2270{ 2271 struct drm_i915_private *dev_priv = dev->dev_private; 2272 2273 intel_read_wm_latency(dev, dev_priv->wm.skl_latency); 2274 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); 2275} 2276 2277static void ilk_compute_wm_config(struct drm_device *dev, 2278 struct intel_wm_config *config) 2279{ 2280 struct intel_crtc *intel_crtc; 2281 2282 /* Compute the currently _active_ config */ 2283 for_each_intel_crtc(dev, intel_crtc) { 2284 const struct intel_pipe_wm *wm = &intel_crtc->wm.active; 2285 2286 if (!wm->pipe_enabled) 2287 continue; 2288 2289 config->sprites_enabled |= wm->sprites_enabled; 2290 config->sprites_scaled |= wm->sprites_scaled; 2291 config->num_pipes_active++; 2292 } 2293} 2294 2295/* Compute new watermarks for the pipe */ 2296static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate, 2297 struct intel_pipe_wm *pipe_wm) 2298{ 2299 struct drm_crtc *crtc = cstate->base.crtc; 2300 struct drm_device *dev = crtc->dev; 2301 const struct drm_i915_private *dev_priv = dev->dev_private; 2302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2303 struct intel_plane *intel_plane; 2304 struct intel_plane_state *sprstate = NULL; 2305 int level, max_level = ilk_wm_max_level(dev); 2306 /* LP0 watermark maximums depend on this pipe alone */ 2307 struct intel_wm_config config = { 2308 .num_pipes_active = 1, 2309 }; 2310 struct ilk_wm_maximums max; 2311 2312 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { 2313 if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) { 2314 sprstate = to_intel_plane_state(intel_plane->base.state); 2315 break; 2316 } 2317 } 2318 2319 config.sprites_enabled = sprstate->visible; 2320 config.sprites_scaled = sprstate->visible && 2321 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 || 2322 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16); 2323 2324 pipe_wm->pipe_enabled = cstate->base.active; 2325 pipe_wm->sprites_enabled = sprstate->visible; 2326 pipe_wm->sprites_scaled = config.sprites_scaled; 2327 2328 /* ILK/SNB: LP2+ watermarks only w/o sprites */ 2329 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible) 2330 max_level = 1; 2331 2332 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ 2333 if (config.sprites_scaled) 2334 max_level = 0; 2335 2336 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]); 2337 2338 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2339 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); 2340 2341 /* LP0 watermarks always use 1/2 DDB partitioning */ 2342 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); 2343 2344 /* At least LP0 must be valid */ 2345 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) 2346 return false; 2347 2348 ilk_compute_wm_reg_maximums(dev, 1, &max); 2349 2350 for (level = 1; level <= max_level; level++) { 2351 struct intel_wm_level wm = {}; 2352 2353 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm); 2354 2355 /* 2356 * Disable any watermark level that exceeds the 2357 * register maximums since such watermarks are 2358 * always invalid. 2359 */ 2360 if (!ilk_validate_wm_level(level, &max, &wm)) 2361 break; 2362 2363 pipe_wm->wm[level] = wm; 2364 } 2365 2366 return true; 2367} 2368 2369/* 2370 * Merge the watermarks from all active pipes for a specific level. 2371 */ 2372static void ilk_merge_wm_level(struct drm_device *dev, 2373 int level, 2374 struct intel_wm_level *ret_wm) 2375{ 2376 const struct intel_crtc *intel_crtc; 2377 2378 ret_wm->enable = true; 2379 2380 for_each_intel_crtc(dev, intel_crtc) { 2381 const struct intel_pipe_wm *active = &intel_crtc->wm.active; 2382 const struct intel_wm_level *wm = &active->wm[level]; 2383 2384 if (!active->pipe_enabled) 2385 continue; 2386 2387 /* 2388 * The watermark values may have been used in the past, 2389 * so we must maintain them in the registers for some 2390 * time even if the level is now disabled. 2391 */ 2392 if (!wm->enable) 2393 ret_wm->enable = false; 2394 2395 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); 2396 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); 2397 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); 2398 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); 2399 } 2400} 2401 2402/* 2403 * Merge all low power watermarks for all active pipes. 2404 */ 2405static void ilk_wm_merge(struct drm_device *dev, 2406 const struct intel_wm_config *config, 2407 const struct ilk_wm_maximums *max, 2408 struct intel_pipe_wm *merged) 2409{ 2410 struct drm_i915_private *dev_priv = dev->dev_private; 2411 int level, max_level = ilk_wm_max_level(dev); 2412 int last_enabled_level = max_level; 2413 2414 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ 2415 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && 2416 config->num_pipes_active > 1) 2417 return; 2418 2419 /* ILK: FBC WM must be disabled always */ 2420 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; 2421 2422 /* merge each WM1+ level */ 2423 for (level = 1; level <= max_level; level++) { 2424 struct intel_wm_level *wm = &merged->wm[level]; 2425 2426 ilk_merge_wm_level(dev, level, wm); 2427 2428 if (level > last_enabled_level) 2429 wm->enable = false; 2430 else if (!ilk_validate_wm_level(level, max, wm)) 2431 /* make sure all following levels get disabled */ 2432 last_enabled_level = level - 1; 2433 2434 /* 2435 * The spec says it is preferred to disable 2436 * FBC WMs instead of disabling a WM level. 2437 */ 2438 if (wm->fbc_val > max->fbc) { 2439 if (wm->enable) 2440 merged->fbc_wm_enabled = false; 2441 wm->fbc_val = 0; 2442 } 2443 } 2444 2445 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ 2446 /* 2447 * FIXME this is racy. FBC might get enabled later. 2448 * What we should check here is whether FBC can be 2449 * enabled sometime later. 2450 */ 2451 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && 2452 intel_fbc_enabled(dev_priv)) { 2453 for (level = 2; level <= max_level; level++) { 2454 struct intel_wm_level *wm = &merged->wm[level]; 2455 2456 wm->enable = false; 2457 } 2458 } 2459} 2460 2461static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) 2462{ 2463 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ 2464 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); 2465} 2466 2467/* The value we need to program into the WM_LPx latency field */ 2468static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) 2469{ 2470 struct drm_i915_private *dev_priv = dev->dev_private; 2471 2472 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2473 return 2 * level; 2474 else 2475 return dev_priv->wm.pri_latency[level]; 2476} 2477 2478static void ilk_compute_wm_results(struct drm_device *dev, 2479 const struct intel_pipe_wm *merged, 2480 enum intel_ddb_partitioning partitioning, 2481 struct ilk_wm_values *results) 2482{ 2483 struct intel_crtc *intel_crtc; 2484 int level, wm_lp; 2485 2486 results->enable_fbc_wm = merged->fbc_wm_enabled; 2487 results->partitioning = partitioning; 2488 2489 /* LP1+ register values */ 2490 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2491 const struct intel_wm_level *r; 2492 2493 level = ilk_wm_lp_to_level(wm_lp, merged); 2494 2495 r = &merged->wm[level]; 2496 2497 /* 2498 * Maintain the watermark values even if the level is 2499 * disabled. Doing otherwise could cause underruns. 2500 */ 2501 results->wm_lp[wm_lp - 1] = 2502 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | 2503 (r->pri_val << WM1_LP_SR_SHIFT) | 2504 r->cur_val; 2505 2506 if (r->enable) 2507 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; 2508 2509 if (INTEL_INFO(dev)->gen >= 8) 2510 results->wm_lp[wm_lp - 1] |= 2511 r->fbc_val << WM1_LP_FBC_SHIFT_BDW; 2512 else 2513 results->wm_lp[wm_lp - 1] |= 2514 r->fbc_val << WM1_LP_FBC_SHIFT; 2515 2516 /* 2517 * Always set WM1S_LP_EN when spr_val != 0, even if the 2518 * level is disabled. Doing otherwise could cause underruns. 2519 */ 2520 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { 2521 WARN_ON(wm_lp != 1); 2522 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; 2523 } else 2524 results->wm_lp_spr[wm_lp - 1] = r->spr_val; 2525 } 2526 2527 /* LP0 register values */ 2528 for_each_intel_crtc(dev, intel_crtc) { 2529 enum pipe pipe = intel_crtc->pipe; 2530 const struct intel_wm_level *r = 2531 &intel_crtc->wm.active.wm[0]; 2532 2533 if (WARN_ON(!r->enable)) 2534 continue; 2535 2536 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; 2537 2538 results->wm_pipe[pipe] = 2539 (r->pri_val << WM0_PIPE_PLANE_SHIFT) | 2540 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | 2541 r->cur_val; 2542 } 2543} 2544 2545/* Find the result with the highest level enabled. Check for enable_fbc_wm in 2546 * case both are at the same level. Prefer r1 in case they're the same. */ 2547static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, 2548 struct intel_pipe_wm *r1, 2549 struct intel_pipe_wm *r2) 2550{ 2551 int level, max_level = ilk_wm_max_level(dev); 2552 int level1 = 0, level2 = 0; 2553 2554 for (level = 1; level <= max_level; level++) { 2555 if (r1->wm[level].enable) 2556 level1 = level; 2557 if (r2->wm[level].enable) 2558 level2 = level; 2559 } 2560 2561 if (level1 == level2) { 2562 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) 2563 return r2; 2564 else 2565 return r1; 2566 } else if (level1 > level2) { 2567 return r1; 2568 } else { 2569 return r2; 2570 } 2571} 2572 2573/* dirty bits used to track which watermarks need changes */ 2574#define WM_DIRTY_PIPE(pipe) (1 << (pipe)) 2575#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) 2576#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) 2577#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) 2578#define WM_DIRTY_FBC (1 << 24) 2579#define WM_DIRTY_DDB (1 << 25) 2580 2581static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, 2582 const struct ilk_wm_values *old, 2583 const struct ilk_wm_values *new) 2584{ 2585 unsigned int dirty = 0; 2586 enum pipe pipe; 2587 int wm_lp; 2588 2589 for_each_pipe(dev_priv, pipe) { 2590 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { 2591 dirty |= WM_DIRTY_LINETIME(pipe); 2592 /* Must disable LP1+ watermarks too */ 2593 dirty |= WM_DIRTY_LP_ALL; 2594 } 2595 2596 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { 2597 dirty |= WM_DIRTY_PIPE(pipe); 2598 /* Must disable LP1+ watermarks too */ 2599 dirty |= WM_DIRTY_LP_ALL; 2600 } 2601 } 2602 2603 if (old->enable_fbc_wm != new->enable_fbc_wm) { 2604 dirty |= WM_DIRTY_FBC; 2605 /* Must disable LP1+ watermarks too */ 2606 dirty |= WM_DIRTY_LP_ALL; 2607 } 2608 2609 if (old->partitioning != new->partitioning) { 2610 dirty |= WM_DIRTY_DDB; 2611 /* Must disable LP1+ watermarks too */ 2612 dirty |= WM_DIRTY_LP_ALL; 2613 } 2614 2615 /* LP1+ watermarks already deemed dirty, no need to continue */ 2616 if (dirty & WM_DIRTY_LP_ALL) 2617 return dirty; 2618 2619 /* Find the lowest numbered LP1+ watermark in need of an update... */ 2620 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2621 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || 2622 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) 2623 break; 2624 } 2625 2626 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ 2627 for (; wm_lp <= 3; wm_lp++) 2628 dirty |= WM_DIRTY_LP(wm_lp); 2629 2630 return dirty; 2631} 2632 2633static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, 2634 unsigned int dirty) 2635{ 2636 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2637 bool changed = false; 2638 2639 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { 2640 previous->wm_lp[2] &= ~WM1_LP_SR_EN; 2641 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); 2642 changed = true; 2643 } 2644 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { 2645 previous->wm_lp[1] &= ~WM1_LP_SR_EN; 2646 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); 2647 changed = true; 2648 } 2649 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { 2650 previous->wm_lp[0] &= ~WM1_LP_SR_EN; 2651 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); 2652 changed = true; 2653 } 2654 2655 /* 2656 * Don't touch WM1S_LP_EN here. 2657 * Doing so could cause underruns. 2658 */ 2659 2660 return changed; 2661} 2662 2663/* 2664 * The spec says we shouldn't write when we don't need, because every write 2665 * causes WMs to be re-evaluated, expending some power. 2666 */ 2667static void ilk_write_wm_values(struct drm_i915_private *dev_priv, 2668 struct ilk_wm_values *results) 2669{ 2670 struct drm_device *dev = dev_priv->dev; 2671 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2672 unsigned int dirty; 2673 uint32_t val; 2674 2675 dirty = ilk_compute_wm_dirty(dev_priv, previous, results); 2676 if (!dirty) 2677 return; 2678 2679 _ilk_disable_lp_wm(dev_priv, dirty); 2680 2681 if (dirty & WM_DIRTY_PIPE(PIPE_A)) 2682 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); 2683 if (dirty & WM_DIRTY_PIPE(PIPE_B)) 2684 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); 2685 if (dirty & WM_DIRTY_PIPE(PIPE_C)) 2686 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); 2687 2688 if (dirty & WM_DIRTY_LINETIME(PIPE_A)) 2689 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); 2690 if (dirty & WM_DIRTY_LINETIME(PIPE_B)) 2691 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); 2692 if (dirty & WM_DIRTY_LINETIME(PIPE_C)) 2693 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); 2694 2695 if (dirty & WM_DIRTY_DDB) { 2696 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2697 val = I915_READ(WM_MISC); 2698 if (results->partitioning == INTEL_DDB_PART_1_2) 2699 val &= ~WM_MISC_DATA_PARTITION_5_6; 2700 else 2701 val |= WM_MISC_DATA_PARTITION_5_6; 2702 I915_WRITE(WM_MISC, val); 2703 } else { 2704 val = I915_READ(DISP_ARB_CTL2); 2705 if (results->partitioning == INTEL_DDB_PART_1_2) 2706 val &= ~DISP_DATA_PARTITION_5_6; 2707 else 2708 val |= DISP_DATA_PARTITION_5_6; 2709 I915_WRITE(DISP_ARB_CTL2, val); 2710 } 2711 } 2712 2713 if (dirty & WM_DIRTY_FBC) { 2714 val = I915_READ(DISP_ARB_CTL); 2715 if (results->enable_fbc_wm) 2716 val &= ~DISP_FBC_WM_DIS; 2717 else 2718 val |= DISP_FBC_WM_DIS; 2719 I915_WRITE(DISP_ARB_CTL, val); 2720 } 2721 2722 if (dirty & WM_DIRTY_LP(1) && 2723 previous->wm_lp_spr[0] != results->wm_lp_spr[0]) 2724 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); 2725 2726 if (INTEL_INFO(dev)->gen >= 7) { 2727 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) 2728 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); 2729 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) 2730 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); 2731 } 2732 2733 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) 2734 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); 2735 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) 2736 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); 2737 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) 2738 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); 2739 2740 dev_priv->wm.hw = *results; 2741} 2742 2743static bool ilk_disable_lp_wm(struct drm_device *dev) 2744{ 2745 struct drm_i915_private *dev_priv = dev->dev_private; 2746 2747 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); 2748} 2749 2750/* 2751 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the 2752 * different active planes. 2753 */ 2754 2755#define SKL_DDB_SIZE 896 /* in blocks */ 2756#define BXT_DDB_SIZE 512 2757 2758static void 2759skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, 2760 struct drm_crtc *for_crtc, 2761 const struct intel_wm_config *config, 2762 const struct skl_pipe_wm_parameters *params, 2763 struct skl_ddb_entry *alloc /* out */) 2764{ 2765 struct drm_crtc *crtc; 2766 unsigned int pipe_size, ddb_size; 2767 int nth_active_pipe; 2768 2769 if (!params->active) { 2770 alloc->start = 0; 2771 alloc->end = 0; 2772 return; 2773 } 2774 2775 if (IS_BROXTON(dev)) 2776 ddb_size = BXT_DDB_SIZE; 2777 else 2778 ddb_size = SKL_DDB_SIZE; 2779 2780 ddb_size -= 4; /* 4 blocks for bypass path allocation */ 2781 2782 nth_active_pipe = 0; 2783 for_each_crtc(dev, crtc) { 2784 if (!to_intel_crtc(crtc)->active) 2785 continue; 2786 2787 if (crtc == for_crtc) 2788 break; 2789 2790 nth_active_pipe++; 2791 } 2792 2793 pipe_size = ddb_size / config->num_pipes_active; 2794 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; 2795 alloc->end = alloc->start + pipe_size; 2796} 2797 2798static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) 2799{ 2800 if (config->num_pipes_active == 1) 2801 return 32; 2802 2803 return 8; 2804} 2805 2806static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) 2807{ 2808 entry->start = reg & 0x3ff; 2809 entry->end = (reg >> 16) & 0x3ff; 2810 if (entry->end) 2811 entry->end += 1; 2812} 2813 2814void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, 2815 struct skl_ddb_allocation *ddb /* out */) 2816{ 2817 enum pipe pipe; 2818 int plane; 2819 u32 val; 2820 2821 memset(ddb, 0, sizeof(*ddb)); 2822 2823 for_each_pipe(dev_priv, pipe) { 2824 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) 2825 continue; 2826 2827 for_each_plane(dev_priv, pipe, plane) { 2828 val = I915_READ(PLANE_BUF_CFG(pipe, plane)); 2829 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], 2830 val); 2831 } 2832 2833 val = I915_READ(CUR_BUF_CFG(pipe)); 2834 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR], 2835 val); 2836 } 2837} 2838 2839static unsigned int 2840skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y) 2841{ 2842 2843 /* for planar format */ 2844 if (p->y_bytes_per_pixel) { 2845 if (y) /* y-plane data rate */ 2846 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel; 2847 else /* uv-plane data rate */ 2848 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel; 2849 } 2850 2851 /* for packed formats */ 2852 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; 2853} 2854 2855/* 2856 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching 2857 * a 8192x4096@32bpp framebuffer: 2858 * 3 * 4096 * 8192 * 4 < 2^32 2859 */ 2860static unsigned int 2861skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, 2862 const struct skl_pipe_wm_parameters *params) 2863{ 2864 unsigned int total_data_rate = 0; 2865 int plane; 2866 2867 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { 2868 const struct intel_plane_wm_parameters *p; 2869 2870 p = ¶ms->plane[plane]; 2871 if (!p->enabled) 2872 continue; 2873 2874 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */ 2875 if (p->y_bytes_per_pixel) { 2876 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */ 2877 } 2878 } 2879 2880 return total_data_rate; 2881} 2882 2883static void 2884skl_allocate_pipe_ddb(struct drm_crtc *crtc, 2885 const struct intel_wm_config *config, 2886 const struct skl_pipe_wm_parameters *params, 2887 struct skl_ddb_allocation *ddb /* out */) 2888{ 2889 struct drm_device *dev = crtc->dev; 2890 struct drm_i915_private *dev_priv = dev->dev_private; 2891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2892 enum pipe pipe = intel_crtc->pipe; 2893 struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; 2894 uint16_t alloc_size, start, cursor_blocks; 2895 uint16_t minimum[I915_MAX_PLANES]; 2896 uint16_t y_minimum[I915_MAX_PLANES]; 2897 unsigned int total_data_rate; 2898 int plane; 2899 2900 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc); 2901 alloc_size = skl_ddb_entry_size(alloc); 2902 if (alloc_size == 0) { 2903 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); 2904 memset(&ddb->plane[pipe][PLANE_CURSOR], 0, 2905 sizeof(ddb->plane[pipe][PLANE_CURSOR])); 2906 return; 2907 } 2908 2909 cursor_blocks = skl_cursor_allocation(config); 2910 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks; 2911 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; 2912 2913 alloc_size -= cursor_blocks; 2914 alloc->end -= cursor_blocks; 2915 2916 /* 1. Allocate the mininum required blocks for each active plane */ 2917 for_each_plane(dev_priv, pipe, plane) { 2918 const struct intel_plane_wm_parameters *p; 2919 2920 p = ¶ms->plane[plane]; 2921 if (!p->enabled) 2922 continue; 2923 2924 minimum[plane] = 8; 2925 alloc_size -= minimum[plane]; 2926 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0; 2927 alloc_size -= y_minimum[plane]; 2928 } 2929 2930 /* 2931 * 2. Distribute the remaining space in proportion to the amount of 2932 * data each plane needs to fetch from memory. 2933 * 2934 * FIXME: we may not allocate every single block here. 2935 */ 2936 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); 2937 2938 start = alloc->start; 2939 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { 2940 const struct intel_plane_wm_parameters *p; 2941 unsigned int data_rate, y_data_rate; 2942 uint16_t plane_blocks, y_plane_blocks = 0; 2943 2944 p = ¶ms->plane[plane]; 2945 if (!p->enabled) 2946 continue; 2947 2948 data_rate = skl_plane_relative_data_rate(p, 0); 2949 2950 /* 2951 * allocation for (packed formats) or (uv-plane part of planar format): 2952 * promote the expression to 64 bits to avoid overflowing, the 2953 * result is < available as data_rate / total_data_rate < 1 2954 */ 2955 plane_blocks = minimum[plane]; 2956 plane_blocks += div_u64((uint64_t)alloc_size * data_rate, 2957 total_data_rate); 2958 2959 ddb->plane[pipe][plane].start = start; 2960 ddb->plane[pipe][plane].end = start + plane_blocks; 2961 2962 start += plane_blocks; 2963 2964 /* 2965 * allocation for y_plane part of planar format: 2966 */ 2967 if (p->y_bytes_per_pixel) { 2968 y_data_rate = skl_plane_relative_data_rate(p, 1); 2969 y_plane_blocks = y_minimum[plane]; 2970 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, 2971 total_data_rate); 2972 2973 ddb->y_plane[pipe][plane].start = start; 2974 ddb->y_plane[pipe][plane].end = start + y_plane_blocks; 2975 2976 start += y_plane_blocks; 2977 } 2978 2979 } 2980 2981} 2982 2983static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) 2984{ 2985 /* TODO: Take into account the scalers once we support them */ 2986 return config->base.adjusted_mode.crtc_clock; 2987} 2988 2989/* 2990 * The max latency should be 257 (max the punit can code is 255 and we add 2us 2991 * for the read latency) and bytes_per_pixel should always be <= 8, so that 2992 * should allow pixel_rate up to ~2 GHz which seems sufficient since max 2993 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. 2994*/ 2995static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, 2996 uint32_t latency) 2997{ 2998 uint32_t wm_intermediate_val, ret; 2999 3000 if (latency == 0) 3001 return UINT_MAX; 3002 3003 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; 3004 ret = DIV_ROUND_UP(wm_intermediate_val, 1000); 3005 3006 return ret; 3007} 3008 3009static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 3010 uint32_t horiz_pixels, uint8_t bytes_per_pixel, 3011 uint64_t tiling, uint32_t latency) 3012{ 3013 uint32_t ret; 3014 uint32_t plane_bytes_per_line, plane_blocks_per_line; 3015 uint32_t wm_intermediate_val; 3016 3017 if (latency == 0) 3018 return UINT_MAX; 3019 3020 plane_bytes_per_line = horiz_pixels * bytes_per_pixel; 3021 3022 if (tiling == I915_FORMAT_MOD_Y_TILED || 3023 tiling == I915_FORMAT_MOD_Yf_TILED) { 3024 plane_bytes_per_line *= 4; 3025 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3026 plane_blocks_per_line /= 4; 3027 } else { 3028 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3029 } 3030 3031 wm_intermediate_val = latency * pixel_rate; 3032 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * 3033 plane_blocks_per_line; 3034 3035 return ret; 3036} 3037 3038static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, 3039 const struct intel_crtc *intel_crtc) 3040{ 3041 struct drm_device *dev = intel_crtc->base.dev; 3042 struct drm_i915_private *dev_priv = dev->dev_private; 3043 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; 3044 enum pipe pipe = intel_crtc->pipe; 3045 3046 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], 3047 sizeof(new_ddb->plane[pipe]))) 3048 return true; 3049 3050 if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR], 3051 sizeof(new_ddb->plane[pipe][PLANE_CURSOR]))) 3052 return true; 3053 3054 return false; 3055} 3056 3057static void skl_compute_wm_global_parameters(struct drm_device *dev, 3058 struct intel_wm_config *config) 3059{ 3060 struct drm_crtc *crtc; 3061 struct drm_plane *plane; 3062 3063 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 3064 config->num_pipes_active += to_intel_crtc(crtc)->active; 3065 3066 /* FIXME: I don't think we need those two global parameters on SKL */ 3067 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { 3068 struct intel_plane *intel_plane = to_intel_plane(plane); 3069 3070 config->sprites_enabled |= intel_plane->wm.enabled; 3071 config->sprites_scaled |= intel_plane->wm.scaled; 3072 } 3073} 3074 3075static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, 3076 struct skl_pipe_wm_parameters *p) 3077{ 3078 struct drm_device *dev = crtc->dev; 3079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3080 enum pipe pipe = intel_crtc->pipe; 3081 struct drm_plane *plane; 3082 struct drm_framebuffer *fb; 3083 int i = 1; /* Index for sprite planes start */ 3084 3085 p->active = intel_crtc->active; 3086 if (p->active) { 3087 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; 3088 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); 3089 3090 fb = crtc->primary->state->fb; 3091 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */ 3092 if (fb) { 3093 p->plane[0].enabled = true; 3094 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? 3095 drm_format_plane_cpp(fb->pixel_format, 1) : 3096 drm_format_plane_cpp(fb->pixel_format, 0); 3097 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? 3098 drm_format_plane_cpp(fb->pixel_format, 0) : 0; 3099 p->plane[0].tiling = fb->modifier[0]; 3100 } else { 3101 p->plane[0].enabled = false; 3102 p->plane[0].bytes_per_pixel = 0; 3103 p->plane[0].y_bytes_per_pixel = 0; 3104 p->plane[0].tiling = DRM_FORMAT_MOD_NONE; 3105 } 3106 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; 3107 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; 3108 p->plane[0].rotation = crtc->primary->state->rotation; 3109 3110 fb = crtc->cursor->state->fb; 3111 p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0; 3112 if (fb) { 3113 p->plane[PLANE_CURSOR].enabled = true; 3114 p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8; 3115 p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w; 3116 p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h; 3117 } else { 3118 p->plane[PLANE_CURSOR].enabled = false; 3119 p->plane[PLANE_CURSOR].bytes_per_pixel = 0; 3120 p->plane[PLANE_CURSOR].horiz_pixels = 64; 3121 p->plane[PLANE_CURSOR].vert_pixels = 64; 3122 } 3123 } 3124 3125 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { 3126 struct intel_plane *intel_plane = to_intel_plane(plane); 3127 3128 if (intel_plane->pipe == pipe && 3129 plane->type == DRM_PLANE_TYPE_OVERLAY) 3130 p->plane[i++] = intel_plane->wm; 3131 } 3132} 3133 3134static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 3135 struct skl_pipe_wm_parameters *p, 3136 struct intel_plane_wm_parameters *p_params, 3137 uint16_t ddb_allocation, 3138 int level, 3139 uint16_t *out_blocks, /* out */ 3140 uint8_t *out_lines /* out */) 3141{ 3142 uint32_t latency = dev_priv->wm.skl_latency[level]; 3143 uint32_t method1, method2; 3144 uint32_t plane_bytes_per_line, plane_blocks_per_line; 3145 uint32_t res_blocks, res_lines; 3146 uint32_t selected_result; 3147 uint8_t bytes_per_pixel; 3148 3149 if (latency == 0 || !p->active || !p_params->enabled) 3150 return false; 3151 3152 bytes_per_pixel = p_params->y_bytes_per_pixel ? 3153 p_params->y_bytes_per_pixel : 3154 p_params->bytes_per_pixel; 3155 method1 = skl_wm_method1(p->pixel_rate, 3156 bytes_per_pixel, 3157 latency); 3158 method2 = skl_wm_method2(p->pixel_rate, 3159 p->pipe_htotal, 3160 p_params->horiz_pixels, 3161 bytes_per_pixel, 3162 p_params->tiling, 3163 latency); 3164 3165 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel; 3166 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3167 3168 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || 3169 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) { 3170 uint32_t min_scanlines = 4; 3171 uint32_t y_tile_minimum; 3172 if (intel_rotation_90_or_270(p_params->rotation)) { 3173 switch (p_params->bytes_per_pixel) { 3174 case 1: 3175 min_scanlines = 16; 3176 break; 3177 case 2: 3178 min_scanlines = 8; 3179 break; 3180 case 8: 3181 WARN(1, "Unsupported pixel depth for rotation"); 3182 } 3183 } 3184 y_tile_minimum = plane_blocks_per_line * min_scanlines; 3185 selected_result = max(method2, y_tile_minimum); 3186 } else { 3187 if ((ddb_allocation / plane_blocks_per_line) >= 1) 3188 selected_result = min(method1, method2); 3189 else 3190 selected_result = method1; 3191 } 3192 3193 res_blocks = selected_result + 1; 3194 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); 3195 3196 if (level >= 1 && level <= 7) { 3197 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || 3198 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) 3199 res_lines += 4; 3200 else 3201 res_blocks++; 3202 } 3203 3204 if (res_blocks >= ddb_allocation || res_lines > 31) 3205 return false; 3206 3207 *out_blocks = res_blocks; 3208 *out_lines = res_lines; 3209 3210 return true; 3211} 3212 3213static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, 3214 struct skl_ddb_allocation *ddb, 3215 struct skl_pipe_wm_parameters *p, 3216 enum pipe pipe, 3217 int level, 3218 int num_planes, 3219 struct skl_wm_level *result) 3220{ 3221 uint16_t ddb_blocks; 3222 int i; 3223 3224 for (i = 0; i < num_planes; i++) { 3225 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); 3226 3227 result->plane_en[i] = skl_compute_plane_wm(dev_priv, 3228 p, &p->plane[i], 3229 ddb_blocks, 3230 level, 3231 &result->plane_res_b[i], 3232 &result->plane_res_l[i]); 3233 } 3234 3235 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]); 3236 result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p, 3237 &p->plane[PLANE_CURSOR], 3238 ddb_blocks, level, 3239 &result->plane_res_b[PLANE_CURSOR], 3240 &result->plane_res_l[PLANE_CURSOR]); 3241} 3242 3243static uint32_t 3244skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p) 3245{ 3246 if (!to_intel_crtc(crtc)->active) 3247 return 0; 3248 3249 if (WARN_ON(p->pixel_rate == 0)) 3250 return 0; 3251 3252 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate); 3253} 3254 3255static void skl_compute_transition_wm(struct drm_crtc *crtc, 3256 struct skl_pipe_wm_parameters *params, 3257 struct skl_wm_level *trans_wm /* out */) 3258{ 3259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3260 int i; 3261 3262 if (!params->active) 3263 return; 3264 3265 /* Until we know more, just disable transition WMs */ 3266 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3267 trans_wm->plane_en[i] = false; 3268 trans_wm->plane_en[PLANE_CURSOR] = false; 3269} 3270 3271static void skl_compute_pipe_wm(struct drm_crtc *crtc, 3272 struct skl_ddb_allocation *ddb, 3273 struct skl_pipe_wm_parameters *params, 3274 struct skl_pipe_wm *pipe_wm) 3275{ 3276 struct drm_device *dev = crtc->dev; 3277 const struct drm_i915_private *dev_priv = dev->dev_private; 3278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3279 int level, max_level = ilk_wm_max_level(dev); 3280 3281 for (level = 0; level <= max_level; level++) { 3282 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, 3283 level, intel_num_planes(intel_crtc), 3284 &pipe_wm->wm[level]); 3285 } 3286 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params); 3287 3288 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm); 3289} 3290 3291static void skl_compute_wm_results(struct drm_device *dev, 3292 struct skl_pipe_wm_parameters *p, 3293 struct skl_pipe_wm *p_wm, 3294 struct skl_wm_values *r, 3295 struct intel_crtc *intel_crtc) 3296{ 3297 int level, max_level = ilk_wm_max_level(dev); 3298 enum pipe pipe = intel_crtc->pipe; 3299 uint32_t temp; 3300 int i; 3301 3302 for (level = 0; level <= max_level; level++) { 3303 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3304 temp = 0; 3305 3306 temp |= p_wm->wm[level].plane_res_l[i] << 3307 PLANE_WM_LINES_SHIFT; 3308 temp |= p_wm->wm[level].plane_res_b[i]; 3309 if (p_wm->wm[level].plane_en[i]) 3310 temp |= PLANE_WM_EN; 3311 3312 r->plane[pipe][i][level] = temp; 3313 } 3314 3315 temp = 0; 3316 3317 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; 3318 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR]; 3319 3320 if (p_wm->wm[level].plane_en[PLANE_CURSOR]) 3321 temp |= PLANE_WM_EN; 3322 3323 r->plane[pipe][PLANE_CURSOR][level] = temp; 3324 3325 } 3326 3327 /* transition WMs */ 3328 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3329 temp = 0; 3330 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; 3331 temp |= p_wm->trans_wm.plane_res_b[i]; 3332 if (p_wm->trans_wm.plane_en[i]) 3333 temp |= PLANE_WM_EN; 3334 3335 r->plane_trans[pipe][i] = temp; 3336 } 3337 3338 temp = 0; 3339 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; 3340 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR]; 3341 if (p_wm->trans_wm.plane_en[PLANE_CURSOR]) 3342 temp |= PLANE_WM_EN; 3343 3344 r->plane_trans[pipe][PLANE_CURSOR] = temp; 3345 3346 r->wm_linetime[pipe] = p_wm->linetime; 3347} 3348 3349static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, 3350 const struct skl_ddb_entry *entry) 3351{ 3352 if (entry->end) 3353 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); 3354 else 3355 I915_WRITE(reg, 0); 3356} 3357 3358static void skl_write_wm_values(struct drm_i915_private *dev_priv, 3359 const struct skl_wm_values *new) 3360{ 3361 struct drm_device *dev = dev_priv->dev; 3362 struct intel_crtc *crtc; 3363 3364 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { 3365 int i, level, max_level = ilk_wm_max_level(dev); 3366 enum pipe pipe = crtc->pipe; 3367 3368 if (!new->dirty[pipe]) 3369 continue; 3370 3371 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); 3372 3373 for (level = 0; level <= max_level; level++) { 3374 for (i = 0; i < intel_num_planes(crtc); i++) 3375 I915_WRITE(PLANE_WM(pipe, i, level), 3376 new->plane[pipe][i][level]); 3377 I915_WRITE(CUR_WM(pipe, level), 3378 new->plane[pipe][PLANE_CURSOR][level]); 3379 } 3380 for (i = 0; i < intel_num_planes(crtc); i++) 3381 I915_WRITE(PLANE_WM_TRANS(pipe, i), 3382 new->plane_trans[pipe][i]); 3383 I915_WRITE(CUR_WM_TRANS(pipe), 3384 new->plane_trans[pipe][PLANE_CURSOR]); 3385 3386 for (i = 0; i < intel_num_planes(crtc); i++) { 3387 skl_ddb_entry_write(dev_priv, 3388 PLANE_BUF_CFG(pipe, i), 3389 &new->ddb.plane[pipe][i]); 3390 skl_ddb_entry_write(dev_priv, 3391 PLANE_NV12_BUF_CFG(pipe, i), 3392 &new->ddb.y_plane[pipe][i]); 3393 } 3394 3395 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), 3396 &new->ddb.plane[pipe][PLANE_CURSOR]); 3397 } 3398} 3399 3400/* 3401 * When setting up a new DDB allocation arrangement, we need to correctly 3402 * sequence the times at which the new allocations for the pipes are taken into 3403 * account or we'll have pipes fetching from space previously allocated to 3404 * another pipe. 3405 * 3406 * Roughly the sequence looks like: 3407 * 1. re-allocate the pipe(s) with the allocation being reduced and not 3408 * overlapping with a previous light-up pipe (another way to put it is: 3409 * pipes with their new allocation strickly included into their old ones). 3410 * 2. re-allocate the other pipes that get their allocation reduced 3411 * 3. allocate the pipes having their allocation increased 3412 * 3413 * Steps 1. and 2. are here to take care of the following case: 3414 * - Initially DDB looks like this: 3415 * | B | C | 3416 * - enable pipe A. 3417 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C 3418 * allocation 3419 * | A | B | C | 3420 * 3421 * We need to sequence the re-allocation: C, B, A (and not B, C, A). 3422 */ 3423 3424static void 3425skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) 3426{ 3427 int plane; 3428 3429 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); 3430 3431 for_each_plane(dev_priv, pipe, plane) { 3432 I915_WRITE(PLANE_SURF(pipe, plane), 3433 I915_READ(PLANE_SURF(pipe, plane))); 3434 } 3435 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); 3436} 3437 3438static bool 3439skl_ddb_allocation_included(const struct skl_ddb_allocation *old, 3440 const struct skl_ddb_allocation *new, 3441 enum pipe pipe) 3442{ 3443 uint16_t old_size, new_size; 3444 3445 old_size = skl_ddb_entry_size(&old->pipe[pipe]); 3446 new_size = skl_ddb_entry_size(&new->pipe[pipe]); 3447 3448 return old_size != new_size && 3449 new->pipe[pipe].start >= old->pipe[pipe].start && 3450 new->pipe[pipe].end <= old->pipe[pipe].end; 3451} 3452 3453static void skl_flush_wm_values(struct drm_i915_private *dev_priv, 3454 struct skl_wm_values *new_values) 3455{ 3456 struct drm_device *dev = dev_priv->dev; 3457 struct skl_ddb_allocation *cur_ddb, *new_ddb; 3458 bool reallocated[I915_MAX_PIPES] = {}; 3459 struct intel_crtc *crtc; 3460 enum pipe pipe; 3461 3462 new_ddb = &new_values->ddb; 3463 cur_ddb = &dev_priv->wm.skl_hw.ddb; 3464 3465 /* 3466 * First pass: flush the pipes with the new allocation contained into 3467 * the old space. 3468 * 3469 * We'll wait for the vblank on those pipes to ensure we can safely 3470 * re-allocate the freed space without this pipe fetching from it. 3471 */ 3472 for_each_intel_crtc(dev, crtc) { 3473 if (!crtc->active) 3474 continue; 3475 3476 pipe = crtc->pipe; 3477 3478 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) 3479 continue; 3480 3481 skl_wm_flush_pipe(dev_priv, pipe, 1); 3482 intel_wait_for_vblank(dev, pipe); 3483 3484 reallocated[pipe] = true; 3485 } 3486 3487 3488 /* 3489 * Second pass: flush the pipes that are having their allocation 3490 * reduced, but overlapping with a previous allocation. 3491 * 3492 * Here as well we need to wait for the vblank to make sure the freed 3493 * space is not used anymore. 3494 */ 3495 for_each_intel_crtc(dev, crtc) { 3496 if (!crtc->active) 3497 continue; 3498 3499 pipe = crtc->pipe; 3500 3501 if (reallocated[pipe]) 3502 continue; 3503 3504 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < 3505 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { 3506 skl_wm_flush_pipe(dev_priv, pipe, 2); 3507 intel_wait_for_vblank(dev, pipe); 3508 reallocated[pipe] = true; 3509 } 3510 } 3511 3512 /* 3513 * Third pass: flush the pipes that got more space allocated. 3514 * 3515 * We don't need to actively wait for the update here, next vblank 3516 * will just get more DDB space with the correct WM values. 3517 */ 3518 for_each_intel_crtc(dev, crtc) { 3519 if (!crtc->active) 3520 continue; 3521 3522 pipe = crtc->pipe; 3523 3524 /* 3525 * At this point, only the pipes more space than before are 3526 * left to re-allocate. 3527 */ 3528 if (reallocated[pipe]) 3529 continue; 3530 3531 skl_wm_flush_pipe(dev_priv, pipe, 3); 3532 } 3533} 3534 3535static bool skl_update_pipe_wm(struct drm_crtc *crtc, 3536 struct skl_pipe_wm_parameters *params, 3537 struct intel_wm_config *config, 3538 struct skl_ddb_allocation *ddb, /* out */ 3539 struct skl_pipe_wm *pipe_wm /* out */) 3540{ 3541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3542 3543 skl_compute_wm_pipe_parameters(crtc, params); 3544 skl_allocate_pipe_ddb(crtc, config, params, ddb); 3545 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm); 3546 3547 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) 3548 return false; 3549 3550 intel_crtc->wm.skl_active = *pipe_wm; 3551 3552 return true; 3553} 3554 3555static void skl_update_other_pipe_wm(struct drm_device *dev, 3556 struct drm_crtc *crtc, 3557 struct intel_wm_config *config, 3558 struct skl_wm_values *r) 3559{ 3560 struct intel_crtc *intel_crtc; 3561 struct intel_crtc *this_crtc = to_intel_crtc(crtc); 3562 3563 /* 3564 * If the WM update hasn't changed the allocation for this_crtc (the 3565 * crtc we are currently computing the new WM values for), other 3566 * enabled crtcs will keep the same allocation and we don't need to 3567 * recompute anything for them. 3568 */ 3569 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) 3570 return; 3571 3572 /* 3573 * Otherwise, because of this_crtc being freshly enabled/disabled, the 3574 * other active pipes need new DDB allocation and WM values. 3575 */ 3576 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, 3577 base.head) { 3578 struct skl_pipe_wm_parameters params = {}; 3579 struct skl_pipe_wm pipe_wm = {}; 3580 bool wm_changed; 3581 3582 if (this_crtc->pipe == intel_crtc->pipe) 3583 continue; 3584 3585 if (!intel_crtc->active) 3586 continue; 3587 3588 wm_changed = skl_update_pipe_wm(&intel_crtc->base, 3589 ¶ms, config, 3590 &r->ddb, &pipe_wm); 3591 3592 /* 3593 * If we end up re-computing the other pipe WM values, it's 3594 * because it was really needed, so we expect the WM values to 3595 * be different. 3596 */ 3597 WARN_ON(!wm_changed); 3598 3599 skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc); 3600 r->dirty[intel_crtc->pipe] = true; 3601 } 3602} 3603 3604static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe) 3605{ 3606 watermarks->wm_linetime[pipe] = 0; 3607 memset(watermarks->plane[pipe], 0, 3608 sizeof(uint32_t) * 8 * I915_MAX_PLANES); 3609 memset(watermarks->plane_trans[pipe], 3610 0, sizeof(uint32_t) * I915_MAX_PLANES); 3611 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0; 3612 3613 /* Clear ddb entries for pipe */ 3614 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry)); 3615 memset(&watermarks->ddb.plane[pipe], 0, 3616 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); 3617 memset(&watermarks->ddb.y_plane[pipe], 0, 3618 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); 3619 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0, 3620 sizeof(struct skl_ddb_entry)); 3621 3622} 3623 3624static void skl_update_wm(struct drm_crtc *crtc) 3625{ 3626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3627 struct drm_device *dev = crtc->dev; 3628 struct drm_i915_private *dev_priv = dev->dev_private; 3629 struct skl_pipe_wm_parameters params = {}; 3630 struct skl_wm_values *results = &dev_priv->wm.skl_results; 3631 struct skl_pipe_wm pipe_wm = {}; 3632 struct intel_wm_config config = {}; 3633 3634 3635 /* Clear all dirty flags */ 3636 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES); 3637 3638 skl_clear_wm(results, intel_crtc->pipe); 3639 3640 skl_compute_wm_global_parameters(dev, &config); 3641 3642 if (!skl_update_pipe_wm(crtc, ¶ms, &config, 3643 &results->ddb, &pipe_wm)) 3644 return; 3645 3646 skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc); 3647 results->dirty[intel_crtc->pipe] = true; 3648 3649 skl_update_other_pipe_wm(dev, crtc, &config, results); 3650 skl_write_wm_values(dev_priv, results); 3651 skl_flush_wm_values(dev_priv, results); 3652 3653 /* store the new configuration */ 3654 dev_priv->wm.skl_hw = *results; 3655} 3656 3657static void 3658skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, 3659 uint32_t sprite_width, uint32_t sprite_height, 3660 int pixel_size, bool enabled, bool scaled) 3661{ 3662 struct intel_plane *intel_plane = to_intel_plane(plane); 3663 struct drm_framebuffer *fb = plane->state->fb; 3664 3665 intel_plane->wm.enabled = enabled; 3666 intel_plane->wm.scaled = scaled; 3667 intel_plane->wm.horiz_pixels = sprite_width; 3668 intel_plane->wm.vert_pixels = sprite_height; 3669 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE; 3670 3671 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */ 3672 intel_plane->wm.bytes_per_pixel = 3673 (fb && fb->pixel_format == DRM_FORMAT_NV12) ? 3674 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size; 3675 intel_plane->wm.y_bytes_per_pixel = 3676 (fb && fb->pixel_format == DRM_FORMAT_NV12) ? 3677 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0; 3678 3679 /* 3680 * Framebuffer can be NULL on plane disable, but it does not 3681 * matter for watermarks if we assume no tiling in that case. 3682 */ 3683 if (fb) 3684 intel_plane->wm.tiling = fb->modifier[0]; 3685 intel_plane->wm.rotation = plane->state->rotation; 3686 3687 skl_update_wm(crtc); 3688} 3689 3690static void ilk_update_wm(struct drm_crtc *crtc) 3691{ 3692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3693 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); 3694 struct drm_device *dev = crtc->dev; 3695 struct drm_i915_private *dev_priv = dev->dev_private; 3696 struct ilk_wm_maximums max; 3697 struct ilk_wm_values results = {}; 3698 enum intel_ddb_partitioning partitioning; 3699 struct intel_pipe_wm pipe_wm = {}; 3700 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; 3701 struct intel_wm_config config = {}; 3702 3703 WARN_ON(cstate->base.active != intel_crtc->active); 3704 3705 intel_compute_pipe_wm(cstate, &pipe_wm); 3706 3707 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) 3708 return; 3709 3710 intel_crtc->wm.active = pipe_wm; 3711 3712 ilk_compute_wm_config(dev, &config); 3713 3714 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); 3715 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); 3716 3717 /* 5/6 split only in single pipe config on IVB+ */ 3718 if (INTEL_INFO(dev)->gen >= 7 && 3719 config.num_pipes_active == 1 && config.sprites_enabled) { 3720 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); 3721 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); 3722 3723 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); 3724 } else { 3725 best_lp_wm = &lp_wm_1_2; 3726 } 3727 3728 partitioning = (best_lp_wm == &lp_wm_1_2) ? 3729 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; 3730 3731 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); 3732 3733 ilk_write_wm_values(dev_priv, &results); 3734} 3735 3736static void 3737ilk_update_sprite_wm(struct drm_plane *plane, 3738 struct drm_crtc *crtc, 3739 uint32_t sprite_width, uint32_t sprite_height, 3740 int pixel_size, bool enabled, bool scaled) 3741{ 3742 struct drm_device *dev = plane->dev; 3743 struct intel_plane *intel_plane = to_intel_plane(plane); 3744 3745 /* 3746 * IVB workaround: must disable low power watermarks for at least 3747 * one frame before enabling scaling. LP watermarks can be re-enabled 3748 * when scaling is disabled. 3749 * 3750 * WaCxSRDisabledForSpriteScaling:ivb 3751 */ 3752 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) 3753 intel_wait_for_vblank(dev, intel_plane->pipe); 3754 3755 ilk_update_wm(crtc); 3756} 3757 3758static void skl_pipe_wm_active_state(uint32_t val, 3759 struct skl_pipe_wm *active, 3760 bool is_transwm, 3761 bool is_cursor, 3762 int i, 3763 int level) 3764{ 3765 bool is_enabled = (val & PLANE_WM_EN) != 0; 3766 3767 if (!is_transwm) { 3768 if (!is_cursor) { 3769 active->wm[level].plane_en[i] = is_enabled; 3770 active->wm[level].plane_res_b[i] = 3771 val & PLANE_WM_BLOCKS_MASK; 3772 active->wm[level].plane_res_l[i] = 3773 (val >> PLANE_WM_LINES_SHIFT) & 3774 PLANE_WM_LINES_MASK; 3775 } else { 3776 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled; 3777 active->wm[level].plane_res_b[PLANE_CURSOR] = 3778 val & PLANE_WM_BLOCKS_MASK; 3779 active->wm[level].plane_res_l[PLANE_CURSOR] = 3780 (val >> PLANE_WM_LINES_SHIFT) & 3781 PLANE_WM_LINES_MASK; 3782 } 3783 } else { 3784 if (!is_cursor) { 3785 active->trans_wm.plane_en[i] = is_enabled; 3786 active->trans_wm.plane_res_b[i] = 3787 val & PLANE_WM_BLOCKS_MASK; 3788 active->trans_wm.plane_res_l[i] = 3789 (val >> PLANE_WM_LINES_SHIFT) & 3790 PLANE_WM_LINES_MASK; 3791 } else { 3792 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled; 3793 active->trans_wm.plane_res_b[PLANE_CURSOR] = 3794 val & PLANE_WM_BLOCKS_MASK; 3795 active->trans_wm.plane_res_l[PLANE_CURSOR] = 3796 (val >> PLANE_WM_LINES_SHIFT) & 3797 PLANE_WM_LINES_MASK; 3798 } 3799 } 3800} 3801 3802static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) 3803{ 3804 struct drm_device *dev = crtc->dev; 3805 struct drm_i915_private *dev_priv = dev->dev_private; 3806 struct skl_wm_values *hw = &dev_priv->wm.skl_hw; 3807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3808 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; 3809 enum pipe pipe = intel_crtc->pipe; 3810 int level, i, max_level; 3811 uint32_t temp; 3812 3813 max_level = ilk_wm_max_level(dev); 3814 3815 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); 3816 3817 for (level = 0; level <= max_level; level++) { 3818 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3819 hw->plane[pipe][i][level] = 3820 I915_READ(PLANE_WM(pipe, i, level)); 3821 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level)); 3822 } 3823 3824 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3825 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); 3826 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe)); 3827 3828 if (!intel_crtc->active) 3829 return; 3830 3831 hw->dirty[pipe] = true; 3832 3833 active->linetime = hw->wm_linetime[pipe]; 3834 3835 for (level = 0; level <= max_level; level++) { 3836 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3837 temp = hw->plane[pipe][i][level]; 3838 skl_pipe_wm_active_state(temp, active, false, 3839 false, i, level); 3840 } 3841 temp = hw->plane[pipe][PLANE_CURSOR][level]; 3842 skl_pipe_wm_active_state(temp, active, false, true, i, level); 3843 } 3844 3845 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3846 temp = hw->plane_trans[pipe][i]; 3847 skl_pipe_wm_active_state(temp, active, true, false, i, 0); 3848 } 3849 3850 temp = hw->plane_trans[pipe][PLANE_CURSOR]; 3851 skl_pipe_wm_active_state(temp, active, true, true, i, 0); 3852} 3853 3854void skl_wm_get_hw_state(struct drm_device *dev) 3855{ 3856 struct drm_i915_private *dev_priv = dev->dev_private; 3857 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; 3858 struct drm_crtc *crtc; 3859 3860 skl_ddb_get_hw_state(dev_priv, ddb); 3861 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 3862 skl_pipe_wm_get_hw_state(crtc); 3863} 3864 3865static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) 3866{ 3867 struct drm_device *dev = crtc->dev; 3868 struct drm_i915_private *dev_priv = dev->dev_private; 3869 struct ilk_wm_values *hw = &dev_priv->wm.hw; 3870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3871 struct intel_pipe_wm *active = &intel_crtc->wm.active; 3872 enum pipe pipe = intel_crtc->pipe; 3873 static const unsigned int wm0_pipe_reg[] = { 3874 [PIPE_A] = WM0_PIPEA_ILK, 3875 [PIPE_B] = WM0_PIPEB_ILK, 3876 [PIPE_C] = WM0_PIPEC_IVB, 3877 }; 3878 3879 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); 3880 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 3881 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); 3882 3883 memset(active, 0, sizeof(*active)); 3884 3885 active->pipe_enabled = intel_crtc->active; 3886 3887 if (active->pipe_enabled) { 3888 u32 tmp = hw->wm_pipe[pipe]; 3889 3890 /* 3891 * For active pipes LP0 watermark is marked as 3892 * enabled, and LP1+ watermaks as disabled since 3893 * we can't really reverse compute them in case 3894 * multiple pipes are active. 3895 */ 3896 active->wm[0].enable = true; 3897 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; 3898 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; 3899 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; 3900 active->linetime = hw->wm_linetime[pipe]; 3901 } else { 3902 int level, max_level = ilk_wm_max_level(dev); 3903 3904 /* 3905 * For inactive pipes, all watermark levels 3906 * should be marked as enabled but zeroed, 3907 * which is what we'd compute them to. 3908 */ 3909 for (level = 0; level <= max_level; level++) 3910 active->wm[level].enable = true; 3911 } 3912} 3913 3914#define _FW_WM(value, plane) \ 3915 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) 3916#define _FW_WM_VLV(value, plane) \ 3917 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) 3918 3919static void vlv_read_wm_values(struct drm_i915_private *dev_priv, 3920 struct vlv_wm_values *wm) 3921{ 3922 enum pipe pipe; 3923 uint32_t tmp; 3924 3925 for_each_pipe(dev_priv, pipe) { 3926 tmp = I915_READ(VLV_DDL(pipe)); 3927 3928 wm->ddl[pipe].primary = 3929 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3930 wm->ddl[pipe].cursor = 3931 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3932 wm->ddl[pipe].sprite[0] = 3933 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3934 wm->ddl[pipe].sprite[1] = 3935 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3936 } 3937 3938 tmp = I915_READ(DSPFW1); 3939 wm->sr.plane = _FW_WM(tmp, SR); 3940 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB); 3941 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB); 3942 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA); 3943 3944 tmp = I915_READ(DSPFW2); 3945 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB); 3946 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA); 3947 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA); 3948 3949 tmp = I915_READ(DSPFW3); 3950 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); 3951 3952 if (IS_CHERRYVIEW(dev_priv)) { 3953 tmp = I915_READ(DSPFW7_CHV); 3954 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); 3955 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); 3956 3957 tmp = I915_READ(DSPFW8_CHV); 3958 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF); 3959 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE); 3960 3961 tmp = I915_READ(DSPFW9_CHV); 3962 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC); 3963 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC); 3964 3965 tmp = I915_READ(DSPHOWM); 3966 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; 3967 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8; 3968 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8; 3969 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8; 3970 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; 3971 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; 3972 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; 3973 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; 3974 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; 3975 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; 3976 } else { 3977 tmp = I915_READ(DSPFW7); 3978 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); 3979 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); 3980 3981 tmp = I915_READ(DSPHOWM); 3982 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; 3983 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; 3984 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; 3985 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; 3986 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; 3987 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; 3988 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; 3989 } 3990} 3991 3992#undef _FW_WM 3993#undef _FW_WM_VLV 3994 3995void vlv_wm_get_hw_state(struct drm_device *dev) 3996{ 3997 struct drm_i915_private *dev_priv = to_i915(dev); 3998 struct vlv_wm_values *wm = &dev_priv->wm.vlv; 3999 struct intel_plane *plane; 4000 enum pipe pipe; 4001 u32 val; 4002 4003 vlv_read_wm_values(dev_priv, wm); 4004 4005 for_each_intel_plane(dev, plane) { 4006 switch (plane->base.type) { 4007 int sprite; 4008 case DRM_PLANE_TYPE_CURSOR: 4009 plane->wm.fifo_size = 63; 4010 break; 4011 case DRM_PLANE_TYPE_PRIMARY: 4012 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); 4013 break; 4014 case DRM_PLANE_TYPE_OVERLAY: 4015 sprite = plane->plane; 4016 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); 4017 break; 4018 } 4019 } 4020 4021 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 4022 wm->level = VLV_WM_LEVEL_PM2; 4023 4024 if (IS_CHERRYVIEW(dev_priv)) { 4025 mutex_lock(&dev_priv->rps.hw_lock); 4026 4027 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 4028 if (val & DSP_MAXFIFO_PM5_ENABLE) 4029 wm->level = VLV_WM_LEVEL_PM5; 4030 4031 /* 4032 * If DDR DVFS is disabled in the BIOS, Punit 4033 * will never ack the request. So if that happens 4034 * assume we don't have to enable/disable DDR DVFS 4035 * dynamically. To test that just set the REQ_ACK 4036 * bit to poke the Punit, but don't change the 4037 * HIGH/LOW bits so that we don't actually change 4038 * the current state. 4039 */ 4040 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 4041 val |= FORCE_DDR_FREQ_REQ_ACK; 4042 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); 4043 4044 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & 4045 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { 4046 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " 4047 "assuming DDR DVFS is disabled\n"); 4048 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; 4049 } else { 4050 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 4051 if ((val & FORCE_DDR_HIGH_FREQ) == 0) 4052 wm->level = VLV_WM_LEVEL_DDR_DVFS; 4053 } 4054 4055 mutex_unlock(&dev_priv->rps.hw_lock); 4056 } 4057 4058 for_each_pipe(dev_priv, pipe) 4059 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", 4060 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor, 4061 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]); 4062 4063 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", 4064 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); 4065} 4066 4067void ilk_wm_get_hw_state(struct drm_device *dev) 4068{ 4069 struct drm_i915_private *dev_priv = dev->dev_private; 4070 struct ilk_wm_values *hw = &dev_priv->wm.hw; 4071 struct drm_crtc *crtc; 4072 4073 for_each_crtc(dev, crtc) 4074 ilk_pipe_wm_get_hw_state(crtc); 4075 4076 hw->wm_lp[0] = I915_READ(WM1_LP_ILK); 4077 hw->wm_lp[1] = I915_READ(WM2_LP_ILK); 4078 hw->wm_lp[2] = I915_READ(WM3_LP_ILK); 4079 4080 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); 4081 if (INTEL_INFO(dev)->gen >= 7) { 4082 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); 4083 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); 4084 } 4085 4086 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4087 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? 4088 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 4089 else if (IS_IVYBRIDGE(dev)) 4090 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? 4091 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 4092 4093 hw->enable_fbc_wm = 4094 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); 4095} 4096 4097/** 4098 * intel_update_watermarks - update FIFO watermark values based on current modes 4099 * 4100 * Calculate watermark values for the various WM regs based on current mode 4101 * and plane configuration. 4102 * 4103 * There are several cases to deal with here: 4104 * - normal (i.e. non-self-refresh) 4105 * - self-refresh (SR) mode 4106 * - lines are large relative to FIFO size (buffer can hold up to 2) 4107 * - lines are small relative to FIFO size (buffer can hold more than 2 4108 * lines), so need to account for TLB latency 4109 * 4110 * The normal calculation is: 4111 * watermark = dotclock * bytes per pixel * latency 4112 * where latency is platform & configuration dependent (we assume pessimal 4113 * values here). 4114 * 4115 * The SR calculation is: 4116 * watermark = (trunc(latency/line time)+1) * surface width * 4117 * bytes per pixel 4118 * where 4119 * line time = htotal / dotclock 4120 * surface width = hdisplay for normal plane and 64 for cursor 4121 * and latency is assumed to be high, as above. 4122 * 4123 * The final value programmed to the register should always be rounded up, 4124 * and include an extra 2 entries to account for clock crossings. 4125 * 4126 * We don't use the sprite, so we can ignore that. And on Crestline we have 4127 * to set the non-SR watermarks to 8. 4128 */ 4129void intel_update_watermarks(struct drm_crtc *crtc) 4130{ 4131 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 4132 4133 if (dev_priv->display.update_wm) 4134 dev_priv->display.update_wm(crtc); 4135} 4136 4137void intel_update_sprite_watermarks(struct drm_plane *plane, 4138 struct drm_crtc *crtc, 4139 uint32_t sprite_width, 4140 uint32_t sprite_height, 4141 int pixel_size, 4142 bool enabled, bool scaled) 4143{ 4144 struct drm_i915_private *dev_priv = plane->dev->dev_private; 4145 4146 if (dev_priv->display.update_sprite_wm) 4147 dev_priv->display.update_sprite_wm(plane, crtc, 4148 sprite_width, sprite_height, 4149 pixel_size, enabled, scaled); 4150} 4151 4152/** 4153 * Lock protecting IPS related data structures 4154 */ 4155DEFINE_SPINLOCK(mchdev_lock); 4156 4157/* Global for IPS driver to get at the current i915 device. Protected by 4158 * mchdev_lock. */ 4159static struct drm_i915_private *i915_mch_dev; 4160 4161bool ironlake_set_drps(struct drm_device *dev, u8 val) 4162{ 4163 struct drm_i915_private *dev_priv = dev->dev_private; 4164 u16 rgvswctl; 4165 4166 assert_spin_locked(&mchdev_lock); 4167 4168 rgvswctl = I915_READ16(MEMSWCTL); 4169 if (rgvswctl & MEMCTL_CMD_STS) { 4170 DRM_DEBUG("gpu busy, RCS change rejected\n"); 4171 return false; /* still busy with another command */ 4172 } 4173 4174 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 4175 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; 4176 I915_WRITE16(MEMSWCTL, rgvswctl); 4177 POSTING_READ16(MEMSWCTL); 4178 4179 rgvswctl |= MEMCTL_CMD_STS; 4180 I915_WRITE16(MEMSWCTL, rgvswctl); 4181 4182 return true; 4183} 4184 4185static void ironlake_enable_drps(struct drm_device *dev) 4186{ 4187 struct drm_i915_private *dev_priv = dev->dev_private; 4188 u32 rgvmodectl = I915_READ(MEMMODECTL); 4189 u8 fmax, fmin, fstart, vstart; 4190 4191 spin_lock_irq(&mchdev_lock); 4192 4193 /* Enable temp reporting */ 4194 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); 4195 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); 4196 4197 /* 100ms RC evaluation intervals */ 4198 I915_WRITE(RCUPEI, 100000); 4199 I915_WRITE(RCDNEI, 100000); 4200 4201 /* Set max/min thresholds to 90ms and 80ms respectively */ 4202 I915_WRITE(RCBMAXAVG, 90000); 4203 I915_WRITE(RCBMINAVG, 80000); 4204 4205 I915_WRITE(MEMIHYST, 1); 4206 4207 /* Set up min, max, and cur for interrupt handling */ 4208 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 4209 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 4210 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 4211 MEMMODE_FSTART_SHIFT; 4212 4213 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> 4214 PXVFREQ_PX_SHIFT; 4215 4216 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ 4217 dev_priv->ips.fstart = fstart; 4218 4219 dev_priv->ips.max_delay = fstart; 4220 dev_priv->ips.min_delay = fmin; 4221 dev_priv->ips.cur_delay = fstart; 4222 4223 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", 4224 fmax, fmin, fstart); 4225 4226 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 4227 4228 /* 4229 * Interrupts will be enabled in ironlake_irq_postinstall 4230 */ 4231 4232 I915_WRITE(VIDSTART, vstart); 4233 POSTING_READ(VIDSTART); 4234 4235 rgvmodectl |= MEMMODE_SWMODE_EN; 4236 I915_WRITE(MEMMODECTL, rgvmodectl); 4237 4238 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) 4239 DRM_ERROR("stuck trying to change perf mode\n"); 4240 mdelay(1); 4241 4242 ironlake_set_drps(dev, fstart); 4243 4244 dev_priv->ips.last_count1 = I915_READ(DMIEC) + 4245 I915_READ(DDREC) + I915_READ(CSIEC); 4246 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); 4247 dev_priv->ips.last_count2 = I915_READ(GFXEC); 4248 dev_priv->ips.last_time2 = ktime_get_raw_ns(); 4249 4250 spin_unlock_irq(&mchdev_lock); 4251} 4252 4253static void ironlake_disable_drps(struct drm_device *dev) 4254{ 4255 struct drm_i915_private *dev_priv = dev->dev_private; 4256 u16 rgvswctl; 4257 4258 spin_lock_irq(&mchdev_lock); 4259 4260 rgvswctl = I915_READ16(MEMSWCTL); 4261 4262 /* Ack interrupts, disable EFC interrupt */ 4263 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); 4264 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); 4265 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); 4266 I915_WRITE(DEIIR, DE_PCU_EVENT); 4267 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); 4268 4269 /* Go back to the starting frequency */ 4270 ironlake_set_drps(dev, dev_priv->ips.fstart); 4271 mdelay(1); 4272 rgvswctl |= MEMCTL_CMD_STS; 4273 I915_WRITE(MEMSWCTL, rgvswctl); 4274 mdelay(1); 4275 4276 spin_unlock_irq(&mchdev_lock); 4277} 4278 4279/* There's a funny hw issue where the hw returns all 0 when reading from 4280 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value 4281 * ourselves, instead of doing a rmw cycle (which might result in us clearing 4282 * all limits and the gpu stuck at whatever frequency it is at atm). 4283 */ 4284static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) 4285{ 4286 u32 limits; 4287 4288 /* Only set the down limit when we've reached the lowest level to avoid 4289 * getting more interrupts, otherwise leave this clear. This prevents a 4290 * race in the hw when coming out of rc6: There's a tiny window where 4291 * the hw runs at the minimal clock before selecting the desired 4292 * frequency, if the down threshold expires in that window we will not 4293 * receive a down interrupt. */ 4294 if (IS_GEN9(dev_priv->dev)) { 4295 limits = (dev_priv->rps.max_freq_softlimit) << 23; 4296 if (val <= dev_priv->rps.min_freq_softlimit) 4297 limits |= (dev_priv->rps.min_freq_softlimit) << 14; 4298 } else { 4299 limits = dev_priv->rps.max_freq_softlimit << 24; 4300 if (val <= dev_priv->rps.min_freq_softlimit) 4301 limits |= dev_priv->rps.min_freq_softlimit << 16; 4302 } 4303 4304 return limits; 4305} 4306 4307static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) 4308{ 4309 int new_power; 4310 u32 threshold_up = 0, threshold_down = 0; /* in % */ 4311 u32 ei_up = 0, ei_down = 0; 4312 4313 new_power = dev_priv->rps.power; 4314 switch (dev_priv->rps.power) { 4315 case LOW_POWER: 4316 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) 4317 new_power = BETWEEN; 4318 break; 4319 4320 case BETWEEN: 4321 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) 4322 new_power = LOW_POWER; 4323 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) 4324 new_power = HIGH_POWER; 4325 break; 4326 4327 case HIGH_POWER: 4328 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) 4329 new_power = BETWEEN; 4330 break; 4331 } 4332 /* Max/min bins are special */ 4333 if (val <= dev_priv->rps.min_freq_softlimit) 4334 new_power = LOW_POWER; 4335 if (val >= dev_priv->rps.max_freq_softlimit) 4336 new_power = HIGH_POWER; 4337 if (new_power == dev_priv->rps.power) 4338 return; 4339 4340 /* Note the units here are not exactly 1us, but 1280ns. */ 4341 switch (new_power) { 4342 case LOW_POWER: 4343 /* Upclock if more than 95% busy over 16ms */ 4344 ei_up = 16000; 4345 threshold_up = 95; 4346 4347 /* Downclock if less than 85% busy over 32ms */ 4348 ei_down = 32000; 4349 threshold_down = 85; 4350 break; 4351 4352 case BETWEEN: 4353 /* Upclock if more than 90% busy over 13ms */ 4354 ei_up = 13000; 4355 threshold_up = 90; 4356 4357 /* Downclock if less than 75% busy over 32ms */ 4358 ei_down = 32000; 4359 threshold_down = 75; 4360 break; 4361 4362 case HIGH_POWER: 4363 /* Upclock if more than 85% busy over 10ms */ 4364 ei_up = 10000; 4365 threshold_up = 85; 4366 4367 /* Downclock if less than 60% busy over 32ms */ 4368 ei_down = 32000; 4369 threshold_down = 60; 4370 break; 4371 } 4372 4373 I915_WRITE(GEN6_RP_UP_EI, 4374 GT_INTERVAL_FROM_US(dev_priv, ei_up)); 4375 I915_WRITE(GEN6_RP_UP_THRESHOLD, 4376 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100))); 4377 4378 I915_WRITE(GEN6_RP_DOWN_EI, 4379 GT_INTERVAL_FROM_US(dev_priv, ei_down)); 4380 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 4381 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100))); 4382 4383 I915_WRITE(GEN6_RP_CONTROL, 4384 GEN6_RP_MEDIA_TURBO | 4385 GEN6_RP_MEDIA_HW_NORMAL_MODE | 4386 GEN6_RP_MEDIA_IS_GFX | 4387 GEN6_RP_ENABLE | 4388 GEN6_RP_UP_BUSY_AVG | 4389 GEN6_RP_DOWN_IDLE_AVG); 4390 4391 dev_priv->rps.power = new_power; 4392 dev_priv->rps.up_threshold = threshold_up; 4393 dev_priv->rps.down_threshold = threshold_down; 4394 dev_priv->rps.last_adj = 0; 4395} 4396 4397static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) 4398{ 4399 u32 mask = 0; 4400 4401 if (val > dev_priv->rps.min_freq_softlimit) 4402 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; 4403 if (val < dev_priv->rps.max_freq_softlimit) 4404 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; 4405 4406 mask &= dev_priv->pm_rps_events; 4407 4408 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); 4409} 4410 4411/* gen6_set_rps is called to update the frequency request, but should also be 4412 * called when the range (min_delay and max_delay) is modified so that we can 4413 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ 4414static void gen6_set_rps(struct drm_device *dev, u8 val) 4415{ 4416 struct drm_i915_private *dev_priv = dev->dev_private; 4417 4418 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ 4419 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) 4420 return; 4421 4422 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4423 WARN_ON(val > dev_priv->rps.max_freq); 4424 WARN_ON(val < dev_priv->rps.min_freq); 4425 4426 /* min/max delay may still have been modified so be sure to 4427 * write the limits value. 4428 */ 4429 if (val != dev_priv->rps.cur_freq) { 4430 gen6_set_rps_thresholds(dev_priv, val); 4431 4432 if (IS_GEN9(dev)) 4433 I915_WRITE(GEN6_RPNSWREQ, 4434 GEN9_FREQUENCY(val)); 4435 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4436 I915_WRITE(GEN6_RPNSWREQ, 4437 HSW_FREQUENCY(val)); 4438 else 4439 I915_WRITE(GEN6_RPNSWREQ, 4440 GEN6_FREQUENCY(val) | 4441 GEN6_OFFSET(0) | 4442 GEN6_AGGRESSIVE_TURBO); 4443 } 4444 4445 /* Make sure we continue to get interrupts 4446 * until we hit the minimum or maximum frequencies. 4447 */ 4448 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); 4449 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 4450 4451 POSTING_READ(GEN6_RPNSWREQ); 4452 4453 dev_priv->rps.cur_freq = val; 4454 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); 4455} 4456 4457static void valleyview_set_rps(struct drm_device *dev, u8 val) 4458{ 4459 struct drm_i915_private *dev_priv = dev->dev_private; 4460 4461 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4462 WARN_ON(val > dev_priv->rps.max_freq); 4463 WARN_ON(val < dev_priv->rps.min_freq); 4464 4465 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), 4466 "Odd GPU freq value\n")) 4467 val &= ~1; 4468 4469 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 4470 4471 if (val != dev_priv->rps.cur_freq) { 4472 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); 4473 if (!IS_CHERRYVIEW(dev_priv)) 4474 gen6_set_rps_thresholds(dev_priv, val); 4475 } 4476 4477 dev_priv->rps.cur_freq = val; 4478 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); 4479} 4480 4481/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down 4482 * 4483 * * If Gfx is Idle, then 4484 * 1. Forcewake Media well. 4485 * 2. Request idle freq. 4486 * 3. Release Forcewake of Media well. 4487*/ 4488static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) 4489{ 4490 u32 val = dev_priv->rps.idle_freq; 4491 4492 if (dev_priv->rps.cur_freq <= val) 4493 return; 4494 4495 /* Wake up the media well, as that takes a lot less 4496 * power than the Render well. */ 4497 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); 4498 valleyview_set_rps(dev_priv->dev, val); 4499 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); 4500} 4501 4502void gen6_rps_busy(struct drm_i915_private *dev_priv) 4503{ 4504 mutex_lock(&dev_priv->rps.hw_lock); 4505 if (dev_priv->rps.enabled) { 4506 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) 4507 gen6_rps_reset_ei(dev_priv); 4508 I915_WRITE(GEN6_PMINTRMSK, 4509 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); 4510 } 4511 mutex_unlock(&dev_priv->rps.hw_lock); 4512} 4513 4514void gen6_rps_idle(struct drm_i915_private *dev_priv) 4515{ 4516 struct drm_device *dev = dev_priv->dev; 4517 4518 mutex_lock(&dev_priv->rps.hw_lock); 4519 if (dev_priv->rps.enabled) { 4520 if (IS_VALLEYVIEW(dev)) 4521 vlv_set_rps_idle(dev_priv); 4522 else 4523 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 4524 dev_priv->rps.last_adj = 0; 4525 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); 4526 } 4527 mutex_unlock(&dev_priv->rps.hw_lock); 4528 4529 spin_lock(&dev_priv->rps.client_lock); 4530 while (!list_empty(&dev_priv->rps.clients)) 4531 list_del_init(dev_priv->rps.clients.next); 4532 spin_unlock(&dev_priv->rps.client_lock); 4533} 4534 4535void gen6_rps_boost(struct drm_i915_private *dev_priv, 4536 struct intel_rps_client *rps, 4537 unsigned long submitted) 4538{ 4539 /* This is intentionally racy! We peek at the state here, then 4540 * validate inside the RPS worker. 4541 */ 4542 if (!(dev_priv->mm.busy && 4543 dev_priv->rps.enabled && 4544 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) 4545 return; 4546 4547 /* Force a RPS boost (and don't count it against the client) if 4548 * the GPU is severely congested. 4549 */ 4550 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) 4551 rps = NULL; 4552 4553 spin_lock(&dev_priv->rps.client_lock); 4554 if (rps == NULL || list_empty(&rps->link)) { 4555 spin_lock_irq(&dev_priv->irq_lock); 4556 if (dev_priv->rps.interrupts_enabled) { 4557 dev_priv->rps.client_boost = true; 4558 queue_work(dev_priv->wq, &dev_priv->rps.work); 4559 } 4560 spin_unlock_irq(&dev_priv->irq_lock); 4561 4562 if (rps != NULL) { 4563 list_add(&rps->link, &dev_priv->rps.clients); 4564 rps->boosts++; 4565 } else 4566 dev_priv->rps.boosts++; 4567 } 4568 spin_unlock(&dev_priv->rps.client_lock); 4569} 4570 4571void intel_set_rps(struct drm_device *dev, u8 val) 4572{ 4573 if (IS_VALLEYVIEW(dev)) 4574 valleyview_set_rps(dev, val); 4575 else 4576 gen6_set_rps(dev, val); 4577} 4578 4579static void gen9_disable_rps(struct drm_device *dev) 4580{ 4581 struct drm_i915_private *dev_priv = dev->dev_private; 4582 4583 I915_WRITE(GEN6_RC_CONTROL, 0); 4584 I915_WRITE(GEN9_PG_ENABLE, 0); 4585} 4586 4587static void gen6_disable_rps(struct drm_device *dev) 4588{ 4589 struct drm_i915_private *dev_priv = dev->dev_private; 4590 4591 I915_WRITE(GEN6_RC_CONTROL, 0); 4592 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); 4593} 4594 4595static void cherryview_disable_rps(struct drm_device *dev) 4596{ 4597 struct drm_i915_private *dev_priv = dev->dev_private; 4598 4599 I915_WRITE(GEN6_RC_CONTROL, 0); 4600} 4601 4602static void valleyview_disable_rps(struct drm_device *dev) 4603{ 4604 struct drm_i915_private *dev_priv = dev->dev_private; 4605 4606 /* we're doing forcewake before Disabling RC6, 4607 * This what the BIOS expects when going into suspend */ 4608 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4609 4610 I915_WRITE(GEN6_RC_CONTROL, 0); 4611 4612 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4613} 4614 4615static void intel_print_rc6_info(struct drm_device *dev, u32 mode) 4616{ 4617 if (IS_VALLEYVIEW(dev)) { 4618 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) 4619 mode = GEN6_RC_CTL_RC6_ENABLE; 4620 else 4621 mode = 0; 4622 } 4623 if (HAS_RC6p(dev)) 4624 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", 4625 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", 4626 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", 4627 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); 4628 4629 else 4630 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", 4631 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); 4632} 4633 4634static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) 4635{ 4636 /* No RC6 before Ironlake and code is gone for ilk. */ 4637 if (INTEL_INFO(dev)->gen < 6) 4638 return 0; 4639 4640 /* Respect the kernel parameter if it is set */ 4641 if (enable_rc6 >= 0) { 4642 int mask; 4643 4644 if (HAS_RC6p(dev)) 4645 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | 4646 INTEL_RC6pp_ENABLE; 4647 else 4648 mask = INTEL_RC6_ENABLE; 4649 4650 if ((enable_rc6 & mask) != enable_rc6) 4651 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", 4652 enable_rc6 & mask, enable_rc6, mask); 4653 4654 return enable_rc6 & mask; 4655 } 4656 4657 if (IS_IVYBRIDGE(dev)) 4658 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 4659 4660 return INTEL_RC6_ENABLE; 4661} 4662 4663int intel_enable_rc6(const struct drm_device *dev) 4664{ 4665 return i915.enable_rc6; 4666} 4667 4668static void gen6_init_rps_frequencies(struct drm_device *dev) 4669{ 4670 struct drm_i915_private *dev_priv = dev->dev_private; 4671 uint32_t rp_state_cap; 4672 u32 ddcc_status = 0; 4673 int ret; 4674 4675 /* All of these values are in units of 50MHz */ 4676 dev_priv->rps.cur_freq = 0; 4677 /* static values from HW: RP0 > RP1 > RPn (min_freq) */ 4678 if (IS_BROXTON(dev)) { 4679 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); 4680 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; 4681 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; 4682 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; 4683 } else { 4684 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 4685 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; 4686 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; 4687 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; 4688 } 4689 4690 /* hw_max = RP0 until we check for overclocking */ 4691 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; 4692 4693 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; 4694 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { 4695 ret = sandybridge_pcode_read(dev_priv, 4696 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, 4697 &ddcc_status); 4698 if (0 == ret) 4699 dev_priv->rps.efficient_freq = 4700 clamp_t(u8, 4701 ((ddcc_status >> 8) & 0xff), 4702 dev_priv->rps.min_freq, 4703 dev_priv->rps.max_freq); 4704 } 4705 4706 if (IS_SKYLAKE(dev)) { 4707 /* Store the frequency values in 16.66 MHZ units, which is 4708 the natural hardware unit for SKL */ 4709 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; 4710 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; 4711 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; 4712 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; 4713 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; 4714 } 4715 4716 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 4717 4718 /* Preserve min/max settings in case of re-init */ 4719 if (dev_priv->rps.max_freq_softlimit == 0) 4720 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 4721 4722 if (dev_priv->rps.min_freq_softlimit == 0) { 4723 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4724 dev_priv->rps.min_freq_softlimit = 4725 max_t(int, dev_priv->rps.efficient_freq, 4726 intel_freq_opcode(dev_priv, 450)); 4727 else 4728 dev_priv->rps.min_freq_softlimit = 4729 dev_priv->rps.min_freq; 4730 } 4731} 4732 4733/* See the Gen9_GT_PM_Programming_Guide doc for the below */ 4734static void gen9_enable_rps(struct drm_device *dev) 4735{ 4736 struct drm_i915_private *dev_priv = dev->dev_private; 4737 4738 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4739 4740 gen6_init_rps_frequencies(dev); 4741 4742 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ 4743 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { 4744 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4745 return; 4746 } 4747 4748 /* Program defaults and thresholds for RPS*/ 4749 I915_WRITE(GEN6_RC_VIDEO_FREQ, 4750 GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); 4751 4752 /* 1 second timeout*/ 4753 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 4754 GT_INTERVAL_FROM_US(dev_priv, 1000000)); 4755 4756 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); 4757 4758 /* Leaning on the below call to gen6_set_rps to program/setup the 4759 * Up/Down EI & threshold registers, as well as the RP_CONTROL, 4760 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ 4761 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 4762 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); 4763 4764 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4765} 4766 4767static void gen9_enable_rc6(struct drm_device *dev) 4768{ 4769 struct drm_i915_private *dev_priv = dev->dev_private; 4770 struct intel_engine_cs *ring; 4771 uint32_t rc6_mask = 0; 4772 int unused; 4773 4774 /* 1a: Software RC state - RC0 */ 4775 I915_WRITE(GEN6_RC_STATE, 0); 4776 4777 /* 1b: Get forcewake during program sequence. Although the driver 4778 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4779 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4780 4781 /* 2a: Disable RC states. */ 4782 I915_WRITE(GEN6_RC_CONTROL, 0); 4783 4784 /* 2b: Program RC6 thresholds.*/ 4785 4786 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ 4787 if (IS_SKYLAKE(dev)) 4788 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); 4789 else 4790 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); 4791 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 4792 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 4793 for_each_ring(ring, dev_priv, unused) 4794 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4795 4796 if (HAS_GUC_UCODE(dev)) 4797 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); 4798 4799 I915_WRITE(GEN6_RC_SLEEP, 0); 4800 4801 /* 2c: Program Coarse Power Gating Policies. */ 4802 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); 4803 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); 4804 4805 /* 3a: Enable RC6 */ 4806 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4807 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 4808 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 4809 "on" : "off"); 4810 /* WaRsUseTimeoutMode */ 4811 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) || 4812 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) { 4813 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ 4814 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4815 GEN7_RC_CTL_TO_MODE | 4816 rc6_mask); 4817 } else { 4818 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ 4819 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4820 GEN6_RC_CTL_EI_MODE(1) | 4821 rc6_mask); 4822 } 4823 4824 /* 4825 * 3b: Enable Coarse Power Gating only when RC6 is enabled. 4826 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. 4827 */ 4828 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || 4829 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0))) 4830 I915_WRITE(GEN9_PG_ENABLE, 0); 4831 else 4832 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 4833 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); 4834 4835 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4836 4837} 4838 4839static void gen8_enable_rps(struct drm_device *dev) 4840{ 4841 struct drm_i915_private *dev_priv = dev->dev_private; 4842 struct intel_engine_cs *ring; 4843 uint32_t rc6_mask = 0; 4844 int unused; 4845 4846 /* 1a: Software RC state - RC0 */ 4847 I915_WRITE(GEN6_RC_STATE, 0); 4848 4849 /* 1c & 1d: Get forcewake during program sequence. Although the driver 4850 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4851 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4852 4853 /* 2a: Disable RC states. */ 4854 I915_WRITE(GEN6_RC_CONTROL, 0); 4855 4856 /* Initialize rps frequencies */ 4857 gen6_init_rps_frequencies(dev); 4858 4859 /* 2b: Program RC6 thresholds.*/ 4860 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 4861 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 4862 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 4863 for_each_ring(ring, dev_priv, unused) 4864 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4865 I915_WRITE(GEN6_RC_SLEEP, 0); 4866 if (IS_BROADWELL(dev)) 4867 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ 4868 else 4869 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 4870 4871 /* 3: Enable RC6 */ 4872 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4873 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 4874 intel_print_rc6_info(dev, rc6_mask); 4875 if (IS_BROADWELL(dev)) 4876 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4877 GEN7_RC_CTL_TO_MODE | 4878 rc6_mask); 4879 else 4880 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4881 GEN6_RC_CTL_EI_MODE(1) | 4882 rc6_mask); 4883 4884 /* 4 Program defaults and thresholds for RPS*/ 4885 I915_WRITE(GEN6_RPNSWREQ, 4886 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 4887 I915_WRITE(GEN6_RC_VIDEO_FREQ, 4888 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 4889 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ 4890 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ 4891 4892 /* Docs recommend 900MHz, and 300 MHz respectively */ 4893 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 4894 dev_priv->rps.max_freq_softlimit << 24 | 4895 dev_priv->rps.min_freq_softlimit << 16); 4896 4897 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ 4898 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ 4899 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ 4900 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ 4901 4902 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 4903 4904 /* 5: Enable RPS */ 4905 I915_WRITE(GEN6_RP_CONTROL, 4906 GEN6_RP_MEDIA_TURBO | 4907 GEN6_RP_MEDIA_HW_NORMAL_MODE | 4908 GEN6_RP_MEDIA_IS_GFX | 4909 GEN6_RP_ENABLE | 4910 GEN6_RP_UP_BUSY_AVG | 4911 GEN6_RP_DOWN_IDLE_AVG); 4912 4913 /* 6: Ring frequency + overclocking (our driver does this later */ 4914 4915 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 4916 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 4917 4918 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4919} 4920 4921static void gen6_enable_rps(struct drm_device *dev) 4922{ 4923 struct drm_i915_private *dev_priv = dev->dev_private; 4924 struct intel_engine_cs *ring; 4925 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; 4926 u32 gtfifodbg; 4927 int rc6_mode; 4928 int i, ret; 4929 4930 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4931 4932 /* Here begins a magic sequence of register writes to enable 4933 * auto-downclocking. 4934 * 4935 * Perhaps there might be some value in exposing these to 4936 * userspace... 4937 */ 4938 I915_WRITE(GEN6_RC_STATE, 0); 4939 4940 /* Clear the DBG now so we don't confuse earlier errors */ 4941 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 4942 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); 4943 I915_WRITE(GTFIFODBG, gtfifodbg); 4944 } 4945 4946 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4947 4948 /* Initialize rps frequencies */ 4949 gen6_init_rps_frequencies(dev); 4950 4951 /* disable the counters and set deterministic thresholds */ 4952 I915_WRITE(GEN6_RC_CONTROL, 0); 4953 4954 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 4955 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 4956 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 4957 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 4958 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 4959 4960 for_each_ring(ring, dev_priv, i) 4961 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4962 4963 I915_WRITE(GEN6_RC_SLEEP, 0); 4964 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 4965 if (IS_IVYBRIDGE(dev)) 4966 I915_WRITE(GEN6_RC6_THRESHOLD, 125000); 4967 else 4968 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 4969 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); 4970 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 4971 4972 /* Check if we are enabling RC6 */ 4973 rc6_mode = intel_enable_rc6(dev_priv->dev); 4974 if (rc6_mode & INTEL_RC6_ENABLE) 4975 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; 4976 4977 /* We don't use those on Haswell */ 4978 if (!IS_HASWELL(dev)) { 4979 if (rc6_mode & INTEL_RC6p_ENABLE) 4980 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 4981 4982 if (rc6_mode & INTEL_RC6pp_ENABLE) 4983 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 4984 } 4985 4986 intel_print_rc6_info(dev, rc6_mask); 4987 4988 I915_WRITE(GEN6_RC_CONTROL, 4989 rc6_mask | 4990 GEN6_RC_CTL_EI_MODE(1) | 4991 GEN6_RC_CTL_HW_ENABLE); 4992 4993 /* Power down if completely idle for over 50ms */ 4994 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); 4995 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 4996 4997 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); 4998 if (ret) 4999 DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); 5000 5001 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); 5002 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ 5003 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", 5004 (dev_priv->rps.max_freq_softlimit & 0xff) * 50, 5005 (pcu_mbox & 0xff) * 50); 5006 dev_priv->rps.max_freq = pcu_mbox & 0xff; 5007 } 5008 5009 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 5010 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 5011 5012 rc6vids = 0; 5013 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 5014 if (IS_GEN6(dev) && ret) { 5015 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); 5016 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 5017 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 5018 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 5019 rc6vids &= 0xffff00; 5020 rc6vids |= GEN6_ENCODE_RC6_VID(450); 5021 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 5022 if (ret) 5023 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 5024 } 5025 5026 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5027} 5028 5029static void __gen6_update_ring_freq(struct drm_device *dev) 5030{ 5031 struct drm_i915_private *dev_priv = dev->dev_private; 5032 int min_freq = 15; 5033 unsigned int gpu_freq; 5034 unsigned int max_ia_freq, min_ring_freq; 5035 unsigned int max_gpu_freq, min_gpu_freq; 5036 int scaling_factor = 180; 5037 struct cpufreq_policy *policy; 5038 5039 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5040 5041 policy = cpufreq_cpu_get(0); 5042 if (policy) { 5043 max_ia_freq = policy->cpuinfo.max_freq; 5044 cpufreq_cpu_put(policy); 5045 } else { 5046 /* 5047 * Default to measured freq if none found, PCU will ensure we 5048 * don't go over 5049 */ 5050 max_ia_freq = tsc_khz; 5051 } 5052 5053 /* Convert from kHz to MHz */ 5054 max_ia_freq /= 1000; 5055 5056 min_ring_freq = I915_READ(DCLK) & 0xf; 5057 /* convert DDR frequency from units of 266.6MHz to bandwidth */ 5058 min_ring_freq = mult_frac(min_ring_freq, 8, 3); 5059 5060 if (IS_SKYLAKE(dev)) { 5061 /* Convert GT frequency to 50 HZ units */ 5062 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; 5063 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; 5064 } else { 5065 min_gpu_freq = dev_priv->rps.min_freq; 5066 max_gpu_freq = dev_priv->rps.max_freq; 5067 } 5068 5069 /* 5070 * For each potential GPU frequency, load a ring frequency we'd like 5071 * to use for memory access. We do this by specifying the IA frequency 5072 * the PCU should use as a reference to determine the ring frequency. 5073 */ 5074 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { 5075 int diff = max_gpu_freq - gpu_freq; 5076 unsigned int ia_freq = 0, ring_freq = 0; 5077 5078 if (IS_SKYLAKE(dev)) { 5079 /* 5080 * ring_freq = 2 * GT. ring_freq is in 100MHz units 5081 * No floor required for ring frequency on SKL. 5082 */ 5083 ring_freq = gpu_freq; 5084 } else if (INTEL_INFO(dev)->gen >= 8) { 5085 /* max(2 * GT, DDR). NB: GT is 50MHz units */ 5086 ring_freq = max(min_ring_freq, gpu_freq); 5087 } else if (IS_HASWELL(dev)) { 5088 ring_freq = mult_frac(gpu_freq, 5, 4); 5089 ring_freq = max(min_ring_freq, ring_freq); 5090 /* leave ia_freq as the default, chosen by cpufreq */ 5091 } else { 5092 /* On older processors, there is no separate ring 5093 * clock domain, so in order to boost the bandwidth 5094 * of the ring, we need to upclock the CPU (ia_freq). 5095 * 5096 * For GPU frequencies less than 750MHz, 5097 * just use the lowest ring freq. 5098 */ 5099 if (gpu_freq < min_freq) 5100 ia_freq = 800; 5101 else 5102 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); 5103 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 5104 } 5105 5106 sandybridge_pcode_write(dev_priv, 5107 GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 5108 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | 5109 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | 5110 gpu_freq); 5111 } 5112} 5113 5114void gen6_update_ring_freq(struct drm_device *dev) 5115{ 5116 struct drm_i915_private *dev_priv = dev->dev_private; 5117 5118 if (!HAS_CORE_RING_FREQ(dev)) 5119 return; 5120 5121 mutex_lock(&dev_priv->rps.hw_lock); 5122 __gen6_update_ring_freq(dev); 5123 mutex_unlock(&dev_priv->rps.hw_lock); 5124} 5125 5126static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) 5127{ 5128 struct drm_device *dev = dev_priv->dev; 5129 u32 val, rp0; 5130 5131 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); 5132 5133 switch (INTEL_INFO(dev)->eu_total) { 5134 case 8: 5135 /* (2 * 4) config */ 5136 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); 5137 break; 5138 case 12: 5139 /* (2 * 6) config */ 5140 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); 5141 break; 5142 case 16: 5143 /* (2 * 8) config */ 5144 default: 5145 /* Setting (2 * 8) Min RP0 for any other combination */ 5146 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); 5147 break; 5148 } 5149 5150 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); 5151 5152 return rp0; 5153} 5154 5155static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) 5156{ 5157 u32 val, rpe; 5158 5159 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); 5160 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; 5161 5162 return rpe; 5163} 5164 5165static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) 5166{ 5167 u32 val, rp1; 5168 5169 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); 5170 rp1 = (val & FB_GFX_FREQ_FUSE_MASK); 5171 5172 return rp1; 5173} 5174 5175static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) 5176{ 5177 u32 val, rp1; 5178 5179 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); 5180 5181 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; 5182 5183 return rp1; 5184} 5185 5186static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) 5187{ 5188 u32 val, rp0; 5189 5190 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); 5191 5192 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; 5193 /* Clamp to max */ 5194 rp0 = min_t(u32, rp0, 0xea); 5195 5196 return rp0; 5197} 5198 5199static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) 5200{ 5201 u32 val, rpe; 5202 5203 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); 5204 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; 5205 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); 5206 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; 5207 5208 return rpe; 5209} 5210 5211static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) 5212{ 5213 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; 5214} 5215 5216/* Check that the pctx buffer wasn't move under us. */ 5217static void valleyview_check_pctx(struct drm_i915_private *dev_priv) 5218{ 5219 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; 5220 5221 WARN_ON(pctx_addr != dev_priv->mm.stolen_base + 5222 dev_priv->vlv_pctx->stolen->start); 5223} 5224 5225 5226/* Check that the pcbr address is not empty. */ 5227static void cherryview_check_pctx(struct drm_i915_private *dev_priv) 5228{ 5229 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; 5230 5231 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); 5232} 5233 5234static void cherryview_setup_pctx(struct drm_device *dev) 5235{ 5236 struct drm_i915_private *dev_priv = dev->dev_private; 5237 unsigned long pctx_paddr, paddr; 5238 struct i915_gtt *gtt = &dev_priv->gtt; 5239 u32 pcbr; 5240 int pctx_size = 32*1024; 5241 5242 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 5243 5244 pcbr = I915_READ(VLV_PCBR); 5245 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { 5246 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 5247 paddr = (dev_priv->mm.stolen_base + 5248 (gtt->stolen_size - pctx_size)); 5249 5250 pctx_paddr = (paddr & (~4095)); 5251 I915_WRITE(VLV_PCBR, pctx_paddr); 5252 } 5253 5254 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); 5255} 5256 5257static void valleyview_setup_pctx(struct drm_device *dev) 5258{ 5259 struct drm_i915_private *dev_priv = dev->dev_private; 5260 struct drm_i915_gem_object *pctx; 5261 unsigned long pctx_paddr; 5262 u32 pcbr; 5263 int pctx_size = 24*1024; 5264 5265 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 5266 5267 pcbr = I915_READ(VLV_PCBR); 5268 if (pcbr) { 5269 /* BIOS set it up already, grab the pre-alloc'd space */ 5270 int pcbr_offset; 5271 5272 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; 5273 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, 5274 pcbr_offset, 5275 I915_GTT_OFFSET_NONE, 5276 pctx_size); 5277 goto out; 5278 } 5279 5280 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 5281 5282 /* 5283 * From the Gunit register HAS: 5284 * The Gfx driver is expected to program this register and ensure 5285 * proper allocation within Gfx stolen memory. For example, this 5286 * register should be programmed such than the PCBR range does not 5287 * overlap with other ranges, such as the frame buffer, protected 5288 * memory, or any other relevant ranges. 5289 */ 5290 pctx = i915_gem_object_create_stolen(dev, pctx_size); 5291 if (!pctx) { 5292 DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); 5293 return; 5294 } 5295 5296 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; 5297 I915_WRITE(VLV_PCBR, pctx_paddr); 5298 5299out: 5300 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); 5301 dev_priv->vlv_pctx = pctx; 5302} 5303 5304static void valleyview_cleanup_pctx(struct drm_device *dev) 5305{ 5306 struct drm_i915_private *dev_priv = dev->dev_private; 5307 5308 if (WARN_ON(!dev_priv->vlv_pctx)) 5309 return; 5310 5311 drm_gem_object_unreference(&dev_priv->vlv_pctx->base); 5312 dev_priv->vlv_pctx = NULL; 5313} 5314 5315static void valleyview_init_gt_powersave(struct drm_device *dev) 5316{ 5317 struct drm_i915_private *dev_priv = dev->dev_private; 5318 u32 val; 5319 5320 valleyview_setup_pctx(dev); 5321 5322 mutex_lock(&dev_priv->rps.hw_lock); 5323 5324 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5325 switch ((val >> 6) & 3) { 5326 case 0: 5327 case 1: 5328 dev_priv->mem_freq = 800; 5329 break; 5330 case 2: 5331 dev_priv->mem_freq = 1066; 5332 break; 5333 case 3: 5334 dev_priv->mem_freq = 1333; 5335 break; 5336 } 5337 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); 5338 5339 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); 5340 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 5341 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 5342 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), 5343 dev_priv->rps.max_freq); 5344 5345 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); 5346 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 5347 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5348 dev_priv->rps.efficient_freq); 5349 5350 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); 5351 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", 5352 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 5353 dev_priv->rps.rp1_freq); 5354 5355 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); 5356 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 5357 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 5358 dev_priv->rps.min_freq); 5359 5360 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 5361 5362 /* Preserve min/max settings in case of re-init */ 5363 if (dev_priv->rps.max_freq_softlimit == 0) 5364 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 5365 5366 if (dev_priv->rps.min_freq_softlimit == 0) 5367 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 5368 5369 mutex_unlock(&dev_priv->rps.hw_lock); 5370} 5371 5372static void cherryview_init_gt_powersave(struct drm_device *dev) 5373{ 5374 struct drm_i915_private *dev_priv = dev->dev_private; 5375 u32 val; 5376 5377 cherryview_setup_pctx(dev); 5378 5379 mutex_lock(&dev_priv->rps.hw_lock); 5380 5381 mutex_lock(&dev_priv->sb_lock); 5382 val = vlv_cck_read(dev_priv, CCK_FUSE_REG); 5383 mutex_unlock(&dev_priv->sb_lock); 5384 5385 switch ((val >> 2) & 0x7) { 5386 case 3: 5387 dev_priv->mem_freq = 2000; 5388 break; 5389 default: 5390 dev_priv->mem_freq = 1600; 5391 break; 5392 } 5393 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); 5394 5395 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); 5396 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 5397 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 5398 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), 5399 dev_priv->rps.max_freq); 5400 5401 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); 5402 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 5403 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5404 dev_priv->rps.efficient_freq); 5405 5406 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); 5407 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", 5408 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 5409 dev_priv->rps.rp1_freq); 5410 5411 /* PUnit validated range is only [RPe, RP0] */ 5412 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; 5413 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 5414 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 5415 dev_priv->rps.min_freq); 5416 5417 WARN_ONCE((dev_priv->rps.max_freq | 5418 dev_priv->rps.efficient_freq | 5419 dev_priv->rps.rp1_freq | 5420 dev_priv->rps.min_freq) & 1, 5421 "Odd GPU freq values\n"); 5422 5423 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 5424 5425 /* Preserve min/max settings in case of re-init */ 5426 if (dev_priv->rps.max_freq_softlimit == 0) 5427 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 5428 5429 if (dev_priv->rps.min_freq_softlimit == 0) 5430 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 5431 5432 mutex_unlock(&dev_priv->rps.hw_lock); 5433} 5434 5435static void valleyview_cleanup_gt_powersave(struct drm_device *dev) 5436{ 5437 valleyview_cleanup_pctx(dev); 5438} 5439 5440static void cherryview_enable_rps(struct drm_device *dev) 5441{ 5442 struct drm_i915_private *dev_priv = dev->dev_private; 5443 struct intel_engine_cs *ring; 5444 u32 gtfifodbg, val, rc6_mode = 0, pcbr; 5445 int i; 5446 5447 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5448 5449 gtfifodbg = I915_READ(GTFIFODBG); 5450 if (gtfifodbg) { 5451 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 5452 gtfifodbg); 5453 I915_WRITE(GTFIFODBG, gtfifodbg); 5454 } 5455 5456 cherryview_check_pctx(dev_priv); 5457 5458 /* 1a & 1b: Get forcewake during program sequence. Although the driver 5459 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 5460 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5461 5462 /* Disable RC states. */ 5463 I915_WRITE(GEN6_RC_CONTROL, 0); 5464 5465 /* 2a: Program RC6 thresholds.*/ 5466 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 5467 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 5468 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 5469 5470 for_each_ring(ring, dev_priv, i) 5471 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5472 I915_WRITE(GEN6_RC_SLEEP, 0); 5473 5474 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ 5475 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); 5476 5477 /* allows RC6 residency counter to work */ 5478 I915_WRITE(VLV_COUNTER_CONTROL, 5479 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 5480 VLV_MEDIA_RC6_COUNT_EN | 5481 VLV_RENDER_RC6_COUNT_EN)); 5482 5483 /* For now we assume BIOS is allocating and populating the PCBR */ 5484 pcbr = I915_READ(VLV_PCBR); 5485 5486 /* 3: Enable RC6 */ 5487 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && 5488 (pcbr >> VLV_PCBR_ADDR_SHIFT)) 5489 rc6_mode = GEN7_RC_CTL_TO_MODE; 5490 5491 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 5492 5493 /* 4 Program defaults and thresholds for RPS*/ 5494 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 5495 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 5496 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 5497 I915_WRITE(GEN6_RP_UP_EI, 66000); 5498 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 5499 5500 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5501 5502 /* 5: Enable RPS */ 5503 I915_WRITE(GEN6_RP_CONTROL, 5504 GEN6_RP_MEDIA_HW_NORMAL_MODE | 5505 GEN6_RP_MEDIA_IS_GFX | 5506 GEN6_RP_ENABLE | 5507 GEN6_RP_UP_BUSY_AVG | 5508 GEN6_RP_DOWN_IDLE_AVG); 5509 5510 /* Setting Fixed Bias */ 5511 val = VLV_OVERRIDE_EN | 5512 VLV_SOC_TDP_EN | 5513 CHV_BIAS_CPU_50_SOC_50; 5514 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); 5515 5516 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5517 5518 /* RPS code assumes GPLL is used */ 5519 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); 5520 5521 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); 5522 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 5523 5524 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 5525 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 5526 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 5527 dev_priv->rps.cur_freq); 5528 5529 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 5530 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5531 dev_priv->rps.efficient_freq); 5532 5533 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 5534 5535 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5536} 5537 5538static void valleyview_enable_rps(struct drm_device *dev) 5539{ 5540 struct drm_i915_private *dev_priv = dev->dev_private; 5541 struct intel_engine_cs *ring; 5542 u32 gtfifodbg, val, rc6_mode = 0; 5543 int i; 5544 5545 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5546 5547 valleyview_check_pctx(dev_priv); 5548 5549 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 5550 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 5551 gtfifodbg); 5552 I915_WRITE(GTFIFODBG, gtfifodbg); 5553 } 5554 5555 /* If VLV, Forcewake all wells, else re-direct to regular path */ 5556 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5557 5558 /* Disable RC states. */ 5559 I915_WRITE(GEN6_RC_CONTROL, 0); 5560 5561 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 5562 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 5563 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 5564 I915_WRITE(GEN6_RP_UP_EI, 66000); 5565 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 5566 5567 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5568 5569 I915_WRITE(GEN6_RP_CONTROL, 5570 GEN6_RP_MEDIA_TURBO | 5571 GEN6_RP_MEDIA_HW_NORMAL_MODE | 5572 GEN6_RP_MEDIA_IS_GFX | 5573 GEN6_RP_ENABLE | 5574 GEN6_RP_UP_BUSY_AVG | 5575 GEN6_RP_DOWN_IDLE_CONT); 5576 5577 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); 5578 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 5579 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 5580 5581 for_each_ring(ring, dev_priv, i) 5582 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5583 5584 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); 5585 5586 /* allows RC6 residency counter to work */ 5587 I915_WRITE(VLV_COUNTER_CONTROL, 5588 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | 5589 VLV_RENDER_RC0_COUNT_EN | 5590 VLV_MEDIA_RC6_COUNT_EN | 5591 VLV_RENDER_RC6_COUNT_EN)); 5592 5593 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 5594 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; 5595 5596 intel_print_rc6_info(dev, rc6_mode); 5597 5598 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 5599 5600 /* Setting Fixed Bias */ 5601 val = VLV_OVERRIDE_EN | 5602 VLV_SOC_TDP_EN | 5603 VLV_BIAS_CPU_125_SOC_875; 5604 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); 5605 5606 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5607 5608 /* RPS code assumes GPLL is used */ 5609 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); 5610 5611 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); 5612 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 5613 5614 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 5615 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 5616 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 5617 dev_priv->rps.cur_freq); 5618 5619 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 5620 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5621 dev_priv->rps.efficient_freq); 5622 5623 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 5624 5625 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5626} 5627 5628static unsigned long intel_pxfreq(u32 vidfreq) 5629{ 5630 unsigned long freq; 5631 int div = (vidfreq & 0x3f0000) >> 16; 5632 int post = (vidfreq & 0x3000) >> 12; 5633 int pre = (vidfreq & 0x7); 5634 5635 if (!pre) 5636 return 0; 5637 5638 freq = ((div * 133333) / ((1<<post) * pre)); 5639 5640 return freq; 5641} 5642 5643static const struct cparams { 5644 u16 i; 5645 u16 t; 5646 u16 m; 5647 u16 c; 5648} cparams[] = { 5649 { 1, 1333, 301, 28664 }, 5650 { 1, 1066, 294, 24460 }, 5651 { 1, 800, 294, 25192 }, 5652 { 0, 1333, 276, 27605 }, 5653 { 0, 1066, 276, 27605 }, 5654 { 0, 800, 231, 23784 }, 5655}; 5656 5657static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) 5658{ 5659 u64 total_count, diff, ret; 5660 u32 count1, count2, count3, m = 0, c = 0; 5661 unsigned long now = jiffies_to_msecs(jiffies), diff1; 5662 int i; 5663 5664 assert_spin_locked(&mchdev_lock); 5665 5666 diff1 = now - dev_priv->ips.last_time1; 5667 5668 /* Prevent division-by-zero if we are asking too fast. 5669 * Also, we don't get interesting results if we are polling 5670 * faster than once in 10ms, so just return the saved value 5671 * in such cases. 5672 */ 5673 if (diff1 <= 10) 5674 return dev_priv->ips.chipset_power; 5675 5676 count1 = I915_READ(DMIEC); 5677 count2 = I915_READ(DDREC); 5678 count3 = I915_READ(CSIEC); 5679 5680 total_count = count1 + count2 + count3; 5681 5682 /* FIXME: handle per-counter overflow */ 5683 if (total_count < dev_priv->ips.last_count1) { 5684 diff = ~0UL - dev_priv->ips.last_count1; 5685 diff += total_count; 5686 } else { 5687 diff = total_count - dev_priv->ips.last_count1; 5688 } 5689 5690 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 5691 if (cparams[i].i == dev_priv->ips.c_m && 5692 cparams[i].t == dev_priv->ips.r_t) { 5693 m = cparams[i].m; 5694 c = cparams[i].c; 5695 break; 5696 } 5697 } 5698 5699 diff = div_u64(diff, diff1); 5700 ret = ((m * diff) + c); 5701 ret = div_u64(ret, 10); 5702 5703 dev_priv->ips.last_count1 = total_count; 5704 dev_priv->ips.last_time1 = now; 5705 5706 dev_priv->ips.chipset_power = ret; 5707 5708 return ret; 5709} 5710 5711unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 5712{ 5713 struct drm_device *dev = dev_priv->dev; 5714 unsigned long val; 5715 5716 if (INTEL_INFO(dev)->gen != 5) 5717 return 0; 5718 5719 spin_lock_irq(&mchdev_lock); 5720 5721 val = __i915_chipset_val(dev_priv); 5722 5723 spin_unlock_irq(&mchdev_lock); 5724 5725 return val; 5726} 5727 5728unsigned long i915_mch_val(struct drm_i915_private *dev_priv) 5729{ 5730 unsigned long m, x, b; 5731 u32 tsfs; 5732 5733 tsfs = I915_READ(TSFS); 5734 5735 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 5736 x = I915_READ8(TR1); 5737 5738 b = tsfs & TSFS_INTR_MASK; 5739 5740 return ((m * x) / 127) - b; 5741} 5742 5743static int _pxvid_to_vd(u8 pxvid) 5744{ 5745 if (pxvid == 0) 5746 return 0; 5747 5748 if (pxvid >= 8 && pxvid < 31) 5749 pxvid = 31; 5750 5751 return (pxvid + 2) * 125; 5752} 5753 5754static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 5755{ 5756 struct drm_device *dev = dev_priv->dev; 5757 const int vd = _pxvid_to_vd(pxvid); 5758 const int vm = vd - 1125; 5759 5760 if (INTEL_INFO(dev)->is_mobile) 5761 return vm > 0 ? vm : 0; 5762 5763 return vd; 5764} 5765 5766static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) 5767{ 5768 u64 now, diff, diffms; 5769 u32 count; 5770 5771 assert_spin_locked(&mchdev_lock); 5772 5773 now = ktime_get_raw_ns(); 5774 diffms = now - dev_priv->ips.last_time2; 5775 do_div(diffms, NSEC_PER_MSEC); 5776 5777 /* Don't divide by 0 */ 5778 if (!diffms) 5779 return; 5780 5781 count = I915_READ(GFXEC); 5782 5783 if (count < dev_priv->ips.last_count2) { 5784 diff = ~0UL - dev_priv->ips.last_count2; 5785 diff += count; 5786 } else { 5787 diff = count - dev_priv->ips.last_count2; 5788 } 5789 5790 dev_priv->ips.last_count2 = count; 5791 dev_priv->ips.last_time2 = now; 5792 5793 /* More magic constants... */ 5794 diff = diff * 1181; 5795 diff = div_u64(diff, diffms * 10); 5796 dev_priv->ips.gfx_power = diff; 5797} 5798 5799void i915_update_gfx_val(struct drm_i915_private *dev_priv) 5800{ 5801 struct drm_device *dev = dev_priv->dev; 5802 5803 if (INTEL_INFO(dev)->gen != 5) 5804 return; 5805 5806 spin_lock_irq(&mchdev_lock); 5807 5808 __i915_update_gfx_val(dev_priv); 5809 5810 spin_unlock_irq(&mchdev_lock); 5811} 5812 5813static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) 5814{ 5815 unsigned long t, corr, state1, corr2, state2; 5816 u32 pxvid, ext_v; 5817 5818 assert_spin_locked(&mchdev_lock); 5819 5820 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); 5821 pxvid = (pxvid >> 24) & 0x7f; 5822 ext_v = pvid_to_extvid(dev_priv, pxvid); 5823 5824 state1 = ext_v; 5825 5826 t = i915_mch_val(dev_priv); 5827 5828 /* Revel in the empirically derived constants */ 5829 5830 /* Correction factor in 1/100000 units */ 5831 if (t > 80) 5832 corr = ((t * 2349) + 135940); 5833 else if (t >= 50) 5834 corr = ((t * 964) + 29317); 5835 else /* < 50 */ 5836 corr = ((t * 301) + 1004); 5837 5838 corr = corr * ((150142 * state1) / 10000 - 78642); 5839 corr /= 100000; 5840 corr2 = (corr * dev_priv->ips.corr); 5841 5842 state2 = (corr2 * state1) / 10000; 5843 state2 /= 100; /* convert to mW */ 5844 5845 __i915_update_gfx_val(dev_priv); 5846 5847 return dev_priv->ips.gfx_power + state2; 5848} 5849 5850unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 5851{ 5852 struct drm_device *dev = dev_priv->dev; 5853 unsigned long val; 5854 5855 if (INTEL_INFO(dev)->gen != 5) 5856 return 0; 5857 5858 spin_lock_irq(&mchdev_lock); 5859 5860 val = __i915_gfx_val(dev_priv); 5861 5862 spin_unlock_irq(&mchdev_lock); 5863 5864 return val; 5865} 5866 5867/** 5868 * i915_read_mch_val - return value for IPS use 5869 * 5870 * Calculate and return a value for the IPS driver to use when deciding whether 5871 * we have thermal and power headroom to increase CPU or GPU power budget. 5872 */ 5873unsigned long i915_read_mch_val(void) 5874{ 5875 struct drm_i915_private *dev_priv; 5876 unsigned long chipset_val, graphics_val, ret = 0; 5877 5878 spin_lock_irq(&mchdev_lock); 5879 if (!i915_mch_dev) 5880 goto out_unlock; 5881 dev_priv = i915_mch_dev; 5882 5883 chipset_val = __i915_chipset_val(dev_priv); 5884 graphics_val = __i915_gfx_val(dev_priv); 5885 5886 ret = chipset_val + graphics_val; 5887 5888out_unlock: 5889 spin_unlock_irq(&mchdev_lock); 5890 5891 return ret; 5892} 5893EXPORT_SYMBOL_GPL(i915_read_mch_val); 5894 5895/** 5896 * i915_gpu_raise - raise GPU frequency limit 5897 * 5898 * Raise the limit; IPS indicates we have thermal headroom. 5899 */ 5900bool i915_gpu_raise(void) 5901{ 5902 struct drm_i915_private *dev_priv; 5903 bool ret = true; 5904 5905 spin_lock_irq(&mchdev_lock); 5906 if (!i915_mch_dev) { 5907 ret = false; 5908 goto out_unlock; 5909 } 5910 dev_priv = i915_mch_dev; 5911 5912 if (dev_priv->ips.max_delay > dev_priv->ips.fmax) 5913 dev_priv->ips.max_delay--; 5914 5915out_unlock: 5916 spin_unlock_irq(&mchdev_lock); 5917 5918 return ret; 5919} 5920EXPORT_SYMBOL_GPL(i915_gpu_raise); 5921 5922/** 5923 * i915_gpu_lower - lower GPU frequency limit 5924 * 5925 * IPS indicates we're close to a thermal limit, so throttle back the GPU 5926 * frequency maximum. 5927 */ 5928bool i915_gpu_lower(void) 5929{ 5930 struct drm_i915_private *dev_priv; 5931 bool ret = true; 5932 5933 spin_lock_irq(&mchdev_lock); 5934 if (!i915_mch_dev) { 5935 ret = false; 5936 goto out_unlock; 5937 } 5938 dev_priv = i915_mch_dev; 5939 5940 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) 5941 dev_priv->ips.max_delay++; 5942 5943out_unlock: 5944 spin_unlock_irq(&mchdev_lock); 5945 5946 return ret; 5947} 5948EXPORT_SYMBOL_GPL(i915_gpu_lower); 5949 5950/** 5951 * i915_gpu_busy - indicate GPU business to IPS 5952 * 5953 * Tell the IPS driver whether or not the GPU is busy. 5954 */ 5955bool i915_gpu_busy(void) 5956{ 5957 struct drm_i915_private *dev_priv; 5958 struct intel_engine_cs *ring; 5959 bool ret = false; 5960 int i; 5961 5962 spin_lock_irq(&mchdev_lock); 5963 if (!i915_mch_dev) 5964 goto out_unlock; 5965 dev_priv = i915_mch_dev; 5966 5967 for_each_ring(ring, dev_priv, i) 5968 ret |= !list_empty(&ring->request_list); 5969 5970out_unlock: 5971 spin_unlock_irq(&mchdev_lock); 5972 5973 return ret; 5974} 5975EXPORT_SYMBOL_GPL(i915_gpu_busy); 5976 5977/** 5978 * i915_gpu_turbo_disable - disable graphics turbo 5979 * 5980 * Disable graphics turbo by resetting the max frequency and setting the 5981 * current frequency to the default. 5982 */ 5983bool i915_gpu_turbo_disable(void) 5984{ 5985 struct drm_i915_private *dev_priv; 5986 bool ret = true; 5987 5988 spin_lock_irq(&mchdev_lock); 5989 if (!i915_mch_dev) { 5990 ret = false; 5991 goto out_unlock; 5992 } 5993 dev_priv = i915_mch_dev; 5994 5995 dev_priv->ips.max_delay = dev_priv->ips.fstart; 5996 5997 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) 5998 ret = false; 5999 6000out_unlock: 6001 spin_unlock_irq(&mchdev_lock); 6002 6003 return ret; 6004} 6005EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); 6006 6007/** 6008 * Tells the intel_ips driver that the i915 driver is now loaded, if 6009 * IPS got loaded first. 6010 * 6011 * This awkward dance is so that neither module has to depend on the 6012 * other in order for IPS to do the appropriate communication of 6013 * GPU turbo limits to i915. 6014 */ 6015static void 6016ips_ping_for_i915_load(void) 6017{ 6018 void (*link)(void); 6019 6020 link = symbol_get(ips_link_to_i915_driver); 6021 if (link) { 6022 link(); 6023 symbol_put(ips_link_to_i915_driver); 6024 } 6025} 6026 6027void intel_gpu_ips_init(struct drm_i915_private *dev_priv) 6028{ 6029 /* We only register the i915 ips part with intel-ips once everything is 6030 * set up, to avoid intel-ips sneaking in and reading bogus values. */ 6031 spin_lock_irq(&mchdev_lock); 6032 i915_mch_dev = dev_priv; 6033 spin_unlock_irq(&mchdev_lock); 6034 6035 ips_ping_for_i915_load(); 6036} 6037 6038void intel_gpu_ips_teardown(void) 6039{ 6040 spin_lock_irq(&mchdev_lock); 6041 i915_mch_dev = NULL; 6042 spin_unlock_irq(&mchdev_lock); 6043} 6044 6045static void intel_init_emon(struct drm_device *dev) 6046{ 6047 struct drm_i915_private *dev_priv = dev->dev_private; 6048 u32 lcfuse; 6049 u8 pxw[16]; 6050 int i; 6051 6052 /* Disable to program */ 6053 I915_WRITE(ECR, 0); 6054 POSTING_READ(ECR); 6055 6056 /* Program energy weights for various events */ 6057 I915_WRITE(SDEW, 0x15040d00); 6058 I915_WRITE(CSIEW0, 0x007f0000); 6059 I915_WRITE(CSIEW1, 0x1e220004); 6060 I915_WRITE(CSIEW2, 0x04000004); 6061 6062 for (i = 0; i < 5; i++) 6063 I915_WRITE(PEW(i), 0); 6064 for (i = 0; i < 3; i++) 6065 I915_WRITE(DEW(i), 0); 6066 6067 /* Program P-state weights to account for frequency power adjustment */ 6068 for (i = 0; i < 16; i++) { 6069 u32 pxvidfreq = I915_READ(PXVFREQ(i)); 6070 unsigned long freq = intel_pxfreq(pxvidfreq); 6071 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> 6072 PXVFREQ_PX_SHIFT; 6073 unsigned long val; 6074 6075 val = vid * vid; 6076 val *= (freq / 1000); 6077 val *= 255; 6078 val /= (127*127*900); 6079 if (val > 0xff) 6080 DRM_ERROR("bad pxval: %ld\n", val); 6081 pxw[i] = val; 6082 } 6083 /* Render standby states get 0 weight */ 6084 pxw[14] = 0; 6085 pxw[15] = 0; 6086 6087 for (i = 0; i < 4; i++) { 6088 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | 6089 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); 6090 I915_WRITE(PXW(i), val); 6091 } 6092 6093 /* Adjust magic regs to magic values (more experimental results) */ 6094 I915_WRITE(OGW0, 0); 6095 I915_WRITE(OGW1, 0); 6096 I915_WRITE(EG0, 0x00007f00); 6097 I915_WRITE(EG1, 0x0000000e); 6098 I915_WRITE(EG2, 0x000e0000); 6099 I915_WRITE(EG3, 0x68000300); 6100 I915_WRITE(EG4, 0x42000000); 6101 I915_WRITE(EG5, 0x00140031); 6102 I915_WRITE(EG6, 0); 6103 I915_WRITE(EG7, 0); 6104 6105 for (i = 0; i < 8; i++) 6106 I915_WRITE(PXWL(i), 0); 6107 6108 /* Enable PMON + select events */ 6109 I915_WRITE(ECR, 0x80000019); 6110 6111 lcfuse = I915_READ(LCFUSE02); 6112 6113 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); 6114} 6115 6116void intel_init_gt_powersave(struct drm_device *dev) 6117{ 6118 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); 6119 6120 if (IS_CHERRYVIEW(dev)) 6121 cherryview_init_gt_powersave(dev); 6122 else if (IS_VALLEYVIEW(dev)) 6123 valleyview_init_gt_powersave(dev); 6124} 6125 6126void intel_cleanup_gt_powersave(struct drm_device *dev) 6127{ 6128 if (IS_CHERRYVIEW(dev)) 6129 return; 6130 else if (IS_VALLEYVIEW(dev)) 6131 valleyview_cleanup_gt_powersave(dev); 6132} 6133 6134static void gen6_suspend_rps(struct drm_device *dev) 6135{ 6136 struct drm_i915_private *dev_priv = dev->dev_private; 6137 6138 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 6139 6140 gen6_disable_rps_interrupts(dev); 6141} 6142 6143/** 6144 * intel_suspend_gt_powersave - suspend PM work and helper threads 6145 * @dev: drm device 6146 * 6147 * We don't want to disable RC6 or other features here, we just want 6148 * to make sure any work we've queued has finished and won't bother 6149 * us while we're suspended. 6150 */ 6151void intel_suspend_gt_powersave(struct drm_device *dev) 6152{ 6153 struct drm_i915_private *dev_priv = dev->dev_private; 6154 6155 if (INTEL_INFO(dev)->gen < 6) 6156 return; 6157 6158 gen6_suspend_rps(dev); 6159 6160 /* Force GPU to min freq during suspend */ 6161 gen6_rps_idle(dev_priv); 6162} 6163 6164void intel_disable_gt_powersave(struct drm_device *dev) 6165{ 6166 struct drm_i915_private *dev_priv = dev->dev_private; 6167 6168 if (IS_IRONLAKE_M(dev)) { 6169 ironlake_disable_drps(dev); 6170 } else if (INTEL_INFO(dev)->gen >= 6) { 6171 intel_suspend_gt_powersave(dev); 6172 6173 mutex_lock(&dev_priv->rps.hw_lock); 6174 if (INTEL_INFO(dev)->gen >= 9) 6175 gen9_disable_rps(dev); 6176 else if (IS_CHERRYVIEW(dev)) 6177 cherryview_disable_rps(dev); 6178 else if (IS_VALLEYVIEW(dev)) 6179 valleyview_disable_rps(dev); 6180 else 6181 gen6_disable_rps(dev); 6182 6183 dev_priv->rps.enabled = false; 6184 mutex_unlock(&dev_priv->rps.hw_lock); 6185 } 6186} 6187 6188static void intel_gen6_powersave_work(struct work_struct *work) 6189{ 6190 struct drm_i915_private *dev_priv = 6191 container_of(work, struct drm_i915_private, 6192 rps.delayed_resume_work.work); 6193 struct drm_device *dev = dev_priv->dev; 6194 6195 mutex_lock(&dev_priv->rps.hw_lock); 6196 6197 gen6_reset_rps_interrupts(dev); 6198 6199 if (IS_CHERRYVIEW(dev)) { 6200 cherryview_enable_rps(dev); 6201 } else if (IS_VALLEYVIEW(dev)) { 6202 valleyview_enable_rps(dev); 6203 } else if (INTEL_INFO(dev)->gen >= 9) { 6204 gen9_enable_rc6(dev); 6205 gen9_enable_rps(dev); 6206 if (IS_SKYLAKE(dev)) 6207 __gen6_update_ring_freq(dev); 6208 } else if (IS_BROADWELL(dev)) { 6209 gen8_enable_rps(dev); 6210 __gen6_update_ring_freq(dev); 6211 } else { 6212 gen6_enable_rps(dev); 6213 __gen6_update_ring_freq(dev); 6214 } 6215 6216 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); 6217 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); 6218 6219 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); 6220 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); 6221 6222 dev_priv->rps.enabled = true; 6223 6224 gen6_enable_rps_interrupts(dev); 6225 6226 mutex_unlock(&dev_priv->rps.hw_lock); 6227 6228 intel_runtime_pm_put(dev_priv); 6229} 6230 6231void intel_enable_gt_powersave(struct drm_device *dev) 6232{ 6233 struct drm_i915_private *dev_priv = dev->dev_private; 6234 6235 /* Powersaving is controlled by the host when inside a VM */ 6236 if (intel_vgpu_active(dev)) 6237 return; 6238 6239 if (IS_IRONLAKE_M(dev)) { 6240 mutex_lock(&dev->struct_mutex); 6241 ironlake_enable_drps(dev); 6242 intel_init_emon(dev); 6243 mutex_unlock(&dev->struct_mutex); 6244 } else if (INTEL_INFO(dev)->gen >= 6) { 6245 /* 6246 * PCU communication is slow and this doesn't need to be 6247 * done at any specific time, so do this out of our fast path 6248 * to make resume and init faster. 6249 * 6250 * We depend on the HW RC6 power context save/restore 6251 * mechanism when entering D3 through runtime PM suspend. So 6252 * disable RPM until RPS/RC6 is properly setup. We can only 6253 * get here via the driver load/system resume/runtime resume 6254 * paths, so the _noresume version is enough (and in case of 6255 * runtime resume it's necessary). 6256 */ 6257 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, 6258 round_jiffies_up_relative(HZ))) 6259 intel_runtime_pm_get_noresume(dev_priv); 6260 } 6261} 6262 6263void intel_reset_gt_powersave(struct drm_device *dev) 6264{ 6265 struct drm_i915_private *dev_priv = dev->dev_private; 6266 6267 if (INTEL_INFO(dev)->gen < 6) 6268 return; 6269 6270 gen6_suspend_rps(dev); 6271 dev_priv->rps.enabled = false; 6272} 6273 6274static void ibx_init_clock_gating(struct drm_device *dev) 6275{ 6276 struct drm_i915_private *dev_priv = dev->dev_private; 6277 6278 /* 6279 * On Ibex Peak and Cougar Point, we need to disable clock 6280 * gating for the panel power sequencer or it will fail to 6281 * start up when no ports are active. 6282 */ 6283 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 6284} 6285 6286static void g4x_disable_trickle_feed(struct drm_device *dev) 6287{ 6288 struct drm_i915_private *dev_priv = dev->dev_private; 6289 enum pipe pipe; 6290 6291 for_each_pipe(dev_priv, pipe) { 6292 I915_WRITE(DSPCNTR(pipe), 6293 I915_READ(DSPCNTR(pipe)) | 6294 DISPPLANE_TRICKLE_FEED_DISABLE); 6295 6296 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); 6297 POSTING_READ(DSPSURF(pipe)); 6298 } 6299} 6300 6301static void ilk_init_lp_watermarks(struct drm_device *dev) 6302{ 6303 struct drm_i915_private *dev_priv = dev->dev_private; 6304 6305 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); 6306 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); 6307 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); 6308 6309 /* 6310 * Don't touch WM1S_LP_EN here. 6311 * Doing so could cause underruns. 6312 */ 6313} 6314 6315static void ironlake_init_clock_gating(struct drm_device *dev) 6316{ 6317 struct drm_i915_private *dev_priv = dev->dev_private; 6318 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 6319 6320 /* 6321 * Required for FBC 6322 * WaFbcDisableDpfcClockGating:ilk 6323 */ 6324 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 6325 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 6326 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 6327 6328 I915_WRITE(PCH_3DCGDIS0, 6329 MARIUNIT_CLOCK_GATE_DISABLE | 6330 SVSMUNIT_CLOCK_GATE_DISABLE); 6331 I915_WRITE(PCH_3DCGDIS1, 6332 VFMUNIT_CLOCK_GATE_DISABLE); 6333 6334 /* 6335 * According to the spec the following bits should be set in 6336 * order to enable memory self-refresh 6337 * The bit 22/21 of 0x42004 6338 * The bit 5 of 0x42020 6339 * The bit 15 of 0x45000 6340 */ 6341 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6342 (I915_READ(ILK_DISPLAY_CHICKEN2) | 6343 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 6344 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 6345 I915_WRITE(DISP_ARB_CTL, 6346 (I915_READ(DISP_ARB_CTL) | 6347 DISP_FBC_WM_DIS)); 6348 6349 ilk_init_lp_watermarks(dev); 6350 6351 /* 6352 * Based on the document from hardware guys the following bits 6353 * should be set unconditionally in order to enable FBC. 6354 * The bit 22 of 0x42000 6355 * The bit 22 of 0x42004 6356 * The bit 7,8,9 of 0x42020. 6357 */ 6358 if (IS_IRONLAKE_M(dev)) { 6359 /* WaFbcAsynchFlipDisableFbcQueue:ilk */ 6360 I915_WRITE(ILK_DISPLAY_CHICKEN1, 6361 I915_READ(ILK_DISPLAY_CHICKEN1) | 6362 ILK_FBCQ_DIS); 6363 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6364 I915_READ(ILK_DISPLAY_CHICKEN2) | 6365 ILK_DPARB_GATE); 6366 } 6367 6368 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 6369 6370 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6371 I915_READ(ILK_DISPLAY_CHICKEN2) | 6372 ILK_ELPIN_409_SELECT); 6373 I915_WRITE(_3D_CHICKEN2, 6374 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 6375 _3D_CHICKEN2_WM_READ_PIPELINED); 6376 6377 /* WaDisableRenderCachePipelinedFlush:ilk */ 6378 I915_WRITE(CACHE_MODE_0, 6379 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 6380 6381 /* WaDisable_RenderCache_OperationalFlush:ilk */ 6382 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6383 6384 g4x_disable_trickle_feed(dev); 6385 6386 ibx_init_clock_gating(dev); 6387} 6388 6389static void cpt_init_clock_gating(struct drm_device *dev) 6390{ 6391 struct drm_i915_private *dev_priv = dev->dev_private; 6392 int pipe; 6393 uint32_t val; 6394 6395 /* 6396 * On Ibex Peak and Cougar Point, we need to disable clock 6397 * gating for the panel power sequencer or it will fail to 6398 * start up when no ports are active. 6399 */ 6400 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 6401 PCH_DPLUNIT_CLOCK_GATE_DISABLE | 6402 PCH_CPUNIT_CLOCK_GATE_DISABLE); 6403 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 6404 DPLS_EDP_PPS_FIX_DIS); 6405 /* The below fixes the weird display corruption, a few pixels shifted 6406 * downward, on (only) LVDS of some HP laptops with IVY. 6407 */ 6408 for_each_pipe(dev_priv, pipe) { 6409 val = I915_READ(TRANS_CHICKEN2(pipe)); 6410 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 6411 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 6412 if (dev_priv->vbt.fdi_rx_polarity_inverted) 6413 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 6414 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 6415 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; 6416 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; 6417 I915_WRITE(TRANS_CHICKEN2(pipe), val); 6418 } 6419 /* WADP0ClockGatingDisable */ 6420 for_each_pipe(dev_priv, pipe) { 6421 I915_WRITE(TRANS_CHICKEN1(pipe), 6422 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 6423 } 6424} 6425 6426static void gen6_check_mch_setup(struct drm_device *dev) 6427{ 6428 struct drm_i915_private *dev_priv = dev->dev_private; 6429 uint32_t tmp; 6430 6431 tmp = I915_READ(MCH_SSKPD); 6432 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) 6433 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", 6434 tmp); 6435} 6436 6437static void gen6_init_clock_gating(struct drm_device *dev) 6438{ 6439 struct drm_i915_private *dev_priv = dev->dev_private; 6440 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 6441 6442 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 6443 6444 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6445 I915_READ(ILK_DISPLAY_CHICKEN2) | 6446 ILK_ELPIN_409_SELECT); 6447 6448 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 6449 I915_WRITE(_3D_CHICKEN, 6450 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); 6451 6452 /* WaDisable_RenderCache_OperationalFlush:snb */ 6453 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6454 6455 /* 6456 * BSpec recoomends 8x4 when MSAA is used, 6457 * however in practice 16x4 seems fastest. 6458 * 6459 * Note that PS/WM thread counts depend on the WIZ hashing 6460 * disable bit, which we don't touch here, but it's good 6461 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6462 */ 6463 I915_WRITE(GEN6_GT_MODE, 6464 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6465 6466 ilk_init_lp_watermarks(dev); 6467 6468 I915_WRITE(CACHE_MODE_0, 6469 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 6470 6471 I915_WRITE(GEN6_UCGCTL1, 6472 I915_READ(GEN6_UCGCTL1) | 6473 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 6474 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 6475 6476 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 6477 * gating disable must be set. Failure to set it results in 6478 * flickering pixels due to Z write ordering failures after 6479 * some amount of runtime in the Mesa "fire" demo, and Unigine 6480 * Sanctuary and Tropics, and apparently anything else with 6481 * alpha test or pixel discard. 6482 * 6483 * According to the spec, bit 11 (RCCUNIT) must also be set, 6484 * but we didn't debug actual testcases to find it out. 6485 * 6486 * WaDisableRCCUnitClockGating:snb 6487 * WaDisableRCPBUnitClockGating:snb 6488 */ 6489 I915_WRITE(GEN6_UCGCTL2, 6490 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 6491 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 6492 6493 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 6494 I915_WRITE(_3D_CHICKEN3, 6495 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); 6496 6497 /* 6498 * Bspec says: 6499 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and 6500 * 3DSTATE_SF number of SF output attributes is more than 16." 6501 */ 6502 I915_WRITE(_3D_CHICKEN3, 6503 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); 6504 6505 /* 6506 * According to the spec the following bits should be 6507 * set in order to enable memory self-refresh and fbc: 6508 * The bit21 and bit22 of 0x42000 6509 * The bit21 and bit22 of 0x42004 6510 * The bit5 and bit7 of 0x42020 6511 * The bit14 of 0x70180 6512 * The bit14 of 0x71180 6513 * 6514 * WaFbcAsynchFlipDisableFbcQueue:snb 6515 */ 6516 I915_WRITE(ILK_DISPLAY_CHICKEN1, 6517 I915_READ(ILK_DISPLAY_CHICKEN1) | 6518 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 6519 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6520 I915_READ(ILK_DISPLAY_CHICKEN2) | 6521 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 6522 I915_WRITE(ILK_DSPCLK_GATE_D, 6523 I915_READ(ILK_DSPCLK_GATE_D) | 6524 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 6525 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 6526 6527 g4x_disable_trickle_feed(dev); 6528 6529 cpt_init_clock_gating(dev); 6530 6531 gen6_check_mch_setup(dev); 6532} 6533 6534static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 6535{ 6536 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); 6537 6538 /* 6539 * WaVSThreadDispatchOverride:ivb,vlv 6540 * 6541 * This actually overrides the dispatch 6542 * mode for all thread types. 6543 */ 6544 reg &= ~GEN7_FF_SCHED_MASK; 6545 reg |= GEN7_FF_TS_SCHED_HW; 6546 reg |= GEN7_FF_VS_SCHED_HW; 6547 reg |= GEN7_FF_DS_SCHED_HW; 6548 6549 I915_WRITE(GEN7_FF_THREAD_MODE, reg); 6550} 6551 6552static void lpt_init_clock_gating(struct drm_device *dev) 6553{ 6554 struct drm_i915_private *dev_priv = dev->dev_private; 6555 6556 /* 6557 * TODO: this bit should only be enabled when really needed, then 6558 * disabled when not needed anymore in order to save power. 6559 */ 6560 if (HAS_PCH_LPT_LP(dev)) 6561 I915_WRITE(SOUTH_DSPCLK_GATE_D, 6562 I915_READ(SOUTH_DSPCLK_GATE_D) | 6563 PCH_LP_PARTITION_LEVEL_DISABLE); 6564 6565 /* WADPOClockGatingDisable:hsw */ 6566 I915_WRITE(TRANS_CHICKEN1(PIPE_A), 6567 I915_READ(TRANS_CHICKEN1(PIPE_A)) | 6568 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 6569} 6570 6571static void lpt_suspend_hw(struct drm_device *dev) 6572{ 6573 struct drm_i915_private *dev_priv = dev->dev_private; 6574 6575 if (HAS_PCH_LPT_LP(dev)) { 6576 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); 6577 6578 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; 6579 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); 6580 } 6581} 6582 6583static void broadwell_init_clock_gating(struct drm_device *dev) 6584{ 6585 struct drm_i915_private *dev_priv = dev->dev_private; 6586 enum pipe pipe; 6587 uint32_t misccpctl; 6588 6589 ilk_init_lp_watermarks(dev); 6590 6591 /* WaSwitchSolVfFArbitrationPriority:bdw */ 6592 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 6593 6594 /* WaPsrDPAMaskVBlankInSRD:bdw */ 6595 I915_WRITE(CHICKEN_PAR1_1, 6596 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); 6597 6598 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 6599 for_each_pipe(dev_priv, pipe) { 6600 I915_WRITE(CHICKEN_PIPESL_1(pipe), 6601 I915_READ(CHICKEN_PIPESL_1(pipe)) | 6602 BDW_DPRS_MASK_VBLANK_SRD); 6603 } 6604 6605 /* WaVSRefCountFullforceMissDisable:bdw */ 6606 /* WaDSRefCountFullforceMissDisable:bdw */ 6607 I915_WRITE(GEN7_FF_THREAD_MODE, 6608 I915_READ(GEN7_FF_THREAD_MODE) & 6609 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 6610 6611 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 6612 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 6613 6614 /* WaDisableSDEUnitClockGating:bdw */ 6615 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 6616 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 6617 6618 /* 6619 * WaProgramL3SqcReg1Default:bdw 6620 * WaTempDisableDOPClkGating:bdw 6621 */ 6622 misccpctl = I915_READ(GEN7_MISCCPCTL); 6623 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 6624 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); 6625 /* 6626 * Wait at least 100 clocks before re-enabling clock gating. See 6627 * the definition of L3SQCREG1 in BSpec. 6628 */ 6629 POSTING_READ(GEN8_L3SQCREG1); 6630 udelay(1); 6631 I915_WRITE(GEN7_MISCCPCTL, misccpctl); 6632 6633 /* 6634 * WaGttCachingOffByDefault:bdw 6635 * GTT cache may not work with big pages, so if those 6636 * are ever enabled GTT cache may need to be disabled. 6637 */ 6638 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); 6639 6640 lpt_init_clock_gating(dev); 6641} 6642 6643static void haswell_init_clock_gating(struct drm_device *dev) 6644{ 6645 struct drm_i915_private *dev_priv = dev->dev_private; 6646 6647 ilk_init_lp_watermarks(dev); 6648 6649 /* L3 caching of data atomics doesn't work -- disable it. */ 6650 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 6651 I915_WRITE(HSW_ROW_CHICKEN3, 6652 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); 6653 6654 /* This is required by WaCatErrorRejectionIssue:hsw */ 6655 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6656 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6657 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6658 6659 /* WaVSRefCountFullforceMissDisable:hsw */ 6660 I915_WRITE(GEN7_FF_THREAD_MODE, 6661 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); 6662 6663 /* WaDisable_RenderCache_OperationalFlush:hsw */ 6664 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6665 6666 /* enable HiZ Raw Stall Optimization */ 6667 I915_WRITE(CACHE_MODE_0_GEN7, 6668 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 6669 6670 /* WaDisable4x2SubspanOptimization:hsw */ 6671 I915_WRITE(CACHE_MODE_1, 6672 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6673 6674 /* 6675 * BSpec recommends 8x4 when MSAA is used, 6676 * however in practice 16x4 seems fastest. 6677 * 6678 * Note that PS/WM thread counts depend on the WIZ hashing 6679 * disable bit, which we don't touch here, but it's good 6680 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6681 */ 6682 I915_WRITE(GEN7_GT_MODE, 6683 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6684 6685 /* WaSampleCChickenBitEnable:hsw */ 6686 I915_WRITE(HALF_SLICE_CHICKEN3, 6687 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); 6688 6689 /* WaSwitchSolVfFArbitrationPriority:hsw */ 6690 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 6691 6692 /* WaRsPkgCStateDisplayPMReq:hsw */ 6693 I915_WRITE(CHICKEN_PAR1_1, 6694 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 6695 6696 lpt_init_clock_gating(dev); 6697} 6698 6699static void ivybridge_init_clock_gating(struct drm_device *dev) 6700{ 6701 struct drm_i915_private *dev_priv = dev->dev_private; 6702 uint32_t snpcr; 6703 6704 ilk_init_lp_watermarks(dev); 6705 6706 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 6707 6708 /* WaDisableEarlyCull:ivb */ 6709 I915_WRITE(_3D_CHICKEN3, 6710 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 6711 6712 /* WaDisableBackToBackFlipFix:ivb */ 6713 I915_WRITE(IVB_CHICKEN3, 6714 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 6715 CHICKEN3_DGMG_DONE_FIX_DISABLE); 6716 6717 /* WaDisablePSDDualDispatchEnable:ivb */ 6718 if (IS_IVB_GT1(dev)) 6719 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 6720 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 6721 6722 /* WaDisable_RenderCache_OperationalFlush:ivb */ 6723 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6724 6725 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 6726 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 6727 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 6728 6729 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 6730 I915_WRITE(GEN7_L3CNTLREG1, 6731 GEN7_WA_FOR_GEN7_L3_CONTROL); 6732 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 6733 GEN7_WA_L3_CHICKEN_MODE); 6734 if (IS_IVB_GT1(dev)) 6735 I915_WRITE(GEN7_ROW_CHICKEN2, 6736 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6737 else { 6738 /* must write both registers */ 6739 I915_WRITE(GEN7_ROW_CHICKEN2, 6740 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6741 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, 6742 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6743 } 6744 6745 /* WaForceL3Serialization:ivb */ 6746 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 6747 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 6748 6749 /* 6750 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 6751 * This implements the WaDisableRCZUnitClockGating:ivb workaround. 6752 */ 6753 I915_WRITE(GEN6_UCGCTL2, 6754 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 6755 6756 /* This is required by WaCatErrorRejectionIssue:ivb */ 6757 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6758 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6759 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6760 6761 g4x_disable_trickle_feed(dev); 6762 6763 gen7_setup_fixed_func_scheduler(dev_priv); 6764 6765 if (0) { /* causes HiZ corruption on ivb:gt1 */ 6766 /* enable HiZ Raw Stall Optimization */ 6767 I915_WRITE(CACHE_MODE_0_GEN7, 6768 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 6769 } 6770 6771 /* WaDisable4x2SubspanOptimization:ivb */ 6772 I915_WRITE(CACHE_MODE_1, 6773 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6774 6775 /* 6776 * BSpec recommends 8x4 when MSAA is used, 6777 * however in practice 16x4 seems fastest. 6778 * 6779 * Note that PS/WM thread counts depend on the WIZ hashing 6780 * disable bit, which we don't touch here, but it's good 6781 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6782 */ 6783 I915_WRITE(GEN7_GT_MODE, 6784 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6785 6786 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 6787 snpcr &= ~GEN6_MBC_SNPCR_MASK; 6788 snpcr |= GEN6_MBC_SNPCR_MED; 6789 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 6790 6791 if (!HAS_PCH_NOP(dev)) 6792 cpt_init_clock_gating(dev); 6793 6794 gen6_check_mch_setup(dev); 6795} 6796 6797static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 6798{ 6799 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); 6800 6801 /* 6802 * Disable trickle feed and enable pnd deadline calculation 6803 */ 6804 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 6805 I915_WRITE(CBR1_VLV, 0); 6806} 6807 6808static void valleyview_init_clock_gating(struct drm_device *dev) 6809{ 6810 struct drm_i915_private *dev_priv = dev->dev_private; 6811 6812 vlv_init_display_clock_gating(dev_priv); 6813 6814 /* WaDisableEarlyCull:vlv */ 6815 I915_WRITE(_3D_CHICKEN3, 6816 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 6817 6818 /* WaDisableBackToBackFlipFix:vlv */ 6819 I915_WRITE(IVB_CHICKEN3, 6820 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 6821 CHICKEN3_DGMG_DONE_FIX_DISABLE); 6822 6823 /* WaPsdDispatchEnable:vlv */ 6824 /* WaDisablePSDDualDispatchEnable:vlv */ 6825 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 6826 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | 6827 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 6828 6829 /* WaDisable_RenderCache_OperationalFlush:vlv */ 6830 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6831 6832 /* WaForceL3Serialization:vlv */ 6833 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 6834 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 6835 6836 /* WaDisableDopClockGating:vlv */ 6837 I915_WRITE(GEN7_ROW_CHICKEN2, 6838 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6839 6840 /* This is required by WaCatErrorRejectionIssue:vlv */ 6841 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6842 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6843 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6844 6845 gen7_setup_fixed_func_scheduler(dev_priv); 6846 6847 /* 6848 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 6849 * This implements the WaDisableRCZUnitClockGating:vlv workaround. 6850 */ 6851 I915_WRITE(GEN6_UCGCTL2, 6852 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 6853 6854 /* WaDisableL3Bank2xClockGate:vlv 6855 * Disabling L3 clock gating- MMIO 940c[25] = 1 6856 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ 6857 I915_WRITE(GEN7_UCGCTL4, 6858 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 6859 6860 /* 6861 * BSpec says this must be set, even though 6862 * WaDisable4x2SubspanOptimization isn't listed for VLV. 6863 */ 6864 I915_WRITE(CACHE_MODE_1, 6865 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6866 6867 /* 6868 * BSpec recommends 8x4 when MSAA is used, 6869 * however in practice 16x4 seems fastest. 6870 * 6871 * Note that PS/WM thread counts depend on the WIZ hashing 6872 * disable bit, which we don't touch here, but it's good 6873 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6874 */ 6875 I915_WRITE(GEN7_GT_MODE, 6876 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6877 6878 /* 6879 * WaIncreaseL3CreditsForVLVB0:vlv 6880 * This is the hardware default actually. 6881 */ 6882 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 6883 6884 /* 6885 * WaDisableVLVClockGating_VBIIssue:vlv 6886 * Disable clock gating on th GCFG unit to prevent a delay 6887 * in the reporting of vblank events. 6888 */ 6889 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 6890} 6891 6892static void cherryview_init_clock_gating(struct drm_device *dev) 6893{ 6894 struct drm_i915_private *dev_priv = dev->dev_private; 6895 6896 vlv_init_display_clock_gating(dev_priv); 6897 6898 /* WaVSRefCountFullforceMissDisable:chv */ 6899 /* WaDSRefCountFullforceMissDisable:chv */ 6900 I915_WRITE(GEN7_FF_THREAD_MODE, 6901 I915_READ(GEN7_FF_THREAD_MODE) & 6902 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 6903 6904 /* WaDisableSemaphoreAndSyncFlipWait:chv */ 6905 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 6906 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 6907 6908 /* WaDisableCSUnitClockGating:chv */ 6909 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | 6910 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 6911 6912 /* WaDisableSDEUnitClockGating:chv */ 6913 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 6914 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 6915 6916 /* 6917 * GTT cache may not work with big pages, so if those 6918 * are ever enabled GTT cache may need to be disabled. 6919 */ 6920 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); 6921} 6922 6923static void g4x_init_clock_gating(struct drm_device *dev) 6924{ 6925 struct drm_i915_private *dev_priv = dev->dev_private; 6926 uint32_t dspclk_gate; 6927 6928 I915_WRITE(RENCLK_GATE_D1, 0); 6929 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 6930 GS_UNIT_CLOCK_GATE_DISABLE | 6931 CL_UNIT_CLOCK_GATE_DISABLE); 6932 I915_WRITE(RAMCLK_GATE_D, 0); 6933 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 6934 OVRUNIT_CLOCK_GATE_DISABLE | 6935 OVCUNIT_CLOCK_GATE_DISABLE; 6936 if (IS_GM45(dev)) 6937 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 6938 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); 6939 6940 /* WaDisableRenderCachePipelinedFlush */ 6941 I915_WRITE(CACHE_MODE_0, 6942 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 6943 6944 /* WaDisable_RenderCache_OperationalFlush:g4x */ 6945 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6946 6947 g4x_disable_trickle_feed(dev); 6948} 6949 6950static void crestline_init_clock_gating(struct drm_device *dev) 6951{ 6952 struct drm_i915_private *dev_priv = dev->dev_private; 6953 6954 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 6955 I915_WRITE(RENCLK_GATE_D2, 0); 6956 I915_WRITE(DSPCLK_GATE_D, 0); 6957 I915_WRITE(RAMCLK_GATE_D, 0); 6958 I915_WRITE16(DEUC, 0); 6959 I915_WRITE(MI_ARB_STATE, 6960 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 6961 6962 /* WaDisable_RenderCache_OperationalFlush:gen4 */ 6963 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6964} 6965 6966static void broadwater_init_clock_gating(struct drm_device *dev) 6967{ 6968 struct drm_i915_private *dev_priv = dev->dev_private; 6969 6970 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 6971 I965_RCC_CLOCK_GATE_DISABLE | 6972 I965_RCPB_CLOCK_GATE_DISABLE | 6973 I965_ISC_CLOCK_GATE_DISABLE | 6974 I965_FBC_CLOCK_GATE_DISABLE); 6975 I915_WRITE(RENCLK_GATE_D2, 0); 6976 I915_WRITE(MI_ARB_STATE, 6977 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 6978 6979 /* WaDisable_RenderCache_OperationalFlush:gen4 */ 6980 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6981} 6982 6983static void gen3_init_clock_gating(struct drm_device *dev) 6984{ 6985 struct drm_i915_private *dev_priv = dev->dev_private; 6986 u32 dstate = I915_READ(D_STATE); 6987 6988 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 6989 DSTATE_DOT_CLOCK_GATING; 6990 I915_WRITE(D_STATE, dstate); 6991 6992 if (IS_PINEVIEW(dev)) 6993 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 6994 6995 /* IIR "flip pending" means done if this bit is set */ 6996 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 6997 6998 /* interrupts should cause a wake up from C3 */ 6999 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); 7000 7001 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 7002 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 7003 7004 I915_WRITE(MI_ARB_STATE, 7005 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7006} 7007 7008static void i85x_init_clock_gating(struct drm_device *dev) 7009{ 7010 struct drm_i915_private *dev_priv = dev->dev_private; 7011 7012 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 7013 7014 /* interrupts should cause a wake up from C3 */ 7015 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | 7016 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); 7017 7018 I915_WRITE(MEM_MODE, 7019 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); 7020} 7021 7022static void i830_init_clock_gating(struct drm_device *dev) 7023{ 7024 struct drm_i915_private *dev_priv = dev->dev_private; 7025 7026 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 7027 7028 I915_WRITE(MEM_MODE, 7029 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | 7030 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); 7031} 7032 7033void intel_init_clock_gating(struct drm_device *dev) 7034{ 7035 struct drm_i915_private *dev_priv = dev->dev_private; 7036 7037 if (dev_priv->display.init_clock_gating) 7038 dev_priv->display.init_clock_gating(dev); 7039} 7040 7041void intel_suspend_hw(struct drm_device *dev) 7042{ 7043 if (HAS_PCH_LPT(dev)) 7044 lpt_suspend_hw(dev); 7045} 7046 7047/* Set up chip specific power management-related functions */ 7048void intel_init_pm(struct drm_device *dev) 7049{ 7050 struct drm_i915_private *dev_priv = dev->dev_private; 7051 7052 intel_fbc_init(dev_priv); 7053 7054 /* For cxsr */ 7055 if (IS_PINEVIEW(dev)) 7056 i915_pineview_get_mem_freq(dev); 7057 else if (IS_GEN5(dev)) 7058 i915_ironlake_get_mem_freq(dev); 7059 7060 /* For FIFO watermark updates */ 7061 if (INTEL_INFO(dev)->gen >= 9) { 7062 skl_setup_wm_latency(dev); 7063 7064 if (IS_BROXTON(dev)) 7065 dev_priv->display.init_clock_gating = 7066 bxt_init_clock_gating; 7067 dev_priv->display.update_wm = skl_update_wm; 7068 dev_priv->display.update_sprite_wm = skl_update_sprite_wm; 7069 } else if (HAS_PCH_SPLIT(dev)) { 7070 ilk_setup_wm_latency(dev); 7071 7072 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && 7073 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || 7074 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && 7075 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { 7076 dev_priv->display.update_wm = ilk_update_wm; 7077 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; 7078 } else { 7079 DRM_DEBUG_KMS("Failed to read display plane latency. " 7080 "Disable CxSR\n"); 7081 } 7082 7083 if (IS_GEN5(dev)) 7084 dev_priv->display.init_clock_gating = ironlake_init_clock_gating; 7085 else if (IS_GEN6(dev)) 7086 dev_priv->display.init_clock_gating = gen6_init_clock_gating; 7087 else if (IS_IVYBRIDGE(dev)) 7088 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; 7089 else if (IS_HASWELL(dev)) 7090 dev_priv->display.init_clock_gating = haswell_init_clock_gating; 7091 else if (INTEL_INFO(dev)->gen == 8) 7092 dev_priv->display.init_clock_gating = broadwell_init_clock_gating; 7093 } else if (IS_CHERRYVIEW(dev)) { 7094 vlv_setup_wm_latency(dev); 7095 7096 dev_priv->display.update_wm = vlv_update_wm; 7097 dev_priv->display.init_clock_gating = 7098 cherryview_init_clock_gating; 7099 } else if (IS_VALLEYVIEW(dev)) { 7100 vlv_setup_wm_latency(dev); 7101 7102 dev_priv->display.update_wm = vlv_update_wm; 7103 dev_priv->display.init_clock_gating = 7104 valleyview_init_clock_gating; 7105 } else if (IS_PINEVIEW(dev)) { 7106 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 7107 dev_priv->is_ddr3, 7108 dev_priv->fsb_freq, 7109 dev_priv->mem_freq)) { 7110 DRM_INFO("failed to find known CxSR latency " 7111 "(found ddr%s fsb freq %d, mem freq %d), " 7112 "disabling CxSR\n", 7113 (dev_priv->is_ddr3 == 1) ? "3" : "2", 7114 dev_priv->fsb_freq, dev_priv->mem_freq); 7115 /* Disable CxSR and never update its watermark again */ 7116 intel_set_memory_cxsr(dev_priv, false); 7117 dev_priv->display.update_wm = NULL; 7118 } else 7119 dev_priv->display.update_wm = pineview_update_wm; 7120 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 7121 } else if (IS_G4X(dev)) { 7122 dev_priv->display.update_wm = g4x_update_wm; 7123 dev_priv->display.init_clock_gating = g4x_init_clock_gating; 7124 } else if (IS_GEN4(dev)) { 7125 dev_priv->display.update_wm = i965_update_wm; 7126 if (IS_CRESTLINE(dev)) 7127 dev_priv->display.init_clock_gating = crestline_init_clock_gating; 7128 else if (IS_BROADWATER(dev)) 7129 dev_priv->display.init_clock_gating = broadwater_init_clock_gating; 7130 } else if (IS_GEN3(dev)) { 7131 dev_priv->display.update_wm = i9xx_update_wm; 7132 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 7133 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 7134 } else if (IS_GEN2(dev)) { 7135 if (INTEL_INFO(dev)->num_pipes == 1) { 7136 dev_priv->display.update_wm = i845_update_wm; 7137 dev_priv->display.get_fifo_size = i845_get_fifo_size; 7138 } else { 7139 dev_priv->display.update_wm = i9xx_update_wm; 7140 dev_priv->display.get_fifo_size = i830_get_fifo_size; 7141 } 7142 7143 if (IS_I85X(dev) || IS_I865G(dev)) 7144 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 7145 else 7146 dev_priv->display.init_clock_gating = i830_init_clock_gating; 7147 } else { 7148 DRM_ERROR("unexpected fall-through in intel_init_pm\n"); 7149 } 7150} 7151 7152int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) 7153{ 7154 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 7155 7156 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 7157 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); 7158 return -EAGAIN; 7159 } 7160 7161 I915_WRITE(GEN6_PCODE_DATA, *val); 7162 I915_WRITE(GEN6_PCODE_DATA1, 0); 7163 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 7164 7165 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 7166 500)) { 7167 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); 7168 return -ETIMEDOUT; 7169 } 7170 7171 *val = I915_READ(GEN6_PCODE_DATA); 7172 I915_WRITE(GEN6_PCODE_DATA, 0); 7173 7174 return 0; 7175} 7176 7177int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) 7178{ 7179 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 7180 7181 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 7182 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); 7183 return -EAGAIN; 7184 } 7185 7186 I915_WRITE(GEN6_PCODE_DATA, val); 7187 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 7188 7189 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 7190 500)) { 7191 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); 7192 return -ETIMEDOUT; 7193 } 7194 7195 I915_WRITE(GEN6_PCODE_DATA, 0); 7196 7197 return 0; 7198} 7199 7200static int vlv_gpu_freq_div(unsigned int czclk_freq) 7201{ 7202 switch (czclk_freq) { 7203 case 200: 7204 return 10; 7205 case 267: 7206 return 12; 7207 case 320: 7208 case 333: 7209 return 16; 7210 case 400: 7211 return 20; 7212 default: 7213 return -1; 7214 } 7215} 7216 7217static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) 7218{ 7219 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7220 7221 div = vlv_gpu_freq_div(czclk_freq); 7222 if (div < 0) 7223 return div; 7224 7225 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); 7226} 7227 7228static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) 7229{ 7230 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7231 7232 mul = vlv_gpu_freq_div(czclk_freq); 7233 if (mul < 0) 7234 return mul; 7235 7236 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; 7237} 7238 7239static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) 7240{ 7241 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7242 7243 div = vlv_gpu_freq_div(czclk_freq) / 2; 7244 if (div < 0) 7245 return div; 7246 7247 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; 7248} 7249 7250static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) 7251{ 7252 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7253 7254 mul = vlv_gpu_freq_div(czclk_freq) / 2; 7255 if (mul < 0) 7256 return mul; 7257 7258 /* CHV needs even values */ 7259 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; 7260} 7261 7262int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) 7263{ 7264 if (IS_GEN9(dev_priv->dev)) 7265 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, 7266 GEN9_FREQ_SCALER); 7267 else if (IS_CHERRYVIEW(dev_priv->dev)) 7268 return chv_gpu_freq(dev_priv, val); 7269 else if (IS_VALLEYVIEW(dev_priv->dev)) 7270 return byt_gpu_freq(dev_priv, val); 7271 else 7272 return val * GT_FREQUENCY_MULTIPLIER; 7273} 7274 7275int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) 7276{ 7277 if (IS_GEN9(dev_priv->dev)) 7278 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, 7279 GT_FREQUENCY_MULTIPLIER); 7280 else if (IS_CHERRYVIEW(dev_priv->dev)) 7281 return chv_freq_opcode(dev_priv, val); 7282 else if (IS_VALLEYVIEW(dev_priv->dev)) 7283 return byt_freq_opcode(dev_priv, val); 7284 else 7285 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); 7286} 7287 7288struct request_boost { 7289 struct work_struct work; 7290 struct drm_i915_gem_request *req; 7291}; 7292 7293static void __intel_rps_boost_work(struct work_struct *work) 7294{ 7295 struct request_boost *boost = container_of(work, struct request_boost, work); 7296 struct drm_i915_gem_request *req = boost->req; 7297 7298 if (!i915_gem_request_completed(req, true)) 7299 gen6_rps_boost(to_i915(req->ring->dev), NULL, 7300 req->emitted_jiffies); 7301 7302 i915_gem_request_unreference__unlocked(req); 7303 kfree(boost); 7304} 7305 7306void intel_queue_rps_boost_for_request(struct drm_device *dev, 7307 struct drm_i915_gem_request *req) 7308{ 7309 struct request_boost *boost; 7310 7311 if (req == NULL || INTEL_INFO(dev)->gen < 6) 7312 return; 7313 7314 if (i915_gem_request_completed(req, true)) 7315 return; 7316 7317 boost = kmalloc(sizeof(*boost), GFP_ATOMIC); 7318 if (boost == NULL) 7319 return; 7320 7321 i915_gem_request_reference(req); 7322 boost->req = req; 7323 7324 INIT_WORK(&boost->work, __intel_rps_boost_work); 7325 queue_work(to_i915(dev)->wq, &boost->work); 7326} 7327 7328void intel_pm_setup(struct drm_device *dev) 7329{ 7330 struct drm_i915_private *dev_priv = dev->dev_private; 7331 7332 mutex_init(&dev_priv->rps.hw_lock); 7333 spin_lock_init(&dev_priv->rps.client_lock); 7334 7335 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 7336 intel_gen6_powersave_work); 7337 INIT_LIST_HEAD(&dev_priv->rps.clients); 7338 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); 7339 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); 7340 7341 dev_priv->pm.suspended = false; 7342} 7343