| /linux-4.4.14/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
10 - reg : Address and size of L2 cache controller registers
11 - cache-size : Size of the entire L2 cache
12 - interrupts : Error interrupt of L2 controller
13 - cache-line-size : Size of L2 cache lines
17 L2: l2-cache-controller@20000 {
21 cache-size = <0x40000>; // L2,256K
|
| D | cache_sram.txt | 11 - fsl,cache-sram-ctlr-handle : points to the L2 controller
17 fsl,cache-sram-ctlr-handle = <&L2>;
|
| D | mpc5200.txt | 180 of three cells; <L1 L2 level>
183 L2 := interrupt number; directly mapped from the value in the
|
| /linux-4.4.14/arch/mips/cavium-octeon/ |
| D | Kconfig | 38 bool "Lock often used kernel code in the L2"
41 Enable locking parts of the kernel into the L2 cache.
44 bool "Lock the TLB handler in L2"
48 Lock the low level TLB fast path into L2.
51 bool "Lock the exception handler in L2"
55 Lock the low level exception handler into L2.
58 bool "Lock the interrupt handler in L2"
62 Lock the low level interrupt handler into L2.
65 bool "Lock the 2nd level interrupt handler in L2"
69 Lock the 2nd level interrupt handler in L2.
[all …]
|
| /linux-4.4.14/arch/arc/kernel/ |
| D | entry-compact.S | 169 ; if L2 IRQ interrupted a L1 ISR, disable preemption
171 ; This is to avoid a potential L1-L2-L1 scenario
173 ; -L2 interrupts L1 (before L1 ISR could run)
176 ; Returns from L2 context fine
177 ; But both L1 and L2 re-enabled, so another L1 can be taken
182 ; L2 interrupting L1 implies both L2 and L1 active
187 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
226 ; out of the L2 interrupt context (drop to pure kernel mode) and jump
349 ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
364 ; However the context returning might not have taken L2 intr itself
[all …]
|
| /linux-4.4.14/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-dt.txt | 34 next-level-cache = <&L2>;
50 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
62 next-level-cache = <&L2>;
|
| D | arm_big_little_dt.txt | 31 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
50 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
|
| /linux-4.4.14/Documentation/devicetree/bindings/arm/ |
| D | l2cc.txt | 1 * ARM L2 Cache Controller
4 implementations of the L2 cache controller with compatible programming models.
9 The ARM L2 cache representation in the device tree should be done as follows:
19 offset needs to be added to the address before passing down to the L2
23 maintenance operations on L1 are broadcasted to the L2 and L2
59 - wt-override: If present then L2 is forced to Write through mode
84 L2: cache-controller {
|
| /linux-4.4.14/arch/arm/boot/dts/ |
| D | highbank.dts | 37 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
65 next-level-cache = <&L2>;
74 next-level-cache = <&L2>;
119 L2: l2-cache { label
|
| D | vexpress-v2p-ca9.dts | 40 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
54 next-level-cache = <&L2>;
61 next-level-cache = <&L2>;
169 L2: cache-controller@1e00a000 { label
230 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
275 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
289 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
|
| D | bcm4708.dtsi | 22 next-level-cache = <&L2>;
29 next-level-cache = <&L2>;
|
| D | vf610.dtsi | 13 next-level-cache = <&L2>;
17 L2: l2-cache@40006000 { label
|
| D | meson8b.dtsi | 61 next-level-cache = <&L2>;
68 next-level-cache = <&L2>;
75 next-level-cache = <&L2>;
82 next-level-cache = <&L2>;
93 L2: l2-cache-controller@c4200000 { label
|
| D | qcom-apq8084.dtsi | 22 next-level-cache = <&L2>;
33 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
55 next-level-cache = <&L2>;
61 L2: l2-cache { label
|
| D | imx6q.dtsi | 28 next-level-cache = <&L2>;
62 next-level-cache = <&L2>;
69 next-level-cache = <&L2>;
76 next-level-cache = <&L2>;
|
| D | meson8.dtsi | 62 next-level-cache = <&L2>;
69 next-level-cache = <&L2>;
76 next-level-cache = <&L2>;
83 next-level-cache = <&L2>;
|
| D | bcm63138.dtsi | 27 next-level-cache = <&L2>;
35 next-level-cache = <&L2>;
67 L2: cache-controller@1d000 { label
|
| D | qcom-msm8974.dtsi | 33 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
55 next-level-cache = <&L2>;
66 next-level-cache = <&L2>;
72 L2: l2-cache { label
|
| D | qcom-msm8660.dtsi | 23 next-level-cache = <&L2>;
31 next-level-cache = <&L2>;
34 L2: l2-cache { label
|
| D | vexpress-v2p-ca5s.dts | 40 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
114 L2: cache-controller@2c0f0000 { label
|
| D | imx6dl.dtsi | 28 next-level-cache = <&L2>;
58 next-level-cache = <&L2>;
|
| D | bcm47081.dtsi | 22 next-level-cache = <&L2>;
|
| D | qcom-msm8960.dtsi | 25 next-level-cache = <&L2>;
35 next-level-cache = <&L2>;
40 L2: l2-cache { label
|
| D | meson6.dtsi | 63 next-level-cache = <&L2>;
70 next-level-cache = <&L2>;
|
| D | bcm-nsp.dtsi | 56 next-level-cache = <&L2>;
61 L2: l2-cache { label
|
| D | spear13xx.dtsi | 27 next-level-cache = <&L2>;
34 next-level-cache = <&L2>;
52 L2: l2-cache { label
|
| D | qcom-ipq8064.dtsi | 22 next-level-cache = <&L2>;
32 next-level-cache = <&L2>;
37 L2: l2-cache { label
|
| D | qcom-apq8064.dtsi | 23 next-level-cache = <&L2>;
34 next-level-cache = <&L2>;
45 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
62 L2: l2-cache { label
|
| D | hi3620.dtsi | 42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
75 L2: l2-cache { label
|
| D | rk3188.dtsi | 60 next-level-cache = <&L2>;
79 next-level-cache = <&L2>;
85 next-level-cache = <&L2>;
91 next-level-cache = <&L2>;
|
| D | bcm-cygnus.dtsi | 51 next-level-cache = <&L2>;
80 L2: l2-cache { label
|
| D | pxa910.dtsi | 29 L2: l2-cache { label
|
| D | socfpga_arria10.dtsi | 39 next-level-cache = <&L2>;
45 next-level-cache = <&L2>;
577 L2: l2-cache@fffff000 { label
|
| D | kirkwood-b3.dts | 12 * L2 cache. If your B3 silently fails to boot, u-boot is probably too
|
| D | socfpga.dtsi | 45 next-level-cache = <&L2>;
51 next-level-cache = <&L2>;
659 L2: l2-cache@fffef000 { label
|
| D | bcm5301x.dtsi | 77 L2: cache-controller@2000 { label
|
| D | stih415.dtsi | 16 L2: cache-controller { label
|
| D | meson.dtsi | 53 L2: l2-cache-controller@c4200000 { label
|
| D | mmp2.dtsi | 30 L2: l2-cache { label
|
| D | rk3066a.dtsi | 60 next-level-cache = <&L2>;
76 next-level-cache = <&L2>;
|
| D | omap4.dtsi | 37 next-level-cache = <&L2>;
48 next-level-cache = <&L2>;
62 L2: l2-cache-controller@48242000 { label
|
| D | bcm21664.dtsi | 93 L2: l2-cache { label
|
| D | zynq-7000.dtsi | 139 L2: cache-controller@f8f02000 { label
|
| D | imx35.dtsi | 51 L2: l2-cache@30000000 { label
|
| D | bcm11351.dtsi | 103 L2: l2-cache { label
|
| D | imx6sl.dtsi | 44 next-level-cache = <&L2>;
108 L2: l2-cache@00a02000 { label
|
| D | armada-xp.dtsi | 78 L2: l2-cache { label
|
| D | sama5d2.dtsi | 71 next-level-cache = <&L2>;
258 L2: cache-controller@00a00000 { label
|
| D | armada-370.dtsi | 128 L2: l2-cache { label
|
| D | rk3xxx.dtsi | 113 L2: l2-cache-controller@10138000 { label
|
| D | arm-realview-pb1176.dts | 191 L2: l2-cache { label
|
| /linux-4.4.14/Documentation/devicetree/bindings/arm/uniphier/ |
| D | cache-uniphier.txt | 17 be 2 for L2 cache, 3 for L3 cache, etc.
23 The L2 cache must exist to use the L3 cache; the cache hierarchy must be
26 Example 1 (system with L2):
38 Example 2 (system with L2 and L3):
|
| /linux-4.4.14/arch/c6x/kernel/ |
| D | head.S | 24 SUB .L2 B6,B5,B6 ; bss size
33 ZERO .L2 B13
34 ZERO .L2 B12
38 CMPLT .L2 B0,0,B1
|
| D | entry.S | 123 MVK .L2 0,B1
221 CMPLTU .L2 B0,B1,B1
327 MVK .L2 1,B2
339 CMPLTU .L2 B0,B1,B1
|
| D | switch_to.S | 51 || MV .L2 B6,B14
|
| /linux-4.4.14/arch/c6x/lib/ |
| D | csum_64plus.S | 57 || ADD .L2 B8,B9,B9
83 CMPGT .L2 B5,0,B0
193 CMPGT .L2 B0,0,B1
293 CMPGT .L2 B4,0,B0
299 || MV .L2 B4,B3
303 [A0] SUB .L2 B3,1,B3
308 SUB .L2 B3,1,B3
319 SUB .L2 B0,1,B0
347 MVK .L2 2,B0
348 AND .L2 B3,B0,B0
|
| /linux-4.4.14/Documentation/devicetree/bindings/opp/ |
| D | opp.txt | 29 next-level-cache = <&L2>;
138 next-level-cache = <&L2>;
148 next-level-cache = <&L2>;
193 next-level-cache = <&L2>;
203 next-level-cache = <&L2>;
213 next-level-cache = <&L2>;
223 next-level-cache = <&L2>;
273 next-level-cache = <&L2>;
283 next-level-cache = <&L2>;
293 next-level-cache = <&L2>;
[all …]
|
| /linux-4.4.14/drivers/net/ethernet/intel/i40evf/ |
| D | i40e_common.c | 590 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
591 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
592 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
595 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
596 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
599 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
600 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
601 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
[all …]
|
| /linux-4.4.14/arch/powerpc/boot/dts/fsl/ |
| D | mpc8572ds_camp_core1.dts | 4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
62 cache-size = <0x80000>; // L2, 512K
84 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
|
| D | mpc8572ds_camp_core0.dts | 4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
45 cache-size = <0x80000>; // L2, 512K
|
| D | p1020rdb-pc_camp_core1.dts | 4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
106 16 /* ecm, mem, L2, pci0, pci1 */
|
| D | p1020si-pre.dtsi | 62 next-level-cache = <&L2>;
68 next-level-cache = <&L2>;
|
| D | p1021si-pre.dtsi | 62 next-level-cache = <&L2>;
68 next-level-cache = <&L2>;
|
| D | bsc9132si-pre.dtsi | 57 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
|
| D | mpc8572si-pre.dtsi | 64 next-level-cache = <&L2>;
70 next-level-cache = <&L2>;
|
| D | p1023si-pre.dtsi | 70 next-level-cache = <&L2>;
76 next-level-cache = <&L2>;
|
| D | p2020si-pre.dtsi | 63 next-level-cache = <&L2>;
69 next-level-cache = <&L2>;
|
| D | p1022si-pre.dtsi | 64 next-level-cache = <&L2>;
70 next-level-cache = <&L2>;
|
| D | bsc9131si-post.dtsi | 96 L2: l2-cache-controller@20000 { label
100 cache-size = <0x40000>; // L2,256K
|
| D | bsc9132si-post.dtsi | 97 L2: l2-cache-controller@20000 { label
101 cache-size = <0x40000>; // L2,256K
|
| D | p1020rdb-pc_camp_core0.dts | 4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
|
| D | mpc8548si-post.dtsi | 136 L2: l2-cache-controller@20000 { label
140 cache-size = <0x80000>; // L2, 512K
|
| D | c293si-post.dtsi | 104 L2: l2-cache-controller@20000 { label
108 cache-size = <0x80000>; // L2,512K
|
| D | p1020rdb.dts | 24 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
|
| D | p1020rdb_36b.dts | 24 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
|
| D | mpc8541cds.dts | 45 next-level-cache = <&L2>;
82 L2: l2-cache-controller@20000 { label
86 cache-size = <0x40000>; // L2, 256K
|
| D | mpc8540ads.dts | 45 next-level-cache = <&L2>;
82 L2: l2-cache-controller@20000 { label
86 cache-size = <0x40000>; // L2, 256K
|
| D | mpc8555cds.dts | 45 next-level-cache = <&L2>;
82 L2: l2-cache-controller@20000 { label
86 cache-size = <0x40000>; // L2, 256K
|
| D | mpc8572si-post.dtsi | 168 L2: l2-cache-controller@20000 { label
172 cache-size = <0x100000>; // L2,1M
|
| D | mpc8544si-post.dtsi | 167 L2: l2-cache-controller@20000 { label
171 cache-size = <0x40000>; // L2, 256K
|
| D | p2020si-post.dtsi | 164 L2: l2-cache-controller@20000 { label
168 cache-size = <0x80000>; // L2,512K
|
| D | p1020si-post.dtsi | 136 L2: l2-cache-controller@20000 { label
140 cache-size = <0x40000>; // L2,256K
|
| D | mpc8536ds.dts | 26 next-level-cache = <&L2>;
|
| D | p1010si-post.dtsi | 148 L2: l2-cache-controller@20000 { label
153 cache-size = <0x40000>; // L2,256K
|
| D | p1021si-post.dtsi | 136 L2: l2-cache-controller@20000 { label
140 cache-size = <0x40000>; // L2,256K
|
| D | mpc8536ds_36b.dts | 26 next-level-cache = <&L2>;
|
| D | mpc8536si-post.dtsi | 192 L2: l2-cache-controller@20000 { label
196 cache-size = <0x80000>; // L2, 512K
|
| D | mpc8568si-post.dtsi | 148 L2: l2-cache-controller@20000 { label
152 cache-size = <0x80000>; // L2, 512K
|
| D | p1022si-post.dtsi | 197 L2: l2-cache-controller@20000 { label
201 cache-size = <0x40000>; // L2,256K
|
| D | bsc9131si-pre.dtsi | 59 next-level-cache = <&L2>;
|
| D | mpc8548si-pre.dtsi | 64 next-level-cache = <&L2>;
|
| D | mpc8569si-pre.dtsi | 62 next-level-cache = <&L2>;
|
| D | mpc8536si-pre.dtsi | 63 next-level-cache = <&L2>;
|
| D | mpc8568si-pre.dtsi | 63 next-level-cache = <&L2>;
|
| D | p1010si-pre.dtsi | 64 next-level-cache = <&L2>;
|
| D | mpc8544si-pre.dtsi | 63 next-level-cache = <&L2>;
|
| D | c293si-pre.dtsi | 60 next-level-cache = <&L2>;
|
| D | mpc8569si-post.dtsi | 142 L2: l2-cache-controller@20000 { label
146 cache-size = <0x80000>; // L2, 512K
|
| D | p1023si-post.dtsi | 198 L2: l2-cache-controller@20000 { label
202 cache-size = <0x40000>; // L2,256K
|
| D | p1020rdb-pc_32b.dts | 47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
|
| D | p1020mbg-pc_32b.dts | 47 /* NOR and L2 switch */
|
| D | p1020mbg-pc_36b.dts | 47 /* NOR and L2 switch */
|
| D | p1020rdb-pc_36b.dts | 47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
|
| D | p1021rdb-pc_32b.dts | 47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
|
| D | p1021rdb-pc_36b.dts | 47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
|
| D | mpc8560ads.dts | 82 L2: l2-cache-controller@20000 { label
86 cache-size = <0x40000>; // L2, 256K
|
| D | p1020rdb-pd.dts | 47 /* NOR, NAND flash, L2 switch and CPLD */
|
| /linux-4.4.14/Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 10 2 = nbclk (L2 Cache clock)
17 2 = l2clk (L2 Cache clock)
23 2 = l2clk (L2 Cache clock)
37 2 = l2clk (L2 Cache clock derived from CPU0 clock)
|
| /linux-4.4.14/Documentation/networking/ |
| D | ipvlan.txt | 10 the master device share the L2 with it's slave devices. I have developed this
31 IPvlan has two modes of operation - L2 and L3. For a given master device,
38 4.1 L2 mode:
47 master device for the L2 processing and routing from that instance will be
61 namespace where L2 on the slave could be changed / misused.
|
| D | switchdev.txt | 145 L2 networks. VLANs can be applied to sub-divide L2 networks. L2-over-L3
157 L2 Forwarding Offload
160 The idea is to offload the L2 data forwarding (switching) path from the kernel
164 To offloading L2 bridging, the switchdev driver/device should support:
275 Flooding L2 domain
278 For a given L2 VLAN domain, the switch device should flood multicast/broadcast
281 vlan L2 domain, can program the switch device for flooding. The packet may
298 of ports scale in the L2 domain as the device is much more efficient at
|
| D | vxge.txt | 85 are not replicated at the internal L2 switch.
|
| D | vrf.txt | 12 impacts only Layer 3 and above so L2 tools (e.g., LLDP) are not affected
20 L2 separation and then VRF devices provide L3 separation.
|
| /linux-4.4.14/arch/score/lib/ |
| D | string.S | 34 ble .L2
40 beq .L2
54 .L2: label
|
| /linux-4.4.14/arch/m68k/lib/ |
| D | divsi3.S | 101 jpl L2
109 L2: movel d1, sp@- label
|
| D | udivsi3.S | 148 jcs L2 | if no carry,
151 L2: subql IMM (1),d4 label
|
| /linux-4.4.14/arch/alpha/kernel/ |
| D | setup.c | 1354 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1377 L2 = external_cache_probe(128*1024, 5); in determine_cpu_caches()
1391 L2 = (car & 1 ? CSHAPE (size, 3, 1) : -1); in determine_cpu_caches()
1405 L2 = CSHAPE (96*1024, width, 3); in determine_cpu_caches()
1439 L2 = ((cbox_config >> 31) & 1 ? CSHAPE (size, 6, 1) : -1); in determine_cpu_caches()
1441 L2 = external_cache_probe(512*1024, 6); in determine_cpu_caches()
1453 L2 = external_cache_probe(1024*1024, 6); in determine_cpu_caches()
1460 L2 = CSHAPE(7*1024*1024/4, 6, 7); in determine_cpu_caches()
1466 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1472 alpha_l2_cacheshape = L2; in determine_cpu_caches()
|
| /linux-4.4.14/Documentation/zh_CN/arm64/ |
| D | memory.txt | 89 | | | +-----------> [29:21] L2 索引
104 | | +--------------------------> [41:29] L2 索引
|
| /linux-4.4.14/arch/m68k/fpsp040/ |
| D | setox.S | 105 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
498 movew L2,L_SCR1(%a6) | ...prefetch L2, no need in CB
506 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
665 | MOVE.W #$3FDC,L2 ...prefetch L2 in CB mode
672 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
|
| /linux-4.4.14/arch/arm/mach-omap2/ |
| D | sleep44xx.S | 153 ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
315 ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
320 ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
323 ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache
|
| D | sleep34xx.S | 428 cmp r0, #0x1 @ should we disable L2 on 3630?
431 bic r0, r0, #2 @ disable L2 cache
484 mov r12, #0x1 @ set up to invalidate L2
501 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
504 orr r1, r1, #2 @ re-enable L2 cache
|
| /linux-4.4.14/arch/arm/mach-tegra/ |
| D | Kconfig | 34 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
45 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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| /linux-4.4.14/arch/sh/lib/ |
| D | __clear_user.S | 81 .L2: dt r3 define
83 bf/s .L2
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| /linux-4.4.14/arch/arm/plat-omap/ |
| D | Kconfig | 118 bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
122 Without this option, L2 Auxiliary control register contents are
128 int "Service ID for the support routine to set L2 AUX control"
132 PPA routine service ID for setting L2 auxiliary control register.
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| /linux-4.4.14/arch/metag/tbx/ |
| D | tbidspram.S | 77 $L2:
84 BR $L2
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| /linux-4.4.14/arch/arm/mm/ |
| D | proc-xsc3.S | 368 orr r0, r0, #0x18 @ cache the page table in L2
441 orr r1, r1, #0x18 @ cache the page table in L2
457 orr r4, r4, #0x18 @ cache the page table in L2
465 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
472 mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
474 orrne r6, r6, #(1 << 26) @ enable L2 if present
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| D | l2c-l2x0-resume.S | 34 @ and can be written whether or not the L2 cache is enabled
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| D | proc-mohawk.S | 333 orr r0, r0, #0x18 @ cache the page table in L2
378 orr r1, r1, #0x18 @ cache the page table in L2
392 orr r4, r4, #0x18 @ cache the page table in L2
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| D | Kconfig | 880 bool "Enable the Feroceon L2 cache controller"
885 This option enables the Feroceon L2 cache controller.
888 bool "Force Feroceon L2 cache write through"
891 Say Y here to use the Feroceon L2 cache in writethrough mode.
921 The PL310 L2 cache controller implements three types of Clean &
933 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
969 bool "Enable the Tauros2 L2 cache controller"
974 This option enables the Tauros2 L2 cache controller (as
988 bool "Enable the L2 cache on XScale3"
993 This option enables the L2 cache on XScale3.
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| D | proc-feroceon.S | 81 mcr p15, 1, r0, c15, c9, 0 @ clean L2
458 1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
511 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
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| D | proc-v7.S | 315 mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
318 mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
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| /linux-4.4.14/arch/blackfin/kernel/cplb-mpu/ |
| D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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| /linux-4.4.14/arch/blackfin/kernel/cplb-nompu/ |
| D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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| /linux-4.4.14/drivers/net/ethernet/atheros/ |
| D | Kconfig | 20 tristate "Atheros L2 Fast Ethernet support"
25 This driver supports the Atheros L2 fast ethernet adapter.
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| /linux-4.4.14/Documentation/devicetree/bindings/arm/mrvl/ |
| D | feroceon.txt | 8 - reg : Address of the L2 cache control register. Mandatory for
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| D | tauros2.txt | 14 L2: l2-cache {
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| /linux-4.4.14/Documentation/devicetree/bindings/arm/calxeda/ |
| D | l2ecc.txt | 1 Calxeda Highbank L2 cache ECC
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| /linux-4.4.14/Documentation/arm64/ |
| D | memory.txt | 69 | | | +-----------> [29:21] L2 index
84 | | +--------------------------> [41:29] L2 index
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| /linux-4.4.14/net/switchdev/ |
| D | Kconfig | 11 meaning of the word "switch". This include devices supporting L2/L3 but
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| /linux-4.4.14/arch/powerpc/boot/dts/ |
| D | stx_gp3_8560.dts | 41 next-level-cache = <&L2>;
78 L2: l2-cache-controller@20000 { label
82 cache-size = <0x40000>; // L2, 256K
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| D | tqm8541.dts | 42 next-level-cache = <&L2>;
79 L2: l2-cache-controller@20000 { label
83 cache-size = <0x40000>; // L2, 256K
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| D | tqm8555.dts | 42 next-level-cache = <&L2>;
79 L2: l2-cache-controller@20000 { label
83 cache-size = <0x40000>; // L2, 256K
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| D | tqm8540.dts | 43 next-level-cache = <&L2>;
80 L2: l2-cache-controller@20000 { label
84 cache-size = <0x40000>; // L2, 256K
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| D | socrates.dts | 43 next-level-cache = <&L2>;
81 L2: l2-cache-controller@20000 { label
85 cache-size = <0x40000>; // L2, 256K
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| D | sbc8548-pre.dtsi | 43 next-level-cache = <&L2>;
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| D | ksi8560.dts | 43 next-level-cache = <&L2>;
79 L2: l2-cache-controller@20000 { label
83 cache-size = <0x40000>; /* L2, 256K */
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| D | tqm8560.dts | 44 next-level-cache = <&L2>;
81 L2: l2-cache-controller@20000 { label
85 cache-size = <0x40000>; // L2, 256K
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| D | stxssa8555.dts | 44 next-level-cache = <&L2>;
81 L2: l2-cache-controller@20000 { label
85 cache-size = <0x40000>; // L2, 256K
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| D | xpedite5200.dts | 42 next-level-cache = <&L2>;
79 L2: l2-cache-controller@20000 { label
83 cache-size = <0x80000>; // L2, 512K
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| D | xpedite5301.dts | 44 next-level-cache = <&L2>;
57 next-level-cache = <&L2>;
194 L2: l2-cache-controller@20000 { label
198 cache-size = <0x100000>; // L2, 1M
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| D | xpedite5370.dts | 42 next-level-cache = <&L2>;
55 next-level-cache = <&L2>;
192 L2: l2-cache-controller@20000 { label
196 cache-size = <0x100000>; // L2, 1M
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| D | xpedite5200_xmon.dts | 46 next-level-cache = <&L2>;
83 L2: l2-cache-controller@20000 { label
87 cache-size = <0x80000>; // L2, 512K
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| D | tqm8548-bigflash.dts | 44 next-level-cache = <&L2>;
81 L2: l2-cache-controller@20000 { label
85 cache-size = <0x80000>; // L2, 512K
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| D | tqm8548.dts | 44 next-level-cache = <&L2>;
81 L2: l2-cache-controller@20000 { label
85 cache-size = <0x80000>; // L2, 512K
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| D | xpedite5330.dts | 80 next-level-cache = <&L2>;
93 next-level-cache = <&L2>;
230 L2: l2-cache-controller@20000 { label
234 cache-size = <0x100000>; // L2, 1M
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| D | xcalibur1501.dts | 43 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
201 L2: l2-cache-controller@20000 { label
205 cache-size = <0x100000>; // L2, 1M
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| D | sbc8548-post.dtsi | 43 L2: l2-cache-controller@20000 { label
47 cache-size = <0x80000>; // L2, 512K
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| D | arches.dts | 131 0x030 0x008>; /* L2 cache DCR's */
133 cache-size = <262144>; /* L2, 256K */
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| D | taishan.dts | 112 0x030 0x008>; /* L2 cache DCR's */
114 cache-size = <262144>; /* L2, 256K */
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| D | canyonlands.dts | 120 0x030 0x008>; /* L2 cache DCR's */
122 cache-size = <262144>; /* L2, 256K */
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| D | glacier.dts | 113 0x030 0x008>; /* L2 cache DCR's */
115 cache-size = <262144>; /* L2, 256K */
|
| /linux-4.4.14/arch/xtensa/lib/ |
| D | memset.S | 85 bbci.l a4, 3, .L2
90 .L2: label
|
| D | usercopy.S | 178 bbci.l a4, 3, .L2
186 .L2: label
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| D | memcopy.S | 168 bbci.l a4, 3, .L2
176 .L2: label
|
| /linux-4.4.14/Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
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| /linux-4.4.14/drivers/cpufreq/ |
| D | s5pv210-cpufreq.c | 111 L0, L1, L2, L3, L4, enumerator
128 {0, L2, 400*1000},
154 [L2] = {
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| D | exynos5440-cpufreq.c | 93 L0, L1, L2, L3, L4, enumerator
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| /linux-4.4.14/drivers/staging/fsl-mc/bus/ |
| D | Kconfig | 19 or L2 switches.
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| /linux-4.4.14/Documentation/devicetree/bindings/arm/omap/ |
| D | mpu.txt | 5 The MPU contain CPUs, GIC, L2 cache and a local PRCM.
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| /linux-4.4.14/Documentation/devicetree/bindings/net/ |
| D | fsl-tsec-phy.txt | 65 buffer descriptors in the L2.
67 in the L2.
69 buffer to stash in the L2.
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| /linux-4.4.14/Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,l2-intc.txt | 17 - brcm,irq-can-wake: If present, this means the L2 controller can be used as a
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| D | st,sti-irq-syscfg.txt | 5 and PL310 L2 Cache IRQs are controlled using System Configuration registers.
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| D | brcm,bcm3380-l2-intc.txt | 28 - brcm,irq-can-wake: if present, this means the L2 controller can be used as a
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| D | brcm,bcm7120-l2-intc.txt | 70 - brcm,irq-can-wake: if present, this means the L2 controller can be used as a
|
| /linux-4.4.14/arch/metag/mm/ |
| D | Kconfig | 73 Press y here to enable support for the Meta Level 2 (L2) cache. This
77 If the bootloader enables the L2 you must press y here to ensure the
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| /linux-4.4.14/Documentation/locking/ |
| D | rt-mutex-design.txt | 129 Mutexes: L1, L2, L3, L4
133 B owns L2
134 C blocked on L2
142 E->L4->D->L3->C->L2->B->L1->A
156 E->L4->D->L3->C->L2-+
168 blocked on mutex L2:
170 G->L2->B->L1->A
176 +->L2-+
239 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
240 The following shows a locking order of L1->L2->L3, but may not actually
[all …]
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| D | lockdep-design.txt | 86 <L1> -> <L2>
87 <L2> -> <L1>
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| /linux-4.4.14/drivers/net/ethernet/intel/i40e/ |
| D | i40e_common.c | 589 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
590 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
591 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
594 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
595 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
598 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
599 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
600 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
601 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
[all …]
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| /linux-4.4.14/Documentation/devicetree/bindings/timer/ |
| D | marvell,armada-370-xp-timer.txt | 22 "nbclk" (L2/coherency fabric clock),
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| /linux-4.4.14/Documentation/devicetree/bindings/watchdog/ |
| D | marvel.txt | 29 "nbclk" (L2/coherency fabric clock),
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| /linux-4.4.14/net/l2tp/ |
| D | Kconfig | 58 mechanism for tunneling Layer 2 (L2) "circuits" across a
63 L2 protocols, including ATM, Frame Relay, HDLC and even raw
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| /linux-4.4.14/Documentation/devicetree/bindings/misc/ |
| D | fsl,qoriq-mc.txt | 9 such as network interfaces, crypto accelerator instances, L2 switches,
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| /linux-4.4.14/Documentation/virtual/kvm/ |
| D | nested-vmx.txt | 31 call L2.
79 The name "vmcs12" refers to the VMCS that L1 builds for L2. In the code we
81 which L0 builds to actually run L2 - how this is done is explained in the
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| /linux-4.4.14/drivers/staging/fsl-mc/ |
| D | README.txt | 26 autonomous L2 switching, virtual Ethernet bridging, and accelerator
35 interfaces, an L2 switch, or accelerator instances.
219 -DPNI <--> L2-switch-port
221 another DPNI, or L2 switch port. The DPNI connection
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| /linux-4.4.14/drivers/soc/qcom/ |
| D | Kconfig | 18 QCOM Platform specific power driver to manage cores and L2 low power
|
| /linux-4.4.14/Documentation/devicetree/bindings/sound/ |
| D | rt5645.txt | 45 * DMIC L2
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| D | nvidia,tegra-audio-rt5677.txt | 50 "DMIC L2", "Internal Mic 2",
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| /linux-4.4.14/arch/blackfin/mach-bf561/ |
| D | secondary.S | 49 L2 = r6; define
|
| /linux-4.4.14/arch/metag/lib/ |
| D | div64.S | 14 $L2:
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| /linux-4.4.14/arch/blackfin/mach-common/ |
| D | head.S | 58 L2 = r6; define
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| /linux-4.4.14/arch/x86/kernel/cpu/ |
| D | perf_event_intel_ds.c | 59 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
85 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); in precise_store_data()
176 val |= P(TLB, MISS) | P(TLB, L2); in load_latency_data()
178 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); in load_latency_data()
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| /linux-4.4.14/arch/mips/ |
| D | Kconfig.debug | 153 bool "L2 cache debugfs entries"
156 Enable this to allow parts of the L2 cache configuration, such as
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| /linux-4.4.14/Documentation/devicetree/bindings/iommu/ |
| D | samsung,sysmmu.txt | 10 another capabilities like L2 TLB or block-fetch buffers to minimize translation
|
| /linux-4.4.14/Documentation/mmc/ |
| D | mmc-async-req.txt | 24 performance gain is 5% for large writes and 10% on large reads on a L2 cache
|
| /linux-4.4.14/tools/perf/util/ |
| D | parse-events.l | 254 LLC|L2 |
|
| /linux-4.4.14/Documentation/infiniband/ |
| D | ipoib.txt | 37 and so the interface MTU has is equal to the IB L2 MTU minus the
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| /linux-4.4.14/Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 49 modes. In a hierarchical power domain SoC, this means L2 and other caches can
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| /linux-4.4.14/arch/arm64/ |
| D | Kconfig | 222 AXI master interface and an L2 cache.
243 master interface and an L2 cache.
285 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
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| /linux-4.4.14/drivers/net/ |
| D | Kconfig | 156 on packets. All interfaces (including the main interface) share L2
157 making it transparent to the connected L2 switch.
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| /linux-4.4.14/arch/parisc/ |
| D | Kconfig | 153 Select this option for the PCX-L2 processor, as used in the
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| /linux-4.4.14/Documentation/thermal/ |
| D | cpu-cooling-api.txt | 160 region (e.g. CPU, Cluster/L2) in each state (e.g. ON, OFF) at an
|