Searched refs:L2 (Results 1 - 200 of 481) sorted by relevance

123

/linux-4.4.14/arch/metag/include/asm/
H A Dl2cache.h11 * L2 is off).
21 * Functions for reading of L2 cache configuration.
24 /* Get raw L2 config register (CORE_CONFIG3) */ meta_l2c_config()
31 /* Get whether the L2 is present */ meta_l2c_is_present()
37 /* Get whether the L2 is configured for write-back instead of write-through */ meta_l2c_is_writeback()
43 /* Get whether the L2 is unified instead of separated code/data */ meta_l2c_is_unified()
49 /* Get the L2 cache size in bytes */ meta_l2c_size()
61 /* Get the number of ways in the L2 cache */ meta_l2c_ways()
72 /* Get the line size of the L2 cache */ meta_l2c_linesize()
88 /* Get the revision ID of the L2 cache */ meta_l2c_revision()
97 * Start an initialisation of the L2 cachelines and wait for completion.
98 * This should only be done in a LOCK1 or LOCK2 critical section while the L2
109 * Start a writeback of dirty L2 cachelines and wait for completion.
119 /* Set whether the L2 cache is enabled. */ _meta_l2c_enable()
132 /* Set whether the L2 cache prefetch is enabled. */ _meta_l2c_pf_enable()
145 /* Return whether the L2 cache is enabled */ _meta_l2c_is_enabled()
151 /* Return whether the L2 cache prefetch is enabled */ _meta_l2c_pf_is_enabled()
158 /* Return whether the L2 cache is enabled */ meta_l2c_is_enabled()
173 * Ensure the L2 cache is disabled.
174 * Return whether the L2 was previously disabled.
179 * Ensure the L2 cache is enabled.
180 * Return whether the L2 was previously enabled.
184 /* Return whether the L2 cache prefetch is enabled */ meta_l2c_pf_is_enabled()
191 * Set whether the L2 cache prefetch is enabled.
192 * Return whether the L2 prefetch was previously enabled.
197 * Flush the L2 cache.
198 * Return 1 if the L2 is disabled.
203 * Write back all dirty cache lines in the L2 cache.
204 * Return 1 if the L2 is disabled or there isn't any writeback.
216 * Purge only works if the L2 is enabled, and involves reading back to meta_l2c_writeback()
H A Dcache.h12 * With an L2 cache, we may invalidate dirty lines, so we need to ensure DMA
H A Dcacheflush.h173 /* prevent write fence and flushbacks being reordered in L2 */ l2c_fence_flush()
185 /* prevent write fence and writebacks being reordered in L2 */ l2c_fence()
200 /* metag_data_cache_flush won't flush L2 cache lines if size >= 4096 */ flush_dcache_region()
H A Dmetag_mem.h612 #define METAC_CORECFG3_L2C_REV_ID_BITS 0x000F0000 /* Revision of L2 cache */
614 #define METAC_CORECFG3_L2C_LINE_SIZE_BITS 0x00003000 /* L2 line size */
617 #define METAC_CORECFG3_L2C_NUM_WAYS_BITS 0x00000F00 /* L2 number of ways (2^n) */
619 #define METAC_CORECFG3_L2C_SIZE_BITS 0x000000F0 /* L2 size (2^n) */
760 #define SYSC_MCMGID_L2CACHEL 0x30 /* L2 Cache Lines (64-bytes/line) */
761 #define SYSC_MCMGID_L2CACHET 0x31 /* L2 Cache Tags (32-bits/line) */
905 #define PERFCHAN_L2C_MISS 0x6 /* L2 Cache miss */
906 #define PERFCHAN_L2C_HIT 0x7 /* L2 Cache hit */
907 #define PERFCHAN_L2C_WRITEBACK 0x8 /* L2 Cache writeback */
1094 /* L2 Cache registers */
/linux-4.4.14/arch/metag/mm/
H A Dl2cache.c8 /* If non-0, then initialise the L2 cache */
10 /* If non-0, then initialise the L2 cache prefetch */
44 * If the L2 cache isn't even present, don't do anything, but say so in meta_l2c_setup()
48 pr_info("L2 Cache: Not present\n"); meta_l2c_setup()
56 pr_warn_once("L2 Cache: unknown line size id (config=0x%08x)\n", meta_l2c_setup()
66 * Enable the L2 cache and print to log whether it was already enabled meta_l2c_setup()
70 pr_info("L2 Cache: Enabling... "); meta_l2c_setup()
76 pr_info("L2 Cache: Not enabling\n"); meta_l2c_setup()
80 * Enable L2 cache prefetch. meta_l2c_setup()
83 pr_info("L2 Cache: Enabling prefetch... "); meta_l2c_setup()
89 pr_info("L2 Cache: Not enabling prefetch\n"); meta_l2c_setup()
106 * writes will get "lost" when the L2 is disabled. meta_l2c_disable()
130 * Init (clearing the L2) can happen while the L2 is disabled, so other meta_l2c_enable()
/linux-4.4.14/arch/arm/mach-bcm/
H A Dkona_l2_cache.c28 pr_info("Secure API not available (%d). Skipping L2 init.\n", kona_l2_cache_init()
35 pr_err("Secure Monitor call failed (%u)! Skipping L2 init.\n", kona_l2_cache_init()
41 * The aux_val and aux_mask have no effect since L2 cache is already kona_l2_cache_init()
46 pr_err("Couldn't enable L2 cache: %d\n", ret); kona_l2_cache_init()
/linux-4.4.14/include/net/
H A Dfirewire.h4 /* Pseudo L2 address */
18 /* Pseudo L2 Header */
H A Ddn_neigh.h13 #define DN_NDFLAG_R2 0x0002 /* Router L2 */
H A Dip6_tunnel.h20 int link; /* ifindex of underlying L2 interface */
H A Ddn_route.h55 #define DN_RT_INFO_L2RT 0x01 /* L2 Router */
/linux-4.4.14/arch/arm/mm/
H A Dcache-feroceon-l2.c2 * arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support
29 * As well as the regular 'clean/invalidate/flush L2 cache line by
30 * MVA' instructions, the Feroceon L2 cache controller also features
31 * 'clean/invalidate L2 range by MVA' operations.
79 * L2 is PIPT and range operations only do a TLB lookup on l2_clean_pa_range()
110 * L2 is PIPT and range operations only do a TLB lookup on l2_inv_pa_range()
204 * If L2 is forced to WT, the L2 will always be clean and we feroceon_l2_clean_range()
238 * time. These are necessary because the L2 cache can only be enabled
312 * Disable L2 Prefetch bit is set. disable_l2_prefetch()
316 pr_info("Feroceon L2: Disabling L2 prefetch.\n"); disable_l2_prefetch()
329 pr_info("Feroceon L2: Enabling L2\n"); enable_l2()
341 "Feroceon L2: bootloader left the L2 cache on!\n"); enable_l2()
356 pr_info("Feroceon L2: Cache support initialised%s.\n", feroceon_l2_init()
H A Dcache-tauros2.c2 * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
118 "mcr p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t" tauros2_disable()
121 "mcr p15, 0, %0, c1, c0, 0 @Disable L2 Cache\n\t" tauros2_disable()
128 "mcr p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t" tauros2_resume()
131 "mcr p15, 0, %0, c1, c0, 0 @Enable L2 Cache\n\t" tauros2_resume()
188 pr_info("Tauros2: %s L2 prefetch.\n", enable_extra_feature()
214 * v5 CPUs with Tauros2 have the L2 cache enable bit tauros2_internal_init()
219 pr_info("Tauros2: Enabling L2 cache.\n"); tauros2_internal_init()
249 * When Tauros2 is used in an ARMv7 system, the L2 tauros2_internal_init()
256 pr_info("Tauros2: Enabling L2 cache.\n"); tauros2_internal_init()
269 pr_info("Tauros2: L2 cache support initialised " tauros2_internal_init()
H A Dcache-aurora-l2.h2 * AURORA shared L2 cache controller support
H A Dcache-xsc3l2.c2 * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
161 * optimize L2 flush all operation by set/way format
210 pr_info("XScale3 L2 cache enabled.\n"); xsc3_l2_init()
H A Dproc-xsc3.S21 * - L2 cache
44 * The cache line size of the L1 I, L1 D and unified L2 cache.
368 orr r0, r0, #0x18 @ cache the page table in L2
441 orr r1, r1, #0x18 @ cache the page table in L2
457 orr r4, r4, #0x18 @ cache the page table in L2
465 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
472 mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
474 orrne r6, r6, #(1 << 26) @ enable L2 if present
H A Dcache-l2x0.c118 * Enable the L2 cache controller. This function must only be
749 * Cortex-A9 auxiliary control register before disabling the L2 cache. l2c310_disable()
858 * L2 cache size = number of ways * way size. __l2c_init()
1362 * If L2 is forced to WT, the L2 will always be clean and we aurora_clean_range()
1416 * broadcasting of cache commands to L2.
1498 * need to be added to the address before passing it to L2 for
1507 * need to break the L2 operation into two, each within its own section.
1513 * By breaking a single L2 operation into two, we may potentially suffer some
1680 /* Tauros3 broadcasts L1 cache operations to L2 */
1735 /* All L2 caches are unified, so this property should be specified */ l2x0_of_init()
1749 /* L2 configuration can only be changed if the cache is disabled */ l2x0_of_init()
H A Dproc-mohawk.S333 orr r0, r0, #0x18 @ cache the page table in L2
378 orr r1, r1, #0x18 @ cache the page table in L2
392 orr r4, r4, #0x18 @ cache the page table in L2
/linux-4.4.14/arch/mips/include/asm/octeon/
H A Dcvmx-l2c.h168 * Configure one of the four L2 Cache performance counters to capture event
172 * @event: The type of L2 Cache event occurrence to count.
181 * Read the given L2 Cache performance counter. The counter must be configured
191 * Return the L2 Cache way partitioning for a given core.
202 * Partitions the L2 cache for a core
220 * Return the L2 Cache way partitioning for the hw blocks.
229 * Partitions the L2 cache for the hardware blocks.
247 * Locks a line in the L2 cache at the specified physical address
257 * Locks a specified memory region in the L2 cache.
263 * Care should be taken to ensure that enough of the L2 cache is left
275 * Unlock and flush a cache line from the L2 cache.
279 * (If address is not in L2, no lines are flushed.)
289 * Unlocks a region of memory that is locked in the L2 cache
299 * Read the L2 controller tag for a given location in L2
322 * Returns L2 cache index
327 * Flushes (and unlocks) the entire L2 cache.
335 * Returns Returns the size of the L2 cache in bytes,
341 * Return the number of sets in the L2 Cache
348 * Return log base 2 of the number of sets in the L2 cache
353 * Return the number of associations in the L2 Cache
360 * Flush a line from the L2 cache
H A Dcvmx-ipd.h41 CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */
42 CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */
43 CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */
44 CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */
H A Dcvmx-asm.h97 * This is a command headed to the L2 controller to tell it to clear
126 /* load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register */
H A Dcvmx-wqe.h63 /* HW sets to the number of L2 bytes prior to the IP */
65 /* set to 1 if we found DSA/VLAN in the L2 */
270 /* set to 1 if we found DSA/VLAN in the L2 */
349 * in the L2 HDR.
365 * - 18 = L2 header malformed: the packet is not long
366 * enough to contain the L2.
H A Dcvmx-pip.h132 * RGM 10 = length mismatch (len did not match len in L2
159 * cover L2 hdr).
195 * Number of identified L2 multicast packets. Does not
201 * Number of identified L2 broadcast packets. Does not
/linux-4.4.14/arch/blackfin/kernel/cplb-mpu/
H A DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
H A Dcplbinit.c82 /* Cover L2 memory */ generate_cplb_tables_cpu()
/linux-4.4.14/arch/blackfin/kernel/cplb-nompu/
H A DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
H A Dcplbinit.c163 /* Addressing hole up to L2 SRAM. */ generate_cplb_tables_all()
166 /* L2 SRAM. */ generate_cplb_tables_all()
203 /* Addressing hole up to L2 SRAM. */ generate_cplb_tables_all()
206 /* L2 SRAM. */ generate_cplb_tables_all()
/linux-4.4.14/arch/mips/mm/
H A Dsc-mips.c20 * MIPS32/MIPS64 L2 cache handling
46 /* L2 cache is permanently enabled */ mips_sc_enable()
51 /* L2 cache is permanently enabled */ mips_sc_disable()
62 * If there is one or more L2 prefetch unit present then enable mips_sc_prefetch_enable()
120 * Check if the L2 cache controller is activated on a particular platform.
121 * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
122 * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
204 * we configure L2? mips_sc_probe()
H A Dcex-sb1.S44 * the L1 and L2) since it is fetched as 0xa0000100.
107 * in the L2 cache or Memory Controller and cannot be
/linux-4.4.14/arch/x86/include/asm/
H A Dxor_64.h16 /* We force the use of the SSE xor block because it can write around L2.
/linux-4.4.14/arch/c6x/kernel/
H A Dhead.S24 SUB .L2 B6,B5,B6 ; bss size
33 ZERO .L2 B13
34 ZERO .L2 B12
38 CMPLT .L2 B0,0,B1
H A Dswitch_to.S51 || MV .L2 B6,B14
H A Dentry.S123 MVK .L2 0,B1
221 CMPLTU .L2 B0,B1,B1
327 MVK .L2 1,B2
339 CMPLTU .L2 B0,B1,B1
401 MVK .L2 0,B0
521 CMPEQ .L2 1,B2,B2
594 MVK .L2 0xc,B1
700 MV .L2 B4,B5
709 MV .L2 B8,B6
/linux-4.4.14/arch/hexagon/include/asm/
H A Dvm_mmu.h47 /* Masks for L2 page table pointer, as function of page size */
69 #define __HEXAGON_C_WB 0x0 /* Write-back, no L2 */
70 #define __HEXAGON_C_WT 0x1 /* Write-through, no L2 */
77 #define __HEXAGON_C_WT_L2 0x5 /* Write-through, with L2 */
78 #define __HEXAGON_C_WB_L2 0x7 /* Write-back, with L2 */
/linux-4.4.14/arch/powerpc/platforms/85xx/
H A Dxes_mpc85xx.c39 #define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */
40 #define MPC85xx_L2CTL_L2I 0x40000000 /* L2 flash invalidate */
41 #define MPC85xx_L2CTL_L2SIZ_MASK 0x30000000 /* L2 SRAM size (R/O) */
59 * xMon may have enabled part of L2 as SRAM, so we need to set it xes_mpc85xx_configure_l2()
62 printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n"); xes_mpc85xx_configure_l2()
68 * Assume L2 SRAM is used fully for cache, so set xes_mpc85xx_configure_l2()
84 * Legacy xMon firmware on some X-ES boards does not enable L2 xes_mpc85xx_fixups()
/linux-4.4.14/arch/powerpc/platforms/powermac/
H A Dcache.S22 * Flush and disable all data caches (dL1, L2, L3). This is used
107 /* When disabling L2, code must be in L1 */
117 1: /* disp-flush L2. The interesting thing here is that the L2 can be
138 /* now disable L2 */
141 /* When disabling L2, code must be in L1 */
153 /* Invalidate L2. This is pre-745x, we clear the L2I bit ourselves */
206 /* Disable L2 prefetching */
273 /* Flush the L2 cache using the hardware assist */
279 /* When disabling/locking L2, code must be in L1 */
281 1: mtspr SPRN_L2CR,r0 /* lock the L2 cache */
300 /* When disabling L2, code must be in L1 */
302 1: mtspr SPRN_L2CR,r3 /* disable the L2 cache */
/linux-4.4.14/arch/arc/kernel/
H A Dentry-compact.S169 ; if L2 IRQ interrupted a L1 ISR, disable preemption
171 ; This is to avoid a potential L1-L2-L1 scenario
173 ; -L2 interrupts L1 (before L1 ISR could run)
176 ; Returns from L2 context fine
177 ; But both L1 and L2 re-enabled, so another L1 can be taken
182 ; L2 interrupting L1 implies both L2 and L1 active
187 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
226 ; out of the L2 interrupt context (drop to pure kernel mode) and jump
349 ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
364 ; However the context returning might not have taken L2 intr itself
365 ; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
366 ; Special considerations needed for the context which took L2 intr
368 ld r9, [sp, PT_event] ; Ensure this is L2 intr context
372 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
375 ; things to what they were, before returning from L2 context
379 bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
H A Dintc-compact.c138 * Now hardware context wise we may still be in L2 ISR (not done rtie)
139 * still we must re-enable both L1 and L2 IRQs
141 * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR
/linux-4.4.14/arch/powerpc/sysdev/
H A Dfsl_85xx_l2ctlr.c4 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
88 dev_err(&dev->dev, "Missing L2 cache-size\n"); mpc85xx_l2ctlr_of_probe()
95 "Entire L2 as cache, provide valid sram offset and size\n"); mpc85xx_l2ctlr_of_probe()
109 dev_err(&dev->dev, "Can't map L2 controller\n"); mpc85xx_l2ctlr_of_probe()
169 dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n"); mpc85xx_l2ctlr_of_remove()
232 MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init");
H A Dfsl_85xx_cache_ctlr.h26 #define L2CR_L2FI 0x40000000 /* L2 flash invalidate */
27 #define L2CR_L2IO 0x00200000 /* L2 instruction only */
51 u32 ctl; /* 0x000 - L2 control */
H A Dppc4xx_soc.c6 * L2 cache routines cloned from arch/ppc/syslib/ibm440gx_common.c which is:
32 * L2-cache
187 printk(KERN_INFO "%dk L2-cache enabled\n", l2_size >> 10); ppc4xx_l2c_probe()
/linux-4.4.14/arch/parisc/kernel/
H A Dhardware.c107 {HPHW_NPROC,0x501,0x4,0x81,"Merlin L2 132 (9000/778/B132L)"},
108 {HPHW_NPROC,0x502,0x4,0x81,"Merlin L2 160 (9000/778/B160L)"},
109 {HPHW_NPROC,0x503,0x4,0x81,"Merlin L2+ 132 (9000/778/B132L)"},
110 {HPHW_NPROC,0x504,0x4,0x81,"Merlin L2+ 180 (9000/778/B180L)"},
111 {HPHW_NPROC,0x505,0x4,0x81,"Raven L2 132 (9000/778/C132L)"},
112 {HPHW_NPROC,0x506,0x4,0x81,"Raven L2 160 (9000/779/C160L)"},
113 {HPHW_NPROC,0x507,0x4,0x81,"Raven L2 180 (9000/779/C180L)"},
114 {HPHW_NPROC,0x508,0x4,0x81,"Raven L2 160 (9000/779/C160L)"},
115 {HPHW_NPROC,0x509,0x4,0x81,"712/132 L2 Upgrade"},
116 {HPHW_NPROC,0x50A,0x4,0x81,"712/160 L2 Upgrade"},
117 {HPHW_NPROC,0x50B,0x4,0x81,"715/132 L2 Upgrade"},
118 {HPHW_NPROC,0x50C,0x4,0x81,"715/160 L2 Upgrade"},
119 {HPHW_NPROC,0x50D,0x4,0x81,"Rocky2 L2 120"},
120 {HPHW_NPROC,0x50E,0x4,0x81,"Rocky2 L2 150"},
121 {HPHW_NPROC,0x50F,0x4,0x81,"Anole L2 132 (744)"},
122 {HPHW_NPROC,0x510,0x4,0x81,"Anole L2 165 (744)"},
123 {HPHW_NPROC,0x511,0x4,0x81,"Kiji L2 132"},
124 {HPHW_NPROC,0x512,0x4,0x81,"UL L2 132 (803/D220,D320)"},
125 {HPHW_NPROC,0x513,0x4,0x81,"UL L2 160 (813/D220,D320)"},
126 {HPHW_NPROC,0x514,0x4,0x81,"Merlin Jr L2 132"},
127 {HPHW_NPROC,0x515,0x4,0x81,"Staccato L2 132"},
128 {HPHW_NPROC,0x516,0x4,0x81,"Staccato L2 180 (A Class 180)"},
365 {HPHW_A_DMA, 0x03B, 0x00089, 0x80, "Raven U/L2 Core FW-SCSI"},
436 {HPHW_BA, 0x04A, 0x00078, 0x0, "Anole L2 132 VME BA"},
437 {HPHW_BA, 0x04C, 0x00078, 0x0, "Anole L2 165 VME BA"},
461 {HPHW_BA, 0x035, 0x00081, 0x0, "PCX-L2 712/132 Core BA"},
462 {HPHW_BA, 0x036, 0x00081, 0x0, "PCX-L2 712/160 Core BA"},
463 {HPHW_BA, 0x03B, 0x00081, 0x0, "Raven U/L2 Core BA"},
472 {HPHW_BA, 0x04B, 0x00081, 0x0, "Anole L2 132 Core BA"},
473 {HPHW_BA, 0x04D, 0x00081, 0x0, "Anole L2 165 Core BA"},
474 {HPHW_BA, 0x04E, 0x00081, 0x0, "Kiji L2 132 Core BA"},
510 {HPHW_BA, 0x05A, 0x0008E, 0x0, "Raven+ L2 Backplane w/EISA Wax BA"},
534 {HPHW_BA, 0x05A, 0x00090, 0x0, "Raven L2 Backplane Wax EISA BA"},
541 {HPHW_BA, 0x04A, 0x00093, 0x0, "Anole L2 132 TIMI BA"},
542 {HPHW_BA, 0x04C, 0x00093, 0x0, "Anole L2 165 TIMI BA"},
692 {HPHW_FIO, 0x05A, 0x00073, 0x0, "Raven+ L2 Backplane w/EISA Wax HIL"},
693 {HPHW_FIO, 0x05B, 0x00073, 0x0, "Raven+ L2 Backplane wo/EISA Wax HIL"},
736 {HPHW_FIO, 0x035, 0x00074, 0x0, "PCX-L2 712/132 Core Centronics"},
737 {HPHW_FIO, 0x036, 0x00074, 0x0, "PCX-L2 712/160 Core Centronics"},
738 {HPHW_FIO, 0x03B, 0x00074, 0x0, "Raven U/L2 Core Centronics"},
747 {HPHW_FIO, 0x04B, 0x00074, 0x0, "Anole L2 132 Core Centronics"},
748 {HPHW_FIO, 0x04D, 0x00074, 0x0, "Anole L2 165 Core Centronics"},
830 {HPHW_FIO, 0x035, 0x0007B, 0x0, "PCX-L2 712/132 Core Audio"},
831 {HPHW_FIO, 0x036, 0x0007B, 0x0, "PCX-L2 712/160 Core Audio"},
832 {HPHW_FIO, 0x03B, 0x0007B, 0x0, "Raven U/L2 Core Audio"},
840 {HPHW_FIO, 0x04B, 0x0007B, 0x0, "Anole L2 132 Core Audio"},
841 {HPHW_FIO, 0x04D, 0x0007B, 0x0, "Anole L2 165 Core Audio"},
842 {HPHW_FIO, 0x04E, 0x0007B, 0x0, "Kiji L2 132 Core Audio"},
882 {HPHW_FIO, 0x035, 0x00082, 0x0, "PCX-L2 712/132 Core SCSI"},
883 {HPHW_FIO, 0x036, 0x00082, 0x0, "PCX-L2 712/160 Core SCSI"},
884 {HPHW_FIO, 0x03B, 0x00082, 0x0, "Raven U/L2 Core SCSI"},
893 {HPHW_FIO, 0x04B, 0x00082, 0x0, "Anole L2 132 Core SCSI"},
894 {HPHW_FIO, 0x04D, 0x00082, 0x0, "Anole L2 165 Core SCSI"},
895 {HPHW_FIO, 0x04E, 0x00082, 0x0, "Kiji L2 132 Core SCSI"},
921 {HPHW_FIO, 0x035, 0x00083, 0x0, "PCX-L2 712/132 Core Floppy"},
922 {HPHW_FIO, 0x036, 0x00083, 0x0, "PCX-L2 712/160 Core Floppy"},
923 {HPHW_FIO, 0x03B, 0x00083, 0x0, "Raven U/L2 Core PC Floppy"},
931 {HPHW_FIO, 0x04E, 0x00083, 0x0, "Kiji L2 132 Core PC Floppy"},
956 {HPHW_FIO, 0x035, 0x00084, 0x0, "PCX-L2 712/132 Core PS/2 Port"},
957 {HPHW_FIO, 0x036, 0x00084, 0x0, "PCX-L2 712/160 Core PS/2 Port"},
958 {HPHW_FIO, 0x03B, 0x00084, 0x0, "Raven U/L2 Core PS/2 Port"},
969 {HPHW_FIO, 0x04B, 0x00084, 0x0, "Anole L2 132 Core PS/2 Port"},
970 {HPHW_FIO, 0x04D, 0x00084, 0x0, "Anole L2 165 Core PS/2 Port"},
971 {HPHW_FIO, 0x04E, 0x00084, 0x0, "Kiji L2 132 Core PS/2 Port"},
997 {HPHW_FIO, 0x035, 0x00085, 0x0, "PCX-L2 712/132 Core Graphics"},
998 {HPHW_FIO, 0x036, 0x00085, 0x0, "PCX-L2 712/160 Core Graphics"},
999 {HPHW_FIO, 0x03B, 0x00085, 0x0, "Raven U/L2 Core Graphics"},
1007 {HPHW_FIO, 0x04B, 0x00085, 0x0, "Anole L2 132 Core Graphics"},
1008 {HPHW_FIO, 0x04D, 0x00085, 0x0, "Anole L2 165 Core Graphics"},
1009 {HPHW_FIO, 0x04E, 0x00085, 0x0, "Kiji L2 132 Core Graphics"},
1026 {HPHW_FIO, 0x04A, 0x00088, 0x0, "Anole L2 132 VME Networking"},
1027 {HPHW_FIO, 0x04C, 0x00088, 0x0, "Anole L2 165 VME Networking"},
1051 {HPHW_FIO, 0x035, 0x0008A, 0x0, "PCX-L2 712/132 Core LAN (802.3)"},
1052 {HPHW_FIO, 0x036, 0x0008A, 0x0, "PCX-L2 712/160 Core LAN (802.3)"},
1053 {HPHW_FIO, 0x03B, 0x0008A, 0x0, "Raven U/L2 Core LAN (802.3)"},
1060 {HPHW_FIO, 0x04B, 0x0008A, 0x0, "Anole L2 132 Core LAN (802.3)"},
1061 {HPHW_FIO, 0x04D, 0x0008A, 0x0, "Anole L2 165 Core LAN (802.3)"},
1062 {HPHW_FIO, 0x04E, 0x0008A, 0x0, "Kiji L2 132 Core LAN (802.3)"},
1069 {HPHW_FIO, 0x006, 0x0008C, 0x0, "Raven U/L2 Dino RS-232"},
1109 {HPHW_FIO, 0x035, 0x0008C, 0x0, "PCX-L2 712/132 Core RS-232"},
1110 {HPHW_FIO, 0x036, 0x0008C, 0x0, "PCX-L2 712/160 Core RS-232"},
1112 {HPHW_FIO, 0x03B, 0x0008C, 0x0, "Raven U/L2 Core RS-232"},
1126 {HPHW_FIO, 0x04A, 0x0008C, 0x0, "Anole L2 132 TIMI RS-232"},
1127 {HPHW_FIO, 0x04B, 0x0008C, 0x0, "Anole L2 l32 Core RS-232"},
1128 {HPHW_FIO, 0x04C, 0x0008D, 0x0, "Anole L2 165 TIMI RS-232"},
1129 {HPHW_FIO, 0x04D, 0x0008C, 0x0, "Anole L2 165 Core RS-232"},
1130 {HPHW_FIO, 0x04E, 0x0008C, 0x0, "Kiji L2 132 Core RS-232"},
1131 {HPHW_FIO, 0x04F, 0x0008C, 0x0, "Kiji L2 132 Dino RS-232"},
1142 {HPHW_FIO, 0x05A, 0x0008C, 0x0, "Raven+ L2 Backplane w EISA RS-232"},
1143 {HPHW_FIO, 0x05B, 0x0008C, 0x0, "Raven+ L2 Backplane w/o EISA RS-232"},
1158 {HPHW_FIO, 0x006, 0x00096, 0x0, "Raven U/L2 Dino PS/2 Port"},
1223 {HPHW_MEMORY, 0x063, 0x00009, 0x00, "712/132 L2 Upgrade"},
1224 {HPHW_MEMORY, 0x064, 0x00009, 0x00, "712/160 L2 Upgrade"},
1225 {HPHW_MEMORY, 0x065, 0x00009, 0x00, "715/132 L2 Upgrade"},
1226 {HPHW_MEMORY, 0x066, 0x00009, 0x00, "715/160 L2 Upgrade"},
1328 [pcxl2] = { "PA7300LC (PCX-L2)", "1.1e" },
/linux-4.4.14/arch/blackfin/kernel/
H A Dkgdb_test.c44 pr_alert("L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); kgdb_l2_test()
45 pr_alert("L2 : code function addr = 0x%p\n", kgdb_l2_test); kgdb_l2_test()
47 pr_alert("L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); kgdb_l2_test()
H A DMakefile39 # the kgdb test puts code into L2 and without linker
H A Dmodule.c102 pr_err("L2 SRAM allocation failed\n"); module_frob_arch_sections()
114 pr_err("L2 SRAM allocation failed\n"); module_frob_arch_sections()
126 pr_err("L2 SRAM allocation failed\n"); module_frob_arch_sections()
H A Dsetup.c133 printk(KERN_INFO " L2 SRAM :" bfin_setup_caches()
157 printk(KERN_INFO " L2 SRAM :" bfin_setup_caches()
230 /* if necessary, copy L2 text/data to L2 SRAM */ bfin_relocate_l1_mem()
1364 "%d KB(L1 dcache) %d KB(L2 cache)\n", show_cpuinfo()
1407 seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); show_cpuinfo()
1408 seq_printf(m, "L2 SRAM\t\t: " show_cpuinfo()
1415 seq_printf(m, "L2 SRAM\t\t: " show_cpuinfo()
H A Dpseudodbg.c16 "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3",
H A Dvmlinux.lds.S247 ASSERT (__l2_len <= L2_LENGTH, "L2 overflow!")
/linux-4.4.14/arch/c6x/platforms/
H A Dcache.c110 * L1 & L2 caches generic functions
285 * L2 caches management
289 * Set L2 operation mode
303 * L2 global-writeback and global-invalidate all
313 * L2 global-writeback all
378 * L2 block operations
425 * L1 and L2 caches configuration
442 /* Set L2 caches on the the whole L2 SRAM memory */ c6x_cache_init()
/linux-4.4.14/arch/ia64/lib/
H A Dcopy_page_mck.S20 * First, note that L1 has a line-size of 64 bytes and L2 a line-size of 128 bytes.
21 * To avoid secondary misses in L2, we prefetch both source and destination with a line-size
22 * of 128 bytes. When both of these lines are in the L2 and the first half of the
33 * should be prefetched, p[C] is TRUE if the second half of an L2 line should be brought
52 * | n[y] | t9 | | (L2 cache line)
59 * to fetch the second-half of the L2 cache line into L1, and the tX words are copied in
65 #define PREFETCH_DIST 8 // McKinley sustains 16 outstanding L2 misses (8 ld, 8 st)
144 (p[D]) st8 [dst_pre_l2] = n[D-C], 128 // M3 prefetch dst from L2
147 (p[C]) ld8 n[0] = [src_pre_l2], 128 // M1 prefetch src from L2
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Dvid.h214 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
215 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
219 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
239 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
240 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
242 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */
263 * 1 - TC/L2
293 * 3 - DST_ADDR using L2
305 * 3 - SRC_ADDR using L2
H A Dcikd.h329 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
330 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
334 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
354 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
355 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
357 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */
378 * 1 - TC/L2
408 * 3 - DST_ADDR using L2
420 * 3 - SRC_ADDR using L2
/linux-4.4.14/include/uapi/linux/
H A Dip6_tunnel.h24 int link; /* ifindex of underlying L2 interface */
36 int link; /* ifindex of underlying L2 interface */
H A Datmsap.h22 #define ATM_L2_NONE 0 /* L2 not specified */
/linux-4.4.14/sound/soc/codecs/
H A Drt5640.c537 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_STO_DAC_MIXER,
555 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_STO_DAC_MIXER,
569 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
580 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
587 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_DIG_MIXER,
637 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_SPK_L_MIXER,
667 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_L3_MIXER,
684 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_R3_MIXER,
768 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_MIXER,
827 "DMIC L1", "DMIC L2", "Mono DAC MIXL"
1079 SND_SOC_DAPM_PGA("DMIC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
1111 SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1119 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1267 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dac_l2_mux),
1277 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5640_PWR_DIG1, RT5640_PWR_DAC_L2_BIT,
1305 SND_SOC_DAPM_SUPPLY("DAC L2 Filter", RT5640_PWR_DIG1,
1328 {"DMIC L2", NULL, "DMIC2"},
1362 {"DMIC L2", NULL, "DMIC CLK"},
1363 {"DMIC L2", NULL, "DMIC2 Power"},
1367 {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
1368 {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
1369 {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
1379 {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
1380 {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
1381 {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
1392 {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
1402 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
1564 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1565 {"DAC L2 Mux", "Base L/R", "Audio DSP"},
1569 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1574 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1578 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
1581 {"DIG MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1583 {"DAC L2", NULL, "Mono DAC MIXL"},
1584 {"DAC L2", NULL, "PLL1", is_sys_clk_from_pll},
1588 {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
1595 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
1597 {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
1600 {"HPO MIX L", "HPO MIX DAC2 Switch", "DAC L2"},
1604 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
1615 {"Stereo DAC MIXL", "DAC L2 Switch", "IF2 DAC L"},
1618 {"Mono DAC MIXL", "DAC L2 Switch", "IF2 DAC L"},
1622 {"Mono DAC MIXR", "DAC L2 Switch", "IF2 DAC L"},
1624 {"DIG MIXL", "DAC L2 Switch", "IF2 DAC L"},
1627 {"IF2 DAC L", NULL, "DAC L2 Filter"},
H A Drt5645.c887 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
905 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
916 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
923 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
934 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
968 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
992 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
1808 SND_SOC_DAPM_INPUT("DMIC L2"),
1854 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1866 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1946 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1948 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1979 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
2115 { "DMIC2", NULL, "DMIC L2" },
2149 {"DMIC L2", NULL, "DMIC CLK"},
2150 {"DMIC L2", NULL, "DMIC2 Power"},
2159 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
2166 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2167 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2176 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2177 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2187 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2200 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2254 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2255 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2256 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2257 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2258 { "DAC L2 Volume", NULL, "dac mono left filter" },
2268 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2276 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2281 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2285 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2289 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2293 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
2299 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2307 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2316 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2326 { "DAC 2", NULL, "DAC L2" },
2395 { "DAC L2", NULL, "A DAC2 L Mux" },
2469 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2476 { "DAC L2", NULL, "Mono DAC MIXL" },
2527 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
H A Drt5670.c917 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_STO_DAC_MIXER,
935 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
946 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
953 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
964 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
992 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_OUT_L1_MIXER,
1177 SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5670_stereo1_adc2_enum);
1186 SOC_DAPM_ENUM("Stereo2 ADC L2 source", rt5670_stereo2_adc2_enum);
1588 SND_SOC_DAPM_INPUT("DMIC L2"),
1643 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1653 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1667 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1794 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
1798 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5670_PWR_DIG1,
1839 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5670_PWR_DIG1,
1937 { "DMIC2", NULL, "DMIC L2" },
1970 { "DMIC L2", NULL, "DMIC CLK" },
1971 { "DMIC L2", NULL, "DMIC2 Power" },
1988 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
1998 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1999 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2008 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2009 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2019 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2032 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2041 { "Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2042 { "Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2052 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux" },
2192 { "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
2193 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2194 { "DAC L2 Mux", "TxDC DAC", "TxDC_DAC" },
2195 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2196 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2197 { "DAC L2 Volume", NULL, "DAC Mono Left Filter" },
2208 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2218 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2223 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2227 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2231 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2237 { "DAC L2", NULL, "Mono DAC MIXL" },
2242 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2255 { "DAC 2", NULL, "DAC L2" },
H A Drt5651.c454 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER,
472 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
483 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
646 SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum);
975 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
983 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1050 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux),
1052 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1179 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1180 {"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"},
1189 {"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"},
1190 {"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"},
1200 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1210 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
1254 {"DAC L2 Mux", "IF1", "IF1 DAC2 L"},
1255 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1256 {"DAC L2 Volume", NULL, "DAC L2 Mux"},
1263 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1286 {"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1292 {"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"},
H A Dtwl4030.c1232 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1244 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1401 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1415 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1419 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1427 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1433 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1440 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1445 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1455 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1465 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1473 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
1567 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1576 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
H A Dwm8983.c319 SOC_DAPM_SINGLE("L2 Switch", WM8983_INPUT_CTRL, 2, 1, 0),
331 SOC_DAPM_SINGLE_TLV("L2 Volume", WM8983_LEFT_ADC_BOOST_CTRL,
423 SND_SOC_DAPM_INPUT("L2"),
478 { "Left Boost Mixer", "L2 Volume", "L2" },
487 { "Left Input Mixer", "L2 Switch", "L2" },
H A Dwm8985.c399 SOC_DAPM_SINGLE("L2 Switch", WM8985_INPUT_CTRL, 2, 1, 0),
411 SOC_DAPM_SINGLE_TLV("L2 Volume", WM8985_LEFT_ADC_BOOST_CTRL,
473 SND_SOC_DAPM_INPUT("L2"),
512 { "Left Boost Mixer", "L2 Volume", "L2" },
521 { "Left Input Mixer", "L2 Switch", "L2" },
/linux-4.4.14/arch/c6x/lib/
H A Dcsum_64plus.S57 || ADD .L2 B8,B9,B9
83 CMPGT .L2 B5,0,B0
193 CMPGT .L2 B0,0,B1
293 CMPGT .L2 B4,0,B0
299 || MV .L2 B4,B3
303 [A0] SUB .L2 B3,1,B3
308 SUB .L2 B3,1,B3
319 SUB .L2 B0,1,B0
347 MVK .L2 2,B0
348 AND .L2 B3,B0,B0
/linux-4.4.14/arch/tile/include/asm/
H A Dcache.h24 /* bytes per L2 cache line */
32 * L2 cacheline size helps ensure that kernel heap allocations are aligned.
42 /* use the cache line size for the L2, which is where it counts */
H A Dpgalloc.h28 /* How big is a kernel L2 page table? */
31 /* We currently allocate user L2 page tables by page (unlike kernel L2s). */
38 /* How many pages do we need, as an "order", for a user L2 page table? */
131 /* How big is a kernel L2 page table? */
H A Dcacheflush.h78 /* Flush a VA range; pads to L2 cacheline boundaries. */ __flush_buffer()
89 /* Flush & invalidate a VA range; pads to L2 cacheline boundaries. */ __finv_buffer()
122 /* Invalidate a VA range; pads to L2 cacheline boundaries. */ __inv_buffer()
H A Dpgtable_32.h49 * end of the page table (e.g. where our L2 page tables are 2KB but
64 * Align the vmalloc area to an L2 page table, and leave a guard page
H A Dpage.h90 * User L2 page tables are managed as one L2 page table per page,
92 * simple, but it's also inefficient, since L2 page tables are much smaller
H A Dfutex.h101 * fault; instead we do a prefetch into the L2.
H A Dhomecache.h30 * It is not present in any cache (L1 or L2).
H A Dpgtable_64.h50 * Align the vmalloc area to an L2 page table. Omit guard pages at
/linux-4.4.14/arch/arm/mach-imx/
H A Dsystem.c109 /* Configure the L2 PREFETCH and POWER registers */ imx_init_l2cache()
113 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 imx_init_l2cache()
114 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 imx_init_l2cache()
H A Dmm-imx3.c93 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These imx3_init_l2x0()
94 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. imx3_init_l2x0()
96 * L2 cache. This should not hurt already working CPUs, as they are using the imx3_init_l2x0()
106 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); imx3_init_l2x0()
111 printk(KERN_ERR "remapping L2 cache area failed\n"); imx3_init_l2x0()
H A Dsuspend-imx6.S79 /* sync L2 cache to drain L2's buffers to DRAM. */
188 /* need to sync L2 cache before DSM. */
/linux-4.4.14/drivers/irqchip/
H A Dirq-brcmstb-l2.c35 /* Register offsets in the L2 interrupt controller */
43 /* L2 intc private data structure */
131 pr_err("failed to remap intc L2 registers\n"); brcmstb_l2_intc_of_init()
202 pr_info("registered L2 intc (mem: 0x%p, parent irq: %d)\n", brcmstb_l2_intc_of_init()
H A Dirq-bcm7120-l2.c32 /* Register offset in the L2 interrupt controller */
346 "BCM7120 L2"); bcm7120_l2_intc_probe_7120()
353 "BCM3380 L2"); bcm7120_l2_intc_probe_3380()
/linux-4.4.14/arch/powerpc/include/asm/
H A Dfsl_pamu_stash.h36 u32 cache; /* cache to stash to: L1,L2,L3 */
H A Dreg.h519 #define L2CR_L2E 0x80000000 /* L2 enable */
520 #define L2CR_L2PE 0x40000000 /* L2 parity enable */
521 #define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
522 #define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
523 #define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
524 #define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
525 #define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
526 #define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
527 #define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
528 #define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
529 #define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
530 #define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
531 #define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
532 #define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
533 #define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
534 #define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
535 #define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
536 #define L2CR_L2DO 0x00400000 /* L2 data only */
537 #define L2CR_L2I 0x00200000 /* L2 global invalidate */
538 #define L2CR_L2CTL 0x00100000 /* L2 RAM control */
539 #define L2CR_L2WT 0x00080000 /* L2 write-through */
540 #define L2CR_L2TS 0x00040000 /* L2 test support */
541 #define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
542 #define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
543 #define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
544 #define L2CR_L2SL 0x00008000 /* L2 DLL slow */
545 #define L2CR_L2DF 0x00004000 /* L2 differential clock */
546 #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
547 #define L2CR_L2IP 0x00000001 /* L2 GI in progress */
548 #define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */
549 #define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */
550 #define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */
551 #define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */
H A Dreg_booke.h182 #define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */
183 #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
284 #define MCSR_BSL2_ERR 0x00000001UL /* Backside L2 cache error */
623 #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
624 #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
625 #define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
626 #define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
627 #define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
628 #define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
629 #define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
630 #define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
631 #define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
632 #define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
633 #define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
634 #define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
H A Dpte-8xx.h37 /* These 4 software bits must be masked out when the L2 entry is loaded
/linux-4.4.14/arch/mips/include/asm/sibyte/
H A Dbcm1480_l2c.h4 * L2 Cache constants and macros File: bcm1480_l2c.h
104 * L2 Misc0 Value Register (Table 60)
135 * L2 Misc1 Value Register (Table 60)
160 * L2 Misc2 Value Register (Table 60)
H A Dsb1250_l2c.h4 * L2 Cache constants and macros File: sb1250_l2c.h
111 * L2 Read Misc. register (A_L2_READ_MISC)
/linux-4.4.14/arch/parisc/include/asm/
H A Dcache.h10 * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
H A Dpgalloc.h14 * Here (for 64 bit kernels) we implement a Hybrid L2/L3 scheme: we
18 * process access to 8TB) so our lookups are effectively L2 for the
/linux-4.4.14/arch/arm/mach-exynos/
H A Dsmc.h24 /* For L2 Cache Access */
H A Dmcpm-exynos.c140 * L2 prefetching before flushing the cache. exynos_cluster_cache_disable()
281 * in a cluster are turned off before turning off the cluster L2. exynos_mcpm_init()
286 * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be exynos_mcpm_init()
H A Dfirmware.c221 * running under secure firmware, require certain registers of L2 exynos_firmware_init()
/linux-4.4.14/drivers/cpuidle/
H A Dcpuidle-mvebu-v7.c66 .desc = "CPU and L2 Fabric power down",
81 .desc = "CPU and L2 Fabric power down",
H A Dcpuidle-big_little.c56 * shutdown has inherent dynamic power costs (L2 writebacks to DRAM
59 * of L2 lines are dirty and require cleaning to DRAM, and takes into
/linux-4.4.14/arch/c6x/include/asm/
H A Dcache.h30 * L2 used as cache
36 * the L2 line size
/linux-4.4.14/arch/arm/mach-spear/
H A Dspear13xx.c32 * for some spear13xx devices for stable L2 operation. spear13xx_l2x0_init()
34 * Enable Early BRESP, L2 prefetch for Instruction and Data, spear13xx_l2x0_init()
/linux-4.4.14/arch/arm/include/asm/mach/
H A Darch.h47 unsigned l2c_aux_val; /* L2 cache aux value */
48 unsigned l2c_aux_mask; /* L2 cache aux mask */
/linux-4.4.14/arch/arm/mach-omap2/
H A Dsleep44xx.S49 * 3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
140 * Clean and invalidate the L2 cache.
153 ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
283 * Restore the L2 AUXCTRL and enable the L2 cache.
285 * OMAP4_MON_L2X0_CTRL_INDEX = Enable the L2 using L2X0 CTRL
287 * L2 cache is already invalidate by ROM code as part
315 ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
320 ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
323 ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache
H A Dsleep34xx.S81 * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
167 * 2 - Only L2 lost (Even L1 is retained we clean it along with L2)
168 * 3 - Both L1 and L2 lost and logic lost
428 cmp r0, #0x1 @ should we disable L2 on 3630?
431 bic r0, r0, #2 @ disable L2 cache
463 /* Restore L2 aux control register */
483 /* Execute smi to invalidate L2 cache */
484 mov r12, #0x1 @ set up to invalidate L2
501 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
504 orr r1, r1, #2 @ re-enable L2 cache
H A Dpm34xx.c176 /* Read L2 AUX ctrl register */ omap34xx_save_context()
194 /* save_state = 2 => Only L2 lost */ omap_sram_idle()
195 /* save_state = 3 => L1, L2 and logic lost */ omap_sram_idle()
/linux-4.4.14/drivers/edac/
H A Dmce_amd.c44 static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
65 "UC during a demand linefill from L2",
95 "L2 Tag ECC error", /* xec = 0x10 */
96 "Hard L2 Tag ECC error",
97 "Multiple hits on L2 tag",
159 pr_cont("during L1 linefill from L2.\n"); f12h_mc0_mce()
251 pr_cont("UC error during a linefill from L2/NB.\n"); f15h_mc0_mce()
322 pr_cont("during a linefill from L2.\n"); k8_mc1_mce()
441 pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec)); k8_mc2_mce()
457 "access from L2.\n", R4_MSG(ec)); k8_mc2_mce()
521 pr_cont("ECC error in L2 tag (%s).\n", f16h_mc2_mce()
528 pr_cont("ECC error in L2 data array (%s).\n", f16h_mc2_mce()
536 pr_cont("Parity error in L2 attribute bits (%s).\n", f16h_mc2_mce()
H A Dedac_core.h105 * CPU caches (L1 and L2)
115 * cache could be composed of L1, L2 and L3 levels of cache.
117 * L2 and maybe L3 caches.
123 * cpu/cpu0/.. <L1 and L2 block directory>
126 * /L2-cache/ce_count
128 * cpu/cpu1/.. <L1 and L2 block directory>
131 * /L2-cache/ce_count
135 * the L1 and L2 directories would be "edac_device_block's"
H A Dmpc85xx_edac.c393 /**************************** L2 Err device ***************************/
395 /************************ L2 SYSFS parts ***********************************/
495 /***************************** L2 ops ***********************************/
507 printk(KERN_ERR "ECC Error in CPU L2 cache\n"); mpc85xx_l2_check()
508 printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect); mpc85xx_l2_check()
509 printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n", mpc85xx_l2_check()
511 printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n", mpc85xx_l2_check()
513 printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n", mpc85xx_l2_check()
515 printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n", mpc85xx_l2_check()
517 printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n", mpc85xx_l2_check()
575 "L2 err regs\n", __func__); mpc85xx_l2_err_probe()
592 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__); mpc85xx_l2_err_probe()
622 "[EDAC] L2 err", edac_dev); mpc85xx_l2_err_probe()
626 "MPC85xx L2 err\n", __func__, pdata->irq); mpc85xx_l2_err_probe()
632 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n", mpc85xx_l2_err_probe()
643 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n"); mpc85xx_l2_err_probe()
1235 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n"); mpc85xx_mc_init()
H A Dhighbank_l2_edac.c154 MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank L2 Cache");
H A Dmpc85xx_edac.h80 * L2 Err defines
/linux-4.4.14/arch/powerpc/kernel/
H A Dl2cr_6xx.S80 causes cache pushes from the L1 cache to go to the L2 cache
86 and L2 Invalidate are the only bits that have not moved.
87 The size is read-only for these processors with internal L2
125 * that invalidates the L2 cache tags.
147 * the size of the L2 cache plus the size of the L1 cache, but 4MB will
159 /* Disable L2 prefetch on some 745x and try to ensure
160 * L2 prefetch engines are idle. As explained by errata
200 /* Set up the L2CR configuration bits (and switch L2 off) */
253 /* Enable L2 HW prefetch on 744x/745x */
H A Didle_6xx.S91 /* Disable L2 prefetch on some 745x and try to ensure
92 * L2 prefetch engines are idle. As explained by errata
H A Dcpu_setup_6xx.S216 * Enable L2 HW prefetch
264 /* Enable L2 HW prefetch, if L2 is enabled
/linux-4.4.14/arch/tile/include/uapi/arch/
H A Dchip_tilegx.h59 /** Size of the L2 cache, in bytes. */
62 /** Log size of an L2 cache line in bytes. */
65 /** Size of an L2 cache line, in bytes. */
68 /** Associativity of the L2 cache. */
107 /** How many simultaneous outstanding victims can the L2 cache have? */
H A Dchip_tilepro.h59 /** Size of the L2 cache, in bytes. */
62 /** Log size of an L2 cache line in bytes. */
65 /** Size of an L2 cache line, in bytes. */
68 /** Associativity of the L2 cache. */
107 /** How many simultaneous outstanding victims can the L2 cache have? */
/linux-4.4.14/drivers/clk/mvebu/
H A Dkirkwood.c40 * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
56 * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
57 * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
58 * 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
174 /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */ mv88f6180_get_clk_ratio()
H A Darmada-375.c26 * For the Armada 375 SoCs, the CPU, DDR and L2 clocks frequencies are
30 * SAR1[21:17] : CPU frequency DDR frequency L2 frequency
H A Ddove.c40 * SAR0[11:9] : CPU to L2 Clock divider ratio
/linux-4.4.14/drivers/s390/net/
H A Dqeth_core_mpc.c182 {IPA_RC_L2_MAC_NOT_AUTH_BY_HYP, "L2 mac not authorized by hypervisor"},
183 {IPA_RC_L2_MAC_NOT_AUTH_BY_ADP, "L2 mac not authorized by adapter"},
184 {IPA_RC_L2_MAC_NOT_FOUND, "L2 mac address not found"},
185 {IPA_RC_L2_INVALID_VLAN_ID, "L2 invalid vlan id"},
186 {IPA_RC_L2_DUP_VLAN_ID, "L2 duplicate vlan id"},
187 {IPA_RC_L2_VLAN_ID_NOT_FOUND, "L2 vlan id not found"},
/linux-4.4.14/arch/arc/include/asm/
H A Dentry-compact.h12 * e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
63 * a L2 IRQ "Interrupts" L1
64 * Thay way although L2 IRQ happened in Kernel mode, stack is still
74 * USER stk) and then we take L2 ISR.
75 * Above brlo alone would treat it as a valid L1-L2 sceanrio
77 * The only feasible way is to make sure this L2 happened in
H A Dcache.h85 /*System-level cache (L2 cache) related Auxiliary registers */
H A Dirqflags-compact.h36 #define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */
/linux-4.4.14/drivers/usb/musb/
H A Dblackfin.h26 * never uses L1 or L2 memory as data destination.
29 * never uses L1 or L2 memory as data source.
/linux-4.4.14/drivers/net/ethernet/intel/i40evf/
H A Di40e_common.c588 /* L2 Packet types */
590 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
591 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
592 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
595 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
596 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
599 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
600 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
601 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
604 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
605 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
606 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
607 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
608 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
609 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
610 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
/linux-4.4.14/arch/x86/kernel/acpi/
H A Dsleep.c68 * with 2-MB L2 Cache and Intel® Processor A100 and A110 on 90 x86_acpi_suspend_lowlevel()
69 * nm process with 512-KB L2 Cache Specification Update". x86_acpi_suspend_lowlevel()
/linux-4.4.14/arch/arc/mm/
H A Ddma.c85 * Evict any existing L1 and/or L2 lines for the backing page dma_alloc_coherent()
90 * can't be used to efficiently flush L1 and/or L2 which need paddr dma_alloc_coherent()
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/pinctrl/
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
/linux-4.4.14/include/dt-bindings/pinctrl/
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
/linux-4.4.14/include/linux/
H A Dptp_classify.h35 #define PTP_CLASS_L2 0x40 /* event in a L2 packet */
69 * PTP_CLASS_V2_{L2,VLAN}, depending on the packet content.
H A DmISDNhw.h47 #define FLG_L2_ACTIVATED 3 /* activated from L2 */
57 #define FLG_L2DATA 14 /* channel use L2 DATA primitivs */
H A DmISDNif.h52 Layer = 01 L2 -> HW
53 Layer = 02 HW -> L2
54 Layer = 04 L3 -> L2
55 Layer = 08 L2 -> L3
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/pinctrl/
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
/linux-4.4.14/arch/metag/tbx/
H A Dtbidspram.S77 $L2:
84 BR $L2
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/pinctrl/
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/pinctrl/
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
/linux-4.4.14/arch/m68k/fpsp040/
H A Dsetox.S105 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
242 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
343 L2: .long 0x3FDC0000,0x82E30865,0x4361C4C6,0x00000000 label
498 movew L2,L_SCR1(%a6) | ...prefetch L2, no need in CB
506 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
665 | MOVE.W #$3FDC,L2 ...prefetch L2 in CB mode
672 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/pinctrl/
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/pinctrl/
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
/linux-4.4.14/drivers/scsi/bnx2fc/
H A Dbnx2fc_debug.h22 #define LOG_MISC 0x10 /* fcoe L2 frame related logs*/
/linux-4.4.14/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-spi.c85 * automatically put on the L2 CRC. For everything __cvmx_helper_spi_probe()
86 * except for the SPI4000 have PKO append the L2 CRC __cvmx_helper_spi_probe()
109 * Normally the ethernet L2 CRC is checked and stripped in the __cvmx_helper_spi_enable()
111 * IPD needs to check the L2 CRC. __cvmx_helper_spi_enable()
H A Dcvmx-l2c.c41 * performing certain L2 operations at a time.
282 * Helper function use to fault in cache lines for L2 cache locking
284 * @addr: Address of base of memory region to read into L2 cache
300 * being in L2. fault_in()
614 * the 'debug core' for the L2. This code must only be executed by
655 * mode all data loads from L2 return special debug data, not __read_l2_tag()
703 * Use L2 cache Index load tag cache instruction, as cvmx_l2c_get_tag()
704 * hardware loads the virtual tag for the L2 cache cvmx_l2c_get_tag()
798 * Return log base 2 of the number of sets in the L2 cache
821 /* Return the number of sets in the L2 Cache */ cvmx_l2c_get_num_sets()
827 /* Return the number of associations in the L2 Cache */ cvmx_l2c_get_num_assoc()
888 * Flush a line from the L2 cache
/linux-4.4.14/arch/blackfin/include/asm/
H A Dmem_map.h27 /* Most parts lack on-chip L2 SRAM */
/linux-4.4.14/arch/arm/mach-mvebu/
H A Dkirkwood-pm.c40 * the array clocks, and also the L2 controller. kirkwood_low_power()
H A Dcoherency.c72 * Disable the "Shared L2 Present" bit in CPU Configuration register
75 * The "Shared L2 Present" bit affects the "level of coherence" value
79 * coherency is used, this bit causes unnecessary flushes of the L2
H A Dpmsu.c215 /* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */ mvebu_v7_pmsu_enable_l2_powerdown_onidle()
251 /* ask HW to power down the L2 Cache if needed */ mvebu_v7_pmsu_idle_prepare()
349 /* cancel ask HW to power down the L2 Cache if possible */ mvebu_v7_pmsu_idle_exit()
406 * idle state due to heavy L1/L2 cache cleanup operations armada_370_cpuidle_init()
/linux-4.4.14/arch/arm/mach-shmobile/
H A Dsetup-emev2.c25 /* 2M mapping for SCU + L2 controller */
/linux-4.4.14/arch/arm/include/asm/
H A Dfirmware.h45 * Initializes L2 cache
H A Dpgtable-3level-hwdef.h101 #define TTBR1_OFFSET (4096 * (1 + 3)) /* only L2, skip pgd + 3*pmd */
H A Dkvm_asm.h42 #define c9_L2CTLR 20 /* Cortex A15/A7 L2 Control Register */
/linux-4.4.14/include/linux/i2c/
H A Dadp5588.h61 #define CMP_CONFG_SENS2 0x32 /* L2 Light Sensor Reference Level, Output Falling for Sensor 1 */
62 #define CMP1_LVL2_TRIP 0x33 /* L2 Light Sensor Hysteresis (Active when Output Rising) for Sensor 1 */
66 #define CMP2_LVL2_TRIP 0x37 /* L2 Light Sensor Reference Level, Output Falling for Sensor 2 */
67 #define CMP2_LVL2_HYS 0x38 /* L2 Light Sensor Hysteresis (Active when Output Rising) for Sensor 2 */
H A Dadp8860.h92 * L2 comparator current 0..1106uA
H A Dadp8870.h89 * L2 comparator current 0..1106uA
/linux-4.4.14/arch/mips/include/asm/
H A Dmips-cm.h22 /* The base address of the CM L2-only sync region */
90 * mips_cm_has_l2sync - determine whether an L2-only sync region is present
92 * Returns true if the system implements an L2-only sync region, else false.
112 /* Size of the L2-only sync region */
419 * mips_cm_l2sync - perform an L2-only sync operation
421 * If an L2-only sync region is present in the system then this function
422 * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
/linux-4.4.14/arch/mips/kernel/
H A Dmips-cm.c111 [0x7] = "L2"
166 * If the L2-only sync region is already enabled then leave it at it's __mips_cm_l2sync_phys_base()
185 /* L2-only sync was introduced with CM major revision 6 */ mips_cm_probe_l2sync()
191 /* Find a location for the L2 sync region */ mips_cm_probe_l2sync()
250 /* probe for an L2-only sync region */ mips_cm_probe()
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb3/
H A Dl2t.h51 * corresponding entry of the HW L2 table and maintains a queue of offload
101 * Getting to the L2 data from an offload device.
/linux-4.4.14/arch/xtensa/lib/
H A Dmemset.S85 bbci.l a4, 3, .L2
90 .L2:
H A Dusercopy.S178 bbci.l a4, 3, .L2
186 .L2:
/linux-4.4.14/arch/sh/kernel/cpu/sh4/
H A Dprobe.c220 * SH-4A's have an optional PIPT L2. cpu_probe()
225 * is the safety net for CPUs that have optional L2 cpu_probe()
/linux-4.4.14/arch/m68k/lib/
H A Ddivsi3.S101 jpl L2
109 L2: movel d1, sp@- label
H A Dudivsi3.S148 jcs L2 | if no carry,
151 L2: subql IMM (1),d4 label
/linux-4.4.14/arch/frv/include/asm/
H A Datomic_defs.h96 " "#op"cc %L1,%L2,%L1,icc0 \n" \
147 " "#op" %L1,%L3,%L2 \n" \
/linux-4.4.14/arch/arm/mach-mmp/
H A Dpm-pxa910.c203 /* disable L2 */ pxa910_pm_enter()
211 /* enable L2 */ pxa910_pm_enter()
/linux-4.4.14/arch/arm/mach-tegra/
H A Dsleep.S74 * set up the correct L2 cache data RAM latency
135 /* Disable L2 cache */
/linux-4.4.14/drivers/iommu/
H A Domap-iopgtable.h19 * "L2 table" address mask and size definitions.
/linux-4.4.14/drivers/net/ethernet/mellanox/mlxsw/
H A Dtrap.h43 /* L2 traps for specific packet types */
/linux-4.4.14/arch/tile/include/hv/
H A Dnetio_intf.h166 /** Length of any custom data before the L2 header, in words. */
178 /** Length of the L2 header, in words. */
198 /** Offset within the L2 header of the innermost ethertype (in halfwords). */
202 /** Offset within the L2 header of the VLAN tag (in halfwords). */
284 /** Whether we should balance on L2, if available */
362 /** To ensure that the L3 header is aligned mod 4, the L2 header should be
363 * aligned mod 4 plus 2, since every supported L2 header is 4n + 2 bytes
365 * before the L2 header.
390 /** The offset of the L2 header from the start of the packet data. */
400 /** The L2 length of the packet. */
710 * the custom header precedes the L2 header in the packet buffer.
727 * the custom header precedes the L2 header in the packet buffer.
753 * the custom header precedes the L2 header in the packet buffer.
772 * the custom header precedes the L2 header in the packet buffer.
786 /** Return the length of the packet's L2 (Ethernet plus VLAN or SNAP) header.
791 * @return The length of the packet's L2 header, in bytes.
807 /** Return the length of the packet, starting with the L2 (Ethernet) header.
822 /** Return a pointer to the start of the packet's L2 (Ethernet) header.
1183 /** Return the length of the packet, starting with the L2 (Ethernet) header.
1197 /** Return the length of the L2 (Ethernet) header.
1202 * @return The length of the packet's L2 header, in bytes.
1243 /** Return a pointer to the packet's L2 (Ethernet) header.
1301 * the custom header precedes the L2 header in the packet buffer.
1320 * the custom header precedes the L2 header in the packet buffer.
1339 * the custom header precedes the L2 header in the packet buffer.
1354 /** Return the length of the packet's L2 (Ethernet plus VLAN or SNAP) header.
1358 * @return The length of the packet's L2 header, in bytes.
1378 /** Return the length of the packet, starting with the L2 (Ethernet) header.
1402 /** Return a pointer to the packet's L2 (Ethernet) header.
1732 /** Set an egress packet's L2 length, using a metadata pointer to speed the
1738 * @param[in] len Packet L2 length, in bytes.
1748 /** Set an egress packet's L2 length.
1752 * @param[in] len Packet L2 length, in bytes.
1763 /** Set an egress packet's L2 header length, using a metadata pointer to
1767 * It is not normally necessary to call this routine; only the L2 length,
1774 * @param[in] len Packet L2 header length, in bytes.
1784 /** Set an egress packet's L2 header length.
1787 * It is not normally necessary to call this routine; only the L2 length,
1793 * @param[in] len Packet L2 header length, in bytes.
1832 * @param[in] start Offset within L2 packet of the first byte to include in
1836 * @param[in] location Offset within L2 packet of the first of the two bytes
1880 * @param[in] start Offset within L2 packet of the first byte to include in
1884 * @param[in] location Offset within L2 packet of the first of the two bytes
2204 its packets' L2 headers (::NETIO_TAG_NONE, ::NETIO_TAG_BRCM,
2454 /** This application expects no tags on its L2 headers. */
2457 /** This application expects Marvell extended tags on its L2 headers. */
2460 /** This application expects Broadcom tags on its L2 headers. */
2671 * bigger than one L2 cache line, and to be aligned modulo its size.
2710 * (e.g., its L2 offset and length) are captured at the time this
/linux-4.4.14/arch/tile/include/uapi/asm/
H A Dcachectl.h34 * to flush the entire L1+L2 data cache from the core. In this case,
/linux-4.4.14/arch/powerpc/perf/
H A De6500-pmu.c53 * Assuming LL means L2, it's not a good match for this model.
H A Dpower7-pmu.c28 #define PM_L2SEL_SH 8 /* L2 event select */
69 * L2 NC P6P5P4P3P2P1
71 * L2 - 16-18 - Required L2SEL value (select field)
294 if (unit == 6) /* L2 events */ power7_compute_mmcr()
H A De500-pmu.c54 * Assuming LL means L2, it's not a good match for this model.
H A Dpower8-pmu.c49 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
53 /* All successful D-side store dispatches for this thread that were L2 Miss */
79 * | | *- L1/L2/L3 cache_sel |
144 #define EVENT_CACHE_SEL_SHIFT 20 /* L2/L3 cache select */
329 * L2/L3 events contain a cache selector field, which is power8_get_constraint()
/linux-4.4.14/arch/mips/include/asm/sn/
H A Dintr.h56 * L2 = INT_PEND0
/linux-4.4.14/arch/metag/lib/
H A Ddiv64.S14 $L2:
/linux-4.4.14/arch/arm/mach-cns3xxx/
H A Dpm.c101 * cns3xxx_cpu_clock - return CPU/L2 clock
/linux-4.4.14/arch/alpha/kernel/
H A Dsetup.c1282 show_cache_size (f, "L2 cache", alpha_l2_cacheshape); show_cpuinfo()
1354 int L1I, L1D, L2, L3; determine_cpu_caches() local
1373 L2 = CSHAPE (size, 5, 1); determine_cpu_caches()
1377 L2 = external_cache_probe(128*1024, 5); determine_cpu_caches()
1391 L2 = (car & 1 ? CSHAPE (size, 3, 1) : -1); determine_cpu_caches()
1405 L2 = CSHAPE (96*1024, width, 3); determine_cpu_caches()
1439 L2 = ((cbox_config >> 31) & 1 ? CSHAPE (size, 6, 1) : -1); determine_cpu_caches()
1441 L2 = external_cache_probe(512*1024, 6); determine_cpu_caches()
1453 L2 = external_cache_probe(1024*1024, 6); determine_cpu_caches()
1460 L2 = CSHAPE(7*1024*1024/4, 6, 7); determine_cpu_caches()
1466 L1I = L1D = L2 = L3 = 0; determine_cpu_caches()
1472 alpha_l2_cacheshape = L2; determine_cpu_caches()
/linux-4.4.14/drivers/devfreq/exynos/
H A Dexynos4_bus.c172 /* DMC L2: 133MHz */
184 /* ACLK200 L2: 133MHz */
194 /* ACLK_GDL/R L2: 160MHz */
212 /* DMC L2: 160MHz */
229 /* DMC L2: 160MHz */
247 /* ACLK_GDL/R L2: 160MHz */
264 /* ACLK_GDL/R L2: 160MHz */
/linux-4.4.14/arch/tile/lib/
H A Dmemcpy_32.S158 /* Intentionally stall for a few cycles to leave L2 cache alone. */
161 /* Intentionally stall for a few cycles to leave L2 cache alone. */
164 /* Intentionally stall for a few cycles to leave L2 cache alone. */
266 /* Load seven words that are L1D hits to cover wh64 L2 usage. */
288 * for the first time, which keeps the L2 busy for two cycles.
292 /* Use two L1D hits to cover the sw L2 access above. */
431 * guarantees all words to load below will be in the L2 cache, which
/linux-4.4.14/arch/blackfin/mm/
H A Dsram-alloc.c194 printk(KERN_ERR "L2 ecc error happened\n"); l2_ecc_err()
205 printk(KERN_ERR "L2 Bank%d error, addr:0x%x\n", l2_ecc_err()
208 panic("L2 Ecc error"); l2_ecc_err()
231 printk(KERN_INFO "Fail to initialize L2 SRAM.\n"); l2_sram_init()
244 printk(KERN_INFO "Blackfin L2 SRAM: %d KB (%d KB free)\n", l2_sram_init()
866 if (_sram_proc_show(m, "L2", &free_l2_sram_head, &used_l2_sram_head)) sram_proc_show()
/linux-4.4.14/drivers/tty/serial/8250/
H A D8250_gsc.c100 { HPHW_FIO, HVERSION_REV_ANY_ID, 0x04E, 0x0008C }, /* Kiji L2 132 */
/linux-4.4.14/drivers/isdn/hardware/eicon/
H A Ddebug_if.h84 #define DIVA_MGT_DBG_IFC_EVENTS 0x00000100 /* Interface/L1/L2 state events */
/linux-4.4.14/drivers/net/wireless/rt2x00/
H A Drt2x00lib.h126 * Apply L2 padding to align both header and payload to 4-byte boundary
131 * rt2x00queue_insert_l2pad - Remove L2 padding from 802.11 frame
135 * Remove L2 padding used to align both header and payload to 4-byte boundary,
136 * by removing the L2 padding the header will no longer be 4-byte aligned.
/linux-4.4.14/drivers/cpufreq/
H A Ds5pv210-cpufreq.c111 L0, L1, L2, L3, L4, enumerator in enum:perf_level
128 {0, L2, 400*1000},
154 [L2] = {
182 /* L2 : [400/200/100][166/83][133/66][200/200] */
H A Dpmac32-cpufreq.c122 /* tweak L2 for high voltage */ cpu_750fx_cpu_speed()
133 /* tweak L2 for low voltage */ cpu_750fx_cpu_speed()
271 /* Save & disable L2 and L3 caches */ pmu_set_cpu_speed()
293 /* Restore L2 cache */ pmu_set_cpu_speed()
/linux-4.4.14/arch/tile/mm/
H A Dinit.c62 /* Create an L2 page table */ alloc_pte()
69 * L2 page tables per controller. We allocate these all at once from
70 * the bootmem allocator and store them here. This saves on kernel L2
71 * page table memory, compared to allocating a full 64K page per L2
78 * L2 page tables are contiguous in memory for each controller.
115 * Place a pointer to an L2 page table in a middle page
440 /* Allocate and fill in L2 page tables */ kernel_physical_mapping_init()
455 /* Allocate enough memory to hold L2 page tables for node. */ kernel_physical_mapping_init()
511 /* Allocate an L2 PTE for the kernel text */ kernel_physical_mapping_init()
H A Dmigrate_32.S118 /* First, flush our L2 cache. */
H A Dmigrate_64.S103 /* First, flush our L2 cache. */
/linux-4.4.14/arch/powerpc/platforms/chrp/
H A Dsetup.c146 /* L2 cache */ chrp_show_cpuinfo()
223 /* Enable L2 cache if needed */ pegasos_set_l2cr()
232 printk ("Pegasos l2cr : L2 cache was not active, " pegasos_set_l2cr()
340 /* On pegasos, enable the L2 cache if not already done by OF */ chrp_setup_arch()
/linux-4.4.14/arch/s390/include/asm/
H A Dpage.h45 * this keeps L1 and L2 data caches alive.
/linux-4.4.14/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/
H A DEventClass.py79 # in L1/L2/L3 or IO operations
/linux-4.4.14/arch/sparc/include/asm/
H A Dprocessor_64.h234 * By contrast, "#one_write" prefetches into the L2 cache prefetch()
246 * L2 cache in "owned" state. prefetchw()
/linux-4.4.14/arch/mips/sibyte/common/
H A Dbus_watcher.c119 seq_printf(m, "L2-d-cor %8ld\nL2-d-bad %8ld\n", bw_proc_show()
121 seq_printf(m, "L2-t-cor %8ld\nL2-t-bad %8ld\n", bw_proc_show()
/linux-4.4.14/arch/arm/mach-hisi/
H A Dplatmcpm.c179 /* Since it's Cortex A15, disable L2 prefetching. */ hip04_cpu_die()
215 /* Wait for clean L2 when the whole cluster is down. */ hip04_cpu_kill()
/linux-4.4.14/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x.h232 /* FCoE L2 connection completions */
235 /* iSCSI L2 */
242 /* FCoE L2 */
296 /* iSCSI L2 */
298 /* FCoE L2 */
1159 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
1163 * serve a regular L2 networking queue. However special L2 queues such
1165 * the CNIC may consume FP-SB reducing the number of possible L2 queues
1169 * regular L2 queues is Y=X-1
1170 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
1171 * c. If the FCoE L2 queue is supported the actual number of L2 queues
1177 * L2 queue is supported. The cid for the FCoE L2 queue is always X.
1503 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1612 /* Flag that indicates that we can start looking for FCoE L2 queue
1792 /* Start index of the "special" (CNIC related) L2 clients */
2063 * if FCOE l2 support is disabled and this is the fcoe L2 queue
2068 * if FCOE l2 support is disabled and this is the fcoe L2 queue
/linux-4.4.14/arch/x86/kvm/
H A Dvmx.c195 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
199 * More than one of these structures may exist, if L1 runs multiple L2 guests.
201 * underlying hardware which will be used to run L2.
249 * To allow migration of L1 (complete with its L2 guests) between
395 /* The guest-physical address of the current VMCS L1 keeps for L2 */
407 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
411 /* L2 must run next, and mustn't decide to exit to L1. */
415 * we must keep them pinned while L2 runs.
428 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
541 * guest (L2), it points to a different VMCS.
1656 /* When we are running a nested L2 guest and L1 specified for it a update_exception_bitmap()
1658 * them to L1. When running L2, we will only handle the exceptions update_exception_bitmap()
2257 * checks whether in a nested guest, we need to inject them to L1 or L2.
2409 * counter, even if a nested guest (L2) is currently running.
2435 * set for L2 remains unchanged, and still needs to be added vmx_write_tsc_offset()
2436 * to the newly set TSC to get L2's TSC. vmx_write_tsc_offset()
2458 /* Even when running L2, the adjustment needs to apply to L1 */ vmx_adjust_tsc_offset_guest()
2486 * valid during nested entry from L1 to L2.
2595 * can use it to avoid exits to L1 - even when L0 runs L2 nested_vmx_setup_ctls_msrs()
2741 * while L1 is in VMXON mode (in L1's root mode, or running an L2). vmx_get_vmx_msr()
5397 * We get here when L2 changed cr0 in a way that did not change handle_set_cr0()
5401 * hardware. It consists of the L2-owned bits from the new handle_set_cr0()
5444 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS handle_clts()
6384 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6385 * We could reuse a single VMCS for all the L2 guests, but we also want the
7577 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7615 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7696 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7697 * should handle it ourselves in L0 (and then continue L2). Only call this
7698 * when in is_guest_mode (L2).
7766 * emulate them for its L2 guest, i.e., allows 3-level nesting! nested_vmx_exit_handled()
7811 * L2 never uses directly L1's EPT, but rather L0's own EPT nested_vmx_exit_handled()
7824 * set XSS to a non-zero value---neither in L1 nor in L2. nested_vmx_exit_handled()
8217 * Currently we do not handle the nested case where L2 has an vmx_set_apic_access_page_addr()
8220 * L1 prepared an APIC access page for L2. vmx_set_apic_access_page_addr()
8222 * For the case where L1 and L2 share the same APIC access page vmx_set_apic_access_page_addr()
8227 * the next L2->L1 exit. vmx_set_apic_access_page_addr()
8287 * Else, fall back to pre-APICv interrupt injection since L2 vmx_hwapic_irr_update()
9461 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9462 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9568 * to exit on each and every L2 page fault. This is done by setting prepare_vmcs02()
9682 * bitwise-or of what L1 wants to trap for L2, and what we want to prepare_vmcs02()
9689 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so prepare_vmcs02()
9726 * The vpid12 is allocated by L1 for L2, so it will not prepare_vmcs02()
9760 * The CR0_READ_SHADOW is what L2 should have expected to read given prepare_vmcs02()
9779 * L1 may access the L2's PDPTR, so save them to construct vmcs12 prepare_vmcs02()
9794 * for running an L2 nested guest.
9985 * the success flag) when L2 exits (see nested_vmx_vmexit()). nested_vmx_run()
9991 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9992 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9995 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9999 * been modified by L2, and L1 knows it. So just leave the old value of
10123 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10124 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10126 * L2 was running (and perhaps made some exits which were handled directly by L0
10129 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10200 * In some cases (usually, nested EPT), L2 is allowed to change its prepare_vmcs12()
10203 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. prepare_vmcs12()
10205 * Additionally, restore L2's PDPTR to vmcs12. prepare_vmcs12()
10263 * L2 to IDT_VECTORING_INFO_FIELD. prepare_vmcs12()
10269 * Drop what we picked up for L2 via vmx_complete_interrupts. It is prepare_vmcs12()
10278 * A part of what we need to when the nested L2 guest exits and we want to
10310 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need load_vmcs12_host_state()
10337 * each L2 its own vpid and exposing the vpid feature to L1. load_vmcs12_host_state()
10349 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ load_vmcs12_host_state()
10419 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10421 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10468 /* Update TSC_OFFSET if TSC was changed while L2 ran */ nested_vmx_vmexit()
10491 * We are now running in L2, mmu_notifier will force to reload the nested_vmx_vmexit()
10492 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. nested_vmx_vmexit()
10497 * Exiting from L2 to L1, we're now back to L1 which thinks it just nested_vmx_vmexit()
10509 /* in case we halted in L2 */ nested_vmx_vmexit()
10524 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10527 * It should only be called before L2 actually succeeded to run, and when
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dcikd.h1802 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
1803 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
1807 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
1827 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
1828 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
1830 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */
1851 * 1 - TC/L2
1881 * 3 - DST_ADDR using L2
1893 * 3 - SRC_ADDR using L2
/linux-4.4.14/arch/x86/kernel/cpu/
H A Dperf_event_amd.c45 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
46 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
49 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
H A Dperf_event_amd_uncore.c184 * NB and L2 counters (MSRs) are shared across all cores that share the amd_uncore_event_init()
185 * same NB / L2 cache. Interrupts can be directed to a single target amd_uncore_event_init()
193 /* NB and L2 counters do not have usr/os/guest/host bits */ amd_uncore_event_init()
/linux-4.4.14/fs/jfs/
H A Djfs_dmap.h82 * - 3 is added to account for the L2, L1, and L0 page for this dmap
97 * - 2 is added to account for the L2, and L1 page for this L0
112 * - 1 is added to account for the L2 page
/linux-4.4.14/drivers/net/ethernet/cavium/thunder/
H A Dnic_reg.h202 u64 lenerr_en:1;/* L2 length error check enable */
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb4/
H A Dl2t.h65 * corresponding entry of the HW L2 table and maintains a queue of offload
/linux-4.4.14/drivers/bcma/
H A Ddriver_pci.c219 /* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
/linux-4.4.14/arch/blackfin/mach-bf561/include/mach/
H A Danomaly.h102 /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
234 /* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
296 /* Execution stall when executing in L2 and doing external accesses */
/linux-4.4.14/arch/blackfin/mach-bf561/
H A Dsecondary.S49 L2 = r6; define
/linux-4.4.14/arch/blackfin/mach-common/
H A Dhead.S58 L2 = r6; define
/linux-4.4.14/include/linux/bcma/
H A Dbcma_driver_pcie2.h11 #define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
/linux-4.4.14/arch/powerpc/platforms/embedded6xx/
H A Dmpc7448_hpc2.c87 "Enabling L2 cache then enabling the HID0 prefetch engine.\n"); mpc7448_hpc2_setup_arch()
/linux-4.4.14/arch/mips/pci/
H A Dpci-octeon.c394 ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */ octeon_pci_initialize()
401 ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */ octeon_pci_initialize()
643 /* Don't put PCI accesses in L2. */ octeon_pci_setup()
679 /* Don't put PCI accesses in L2. */ octeon_pci_setup()
/linux-4.4.14/arch/arm/mach-nomadik/
H A Dcpu-8815.c82 #define NOMADIK_L2CC_BASE 0x10210000 /* L2 Cache controller */
/linux-4.4.14/arch/arm/kernel/
H A Dreboot.c68 /* Disable the L2 if we're the last man standing. */ _soft_restart()
/linux-4.4.14/sound/soc/rockchip/
H A Drockchip_rt5645.c51 {"DMIC L2", NULL, "Int Mic"},
/linux-4.4.14/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_ethtool.c78 /* L2 error */
87 /* L2 Pkt type */
/linux-4.4.14/arch/blackfin/mach-bf609/include/mach/
H A Dirq.h18 #define IRQ_L2CTL0_ECC_ERR BFIN_IRQ(4) /* L2 ECC Error */
19 #define IRQ_L2CTL0_ECC_WARN BFIN_IRQ(5) /* L2 ECC Waring */

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