1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24#ifndef CIK_H 25#define CIK_H 26 27#define MC_SEQ_MISC0__MT__MASK 0xf0000000 28#define MC_SEQ_MISC0__MT__GDDR1 0x10000000 29#define MC_SEQ_MISC0__MT__DDR2 0x20000000 30#define MC_SEQ_MISC0__MT__GDDR3 0x30000000 31#define MC_SEQ_MISC0__MT__GDDR4 0x40000000 32#define MC_SEQ_MISC0__MT__GDDR5 0x50000000 33#define MC_SEQ_MISC0__MT__HBM 0x60000000 34#define MC_SEQ_MISC0__MT__DDR3 0xB0000000 35 36#define CP_ME_TABLE_SIZE 96 37 38/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 39#define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) 40#define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) 41#define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) 42#define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) 43#define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) 44#define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) 45 46#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 47#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 48 49#define CIK_RB_BITMAP_WIDTH_PER_SH 2 50#define HAWAII_RB_BITMAP_WIDTH_PER_SH 4 51 52#define AMDGPU_NUM_OF_VMIDS 8 53 54#define PIPEID(x) ((x) << 0) 55#define MEID(x) ((x) << 2) 56#define VMID(x) ((x) << 4) 57#define QUEUEID(x) ((x) << 8) 58 59#define mmCC_DRM_ID_STRAPS 0x1559 60#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 61 62#define mmCHUB_CONTROL 0x619 63#define BYPASS_VM (1 << 0) 64 65#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 66 67#define mmGRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02 68#define LUT_10BIT_BYPASS_EN (1 << 8) 69 70# define CURSOR_MONO 0 71# define CURSOR_24_1 1 72# define CURSOR_24_8_PRE_MULT 2 73# define CURSOR_24_8_UNPRE_MULT 3 74# define CURSOR_URGENT_ALWAYS 0 75# define CURSOR_URGENT_1_8 1 76# define CURSOR_URGENT_1_4 2 77# define CURSOR_URGENT_3_8 3 78# define CURSOR_URGENT_1_2 4 79 80# define GRPH_DEPTH_8BPP 0 81# define GRPH_DEPTH_16BPP 1 82# define GRPH_DEPTH_32BPP 2 83/* 8 BPP */ 84# define GRPH_FORMAT_INDEXED 0 85/* 16 BPP */ 86# define GRPH_FORMAT_ARGB1555 0 87# define GRPH_FORMAT_ARGB565 1 88# define GRPH_FORMAT_ARGB4444 2 89# define GRPH_FORMAT_AI88 3 90# define GRPH_FORMAT_MONO16 4 91# define GRPH_FORMAT_BGRA5551 5 92/* 32 BPP */ 93# define GRPH_FORMAT_ARGB8888 0 94# define GRPH_FORMAT_ARGB2101010 1 95# define GRPH_FORMAT_32BPP_DIG 2 96# define GRPH_FORMAT_8B_ARGB2101010 3 97# define GRPH_FORMAT_BGRA1010102 4 98# define GRPH_FORMAT_8B_BGRA1010102 5 99# define GRPH_FORMAT_RGB111110 6 100# define GRPH_FORMAT_BGR101111 7 101# define ADDR_SURF_MACRO_TILE_ASPECT_1 0 102# define ADDR_SURF_MACRO_TILE_ASPECT_2 1 103# define ADDR_SURF_MACRO_TILE_ASPECT_4 2 104# define ADDR_SURF_MACRO_TILE_ASPECT_8 3 105# define GRPH_ARRAY_LINEAR_GENERAL 0 106# define GRPH_ARRAY_LINEAR_ALIGNED 1 107# define GRPH_ARRAY_1D_TILED_THIN1 2 108# define GRPH_ARRAY_2D_TILED_THIN1 4 109# define DISPLAY_MICRO_TILING 0 110# define THIN_MICRO_TILING 1 111# define DEPTH_MICRO_TILING 2 112# define ROTATED_MICRO_TILING 4 113# define GRPH_ENDIAN_NONE 0 114# define GRPH_ENDIAN_8IN16 1 115# define GRPH_ENDIAN_8IN32 2 116# define GRPH_ENDIAN_8IN64 3 117# define GRPH_RED_SEL_R 0 118# define GRPH_RED_SEL_G 1 119# define GRPH_RED_SEL_B 2 120# define GRPH_RED_SEL_A 3 121# define GRPH_GREEN_SEL_G 0 122# define GRPH_GREEN_SEL_B 1 123# define GRPH_GREEN_SEL_A 2 124# define GRPH_GREEN_SEL_R 3 125# define GRPH_BLUE_SEL_B 0 126# define GRPH_BLUE_SEL_A 1 127# define GRPH_BLUE_SEL_R 2 128# define GRPH_BLUE_SEL_G 3 129# define GRPH_ALPHA_SEL_A 0 130# define GRPH_ALPHA_SEL_R 1 131# define GRPH_ALPHA_SEL_G 2 132# define GRPH_ALPHA_SEL_B 3 133# define INPUT_GAMMA_USE_LUT 0 134# define INPUT_GAMMA_BYPASS 1 135# define INPUT_GAMMA_SRGB_24 2 136# define INPUT_GAMMA_XVYCC_222 3 137 138# define INPUT_CSC_BYPASS 0 139# define INPUT_CSC_PROG_COEFF 1 140# define INPUT_CSC_PROG_SHARED_MATRIXA 2 141 142# define OUTPUT_CSC_BYPASS 0 143# define OUTPUT_CSC_TV_RGB 1 144# define OUTPUT_CSC_YCBCR_601 2 145# define OUTPUT_CSC_YCBCR_709 3 146# define OUTPUT_CSC_PROG_COEFF 4 147# define OUTPUT_CSC_PROG_SHARED_MATRIXB 5 148 149# define DEGAMMA_BYPASS 0 150# define DEGAMMA_SRGB_24 1 151# define DEGAMMA_XVYCC_222 2 152# define GAMUT_REMAP_BYPASS 0 153# define GAMUT_REMAP_PROG_COEFF 1 154# define GAMUT_REMAP_PROG_SHARED_MATRIXA 2 155# define GAMUT_REMAP_PROG_SHARED_MATRIXB 3 156 157# define REGAMMA_BYPASS 0 158# define REGAMMA_SRGB_24 1 159# define REGAMMA_XVYCC_222 2 160# define REGAMMA_PROG_A 3 161# define REGAMMA_PROG_B 4 162 163# define FMT_CLAMP_6BPC 0 164# define FMT_CLAMP_8BPC 1 165# define FMT_CLAMP_10BPC 2 166 167# define HDMI_24BIT_DEEP_COLOR 0 168# define HDMI_30BIT_DEEP_COLOR 1 169# define HDMI_36BIT_DEEP_COLOR 2 170# define HDMI_ACR_HW 0 171# define HDMI_ACR_32 1 172# define HDMI_ACR_44 2 173# define HDMI_ACR_48 3 174# define HDMI_ACR_X1 1 175# define HDMI_ACR_X2 2 176# define HDMI_ACR_X4 4 177# define AFMT_AVI_INFO_Y_RGB 0 178# define AFMT_AVI_INFO_Y_YCBCR422 1 179# define AFMT_AVI_INFO_Y_YCBCR444 2 180 181#define NO_AUTO 0 182#define ES_AUTO 1 183#define GS_AUTO 2 184#define ES_AND_GS_AUTO 3 185 186# define ARRAY_MODE(x) ((x) << 2) 187# define PIPE_CONFIG(x) ((x) << 6) 188# define TILE_SPLIT(x) ((x) << 11) 189# define MICRO_TILE_MODE_NEW(x) ((x) << 22) 190# define SAMPLE_SPLIT(x) ((x) << 25) 191# define BANK_WIDTH(x) ((x) << 0) 192# define BANK_HEIGHT(x) ((x) << 2) 193# define MACRO_TILE_ASPECT(x) ((x) << 4) 194# define NUM_BANKS(x) ((x) << 6) 195 196#define MSG_ENTER_RLC_SAFE_MODE 1 197#define MSG_EXIT_RLC_SAFE_MODE 0 198 199/* 200 * PM4 201 */ 202#define PACKET_TYPE0 0 203#define PACKET_TYPE1 1 204#define PACKET_TYPE2 2 205#define PACKET_TYPE3 3 206 207#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 208#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 209#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 210#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 211#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 212 ((reg) & 0xFFFF) | \ 213 ((n) & 0x3FFF) << 16) 214#define CP_PACKET2 0x80000000 215#define PACKET2_PAD_SHIFT 0 216#define PACKET2_PAD_MASK (0x3fffffff << 0) 217 218#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 219 220#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 221 (((op) & 0xFF) << 8) | \ 222 ((n) & 0x3FFF) << 16) 223 224#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 225 226/* Packet 3 types */ 227#define PACKET3_NOP 0x10 228#define PACKET3_SET_BASE 0x11 229#define PACKET3_BASE_INDEX(x) ((x) << 0) 230#define CE_PARTITION_BASE 3 231#define PACKET3_CLEAR_STATE 0x12 232#define PACKET3_INDEX_BUFFER_SIZE 0x13 233#define PACKET3_DISPATCH_DIRECT 0x15 234#define PACKET3_DISPATCH_INDIRECT 0x16 235#define PACKET3_ATOMIC_GDS 0x1D 236#define PACKET3_ATOMIC_MEM 0x1E 237#define PACKET3_OCCLUSION_QUERY 0x1F 238#define PACKET3_SET_PREDICATION 0x20 239#define PACKET3_REG_RMW 0x21 240#define PACKET3_COND_EXEC 0x22 241#define PACKET3_PRED_EXEC 0x23 242#define PACKET3_DRAW_INDIRECT 0x24 243#define PACKET3_DRAW_INDEX_INDIRECT 0x25 244#define PACKET3_INDEX_BASE 0x26 245#define PACKET3_DRAW_INDEX_2 0x27 246#define PACKET3_CONTEXT_CONTROL 0x28 247#define PACKET3_INDEX_TYPE 0x2A 248#define PACKET3_DRAW_INDIRECT_MULTI 0x2C 249#define PACKET3_DRAW_INDEX_AUTO 0x2D 250#define PACKET3_NUM_INSTANCES 0x2F 251#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 252#define PACKET3_INDIRECT_BUFFER_CONST 0x33 253#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 254#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 255#define PACKET3_DRAW_PREAMBLE 0x36 256#define PACKET3_WRITE_DATA 0x37 257#define WRITE_DATA_DST_SEL(x) ((x) << 8) 258 /* 0 - register 259 * 1 - memory (sync - via GRBM) 260 * 2 - gl2 261 * 3 - gds 262 * 4 - reserved 263 * 5 - memory (async - direct) 264 */ 265#define WR_ONE_ADDR (1 << 16) 266#define WR_CONFIRM (1 << 20) 267#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 268 /* 0 - LRU 269 * 1 - Stream 270 */ 271#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 272 /* 0 - me 273 * 1 - pfp 274 * 2 - ce 275 */ 276#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 277#define PACKET3_MEM_SEMAPHORE 0x39 278# define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 279# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 280# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 281# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 282# define PACKET3_SEM_SEL_WAIT (0x7 << 29) 283#define PACKET3_COPY_DW 0x3B 284#define PACKET3_WAIT_REG_MEM 0x3C 285#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 286 /* 0 - always 287 * 1 - < 288 * 2 - <= 289 * 3 - == 290 * 4 - != 291 * 5 - >= 292 * 6 - > 293 */ 294#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 295 /* 0 - reg 296 * 1 - mem 297 */ 298#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 299 /* 0 - wait_reg_mem 300 * 1 - wr_wait_wr_reg 301 */ 302#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 303 /* 0 - me 304 * 1 - pfp 305 */ 306#define PACKET3_INDIRECT_BUFFER 0x3F 307#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 308#define INDIRECT_BUFFER_VALID (1 << 23) 309#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 310 /* 0 - LRU 311 * 1 - Stream 312 * 2 - Bypass 313 */ 314#define PACKET3_COPY_DATA 0x40 315#define PACKET3_PFP_SYNC_ME 0x42 316#define PACKET3_SURFACE_SYNC 0x43 317# define PACKET3_DEST_BASE_0_ENA (1 << 0) 318# define PACKET3_DEST_BASE_1_ENA (1 << 1) 319# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 320# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 321# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 322# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 323# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 324# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 325# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 326# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 327# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 328# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 329# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 330# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 331# define PACKET3_DEST_BASE_2_ENA (1 << 19) 332# define PACKET3_DEST_BASE_3_ENA (1 << 21) 333# define PACKET3_TCL1_ACTION_ENA (1 << 22) 334# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 335# define PACKET3_CB_ACTION_ENA (1 << 25) 336# define PACKET3_DB_ACTION_ENA (1 << 26) 337# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 338# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 339# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 340#define PACKET3_COND_WRITE 0x45 341#define PACKET3_EVENT_WRITE 0x46 342#define EVENT_TYPE(x) ((x) << 0) 343#define EVENT_INDEX(x) ((x) << 8) 344 /* 0 - any non-TS event 345 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 346 * 2 - SAMPLE_PIPELINESTAT 347 * 3 - SAMPLE_STREAMOUTSTAT* 348 * 4 - *S_PARTIAL_FLUSH 349 * 5 - EOP events 350 * 6 - EOS events 351 */ 352#define PACKET3_EVENT_WRITE_EOP 0x47 353#define EOP_TCL1_VOL_ACTION_EN (1 << 12) 354#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 355#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 356#define EOP_TCL1_ACTION_EN (1 << 16) 357#define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 358#define EOP_TCL2_VOLATILE (1 << 24) 359#define EOP_CACHE_POLICY(x) ((x) << 25) 360 /* 0 - LRU 361 * 1 - Stream 362 * 2 - Bypass 363 */ 364#define DATA_SEL(x) ((x) << 29) 365 /* 0 - discard 366 * 1 - send low 32bit data 367 * 2 - send 64bit data 368 * 3 - send 64bit GPU counter value 369 * 4 - send 64bit sys counter value 370 */ 371#define INT_SEL(x) ((x) << 24) 372 /* 0 - none 373 * 1 - interrupt only (DATA_SEL = 0) 374 * 2 - interrupt when data write is confirmed 375 */ 376#define DST_SEL(x) ((x) << 16) 377 /* 0 - MC 378 * 1 - TC/L2 379 */ 380#define PACKET3_EVENT_WRITE_EOS 0x48 381#define PACKET3_RELEASE_MEM 0x49 382#define PACKET3_PREAMBLE_CNTL 0x4A 383# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 384# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 385#define PACKET3_DMA_DATA 0x50 386/* 1. header 387 * 2. CONTROL 388 * 3. SRC_ADDR_LO or DATA [31:0] 389 * 4. SRC_ADDR_HI [31:0] 390 * 5. DST_ADDR_LO [31:0] 391 * 6. DST_ADDR_HI [7:0] 392 * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 393 */ 394/* CONTROL */ 395# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 396 /* 0 - ME 397 * 1 - PFP 398 */ 399# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 400 /* 0 - LRU 401 * 1 - Stream 402 * 2 - Bypass 403 */ 404# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 405# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 406 /* 0 - DST_ADDR using DAS 407 * 1 - GDS 408 * 3 - DST_ADDR using L2 409 */ 410# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 411 /* 0 - LRU 412 * 1 - Stream 413 * 2 - Bypass 414 */ 415# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 416# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 417 /* 0 - SRC_ADDR using SAS 418 * 1 - GDS 419 * 2 - DATA 420 * 3 - SRC_ADDR using L2 421 */ 422# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 423/* COMMAND */ 424# define PACKET3_DMA_DATA_DIS_WC (1 << 21) 425# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 426 /* 0 - none 427 * 1 - 8 in 16 428 * 2 - 8 in 32 429 * 3 - 8 in 64 430 */ 431# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 432 /* 0 - none 433 * 1 - 8 in 16 434 * 2 - 8 in 32 435 * 3 - 8 in 64 436 */ 437# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 438 /* 0 - memory 439 * 1 - register 440 */ 441# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 442 /* 0 - memory 443 * 1 - register 444 */ 445# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 446# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 447# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 448#define PACKET3_AQUIRE_MEM 0x58 449#define PACKET3_REWIND 0x59 450#define PACKET3_LOAD_UCONFIG_REG 0x5E 451#define PACKET3_LOAD_SH_REG 0x5F 452#define PACKET3_LOAD_CONFIG_REG 0x60 453#define PACKET3_LOAD_CONTEXT_REG 0x61 454#define PACKET3_SET_CONFIG_REG 0x68 455#define PACKET3_SET_CONFIG_REG_START 0x00002000 456#define PACKET3_SET_CONFIG_REG_END 0x00002c00 457#define PACKET3_SET_CONTEXT_REG 0x69 458#define PACKET3_SET_CONTEXT_REG_START 0x0000a000 459#define PACKET3_SET_CONTEXT_REG_END 0x0000a400 460#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 461#define PACKET3_SET_SH_REG 0x76 462#define PACKET3_SET_SH_REG_START 0x00002c00 463#define PACKET3_SET_SH_REG_END 0x00003000 464#define PACKET3_SET_SH_REG_OFFSET 0x77 465#define PACKET3_SET_QUEUE_REG 0x78 466#define PACKET3_SET_UCONFIG_REG 0x79 467#define PACKET3_SET_UCONFIG_REG_START 0x0000c000 468#define PACKET3_SET_UCONFIG_REG_END 0x0000c400 469#define PACKET3_SCRATCH_RAM_WRITE 0x7D 470#define PACKET3_SCRATCH_RAM_READ 0x7E 471#define PACKET3_LOAD_CONST_RAM 0x80 472#define PACKET3_WRITE_CONST_RAM 0x81 473#define PACKET3_DUMP_CONST_RAM 0x83 474#define PACKET3_INCREMENT_CE_COUNTER 0x84 475#define PACKET3_INCREMENT_DE_COUNTER 0x85 476#define PACKET3_WAIT_ON_CE_COUNTER 0x86 477#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 478#define PACKET3_SWITCH_BUFFER 0x8B 479 480/* SDMA - first instance at 0xd000, second at 0xd800 */ 481#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 482#define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ 483#define SDMA_MAX_INSTANCE 2 484 485#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 486 (((sub_op) & 0xFF) << 8) | \ 487 (((op) & 0xFF) << 0)) 488/* sDMA opcodes */ 489#define SDMA_OPCODE_NOP 0 490# define SDMA_NOP_COUNT(x) (((x) & 0x3FFF) << 16) 491#define SDMA_OPCODE_COPY 1 492# define SDMA_COPY_SUB_OPCODE_LINEAR 0 493# define SDMA_COPY_SUB_OPCODE_TILED 1 494# define SDMA_COPY_SUB_OPCODE_SOA 3 495# define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 496# define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 497# define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 498#define SDMA_OPCODE_WRITE 2 499# define SDMA_WRITE_SUB_OPCODE_LINEAR 0 500# define SDMA_WRTIE_SUB_OPCODE_TILED 1 501#define SDMA_OPCODE_INDIRECT_BUFFER 4 502#define SDMA_OPCODE_FENCE 5 503#define SDMA_OPCODE_TRAP 6 504#define SDMA_OPCODE_SEMAPHORE 7 505# define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 506 /* 0 - increment 507 * 1 - write 1 508 */ 509# define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 510 /* 0 - wait 511 * 1 - signal 512 */ 513# define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 514 /* mailbox */ 515#define SDMA_OPCODE_POLL_REG_MEM 8 516# define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 517 /* 0 - wait_reg_mem 518 * 1 - wr_wait_wr_reg 519 */ 520# define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 521 /* 0 - always 522 * 1 - < 523 * 2 - <= 524 * 3 - == 525 * 4 - != 526 * 5 - >= 527 * 6 - > 528 */ 529# define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 530 /* 0 = register 531 * 1 = memory 532 */ 533#define SDMA_OPCODE_COND_EXEC 9 534#define SDMA_OPCODE_CONSTANT_FILL 11 535# define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 536 /* 0 = byte fill 537 * 2 = DW fill 538 */ 539#define SDMA_OPCODE_GENERATE_PTE_PDE 12 540#define SDMA_OPCODE_TIMESTAMP 13 541# define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 542# define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 543# define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 544#define SDMA_OPCODE_SRBM_WRITE 14 545# define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 546 /* byte mask */ 547 548#define VCE_CMD_NO_OP 0x00000000 549#define VCE_CMD_END 0x00000001 550#define VCE_CMD_IB 0x00000002 551#define VCE_CMD_FENCE 0x00000003 552#define VCE_CMD_TRAP 0x00000004 553#define VCE_CMD_IB_AUTO 0x00000005 554#define VCE_CMD_SEMAPHORE 0x00000006 555 556/* if PTR32, these are the bases for scratch and lds */ 557#define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 558#define SHARED_BASE(x) ((x) << 16) /* LDS */ 559 560#define KFD_CIK_SDMA_QUEUE_OFFSET 0x200 561 562/* valid for both DEFAULT_MTYPE and APE1_MTYPE */ 563enum { 564 MTYPE_CACHED = 0, 565 MTYPE_NONCACHED = 3 566}; 567 568#endif 569