1/* 2 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver 3 * 4 * Copyright (C) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 17 18#include <linux/init.h> 19#include <linux/slab.h> 20#include <linux/module.h> 21#include <linux/kconfig.h> 22#include <linux/platform_device.h> 23#include <linux/spinlock.h> 24#include <linux/of.h> 25#include <linux/of_irq.h> 26#include <linux/of_address.h> 27#include <linux/of_platform.h> 28#include <linux/interrupt.h> 29#include <linux/irq.h> 30#include <linux/io.h> 31#include <linux/irqdomain.h> 32#include <linux/irqchip.h> 33#include <linux/irqchip/chained_irq.h> 34 35/* Register offsets in the L2 interrupt controller */ 36#define CPU_STATUS 0x00 37#define CPU_SET 0x04 38#define CPU_CLEAR 0x08 39#define CPU_MASK_STATUS 0x0c 40#define CPU_MASK_SET 0x10 41#define CPU_MASK_CLEAR 0x14 42 43/* L2 intc private data structure */ 44struct brcmstb_l2_intc_data { 45 int parent_irq; 46 void __iomem *base; 47 struct irq_domain *domain; 48 bool can_wake; 49 u32 saved_mask; /* for suspend/resume */ 50}; 51 52static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc) 53{ 54 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc); 55 struct irq_chip_generic *gc = irq_get_domain_generic_chip(b->domain, 0); 56 struct irq_chip *chip = irq_desc_get_chip(desc); 57 unsigned int irq; 58 u32 status; 59 60 chained_irq_enter(chip, desc); 61 62 status = irq_reg_readl(gc, CPU_STATUS) & 63 ~(irq_reg_readl(gc, CPU_MASK_STATUS)); 64 65 if (status == 0) { 66 raw_spin_lock(&desc->lock); 67 handle_bad_irq(desc); 68 raw_spin_unlock(&desc->lock); 69 goto out; 70 } 71 72 do { 73 irq = ffs(status) - 1; 74 /* ack at our level */ 75 irq_reg_writel(gc, 1 << irq, CPU_CLEAR); 76 status &= ~(1 << irq); 77 generic_handle_irq(irq_find_mapping(b->domain, irq)); 78 } while (status); 79out: 80 chained_irq_exit(chip, desc); 81} 82 83static void brcmstb_l2_intc_suspend(struct irq_data *d) 84{ 85 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 86 struct brcmstb_l2_intc_data *b = gc->private; 87 88 irq_gc_lock(gc); 89 /* Save the current mask */ 90 b->saved_mask = irq_reg_readl(gc, CPU_MASK_STATUS); 91 92 if (b->can_wake) { 93 /* Program the wakeup mask */ 94 irq_reg_writel(gc, ~gc->wake_active, CPU_MASK_SET); 95 irq_reg_writel(gc, gc->wake_active, CPU_MASK_CLEAR); 96 } 97 irq_gc_unlock(gc); 98} 99 100static void brcmstb_l2_intc_resume(struct irq_data *d) 101{ 102 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 103 struct brcmstb_l2_intc_data *b = gc->private; 104 105 irq_gc_lock(gc); 106 /* Clear unmasked non-wakeup interrupts */ 107 irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active, CPU_CLEAR); 108 109 /* Restore the saved mask */ 110 irq_reg_writel(gc, b->saved_mask, CPU_MASK_SET); 111 irq_reg_writel(gc, ~b->saved_mask, CPU_MASK_CLEAR); 112 irq_gc_unlock(gc); 113} 114 115int __init brcmstb_l2_intc_of_init(struct device_node *np, 116 struct device_node *parent) 117{ 118 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 119 struct brcmstb_l2_intc_data *data; 120 struct irq_chip_generic *gc; 121 struct irq_chip_type *ct; 122 int ret; 123 unsigned int flags; 124 125 data = kzalloc(sizeof(*data), GFP_KERNEL); 126 if (!data) 127 return -ENOMEM; 128 129 data->base = of_iomap(np, 0); 130 if (!data->base) { 131 pr_err("failed to remap intc L2 registers\n"); 132 ret = -ENOMEM; 133 goto out_free; 134 } 135 136 /* Disable all interrupts by default */ 137 writel(0xffffffff, data->base + CPU_MASK_SET); 138 139 /* Wakeup interrupts may be retained from S5 (cold boot) */ 140 data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake"); 141 if (!data->can_wake) 142 writel(0xffffffff, data->base + CPU_CLEAR); 143 144 data->parent_irq = irq_of_parse_and_map(np, 0); 145 if (!data->parent_irq) { 146 pr_err("failed to find parent interrupt\n"); 147 ret = -EINVAL; 148 goto out_unmap; 149 } 150 151 data->domain = irq_domain_add_linear(np, 32, 152 &irq_generic_chip_ops, NULL); 153 if (!data->domain) { 154 ret = -ENOMEM; 155 goto out_unmap; 156 } 157 158 /* MIPS chips strapped for BE will automagically configure the 159 * peripheral registers for CPU-native byte order. 160 */ 161 flags = 0; 162 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 163 flags |= IRQ_GC_BE_IO; 164 165 /* Allocate a single Generic IRQ chip for this node */ 166 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, 167 np->full_name, handle_edge_irq, clr, 0, flags); 168 if (ret) { 169 pr_err("failed to allocate generic irq chip\n"); 170 goto out_free_domain; 171 } 172 173 /* Set the IRQ chaining logic */ 174 irq_set_chained_handler_and_data(data->parent_irq, 175 brcmstb_l2_intc_irq_handle, data); 176 177 gc = irq_get_domain_generic_chip(data->domain, 0); 178 gc->reg_base = data->base; 179 gc->private = data; 180 ct = gc->chip_types; 181 182 ct->chip.irq_ack = irq_gc_ack_set_bit; 183 ct->regs.ack = CPU_CLEAR; 184 185 ct->chip.irq_mask = irq_gc_mask_disable_reg; 186 ct->regs.disable = CPU_MASK_SET; 187 188 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 189 ct->regs.enable = CPU_MASK_CLEAR; 190 191 ct->chip.irq_suspend = brcmstb_l2_intc_suspend; 192 ct->chip.irq_resume = brcmstb_l2_intc_resume; 193 194 if (data->can_wake) { 195 /* This IRQ chip can wake the system, set all child interrupts 196 * in wake_enabled mask 197 */ 198 gc->wake_enabled = 0xffffffff; 199 ct->chip.irq_set_wake = irq_gc_set_wake; 200 } 201 202 pr_info("registered L2 intc (mem: 0x%p, parent irq: %d)\n", 203 data->base, data->parent_irq); 204 205 return 0; 206 207out_free_domain: 208 irq_domain_remove(data->domain); 209out_unmap: 210 iounmap(data->base); 211out_free: 212 kfree(data); 213 return ret; 214} 215IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_intc_of_init); 216