1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2010 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28/* 29 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging 30 * facilities. 31 */ 32 33#ifndef __CVMX_L2C_H__ 34#define __CVMX_L2C_H__ 35 36#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */ 37#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */ 38#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */ 39 40 41#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */ 42#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) 43 44/* Defines for index aliasing computations */ 45#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits()) 46#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) 47#define CVMX_L2C_MEMBANK_SELECT_SIZE 4096 48 49/* Defines for Virtualizations, valid only from Octeon II onwards. */ 50#define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 64 : 0) 51#define CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 32 : 0) 52 53union cvmx_l2c_tag { 54 uint64_t u64; 55 struct { 56#ifdef __BIG_ENDIAN_BITFIELD 57 uint64_t reserved:28; 58 uint64_t V:1; /* Line valid */ 59 uint64_t D:1; /* Line dirty */ 60 uint64_t L:1; /* Line locked */ 61 uint64_t U:1; /* Use, LRU eviction */ 62 uint64_t addr:32; /* Phys mem (not all bits valid) */ 63#else 64 uint64_t addr:32; /* Phys mem (not all bits valid) */ 65 uint64_t U:1; /* Use, LRU eviction */ 66 uint64_t L:1; /* Line locked */ 67 uint64_t D:1; /* Line dirty */ 68 uint64_t V:1; /* Line valid */ 69 uint64_t reserved:28; 70#endif 71 } s; 72}; 73 74/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */ 75#define CVMX_L2C_TADS 1 76 77 /* L2C Performance Counter events. */ 78enum cvmx_l2c_event { 79 CVMX_L2C_EVENT_CYCLES = 0, 80 CVMX_L2C_EVENT_INSTRUCTION_MISS = 1, 81 CVMX_L2C_EVENT_INSTRUCTION_HIT = 2, 82 CVMX_L2C_EVENT_DATA_MISS = 3, 83 CVMX_L2C_EVENT_DATA_HIT = 4, 84 CVMX_L2C_EVENT_MISS = 5, 85 CVMX_L2C_EVENT_HIT = 6, 86 CVMX_L2C_EVENT_VICTIM_HIT = 7, 87 CVMX_L2C_EVENT_INDEX_CONFLICT = 8, 88 CVMX_L2C_EVENT_TAG_PROBE = 9, 89 CVMX_L2C_EVENT_TAG_UPDATE = 10, 90 CVMX_L2C_EVENT_TAG_COMPLETE = 11, 91 CVMX_L2C_EVENT_TAG_DIRTY = 12, 92 CVMX_L2C_EVENT_DATA_STORE_NOP = 13, 93 CVMX_L2C_EVENT_DATA_STORE_READ = 14, 94 CVMX_L2C_EVENT_DATA_STORE_WRITE = 15, 95 CVMX_L2C_EVENT_FILL_DATA_VALID = 16, 96 CVMX_L2C_EVENT_WRITE_REQUEST = 17, 97 CVMX_L2C_EVENT_READ_REQUEST = 18, 98 CVMX_L2C_EVENT_WRITE_DATA_VALID = 19, 99 CVMX_L2C_EVENT_XMC_NOP = 20, 100 CVMX_L2C_EVENT_XMC_LDT = 21, 101 CVMX_L2C_EVENT_XMC_LDI = 22, 102 CVMX_L2C_EVENT_XMC_LDD = 23, 103 CVMX_L2C_EVENT_XMC_STF = 24, 104 CVMX_L2C_EVENT_XMC_STT = 25, 105 CVMX_L2C_EVENT_XMC_STP = 26, 106 CVMX_L2C_EVENT_XMC_STC = 27, 107 CVMX_L2C_EVENT_XMC_DWB = 28, 108 CVMX_L2C_EVENT_XMC_PL2 = 29, 109 CVMX_L2C_EVENT_XMC_PSL1 = 30, 110 CVMX_L2C_EVENT_XMC_IOBLD = 31, 111 CVMX_L2C_EVENT_XMC_IOBST = 32, 112 CVMX_L2C_EVENT_XMC_IOBDMA = 33, 113 CVMX_L2C_EVENT_XMC_IOBRSP = 34, 114 CVMX_L2C_EVENT_XMC_BUS_VALID = 35, 115 CVMX_L2C_EVENT_XMC_MEM_DATA = 36, 116 CVMX_L2C_EVENT_XMC_REFL_DATA = 37, 117 CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38, 118 CVMX_L2C_EVENT_RSC_NOP = 39, 119 CVMX_L2C_EVENT_RSC_STDN = 40, 120 CVMX_L2C_EVENT_RSC_FILL = 41, 121 CVMX_L2C_EVENT_RSC_REFL = 42, 122 CVMX_L2C_EVENT_RSC_STIN = 43, 123 CVMX_L2C_EVENT_RSC_SCIN = 44, 124 CVMX_L2C_EVENT_RSC_SCFL = 45, 125 CVMX_L2C_EVENT_RSC_SCDN = 46, 126 CVMX_L2C_EVENT_RSC_DATA_VALID = 47, 127 CVMX_L2C_EVENT_RSC_VALID_FILL = 48, 128 CVMX_L2C_EVENT_RSC_VALID_STRSP = 49, 129 CVMX_L2C_EVENT_RSC_VALID_REFL = 50, 130 CVMX_L2C_EVENT_LRF_REQ = 51, 131 CVMX_L2C_EVENT_DT_RD_ALLOC = 52, 132 CVMX_L2C_EVENT_DT_WR_INVAL = 53, 133 CVMX_L2C_EVENT_MAX 134}; 135 136/* L2C Performance Counter events for Octeon2. */ 137enum cvmx_l2c_tad_event { 138 CVMX_L2C_TAD_EVENT_NONE = 0, 139 CVMX_L2C_TAD_EVENT_TAG_HIT = 1, 140 CVMX_L2C_TAD_EVENT_TAG_MISS = 2, 141 CVMX_L2C_TAD_EVENT_TAG_NOALLOC = 3, 142 CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4, 143 CVMX_L2C_TAD_EVENT_SC_FAIL = 5, 144 CVMX_L2C_TAD_EVENT_SC_PASS = 6, 145 CVMX_L2C_TAD_EVENT_LFB_VALID = 7, 146 CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8, 147 CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB = 9, 148 CVMX_L2C_TAD_EVENT_QUAD0_INDEX = 128, 149 CVMX_L2C_TAD_EVENT_QUAD0_READ = 129, 150 CVMX_L2C_TAD_EVENT_QUAD0_BANK = 130, 151 CVMX_L2C_TAD_EVENT_QUAD0_WDAT = 131, 152 CVMX_L2C_TAD_EVENT_QUAD1_INDEX = 144, 153 CVMX_L2C_TAD_EVENT_QUAD1_READ = 145, 154 CVMX_L2C_TAD_EVENT_QUAD1_BANK = 146, 155 CVMX_L2C_TAD_EVENT_QUAD1_WDAT = 147, 156 CVMX_L2C_TAD_EVENT_QUAD2_INDEX = 160, 157 CVMX_L2C_TAD_EVENT_QUAD2_READ = 161, 158 CVMX_L2C_TAD_EVENT_QUAD2_BANK = 162, 159 CVMX_L2C_TAD_EVENT_QUAD2_WDAT = 163, 160 CVMX_L2C_TAD_EVENT_QUAD3_INDEX = 176, 161 CVMX_L2C_TAD_EVENT_QUAD3_READ = 177, 162 CVMX_L2C_TAD_EVENT_QUAD3_BANK = 178, 163 CVMX_L2C_TAD_EVENT_QUAD3_WDAT = 179, 164 CVMX_L2C_TAD_EVENT_MAX 165}; 166 167/** 168 * Configure one of the four L2 Cache performance counters to capture event 169 * occurrences. 170 * 171 * @counter: The counter to configure. Range 0..3. 172 * @event: The type of L2 Cache event occurrence to count. 173 * @clear_on_read: When asserted, any read of the performance counter 174 * clears the counter. 175 * 176 * @note The routine does not clear the counter. 177 */ 178void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, uint32_t clear_on_read); 179 180/** 181 * Read the given L2 Cache performance counter. The counter must be configured 182 * before reading, but this routine does not enforce this requirement. 183 * 184 * @counter: The counter to configure. Range 0..3. 185 * 186 * Returns The current counter value. 187 */ 188uint64_t cvmx_l2c_read_perf(uint32_t counter); 189 190/** 191 * Return the L2 Cache way partitioning for a given core. 192 * 193 * @core: The core processor of interest. 194 * 195 * Returns The mask specifying the partitioning. 0 bits in mask indicates 196 * the cache 'ways' that a core can evict from. 197 * -1 on error 198 */ 199int cvmx_l2c_get_core_way_partition(uint32_t core); 200 201/** 202 * Partitions the L2 cache for a core 203 * 204 * @core: The core that the partitioning applies to. 205 * @mask: The partitioning of the ways expressed as a binary 206 * mask. A 0 bit allows the core to evict cache lines from 207 * a way, while a 1 bit blocks the core from evicting any 208 * lines from that way. There must be at least one allowed 209 * way (0 bit) in the mask. 210 * 211 212 * @note If any ways are blocked for all cores and the HW blocks, then 213 * those ways will never have any cache lines evicted from them. 214 * All cores and the hardware blocks are free to read from all 215 * ways regardless of the partitioning. 216 */ 217int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); 218 219/** 220 * Return the L2 Cache way partitioning for the hw blocks. 221 * 222 * Returns The mask specifying the reserved way. 0 bits in mask indicates 223 * the cache 'ways' that a core can evict from. 224 * -1 on error 225 */ 226int cvmx_l2c_get_hw_way_partition(void); 227 228/** 229 * Partitions the L2 cache for the hardware blocks. 230 * 231 * @mask: The partitioning of the ways expressed as a binary 232 * mask. A 0 bit allows the core to evict cache lines from 233 * a way, while a 1 bit blocks the core from evicting any 234 * lines from that way. There must be at least one allowed 235 * way (0 bit) in the mask. 236 * 237 238 * @note If any ways are blocked for all cores and the HW blocks, then 239 * those ways will never have any cache lines evicted from them. 240 * All cores and the hardware blocks are free to read from all 241 * ways regardless of the partitioning. 242 */ 243int cvmx_l2c_set_hw_way_partition(uint32_t mask); 244 245 246/** 247 * Locks a line in the L2 cache at the specified physical address 248 * 249 * @addr: physical address of line to lock 250 * 251 * Returns 0 on success, 252 * 1 if line not locked. 253 */ 254int cvmx_l2c_lock_line(uint64_t addr); 255 256/** 257 * Locks a specified memory region in the L2 cache. 258 * 259 * Note that if not all lines can be locked, that means that all 260 * but one of the ways (associations) available to the locking 261 * core are locked. Having only 1 association available for 262 * normal caching may have a significant adverse affect on performance. 263 * Care should be taken to ensure that enough of the L2 cache is left 264 * unlocked to allow for normal caching of DRAM. 265 * 266 * @start: Physical address of the start of the region to lock 267 * @len: Length (in bytes) of region to lock 268 * 269 * Returns Number of requested lines that where not locked. 270 * 0 on success (all locked) 271 */ 272int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len); 273 274/** 275 * Unlock and flush a cache line from the L2 cache. 276 * IMPORTANT: Must only be run by one core at a time due to use 277 * of L2C debug features. 278 * Note that this function will flush a matching but unlocked cache line. 279 * (If address is not in L2, no lines are flushed.) 280 * 281 * @address: Physical address to unlock 282 * 283 * Returns 0: line not unlocked 284 * 1: line unlocked 285 */ 286int cvmx_l2c_unlock_line(uint64_t address); 287 288/** 289 * Unlocks a region of memory that is locked in the L2 cache 290 * 291 * @start: start physical address 292 * @len: length (in bytes) to unlock 293 * 294 * Returns Number of locked lines that the call unlocked 295 */ 296int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len); 297 298/** 299 * Read the L2 controller tag for a given location in L2 300 * 301 * @association: 302 * Which association to read line from 303 * @index: Which way to read from. 304 * 305 * Returns l2c tag structure for line requested. 306 */ 307union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index); 308 309/* Wrapper providing a deprecated old function name */ 310static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) __attribute__((deprecated)); 311static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) 312{ 313 return cvmx_l2c_get_tag(association, index); 314} 315 316 317/** 318 * Returns the cache index for a given physical address 319 * 320 * @addr: physical address 321 * 322 * Returns L2 cache index 323 */ 324uint32_t cvmx_l2c_address_to_index(uint64_t addr); 325 326/** 327 * Flushes (and unlocks) the entire L2 cache. 328 * IMPORTANT: Must only be run by one core at a time due to use 329 * of L2C debug features. 330 */ 331void cvmx_l2c_flush(void); 332 333/** 334 * 335 * Returns Returns the size of the L2 cache in bytes, 336 * -1 on error (unrecognized model) 337 */ 338int cvmx_l2c_get_cache_size_bytes(void); 339 340/** 341 * Return the number of sets in the L2 Cache 342 * 343 * Returns 344 */ 345int cvmx_l2c_get_num_sets(void); 346 347/** 348 * Return log base 2 of the number of sets in the L2 cache 349 * Returns 350 */ 351int cvmx_l2c_get_set_bits(void); 352/** 353 * Return the number of associations in the L2 Cache 354 * 355 * Returns 356 */ 357int cvmx_l2c_get_num_assoc(void); 358 359/** 360 * Flush a line from the L2 cache 361 * This should only be called from one core at a time, as this routine 362 * sets the core to the 'debug' core in order to flush the line. 363 * 364 * @assoc: Association (or way) to flush 365 * @index: Index to flush 366 */ 367void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index); 368 369#endif /* __CVMX_L2C_H__ */ 370