| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | nv20.c | 30 u32 flags, struct nvkm_fb_tile *tile) in nv20_fb_tile_init() argument
32 tile->addr = 0x00000001 | addr; in nv20_fb_tile_init()
33 tile->limit = max(1u, addr + size) - 1; in nv20_fb_tile_init()
34 tile->pitch = pitch; in nv20_fb_tile_init()
36 pfb->tile.comp(pfb, i, size, flags, tile); in nv20_fb_tile_init()
37 tile->addr |= 2; in nv20_fb_tile_init()
43 struct nvkm_fb_tile *tile) in nv20_fb_tile_comp() argument
47 if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv20_fb_tile_comp()
48 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ in nv20_fb_tile_comp()
49 else tile->zcomp = 0x04000000; /* Z24S8 */ in nv20_fb_tile_comp()
[all …]
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| D | nv10.c | 30 u32 flags, struct nvkm_fb_tile *tile) in nv10_fb_tile_init() argument
32 tile->addr = 0x80000000 | addr; in nv10_fb_tile_init()
33 tile->limit = max(1u, addr + size) - 1; in nv10_fb_tile_init()
34 tile->pitch = pitch; in nv10_fb_tile_init()
38 nv10_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_fini() argument
40 tile->addr = 0; in nv10_fb_tile_fini()
41 tile->limit = 0; in nv10_fb_tile_fini()
42 tile->pitch = 0; in nv10_fb_tile_fini()
43 tile->zcomp = 0; in nv10_fb_tile_fini()
47 nv10_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_prog() argument
[all …]
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| D | nv30.c | 32 u32 flags, struct nvkm_fb_tile *tile) in nv30_fb_tile_init() argument
36 tile->addr = (0 << 4); in nv30_fb_tile_init()
38 if (pfb->tile.comp) /* z compression */ in nv30_fb_tile_init()
39 pfb->tile.comp(pfb, i, size, flags, tile); in nv30_fb_tile_init()
40 tile->addr = (1 << 4); in nv30_fb_tile_init()
43 tile->addr |= 0x00000001; /* enable */ in nv30_fb_tile_init()
44 tile->addr |= addr; in nv30_fb_tile_init()
45 tile->limit = max(1u, addr + size) - 1; in nv30_fb_tile_init()
46 tile->pitch = pitch; in nv30_fb_tile_init()
51 struct nvkm_fb_tile *tile) in nv30_fb_tile_comp() argument
[all …]
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| D | nv36.c | 30 struct nvkm_fb_tile *tile) in nv36_fb_tile_comp() argument
34 if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv36_fb_tile_comp()
35 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ in nv36_fb_tile_comp()
36 else tile->zcomp |= 0x20000000; /* Z24S8 */ in nv36_fb_tile_comp()
37 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv36_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; in nv36_fb_tile_comp()
40 tile->zcomp |= 0x80000000; in nv36_fb_tile_comp()
56 .tile.regions = 8,
57 .tile.init = nv30_fb_tile_init,
58 .tile.comp = nv36_fb_tile_comp,
[all …]
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| D | nv35.c | 30 struct nvkm_fb_tile *tile) in nv35_fb_tile_comp() argument
34 if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv35_fb_tile_comp()
35 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ in nv35_fb_tile_comp()
36 else tile->zcomp |= 0x08000000; /* Z24S8 */ in nv35_fb_tile_comp()
37 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv35_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; in nv35_fb_tile_comp()
40 tile->zcomp |= 0x40000000; in nv35_fb_tile_comp()
56 .tile.regions = 8,
57 .tile.init = nv30_fb_tile_init,
58 .tile.comp = nv35_fb_tile_comp,
[all …]
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| D | nv40.c | 30 struct nvkm_fb_tile *tile) in nv40_fb_tile_comp() argument
35 !nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
36 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
37 tile->zcomp |= ((tile->tag->offset ) >> 8); in nv40_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; in nv40_fb_tile_comp()
40 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
70 .tile.regions = 8,
71 .tile.init = nv30_fb_tile_init,
72 .tile.comp = nv40_fb_tile_comp,
73 .tile.fini = nv20_fb_tile_fini,
[all …]
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| D | nv25.c | 30 struct nvkm_fb_tile *tile) in nv25_fb_tile_comp() argument
34 if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { in nv25_fb_tile_comp()
35 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ in nv25_fb_tile_comp()
36 else tile->zcomp = 0x00200000; /* Z24S8 */ in nv25_fb_tile_comp()
37 tile->zcomp |= tile->tag->offset; in nv25_fb_tile_comp()
39 tile->zcomp |= 0x01000000; in nv25_fb_tile_comp()
55 .tile.regions = 8,
56 .tile.init = nv20_fb_tile_init,
57 .tile.comp = nv25_fb_tile_comp,
58 .tile.fini = nv20_fb_tile_fini,
[all …]
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| D | nv44.c | 30 u32 flags, struct nvkm_fb_tile *tile) in nv44_fb_tile_init() argument
32 tile->addr = 0x00000001; /* mode = vram */ in nv44_fb_tile_init()
33 tile->addr |= addr; in nv44_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv44_fb_tile_init()
35 tile->pitch = pitch; in nv44_fb_tile_init()
39 nv44_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) in nv44_fb_tile_prog() argument
41 nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
42 nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); in nv44_fb_tile_prog()
43 nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
73 .tile.regions = 12,
[all …]
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| D | nv46.c | 30 u32 flags, struct nvkm_fb_tile *tile) in nv46_fb_tile_init() argument
33 if (!(flags & 4)) tile->addr = (0 << 3); in nv46_fb_tile_init()
34 else tile->addr = (1 << 3); in nv46_fb_tile_init()
36 tile->addr |= 0x00000001; /* mode = vram */ in nv46_fb_tile_init()
37 tile->addr |= addr; in nv46_fb_tile_init()
38 tile->limit = max(1u, addr + size) - 1; in nv46_fb_tile_init()
39 tile->pitch = pitch; in nv46_fb_tile_init()
53 .tile.regions = 15,
54 .tile.init = nv46_fb_tile_init,
55 .tile.fini = nv20_fb_tile_fini,
[all …]
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| D | nv41.c | 29 nv41_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) in nv41_fb_tile_prog() argument
31 nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
32 nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
33 nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
35 nv_wr32(pfb, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
63 .tile.regions = 12,
64 .tile.init = nv30_fb_tile_init,
65 .tile.comp = nv40_fb_tile_comp,
66 .tile.fini = nv20_fb_tile_fini,
67 .tile.prog = nv41_fb_tile_prog,
|
| D | nv04.c | 68 priv->base.tile.regions = impl->tile.regions; in nv04_fb_ctor()
69 priv->base.tile.init = impl->tile.init; in nv04_fb_ctor()
70 priv->base.tile.comp = impl->tile.comp; in nv04_fb_ctor()
71 priv->base.tile.fini = impl->tile.fini; in nv04_fb_ctor()
72 priv->base.tile.prog = impl->tile.prog; in nv04_fb_ctor()
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| D | nv47.c | 39 .tile.regions = 15,
40 .tile.init = nv30_fb_tile_init,
41 .tile.comp = nv40_fb_tile_comp,
42 .tile.fini = nv20_fb_tile_fini,
43 .tile.prog = nv41_fb_tile_prog,
|
| D | nv49.c | 39 .tile.regions = 15,
40 .tile.init = nv30_fb_tile_init,
41 .tile.comp = nv40_fb_tile_comp,
42 .tile.fini = nv20_fb_tile_fini,
43 .tile.prog = nv41_fb_tile_prog,
|
| D | nv4e.c | 39 .tile.regions = 12,
40 .tile.init = nv46_fb_tile_init,
41 .tile.fini = nv20_fb_tile_fini,
42 .tile.prog = nv44_fb_tile_prog,
|
| D | nv1a.c | 39 .tile.regions = 8,
40 .tile.init = nv10_fb_tile_init,
41 .tile.fini = nv10_fb_tile_fini,
42 .tile.prog = nv10_fb_tile_prog,
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| D | base.c | 83 for (i = 0; i < pfb->tile.regions; i++) in _nvkm_fb_init()
84 pfb->tile.prog(pfb, i, &pfb->tile.region[i]); in _nvkm_fb_init()
95 for (i = 0; i < pfb->tile.regions; i++) in _nvkm_fb_dtor()
96 pfb->tile.fini(pfb, i, &pfb->tile.region[i]); in _nvkm_fb_dtor()
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| D | nv04.h | 25 } tile; member
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | nv40.c | 208 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; in nv40_gr_tile_prog() local
223 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile_prog()
224 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile_prog()
225 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile_prog()
226 nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile_prog()
227 nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile_prog()
228 nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile_prog()
232 nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv40_gr_tile_prog()
233 nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile_prog()
238 nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); in nv40_gr_tile_prog()
[all …]
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| D | nv20.c | 160 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; in nv20_gr_tile_prog() local
168 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv20_gr_tile_prog()
169 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv20_gr_tile_prog()
170 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); in nv20_gr_tile_prog()
173 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit); in nv20_gr_tile_prog()
175 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch); in nv20_gr_tile_prog()
177 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr); in nv20_gr_tile_prog()
180 nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv20_gr_tile_prog()
182 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp); in nv20_gr_tile_prog()
328 for (i = 0; i < pfb->tile.regions; i++) in nv20_gr_init()
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| D | nv10.c | 1122 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; in nv10_gr_tile_prog() local
1130 nv_wr32(priv, NV10_PGRAPH_TLIMIT(i), tile->limit); in nv10_gr_tile_prog()
1131 nv_wr32(priv, NV10_PGRAPH_TSIZE(i), tile->pitch); in nv10_gr_tile_prog()
1132 nv_wr32(priv, NV10_PGRAPH_TILE(i), tile->addr); in nv10_gr_tile_prog()
1283 for (i = 0; i < pfb->tile.regions; i++) in nv10_gr_init()
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| D | nv30.c | 202 for (i = 0; i < pfb->tile.regions; i++) in nv30_gr_init()
|
| /linux-4.1.27/arch/tile/ |
| D | Makefile | 17 CROSS_COMPILE := $(TILERA_ROOT)/bin/tile-
38 ifeq ($(ARCH),tile)
54 head-y := arch/tile/kernel/head_$(BITS).o
56 libs-y += arch/tile/lib/
60 core-y += arch/tile/
62 core-$(CONFIG_TILE_GXIO) += arch/tile/gxio/
65 INSTALL_PATH ?= $(TILERA_ROOT)/tile/boot
|
| D | Kconfig.debug | 22 defined in arch/tile/kernel/hvglue.S. This allows tracing
|
| D | Kconfig | 148 default "arch/tile/configs/tilepro_defconfig" if !TILEGX
149 default "arch/tile/configs/tilegx_defconfig" if TILEGX
398 source "arch/tile/gxio/Kconfig"
465 source "arch/tile/Kconfig.debug"
473 source "arch/tile/kvm/Kconfig"
|
| /linux-4.1.27/Documentation/devicetree/bindings/arm/ |
| D | vexpress.txt | 8 The motherboard and each core tile should be described by a separate
9 Device Tree source file, with the tile's description including
21 where <model> is the full tile model name (as used in the tile's
27 If a tile comes in several variants or can be used in more then one
40 - tile model name (use name from the tile's Technical Reference
43 - tile's HBI number (unique ARM's board model ID, visible on the
106 0xf means "master" site (site containing main CPU tile)
123 between the motherboard and the tile. The first cell defines the Chip
125 All interrupt lines between the motherboard and the tile are active
140 can be used to obtain required phandle in the tile's "aliases" node:
[all …]
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| D | vexpress-scc.txt | 16 where <model> is the full tile model name (as used
17 in the tile's Technical Reference Manual),
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| D | versatile-fpga-irq.txt | 5 controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
|
| /linux-4.1.27/drivers/hid/ |
| D | hid-picolcd_fb.c | 101 int chip, int tile) in picolcd_fb_send_tile() argument
124 hid_set_field(report1->field[0], 4, 0xb8 | tile); in picolcd_fb_send_tile()
137 tdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_send_tile()
152 int chip, int tile) in picolcd_fb_update_tile() argument
156 u8 *vdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_update_tile()
160 const u8 *bdata = bitmap + tile * 256 + chip * 8 + b * 32; in picolcd_fb_update_tile()
168 const u8 *bdata = bitmap + (tile * 256 + chip * 8 + b * 32) * 8; in picolcd_fb_update_tile()
237 int chip, tile, n; in picolcd_fb_update() local
258 for (tile = 0; tile < 8; tile++) { in picolcd_fb_update()
261 fbdata->bpp, chip, tile)) in picolcd_fb_update()
[all …]
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| /linux-4.1.27/drivers/gpu/drm/nouveau/ |
| D | nouveau_bo.c | 50 int i = reg - drm->tile.reg; in nv10_bo_update_tile_region()
52 struct nvkm_fb_tile *tile = &pfb->tile.region[i]; in nv10_bo_update_tile_region() local
57 if (tile->pitch) in nv10_bo_update_tile_region()
58 pfb->tile.fini(pfb, i, tile); in nv10_bo_update_tile_region()
61 pfb->tile.init(pfb, i, addr, size, pitch, flags, tile); in nv10_bo_update_tile_region()
63 pfb->tile.prog(pfb, i, tile); in nv10_bo_update_tile_region()
75 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; in nv10_bo_get_tile_region() local
77 spin_lock(&drm->tile.lock); in nv10_bo_get_tile_region()
79 if (!tile->used && in nv10_bo_get_tile_region()
80 (!tile->fence || nouveau_fence_done(tile->fence))) in nv10_bo_get_tile_region()
[all …]
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| D | nouveau_bo.h | 31 struct nouveau_drm_tile *tile; member
|
| D | nouveau_drm.h | 156 } tile; member
|
| D | nv50_display.c | 2374 u8 tile = nvbo->tile_mode; in nv50_fb_ctor() local
2377 tile >>= 4; /* yep.. */ in nv50_fb_ctor()
2392 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : in nv50_fb_ctor()
2397 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : in nv50_fb_ctor()
2400 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : in nv50_fb_ctor()
|
| D | nouveau_drm.c | 387 spin_lock_init(&drm->tile.lock); in nouveau_drm_load()
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/ |
| D | nv31.c | 185 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; in nv31_mpeg_tile_prog() local
188 nv_wr32(priv, 0x00b008 + (i * 0x10), tile->pitch); in nv31_mpeg_tile_prog()
189 nv_wr32(priv, 0x00b004 + (i * 0x10), tile->limit); in nv31_mpeg_tile_prog()
190 nv_wr32(priv, 0x00b000 + (i * 0x10), tile->addr); in nv31_mpeg_tile_prog()
274 for (i = 0; i < pfb->tile.regions; i++) in nv31_mpeg_init()
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| /linux-4.1.27/arch/tile/kernel/ |
| D | smp.c | 240 HV_Coord tile; in ipi_init() local
244 tile.x = cpu_x(cpu); in ipi_init()
245 tile.y = cpu_y(cpu); in ipi_init()
246 if (hv_get_ipi_pte(tile, KERNEL_PL, &pte) != 0) in ipi_init()
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| D | vmlinux.lds.S | 10 OUTPUT_ARCH(tile)
|
| D | Makefile | 10 intvec_$(BITS).o regs_$(BITS).o tile-desc_$(BITS).o
|
| D | hvglue_trace.c | 192 HV_WRAP3(int, hv_get_ipi_pte, HV_Coord, tile, int, pl, HV_PTE*, pte)
199 HV_WRAP2(HV_Errno, hv_trigger_ipi, HV_Coord, tile, int, interrupt)
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| /linux-4.1.27/tools/perf/config/ |
| D | Makefile.arch | 11 -e s/tile.*/tile/ )
|
| /linux-4.1.27/arch/arm/mach-vexpress/ |
| D | Kconfig | 52 tile support or Flattened Device Tree based support options.
67 The TC2 (A15x2 A7x3) versatile express core tile integrates a logic
80 with a TC2 (A15x2 A7x3) big.LITTLE core tile.
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| /linux-4.1.27/arch/arm/mach-realview/ |
| D | Kconfig | 33 Enable support for the Cortex-A9MPCore tile fitted to the
46 Enable support for the ARM11MPCore tile fitted to the Realview(R)
53 Enable support for the ARM11MPCore Revision B tile on the
56 not compatible with other revisions of the ARM11MPCore tile.
|
| /linux-4.1.27/arch/frv/kernel/ |
| D | head.S | 549 # split a tile off of the region defined by GR8-GR9
552 # GR4 - IAMPR value representing tile
553 # GR5 - DAMPR value representing tile
554 # GR6 - IAMLR value representing tile
555 # GR7 - DAMLR value representing tile
557 # GR9 region top pointer updated to exclude new tile
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| D | head-uc-fr451.S | 64 movgs gr5,dampr11 ; General I/O tile
67 # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
|
| D | head-uc-fr401.S | 250 movgs gr5,dampr7 ; General I/O tile
252 # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
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| D | head-mmu-fr451.S | 248 movgs gr5,damlr11 ; General I/O tile
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| D | head-uc-fr555.S | 240 # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
|
| /linux-4.1.27/drivers/gpu/drm/ |
| D | drm_edid.c | 3959 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; in drm_parse_display_id() local
3966 w = tile->tile_size[0] | tile->tile_size[1] << 8; in drm_parse_display_id()
3967 h = tile->tile_size[2] | tile->tile_size[3] << 8; in drm_parse_display_id()
3969 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); in drm_parse_display_id()
3970 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); in drm_parse_display_id()
3971 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); in drm_parse_display_id()
3972 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); in drm_parse_display_id()
3975 if (tile->tile_cap & 0x80) in drm_parse_display_id()
3985 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); in drm_parse_display_id()
3989 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); in drm_parse_display_id()
[all …]
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| D | drm_crtc.c | 4337 char tile[256]; in drm_mode_connector_set_tile_property() local
4349 snprintf(tile, 256, "%d:%d:%d:%d:%d:%d:%d:%d", in drm_mode_connector_set_tile_property()
4354 size = strlen(tile) + 1; in drm_mode_connector_set_tile_property()
4357 size, tile); in drm_mode_connector_set_tile_property()
|
| /linux-4.1.27/arch/tile/kernel/vdso/ |
| D | vdso.lds.S | 18 OUTPUT_ARCH(tile)
|
| /linux-4.1.27/arch/arm/include/debug/ |
| D | vexpress.S | 29 @ - the original A9 core tile (based on ARM Cortex-A9 r0p1)
|
| /linux-4.1.27/drivers/char/ |
| D | Makefile | 63 obj-$(CONFIG_TILE_SROM) += tile-srom.o
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
| D | fb.h | 67 } tile; member
|
| /linux-4.1.27/drivers/net/ethernet/ |
| D | Makefile | 80 obj-$(CONFIG_TILE_NET) += tile/
|
| D | Kconfig | 170 source "drivers/net/ethernet/tile/Kconfig"
|
| /linux-4.1.27/drivers/video/fbdev/ |
| D | gbefb.c | 1011 u16 *tile; in gbefb_mmap() local
1029 tile = &gbe_tiles.cpu[offset >> TILE_SHIFT]; in gbefb_mmap()
1035 phys_addr = (((unsigned long) (*tile)) << TILE_SHIFT) + offset; in gbefb_mmap()
1048 tile++; in gbefb_mmap()
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| D | cirrusfb.c | 867 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407); in cirrusfb_set_par_foo() local
877 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407); in cirrusfb_set_par_foo()
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| D | Kconfig | 211 This enables tile blitting. Tile blitting is a drawing technique
214 default drawing element is a tile, drawing functions will be passed
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| /linux-4.1.27/arch/tile/include/hv/ |
| D | hypervisor.h | 594 int hv_get_ipi_pte(HV_Coord tile, int pl, HV_PTE* pte);
661 HV_Errno hv_trigger_ipi(HV_Coord tile, int interrupt);
|
| /linux-4.1.27/drivers/rtc/ |
| D | Makefile | 143 obj-$(CONFIG_RTC_DRV_TILE) += rtc-tile.o
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| /linux-4.1.27/ |
| D | Makefile | 282 SRCARCH := tile
285 SRCARCH := tile
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| D | MAINTAINERS | 9958 F: arch/tile/
9959 F: drivers/char/tile-srom.c
9961 F: drivers/net/ethernet/tile/
9962 F: drivers/rtc/rtc-tile.c
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| /linux-4.1.27/Documentation/ |
| D | kmemleak.txt | 14 Kmemleak is supported on x86, arm, powerpc, sparc, sh, microblaze, ppc, mips, s390, metag and tile.
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| /linux-4.1.27/Documentation/frv/ |
| D | features.txt | 120 (1) The core kernel image is covered by as small a tile as possible
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| /linux-4.1.27/Documentation/ioctl/ |
| D | ioctl-number.txt | 300 0xA2 00-0F arch/tile/include/asm/hardwall.h
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| /linux-4.1.27/mm/ |
| D | Kconfig | 299 # On the 'tile' arch, USB OHCI needs the bounce pool since tilegx will often
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| /linux-4.1.27/arch/arm/ |
| D | Kconfig.debug | 1101 bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)"
1106 this applies only to the V2P-CA9 tile.
|