208 	struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];  in nv40_gr_tile_prog()  local
223 		nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);  in nv40_gr_tile_prog()
224 		nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);  in nv40_gr_tile_prog()
225 		nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);  in nv40_gr_tile_prog()
226 		nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);  in nv40_gr_tile_prog()
227 		nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);  in nv40_gr_tile_prog()
228 		nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);  in nv40_gr_tile_prog()
232 			nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);  in nv40_gr_tile_prog()
233 			nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);  in nv40_gr_tile_prog()
238 			nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp);  in nv40_gr_tile_prog()
239 			nv_wr32(priv, NV41_PGRAPH_ZCOMP1(i), tile->zcomp);  in nv40_gr_tile_prog()
247 		nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);  in nv40_gr_tile_prog()
248 		nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);  in nv40_gr_tile_prog()
249 		nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);  in nv40_gr_tile_prog()
259 		nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch);  in nv40_gr_tile_prog()
260 		nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit);  in nv40_gr_tile_prog()
261 		nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr);  in nv40_gr_tile_prog()
262 		nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);  in nv40_gr_tile_prog()
263 		nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);  in nv40_gr_tile_prog()
264 		nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);  in nv40_gr_tile_prog()
269 			nv_wr32(priv, NV47_PGRAPH_ZCOMP0(i), tile->zcomp);  in nv40_gr_tile_prog()
270 			nv_wr32(priv, NV47_PGRAPH_ZCOMP1(i), tile->zcomp);  in nv40_gr_tile_prog()
473 	for (i = 0; i < pfb->tile.regions; i++)  in nv40_gr_init()