Lines Matching refs:tile

8 The motherboard and each core tile should be described by a separate
9 Device Tree source file, with the tile's description including
21   where <model> is the full tile model name (as used in the tile's
27   If a tile comes in several variants or can be used in more then one
40 - tile model name (use name from the tile's Technical Reference
43 - tile's HBI number (unique ARM's board model ID, visible on the
106   0xf means "master" site (site containing main CPU tile)
123 between the motherboard and the tile. The first cell defines the Chip
125 All interrupt lines between the motherboard and the tile are active
140 can be used to obtain required phandle in the tile's "aliases" node:
149 The tile description should define a "smb" node, describing the
150 Static Memory Bus between the tile and motherboard. It must define
164 Example of a VE tile description (simplified)