Searched refs:reg (Results 1 - 200 of 5403) sorted by relevance

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/linux-4.1.27/arch/parisc/include/asm/
H A Dasmregs.h24 rp: .reg %r2
25 arg3: .reg %r23
26 arg2: .reg %r24
27 arg1: .reg %r25
28 arg0: .reg %r26
29 dp: .reg %r27
30 ret0: .reg %r28
31 ret1: .reg %r29
32 sl: .reg %r29
33 sp: .reg %r30
37 arg7: .reg r19
38 arg6: .reg r20
39 arg5: .reg r21
40 arg4: .reg r22
41 gp: .reg r27
42 ap: .reg r29
46 r0: .reg %r0
47 r1: .reg %r1
48 r2: .reg %r2
49 r3: .reg %r3
50 r4: .reg %r4
51 r5: .reg %r5
52 r6: .reg %r6
53 r7: .reg %r7
54 r8: .reg %r8
55 r9: .reg %r9
56 r10: .reg %r10
57 r11: .reg %r11
58 r12: .reg %r12
59 r13: .reg %r13
60 r14: .reg %r14
61 r15: .reg %r15
62 r16: .reg %r16
63 r17: .reg %r17
64 r18: .reg %r18
65 r19: .reg %r19
66 r20: .reg %r20
67 r21: .reg %r21
68 r22: .reg %r22
69 r23: .reg %r23
70 r24: .reg %r24
71 r25: .reg %r25
72 r26: .reg %r26
73 r27: .reg %r27
74 r28: .reg %r28
75 r29: .reg %r29
76 r30: .reg %r30
77 r31: .reg %r31
82 sr0: .reg %sr0
83 sr1: .reg %sr1
84 sr2: .reg %sr2
85 sr3: .reg %sr3
86 sr4: .reg %sr4
87 sr5: .reg %sr5
88 sr6: .reg %sr6
89 sr7: .reg %sr7
94 fr0: .reg %fr0
95 fr1: .reg %fr1
96 fr2: .reg %fr2
97 fr3: .reg %fr3
98 fr4: .reg %fr4
99 fr5: .reg %fr5
100 fr6: .reg %fr6
101 fr7: .reg %fr7
102 fr8: .reg %fr8
103 fr9: .reg %fr9
104 fr10: .reg %fr10
105 fr11: .reg %fr11
106 fr12: .reg %fr12
107 fr13: .reg %fr13
108 fr14: .reg %fr14
109 fr15: .reg %fr15
110 fr16: .reg %fr16
111 fr17: .reg %fr17
112 fr18: .reg %fr18
113 fr19: .reg %fr19
114 fr20: .reg %fr20
115 fr21: .reg %fr21
116 fr22: .reg %fr22
117 fr23: .reg %fr23
118 fr24: .reg %fr24
119 fr25: .reg %fr25
120 fr26: .reg %fr26
121 fr27: .reg %fr27
122 fr28: .reg %fr28
123 fr29: .reg %fr29
124 fr30: .reg %fr30
125 fr31: .reg %fr31
130 rctr: .reg %cr0
131 pidr1: .reg %cr8
132 pidr2: .reg %cr9
133 ccr: .reg %cr10
134 sar: .reg %cr11
135 pidr3: .reg %cr12
136 pidr4: .reg %cr13
137 iva: .reg %cr14
138 eiem: .reg %cr15
139 itmr: .reg %cr16
140 pcsq: .reg %cr17
141 pcoq: .reg %cr18
142 iir: .reg %cr19
143 isr: .reg %cr20
144 ior: .reg %cr21
145 ipsw: .reg %cr22
146 eirr: .reg %cr23
147 tr0: .reg %cr24
148 tr1: .reg %cr25
149 tr2: .reg %cr26
150 tr3: .reg %cr27
151 tr4: .reg %cr28
152 tr5: .reg %cr29
153 tr6: .reg %cr30
154 tr7: .reg %cr31
157 cr0: .reg %cr0
158 cr8: .reg %cr8
159 cr9: .reg %cr9
160 cr10: .reg %cr10
161 cr11: .reg %cr11
162 cr12: .reg %cr12
163 cr13: .reg %cr13
164 cr14: .reg %cr14
165 cr15: .reg %cr15
166 cr16: .reg %cr16
167 cr17: .reg %cr17
168 cr18: .reg %cr18
169 cr19: .reg %cr19
170 cr20: .reg %cr20
171 cr21: .reg %cr21
172 cr22: .reg %cr22
173 cr23: .reg %cr23
174 cr24: .reg %cr24
175 cr25: .reg %cr25
176 cr26: .reg %cr26
177 cr27: .reg %cr27
178 cr28: .reg %cr28
179 cr29: .reg %cr29
180 cr30: .reg %cr30
181 cr31: .reg %cr31
H A Dspecial_insns.h4 #define mfctl(reg) ({ \
7 "mfctl " #reg ",%0" : \
26 #define mfsp(reg) ({ \
29 "mfsp " #reg ",%0" : \
/linux-4.1.27/arch/mips/include/asm/
H A Dasm-eva.h18 #define kernel_ll(reg, addr) "ll " reg ", " addr "\n"
19 #define kernel_sc(reg, addr) "sc " reg ", " addr "\n"
20 #define kernel_lw(reg, addr) "lw " reg ", " addr "\n"
21 #define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n"
22 #define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n"
23 #define kernel_lh(reg, addr) "lh " reg ", " addr "\n"
24 #define kernel_lb(reg, addr) "lb " reg ", " addr "\n"
25 #define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n"
26 #define kernel_sw(reg, addr) "sw " reg ", " addr "\n"
27 #define kernel_swl(reg, addr) "swl " reg ", " addr "\n"
28 #define kernel_swr(reg, addr) "swr " reg ", " addr "\n"
29 #define kernel_sh(reg, addr) "sh " reg ", " addr "\n"
30 #define kernel_sb(reg, addr) "sb " reg ", " addr "\n"
37 #define kernel_sd(reg, addr) user_sw(reg, addr)
38 #define kernel_ld(reg, addr) user_lw(reg, addr)
40 #define kernel_sd(reg, addr) "sd " reg", " addr "\n"
41 #define kernel_ld(reg, addr) "ld " reg", " addr "\n"
46 #define __BUILD_EVA_INSN(insn, reg, addr) \
50 " "insn" "reg", "addr "\n" \
54 #define user_ll(reg, addr) __BUILD_EVA_INSN("lle", reg, addr)
55 #define user_sc(reg, addr) __BUILD_EVA_INSN("sce", reg, addr)
56 #define user_lw(reg, addr) __BUILD_EVA_INSN("lwe", reg, addr)
57 #define user_lwl(reg, addr) __BUILD_EVA_INSN("lwle", reg, addr)
58 #define user_lwr(reg, addr) __BUILD_EVA_INSN("lwre", reg, addr)
59 #define user_lh(reg, addr) __BUILD_EVA_INSN("lhe", reg, addr)
60 #define user_lb(reg, addr) __BUILD_EVA_INSN("lbe", reg, addr)
61 #define user_lbu(reg, addr) __BUILD_EVA_INSN("lbue", reg, addr)
63 #define user_ld(reg, addr) user_lw(reg, addr)
64 #define user_sw(reg, addr) __BUILD_EVA_INSN("swe", reg, addr)
65 #define user_swl(reg, addr) __BUILD_EVA_INSN("swle", reg, addr)
66 #define user_swr(reg, addr) __BUILD_EVA_INSN("swre", reg, addr)
67 #define user_sh(reg, addr) __BUILD_EVA_INSN("she", reg, addr)
68 #define user_sb(reg, addr) __BUILD_EVA_INSN("sbe", reg, addr)
70 #define user_sd(reg, addr) user_sw(reg, addr)
75 #define user_ll(reg, addr) kernel_ll(reg, addr)
76 #define user_sc(reg, addr) kernel_sc(reg, addr)
77 #define user_lw(reg, addr) kernel_lw(reg, addr)
78 #define user_lwl(reg, addr) kernel_lwl(reg, addr)
79 #define user_lwr(reg, addr) kernel_lwr(reg, addr)
80 #define user_lh(reg, addr) kernel_lh(reg, addr)
81 #define user_lb(reg, addr) kernel_lb(reg, addr)
82 #define user_lbu(reg, addr) kernel_lbu(reg, addr)
83 #define user_sw(reg, addr) kernel_sw(reg, addr)
84 #define user_swl(reg, addr) kernel_swl(reg, addr)
85 #define user_swr(reg, addr) kernel_swr(reg, addr)
86 #define user_sh(reg, addr) kernel_sh(reg, addr)
87 #define user_sb(reg, addr) kernel_sb(reg, addr)
90 #define user_sd(reg, addr) kernel_sw(reg, addr)
91 #define user_ld(reg, addr) kernel_lw(reg, addr)
93 #define user_sd(reg, addr) kernel_sd(reg, addr)
94 #define user_ld(reg, addr) kernel_ld(reg, addr)
102 #define kernel_ll(reg, addr) ll reg, addr
103 #define kernel_sc(reg, addr) sc reg, addr
104 #define kernel_lw(reg, addr) lw reg, addr
105 #define kernel_lwl(reg, addr) lwl reg, addr
106 #define kernel_lwr(reg, addr) lwr reg, addr
107 #define kernel_lh(reg, addr) lh reg, addr
108 #define kernel_lb(reg, addr) lb reg, addr
109 #define kernel_lbu(reg, addr) lbu reg, addr
110 #define kernel_sw(reg, addr) sw reg, addr
111 #define kernel_swl(reg, addr) swl reg, addr
112 #define kernel_swr(reg, addr) swr reg, addr
113 #define kernel_sh(reg, addr) sh reg, addr
114 #define kernel_sb(reg, addr) sb reg, addr
121 #define kernel_sd(reg, addr) user_sw(reg, addr)
122 #define kernel_ld(reg, addr) user_lw(reg, addr)
124 #define kernel_sd(reg, addr) sd reg, addr
125 #define kernel_ld(reg, addr) ld reg, addr
130 #define __BUILD_EVA_INSN(insn, reg, addr) \
134 insn reg, addr; \
138 #define user_ll(reg, addr) __BUILD_EVA_INSN(lle, reg, addr)
139 #define user_sc(reg, addr) __BUILD_EVA_INSN(sce, reg, addr)
140 #define user_lw(reg, addr) __BUILD_EVA_INSN(lwe, reg, addr)
141 #define user_lwl(reg, addr) __BUILD_EVA_INSN(lwle, reg, addr)
142 #define user_lwr(reg, addr) __BUILD_EVA_INSN(lwre, reg, addr)
143 #define user_lh(reg, addr) __BUILD_EVA_INSN(lhe, reg, addr)
144 #define user_lb(reg, addr) __BUILD_EVA_INSN(lbe, reg, addr)
145 #define user_lbu(reg, addr) __BUILD_EVA_INSN(lbue, reg, addr)
147 #define user_ld(reg, addr) user_lw(reg, addr)
148 #define user_sw(reg, addr) __BUILD_EVA_INSN(swe, reg, addr)
149 #define user_swl(reg, addr) __BUILD_EVA_INSN(swle, reg, addr)
150 #define user_swr(reg, addr) __BUILD_EVA_INSN(swre, reg, addr)
151 #define user_sh(reg, addr) __BUILD_EVA_INSN(she, reg, addr)
152 #define user_sb(reg, addr) __BUILD_EVA_INSN(sbe, reg, addr)
154 #define user_sd(reg, addr) user_sw(reg, addr)
158 #define user_ll(reg, addr) kernel_ll(reg, addr)
159 #define user_sc(reg, addr) kernel_sc(reg, addr)
160 #define user_lw(reg, addr) kernel_lw(reg, addr)
161 #define user_lwl(reg, addr) kernel_lwl(reg, addr)
162 #define user_lwr(reg, addr) kernel_lwr(reg, addr)
163 #define user_lh(reg, addr) kernel_lh(reg, addr)
164 #define user_lb(reg, addr) kernel_lb(reg, addr)
165 #define user_lbu(reg, addr) kernel_lbu(reg, addr)
166 #define user_sw(reg, addr) kernel_sw(reg, addr)
167 #define user_swl(reg, addr) kernel_swl(reg, addr)
168 #define user_swr(reg, addr) kernel_swr(reg, addr)
169 #define user_sh(reg, addr) kernel_sh(reg, addr)
170 #define user_sb(reg, addr) kernel_sb(reg, addr)
173 #define user_sd(reg, addr) kernel_sw(reg, addr)
174 #define user_ld(reg, addr) kernel_lw(reg, addr)
176 #define user_sd(reg, addr) kernel_sd(reg, addr)
177 #define user_ld(reg, addr) kernel_sd(reg, addr)
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
H A Diop_version_defs.h15 #define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
H A Diop_sap_in_defs.h15 #define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
H A Diop_sap_out_defs.h15 #define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
/linux-4.1.27/drivers/memory/tegra/
H A Dtegra114.c28 .reg = 0x228,
32 .reg = 0x2e8,
42 .reg = 0x228,
46 .reg = 0x2f4,
56 .reg = 0x228,
60 .reg = 0x2e8,
70 .reg = 0x228,
74 .reg = 0x2f4,
84 .reg = 0x228,
88 .reg = 0x2ec,
98 .reg = 0x228,
102 .reg = 0x2f8,
112 .reg = 0x228,
116 .reg = 0x300,
126 .reg = 0x228,
130 .reg = 0x308,
140 .reg = 0x228,
144 .reg = 0x308,
154 .reg = 0x228,
158 .reg = 0x2e4,
168 .reg = 0x228,
172 .reg = 0x2f0,
182 .reg = 0x228,
186 .reg = 0x2fc,
196 .reg = 0x228,
200 .reg = 0x334,
210 .reg = 0x228,
214 .reg = 0x33c,
224 .reg = 0x228,
228 .reg = 0x30c,
238 .reg = 0x228,
242 .reg = 0x318,
252 .reg = 0x228,
256 .reg = 0x310,
266 .reg = 0x228,
270 .reg = 0x310,
280 .reg = 0x228,
284 .reg = 0x334,
294 .reg = 0x228,
298 .reg = 0x328,
308 .reg = 0x228,
312 .reg = 0x344,
322 .reg = 0x228,
326 .reg = 0x344,
336 .reg = 0x22c,
340 .reg = 0x338,
350 .reg = 0x22c,
354 .reg = 0x354,
364 .reg = 0x22c,
368 .reg = 0x354,
378 .reg = 0x22c,
382 .reg = 0x358,
392 .reg = 0x22c,
396 .reg = 0x358,
406 .reg = 0x324,
416 .reg = 0x320,
426 .reg = 0x22c,
430 .reg = 0x300,
440 .reg = 0x22c,
444 .reg = 0x304,
454 .reg = 0x22c,
458 .reg = 0x304,
468 .reg = 0x22c,
472 .reg = 0x328,
482 .reg = 0x22c,
486 .reg = 0x364,
496 .reg = 0x22c,
500 .reg = 0x368,
510 .reg = 0x22c,
514 .reg = 0x368,
524 .reg = 0x22c,
528 .reg = 0x36c,
538 .reg = 0x22c,
542 .reg = 0x30c,
552 .reg = 0x22c,
556 .reg = 0x2e4,
566 .reg = 0x22c,
570 .reg = 0x338,
580 .reg = 0x22c,
584 .reg = 0x340,
594 .reg = 0x22c,
598 .reg = 0x318,
608 .reg = 0x22c,
612 .reg = 0x314,
622 .reg = 0x22c,
626 .reg = 0x31c,
636 .reg = 0x324,
646 .reg = 0x320,
656 .reg = 0x22c,
660 .reg = 0x348,
670 .reg = 0x22c,
674 .reg = 0x348,
684 .reg = 0x22c,
688 .reg = 0x35c,
698 .reg = 0x22c,
702 .reg = 0x35c,
712 .reg = 0x230,
716 .reg = 0x360,
726 .reg = 0x230,
730 .reg = 0x360,
740 .reg = 0x230,
744 .reg = 0x37c,
754 .reg = 0x230,
758 .reg = 0x37c,
768 .reg = 0x230,
772 .reg = 0x380,
782 .reg = 0x230,
786 .reg = 0x380,
796 .reg = 0x230,
800 .reg = 0x388,
810 .reg = 0x230,
814 .reg = 0x384,
824 .reg = 0x230,
828 .reg = 0x388,
838 .reg = 0x230,
842 .reg = 0x384,
852 .reg = 0x38c,
862 .reg = 0x38c,
872 .reg = 0x230,
876 .reg = 0x390,
886 .reg = 0x230,
890 .reg = 0x390,
899 { .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
900 { .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
901 { .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
902 { .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
903 { .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
904 { .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
905 { .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
906 { .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
907 { .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
908 { .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
909 { .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
910 { .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
911 { .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
912 { .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
913 { .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
914 { .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
H A Dtegra124.c28 .reg = 0x228,
32 .reg = 0x2e8,
42 .reg = 0x228,
46 .reg = 0x2f4,
56 .reg = 0x228,
60 .reg = 0x2e8,
70 .reg = 0x228,
74 .reg = 0x2f4,
84 .reg = 0x228,
88 .reg = 0x2ec,
98 .reg = 0x228,
102 .reg = 0x2f8,
112 .reg = 0x228,
116 .reg = 0x2e0,
126 .reg = 0x228,
130 .reg = 0x2e4,
140 .reg = 0x228,
144 .reg = 0x2f0,
154 .reg = 0x228,
158 .reg = 0x2fc,
168 .reg = 0x228,
172 .reg = 0x318,
182 .reg = 0x228,
186 .reg = 0x310,
196 .reg = 0x228,
200 .reg = 0x310,
210 .reg = 0x228,
214 .reg = 0x328,
224 .reg = 0x228,
228 .reg = 0x344,
238 .reg = 0x228,
242 .reg = 0x344,
252 .reg = 0x228,
256 .reg = 0x350,
266 .reg = 0x22c,
270 .reg = 0x354,
280 .reg = 0x22c,
284 .reg = 0x354,
294 .reg = 0x22c,
298 .reg = 0x358,
308 .reg = 0x22c,
312 .reg = 0x358,
322 .reg = 0x324,
332 .reg = 0x320,
342 .reg = 0x22c,
346 .reg = 0x328,
356 .reg = 0x22c,
360 .reg = 0x2e0,
370 .reg = 0x22c,
374 .reg = 0x2e4,
384 .reg = 0x22c,
388 .reg = 0x318,
398 .reg = 0x22c,
402 .reg = 0x314,
412 .reg = 0x324,
422 .reg = 0x320,
432 .reg = 0x22c,
436 .reg = 0x348,
446 .reg = 0x22c,
450 .reg = 0x348,
460 .reg = 0x22c,
464 .reg = 0x350,
474 .reg = 0x22c,
478 .reg = 0x35c,
488 .reg = 0x22c,
492 .reg = 0x35c,
502 .reg = 0x230,
506 .reg = 0x360,
516 .reg = 0x230,
520 .reg = 0x360,
530 .reg = 0x230,
534 .reg = 0x370,
544 .reg = 0x230,
548 .reg = 0x374,
558 .reg = 0x230,
562 .reg = 0x374,
572 .reg = 0x230,
576 .reg = 0x37c,
586 .reg = 0x230,
590 .reg = 0x37c,
600 .reg = 0x230,
604 .reg = 0x380,
614 .reg = 0x230,
618 .reg = 0x380,
628 .reg = 0x230,
632 .reg = 0x384,
642 .reg = 0x230,
646 .reg = 0x388,
656 .reg = 0x230,
660 .reg = 0x388,
670 .reg = 0x230,
674 .reg = 0x390,
684 .reg = 0x230,
688 .reg = 0x390,
698 .reg = 0x230,
702 .reg = 0x3a4,
712 .reg = 0x230,
716 .reg = 0x3a4,
727 .reg = 0x230,
731 .reg = 0x3c8,
742 .reg = 0x230,
746 .reg = 0x3c8,
756 .reg = 0x230,
760 .reg = 0x2f0,
770 .reg = 0x234,
774 .reg = 0x3b8,
784 .reg = 0x234,
788 .reg = 0x3bc,
798 .reg = 0x234,
802 .reg = 0x3c0,
812 .reg = 0x234,
816 .reg = 0x3c4,
826 .reg = 0x234,
830 .reg = 0x3b8,
840 .reg = 0x234,
844 .reg = 0x3bc,
854 .reg = 0x234,
858 .reg = 0x3c0,
868 .reg = 0x234,
872 .reg = 0x3c4,
882 .reg = 0x234,
886 .reg = 0x394,
896 .reg = 0x234,
900 .reg = 0x394,
910 .reg = 0x234,
914 .reg = 0x398,
924 .reg = 0x234,
928 .reg = 0x3c8,
937 { .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
938 { .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
939 { .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
940 { .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
941 { .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
942 { .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
943 { .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
944 { .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
945 { .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
946 { .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
947 { .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
948 { .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
949 { .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
950 { .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
951 { .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
952 { .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
953 { .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
954 { .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
955 { .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
956 { .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
957 { .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
958 { .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
959 { .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
H A Dtegra30.c28 .reg = 0x228,
32 .reg = 0x2e8,
42 .reg = 0x228,
46 .reg = 0x2f4,
56 .reg = 0x228,
60 .reg = 0x2e8,
70 .reg = 0x228,
74 .reg = 0x2f4,
84 .reg = 0x228,
88 .reg = 0x2ec,
98 .reg = 0x228,
102 .reg = 0x2f8,
112 .reg = 0x228,
116 .reg = 0x2ec,
126 .reg = 0x228,
130 .reg = 0x2f8,
140 .reg = 0x228,
144 .reg = 0x300,
154 .reg = 0x228,
158 .reg = 0x308,
168 .reg = 0x228,
172 .reg = 0x308,
182 .reg = 0x228,
186 .reg = 0x328,
196 .reg = 0x228,
200 .reg = 0x364,
210 .reg = 0x228,
214 .reg = 0x2e0,
224 .reg = 0x228,
228 .reg = 0x2e4,
238 .reg = 0x228,
242 .reg = 0x2f0,
252 .reg = 0x228,
256 .reg = 0x2fc,
266 .reg = 0x228,
270 .reg = 0x334,
280 .reg = 0x228,
284 .reg = 0x33c,
294 .reg = 0x228,
298 .reg = 0x30c,
308 .reg = 0x228,
312 .reg = 0x318,
322 .reg = 0x228,
326 .reg = 0x310,
336 .reg = 0x228,
340 .reg = 0x310,
350 .reg = 0x228,
354 .reg = 0x334,
364 .reg = 0x228,
368 .reg = 0x33c,
378 .reg = 0x228,
382 .reg = 0x328,
392 .reg = 0x228,
396 .reg = 0x32c,
406 .reg = 0x228,
410 .reg = 0x32c,
420 .reg = 0x228,
424 .reg = 0x344,
434 .reg = 0x228,
438 .reg = 0x344,
448 .reg = 0x228,
452 .reg = 0x350,
462 .reg = 0x22c,
466 .reg = 0x338,
476 .reg = 0x22c,
480 .reg = 0x340,
490 .reg = 0x22c,
494 .reg = 0x354,
504 .reg = 0x22c,
508 .reg = 0x354,
518 .reg = 0x22c,
522 .reg = 0x358,
532 .reg = 0x22c,
536 .reg = 0x358,
546 .reg = 0x324,
556 .reg = 0x320,
566 .reg = 0x22c,
570 .reg = 0x300,
580 .reg = 0x22c,
584 .reg = 0x304,
594 .reg = 0x22c,
598 .reg = 0x304,
608 .reg = 0x22c,
612 .reg = 0x330,
622 .reg = 0x22c,
626 .reg = 0x364,
636 .reg = 0x22c,
640 .reg = 0x368,
650 .reg = 0x22c,
654 .reg = 0x368,
664 .reg = 0x22c,
668 .reg = 0x36c,
678 .reg = 0x22c,
682 .reg = 0x30c,
692 .reg = 0x22c,
696 .reg = 0x2e0,
706 .reg = 0x22c,
710 .reg = 0x2e4,
720 .reg = 0x22c,
724 .reg = 0x338,
734 .reg = 0x22c,
738 .reg = 0x340,
748 .reg = 0x22c,
752 .reg = 0x318,
762 .reg = 0x22c,
766 .reg = 0x314,
776 .reg = 0x22c,
780 .reg = 0x31c,
790 .reg = 0x324,
800 .reg = 0x320,
810 .reg = 0x22c,
814 .reg = 0x330,
824 .reg = 0x22c,
828 .reg = 0x348,
838 .reg = 0x22c,
842 .reg = 0x348,
852 .reg = 0x22c,
856 .reg = 0x350,
866 .reg = 0x22c,
870 .reg = 0x35c,
880 .reg = 0x22c,
884 .reg = 0x35c,
894 .reg = 0x230,
898 .reg = 0x360,
908 .reg = 0x230,
912 .reg = 0x360,
921 { .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
922 { .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
923 { .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
924 { .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
925 { .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 },
926 { .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
927 { .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
928 { .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
929 { .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
930 { .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
931 { .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
932 { .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
933 { .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
934 { .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
935 { .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
936 { .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
/linux-4.1.27/drivers/gpu/drm/exynos/
H A Dexynos_dp_reg.c29 u32 reg; exynos_dp_enable_video_mute() local
32 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); exynos_dp_enable_video_mute()
33 reg |= HDCP_VIDEO_MUTE; exynos_dp_enable_video_mute()
34 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); exynos_dp_enable_video_mute()
36 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); exynos_dp_enable_video_mute()
37 reg &= ~HDCP_VIDEO_MUTE; exynos_dp_enable_video_mute()
38 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); exynos_dp_enable_video_mute()
44 u32 reg; exynos_dp_stop_video() local
46 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); exynos_dp_stop_video()
47 reg &= ~VIDEO_EN; exynos_dp_stop_video()
48 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); exynos_dp_stop_video()
53 u32 reg; exynos_dp_lane_swap() local
56 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | exynos_dp_lane_swap()
59 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | exynos_dp_lane_swap()
62 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); exynos_dp_lane_swap()
67 u32 reg; exynos_dp_init_analog_param() local
69 reg = TX_TERMINAL_CTRL_50_OHM; exynos_dp_init_analog_param()
70 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); exynos_dp_init_analog_param()
72 reg = SEL_24M | TX_DVDD_BIT_1_0625V; exynos_dp_init_analog_param()
73 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); exynos_dp_init_analog_param()
75 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; exynos_dp_init_analog_param()
76 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); exynos_dp_init_analog_param()
78 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | exynos_dp_init_analog_param()
80 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); exynos_dp_init_analog_param()
82 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | exynos_dp_init_analog_param()
84 writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL); exynos_dp_init_analog_param()
109 u32 reg; exynos_dp_reset() local
114 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | exynos_dp_reset()
117 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); exynos_dp_reset()
119 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | exynos_dp_reset()
122 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); exynos_dp_reset()
159 u32 reg; exynos_dp_config_interrupt() local
162 reg = COMMON_INT_MASK_1; exynos_dp_config_interrupt()
163 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1); exynos_dp_config_interrupt()
165 reg = COMMON_INT_MASK_2; exynos_dp_config_interrupt()
166 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2); exynos_dp_config_interrupt()
168 reg = COMMON_INT_MASK_3; exynos_dp_config_interrupt()
169 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3); exynos_dp_config_interrupt()
171 reg = COMMON_INT_MASK_4; exynos_dp_config_interrupt()
172 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4); exynos_dp_config_interrupt()
174 reg = INT_STA_MASK; exynos_dp_config_interrupt()
175 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK); exynos_dp_config_interrupt()
180 u32 reg; exynos_dp_get_pll_lock_status() local
182 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); exynos_dp_get_pll_lock_status()
183 if (reg & PLL_LOCK) exynos_dp_get_pll_lock_status()
191 u32 reg; exynos_dp_set_pll_power_down() local
194 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); exynos_dp_set_pll_power_down()
195 reg |= DP_PLL_PD; exynos_dp_set_pll_power_down()
196 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); exynos_dp_set_pll_power_down()
198 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); exynos_dp_set_pll_power_down()
199 reg &= ~DP_PLL_PD; exynos_dp_set_pll_power_down()
200 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); exynos_dp_set_pll_power_down()
208 u32 reg; exynos_dp_set_analog_power_down() local
213 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
214 reg |= AUX_PD; exynos_dp_set_analog_power_down()
215 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
217 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
218 reg &= ~AUX_PD; exynos_dp_set_analog_power_down()
219 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
224 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
225 reg |= CH0_PD; exynos_dp_set_analog_power_down()
226 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
228 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
229 reg &= ~CH0_PD; exynos_dp_set_analog_power_down()
230 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
235 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
236 reg |= CH1_PD; exynos_dp_set_analog_power_down()
237 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
239 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
240 reg &= ~CH1_PD; exynos_dp_set_analog_power_down()
241 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
246 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
247 reg |= CH2_PD; exynos_dp_set_analog_power_down()
248 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
250 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
251 reg &= ~CH2_PD; exynos_dp_set_analog_power_down()
252 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
257 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
258 reg |= CH3_PD; exynos_dp_set_analog_power_down()
259 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
261 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
262 reg &= ~CH3_PD; exynos_dp_set_analog_power_down()
263 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
268 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
269 reg |= DP_PHY_PD; exynos_dp_set_analog_power_down()
270 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
272 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
273 reg &= ~DP_PHY_PD; exynos_dp_set_analog_power_down()
274 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
279 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | exynos_dp_set_analog_power_down()
281 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
293 u32 reg; exynos_dp_init_analog_func() local
298 reg = PLL_LOCK_CHG; exynos_dp_init_analog_func()
299 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); exynos_dp_init_analog_func()
301 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); exynos_dp_init_analog_func()
302 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); exynos_dp_init_analog_func()
303 writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL); exynos_dp_init_analog_func()
320 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); exynos_dp_init_analog_func()
321 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N exynos_dp_init_analog_func()
323 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); exynos_dp_init_analog_func()
328 u32 reg; exynos_dp_clear_hotplug_interrupts() local
333 reg = HOTPLUG_CHG | HPD_LOST | PLUG; exynos_dp_clear_hotplug_interrupts()
334 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); exynos_dp_clear_hotplug_interrupts()
336 reg = INT_HPD; exynos_dp_clear_hotplug_interrupts()
337 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); exynos_dp_clear_hotplug_interrupts()
342 u32 reg; exynos_dp_init_hpd() local
349 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); exynos_dp_init_hpd()
350 reg &= ~(F_HPD | HPD_CTRL); exynos_dp_init_hpd()
351 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); exynos_dp_init_hpd()
356 u32 reg; exynos_dp_get_irq_type() local
359 reg = gpio_get_value(dp->hpd_gpio); exynos_dp_get_irq_type()
360 if (reg) exynos_dp_get_irq_type()
366 reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); exynos_dp_get_irq_type()
368 if (reg & PLUG) exynos_dp_get_irq_type()
371 if (reg & HPD_LOST) exynos_dp_get_irq_type()
374 if (reg & HOTPLUG_CHG) exynos_dp_get_irq_type()
383 u32 reg; exynos_dp_reset_aux() local
386 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); exynos_dp_reset_aux()
387 reg |= AUX_FUNC_EN_N; exynos_dp_reset_aux()
388 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); exynos_dp_reset_aux()
393 u32 reg; exynos_dp_init_aux() local
396 reg = RPLY_RECEIV | AUX_ERR; exynos_dp_init_aux()
397 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); exynos_dp_init_aux()
402 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)| exynos_dp_init_aux()
404 writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL); exynos_dp_init_aux()
407 reg = DEFER_CTRL_EN | DEFER_COUNT(1); exynos_dp_init_aux()
408 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL); exynos_dp_init_aux()
411 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); exynos_dp_init_aux()
412 reg &= ~AUX_FUNC_EN_N; exynos_dp_init_aux()
413 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); exynos_dp_init_aux()
418 u32 reg; exynos_dp_get_plug_in_status() local
424 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); exynos_dp_get_plug_in_status()
425 if (reg & HPD_STATUS) exynos_dp_get_plug_in_status()
434 u32 reg; exynos_dp_enable_sw_function() local
436 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1); exynos_dp_enable_sw_function()
437 reg &= ~SW_FUNC_EN_N; exynos_dp_enable_sw_function()
438 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); exynos_dp_enable_sw_function()
443 int reg; exynos_dp_start_aux_transaction() local
448 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); exynos_dp_start_aux_transaction()
449 reg |= AUX_EN; exynos_dp_start_aux_transaction()
450 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); exynos_dp_start_aux_transaction()
453 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); exynos_dp_start_aux_transaction()
454 while (!(reg & RPLY_RECEIV)) { exynos_dp_start_aux_transaction()
460 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); exynos_dp_start_aux_transaction()
468 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); exynos_dp_start_aux_transaction()
469 if (reg & AUX_ERR) { exynos_dp_start_aux_transaction()
475 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA); exynos_dp_start_aux_transaction()
476 if ((reg & AUX_STATUS_MASK) != 0) { exynos_dp_start_aux_transaction()
478 reg & AUX_STATUS_MASK); exynos_dp_start_aux_transaction()
489 u32 reg; exynos_dp_write_byte_to_dpcd() local
495 reg = BUF_CLR; exynos_dp_write_byte_to_dpcd()
496 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); exynos_dp_write_byte_to_dpcd()
499 reg = AUX_ADDR_7_0(reg_addr); exynos_dp_write_byte_to_dpcd()
500 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); exynos_dp_write_byte_to_dpcd()
501 reg = AUX_ADDR_15_8(reg_addr); exynos_dp_write_byte_to_dpcd()
502 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); exynos_dp_write_byte_to_dpcd()
503 reg = AUX_ADDR_19_16(reg_addr); exynos_dp_write_byte_to_dpcd()
504 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); exynos_dp_write_byte_to_dpcd()
507 reg = (unsigned int)data; exynos_dp_write_byte_to_dpcd()
508 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0); exynos_dp_write_byte_to_dpcd()
515 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; exynos_dp_write_byte_to_dpcd()
516 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); exynos_dp_write_byte_to_dpcd()
534 u32 reg; exynos_dp_read_byte_from_dpcd() local
540 reg = BUF_CLR; exynos_dp_read_byte_from_dpcd()
541 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); exynos_dp_read_byte_from_dpcd()
544 reg = AUX_ADDR_7_0(reg_addr); exynos_dp_read_byte_from_dpcd()
545 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); exynos_dp_read_byte_from_dpcd()
546 reg = AUX_ADDR_15_8(reg_addr); exynos_dp_read_byte_from_dpcd()
547 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); exynos_dp_read_byte_from_dpcd()
548 reg = AUX_ADDR_19_16(reg_addr); exynos_dp_read_byte_from_dpcd()
549 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); exynos_dp_read_byte_from_dpcd()
556 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; exynos_dp_read_byte_from_dpcd()
557 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); exynos_dp_read_byte_from_dpcd()
569 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0); exynos_dp_read_byte_from_dpcd()
570 *data = (unsigned char)(reg & 0xff); exynos_dp_read_byte_from_dpcd()
580 u32 reg; exynos_dp_write_bytes_to_dpcd() local
588 reg = BUF_CLR; exynos_dp_write_bytes_to_dpcd()
589 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); exynos_dp_write_bytes_to_dpcd()
601 reg = AUX_ADDR_7_0(reg_addr + start_offset); exynos_dp_write_bytes_to_dpcd()
602 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); exynos_dp_write_bytes_to_dpcd()
603 reg = AUX_ADDR_15_8(reg_addr + start_offset); exynos_dp_write_bytes_to_dpcd()
604 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); exynos_dp_write_bytes_to_dpcd()
605 reg = AUX_ADDR_19_16(reg_addr + start_offset); exynos_dp_write_bytes_to_dpcd()
606 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); exynos_dp_write_bytes_to_dpcd()
610 reg = data[start_offset + cur_data_idx]; exynos_dp_write_bytes_to_dpcd()
611 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0 exynos_dp_write_bytes_to_dpcd()
620 reg = AUX_LENGTH(cur_data_count) | exynos_dp_write_bytes_to_dpcd()
622 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); exynos_dp_write_bytes_to_dpcd()
644 u32 reg; exynos_dp_read_bytes_from_dpcd() local
652 reg = BUF_CLR; exynos_dp_read_bytes_from_dpcd()
653 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); exynos_dp_read_bytes_from_dpcd()
666 reg = AUX_ADDR_7_0(reg_addr + start_offset); exynos_dp_read_bytes_from_dpcd()
667 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); exynos_dp_read_bytes_from_dpcd()
668 reg = AUX_ADDR_15_8(reg_addr + start_offset); exynos_dp_read_bytes_from_dpcd()
669 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); exynos_dp_read_bytes_from_dpcd()
670 reg = AUX_ADDR_19_16(reg_addr + start_offset); exynos_dp_read_bytes_from_dpcd()
671 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); exynos_dp_read_bytes_from_dpcd()
678 reg = AUX_LENGTH(cur_data_count) | exynos_dp_read_bytes_from_dpcd()
680 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); exynos_dp_read_bytes_from_dpcd()
693 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0 exynos_dp_read_bytes_from_dpcd()
696 (unsigned char)reg; exynos_dp_read_bytes_from_dpcd()
709 u32 reg; exynos_dp_select_i2c_device() local
713 reg = device_addr; exynos_dp_select_i2c_device()
714 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); exynos_dp_select_i2c_device()
726 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | exynos_dp_select_i2c_device()
728 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); exynos_dp_select_i2c_device()
743 u32 reg; exynos_dp_read_byte_from_i2c() local
749 reg = BUF_CLR; exynos_dp_read_byte_from_i2c()
750 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); exynos_dp_read_byte_from_i2c()
762 reg = AUX_TX_COMM_I2C_TRANSACTION | exynos_dp_read_byte_from_i2c()
764 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); exynos_dp_read_byte_from_i2c()
788 u32 reg; exynos_dp_read_bytes_from_i2c() local
797 reg = BUF_CLR; exynos_dp_read_bytes_from_i2c()
798 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); exynos_dp_read_bytes_from_i2c()
801 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); exynos_dp_read_bytes_from_i2c()
802 reg &= ~ADDR_ONLY; exynos_dp_read_bytes_from_i2c()
803 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); exynos_dp_read_bytes_from_i2c()
821 reg = AUX_LENGTH(16) | exynos_dp_read_bytes_from_i2c()
824 writel(reg, dp->reg_base + exynos_dp_read_bytes_from_i2c()
837 reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM); exynos_dp_read_bytes_from_i2c()
838 if (reg == AUX_RX_COMM_AUX_DEFER || exynos_dp_read_bytes_from_i2c()
839 reg == AUX_RX_COMM_I2C_DEFER) { exynos_dp_read_bytes_from_i2c()
840 dev_err(dp->dev, "Defer: %d\n\n", reg); exynos_dp_read_bytes_from_i2c()
846 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0 exynos_dp_read_bytes_from_i2c()
848 edid[i + cur_data_idx] = (unsigned char)reg; exynos_dp_read_bytes_from_i2c()
857 u32 reg; exynos_dp_set_link_bandwidth() local
859 reg = bwtype; exynos_dp_set_link_bandwidth()
861 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET); exynos_dp_set_link_bandwidth()
866 u32 reg; exynos_dp_get_link_bandwidth() local
868 reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET); exynos_dp_get_link_bandwidth()
869 *bwtype = reg; exynos_dp_get_link_bandwidth()
874 u32 reg; exynos_dp_set_lane_count() local
876 reg = count; exynos_dp_set_lane_count()
877 writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET); exynos_dp_set_lane_count()
882 u32 reg; exynos_dp_get_lane_count() local
884 reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET); exynos_dp_get_lane_count()
885 *count = reg; exynos_dp_get_lane_count()
890 u32 reg; exynos_dp_enable_enhanced_mode() local
893 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); exynos_dp_enable_enhanced_mode()
894 reg |= ENHANCED; exynos_dp_enable_enhanced_mode()
895 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); exynos_dp_enable_enhanced_mode()
897 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); exynos_dp_enable_enhanced_mode()
898 reg &= ~ENHANCED; exynos_dp_enable_enhanced_mode()
899 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); exynos_dp_enable_enhanced_mode()
906 u32 reg; exynos_dp_set_training_pattern() local
910 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; exynos_dp_set_training_pattern()
911 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_set_training_pattern()
914 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; exynos_dp_set_training_pattern()
915 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_set_training_pattern()
918 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; exynos_dp_set_training_pattern()
919 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_set_training_pattern()
922 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; exynos_dp_set_training_pattern()
923 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_set_training_pattern()
926 reg = SCRAMBLING_ENABLE | exynos_dp_set_training_pattern()
929 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_set_training_pattern()
938 u32 reg; exynos_dp_set_lane0_pre_emphasis() local
940 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); exynos_dp_set_lane0_pre_emphasis()
941 reg &= ~PRE_EMPHASIS_SET_MASK; exynos_dp_set_lane0_pre_emphasis()
942 reg |= level << PRE_EMPHASIS_SET_SHIFT; exynos_dp_set_lane0_pre_emphasis()
943 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); exynos_dp_set_lane0_pre_emphasis()
948 u32 reg; exynos_dp_set_lane1_pre_emphasis() local
950 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); exynos_dp_set_lane1_pre_emphasis()
951 reg &= ~PRE_EMPHASIS_SET_MASK; exynos_dp_set_lane1_pre_emphasis()
952 reg |= level << PRE_EMPHASIS_SET_SHIFT; exynos_dp_set_lane1_pre_emphasis()
953 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); exynos_dp_set_lane1_pre_emphasis()
958 u32 reg; exynos_dp_set_lane2_pre_emphasis() local
960 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); exynos_dp_set_lane2_pre_emphasis()
961 reg &= ~PRE_EMPHASIS_SET_MASK; exynos_dp_set_lane2_pre_emphasis()
962 reg |= level << PRE_EMPHASIS_SET_SHIFT; exynos_dp_set_lane2_pre_emphasis()
963 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); exynos_dp_set_lane2_pre_emphasis()
968 u32 reg; exynos_dp_set_lane3_pre_emphasis() local
970 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); exynos_dp_set_lane3_pre_emphasis()
971 reg &= ~PRE_EMPHASIS_SET_MASK; exynos_dp_set_lane3_pre_emphasis()
972 reg |= level << PRE_EMPHASIS_SET_SHIFT; exynos_dp_set_lane3_pre_emphasis()
973 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); exynos_dp_set_lane3_pre_emphasis()
979 u32 reg; exynos_dp_set_lane0_link_training() local
981 reg = training_lane; exynos_dp_set_lane0_link_training()
982 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); exynos_dp_set_lane0_link_training()
988 u32 reg; exynos_dp_set_lane1_link_training() local
990 reg = training_lane; exynos_dp_set_lane1_link_training()
991 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); exynos_dp_set_lane1_link_training()
997 u32 reg; exynos_dp_set_lane2_link_training() local
999 reg = training_lane; exynos_dp_set_lane2_link_training()
1000 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); exynos_dp_set_lane2_link_training()
1006 u32 reg; exynos_dp_set_lane3_link_training() local
1008 reg = training_lane; exynos_dp_set_lane3_link_training()
1009 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); exynos_dp_set_lane3_link_training()
1014 u32 reg; exynos_dp_get_lane0_link_training() local
1016 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); exynos_dp_get_lane0_link_training()
1017 return reg; exynos_dp_get_lane0_link_training()
1022 u32 reg; exynos_dp_get_lane1_link_training() local
1024 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); exynos_dp_get_lane1_link_training()
1025 return reg; exynos_dp_get_lane1_link_training()
1030 u32 reg; exynos_dp_get_lane2_link_training() local
1032 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); exynos_dp_get_lane2_link_training()
1033 return reg; exynos_dp_get_lane2_link_training()
1038 u32 reg; exynos_dp_get_lane3_link_training() local
1040 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); exynos_dp_get_lane3_link_training()
1041 return reg; exynos_dp_get_lane3_link_training()
1046 u32 reg; exynos_dp_reset_macro() local
1048 reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST); exynos_dp_reset_macro()
1049 reg |= MACRO_RST; exynos_dp_reset_macro()
1050 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); exynos_dp_reset_macro()
1055 reg &= ~MACRO_RST; exynos_dp_reset_macro()
1056 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); exynos_dp_reset_macro()
1061 u32 reg; exynos_dp_init_video() local
1063 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; exynos_dp_init_video()
1064 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); exynos_dp_init_video()
1066 reg = 0x0; exynos_dp_init_video()
1067 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); exynos_dp_init_video()
1069 reg = CHA_CRI(4) | CHA_CTRL; exynos_dp_init_video()
1070 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); exynos_dp_init_video()
1072 reg = 0x0; exynos_dp_init_video()
1073 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); exynos_dp_init_video()
1075 reg = VID_HRES_TH(2) | VID_VRES_TH(0); exynos_dp_init_video()
1076 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8); exynos_dp_init_video()
1081 u32 reg; exynos_dp_set_video_color_format() local
1084 reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) | exynos_dp_set_video_color_format()
1087 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2); exynos_dp_set_video_color_format()
1090 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3); exynos_dp_set_video_color_format()
1091 reg &= ~IN_YC_COEFFI_MASK; exynos_dp_set_video_color_format()
1093 reg |= IN_YC_COEFFI_ITU709; exynos_dp_set_video_color_format()
1095 reg |= IN_YC_COEFFI_ITU601; exynos_dp_set_video_color_format()
1096 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3); exynos_dp_set_video_color_format()
1101 u32 reg; exynos_dp_is_slave_video_stream_clock_on() local
1103 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); exynos_dp_is_slave_video_stream_clock_on()
1104 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); exynos_dp_is_slave_video_stream_clock_on()
1106 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); exynos_dp_is_slave_video_stream_clock_on()
1108 if (!(reg & DET_STA)) { exynos_dp_is_slave_video_stream_clock_on()
1113 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); exynos_dp_is_slave_video_stream_clock_on()
1114 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); exynos_dp_is_slave_video_stream_clock_on()
1116 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); exynos_dp_is_slave_video_stream_clock_on()
1119 if (reg & CHA_STA) { exynos_dp_is_slave_video_stream_clock_on()
1132 u32 reg; exynos_dp_set_video_cr_mn() local
1135 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); exynos_dp_set_video_cr_mn()
1136 reg |= FIX_M_VID; exynos_dp_set_video_cr_mn()
1137 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); exynos_dp_set_video_cr_mn()
1138 reg = m_value & 0xff; exynos_dp_set_video_cr_mn()
1139 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0); exynos_dp_set_video_cr_mn()
1140 reg = (m_value >> 8) & 0xff; exynos_dp_set_video_cr_mn()
1141 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1); exynos_dp_set_video_cr_mn()
1142 reg = (m_value >> 16) & 0xff; exynos_dp_set_video_cr_mn()
1143 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2); exynos_dp_set_video_cr_mn()
1145 reg = n_value & 0xff; exynos_dp_set_video_cr_mn()
1146 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0); exynos_dp_set_video_cr_mn()
1147 reg = (n_value >> 8) & 0xff; exynos_dp_set_video_cr_mn()
1148 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1); exynos_dp_set_video_cr_mn()
1149 reg = (n_value >> 16) & 0xff; exynos_dp_set_video_cr_mn()
1150 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2); exynos_dp_set_video_cr_mn()
1152 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); exynos_dp_set_video_cr_mn()
1153 reg &= ~FIX_M_VID; exynos_dp_set_video_cr_mn()
1154 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); exynos_dp_set_video_cr_mn()
1164 u32 reg; exynos_dp_set_video_timing_mode() local
1167 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_set_video_timing_mode()
1168 reg &= ~FORMAT_SEL; exynos_dp_set_video_timing_mode()
1169 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_set_video_timing_mode()
1171 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_set_video_timing_mode()
1172 reg |= FORMAT_SEL; exynos_dp_set_video_timing_mode()
1173 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_set_video_timing_mode()
1179 u32 reg; exynos_dp_enable_video_master() local
1182 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); exynos_dp_enable_video_master()
1183 reg &= ~VIDEO_MODE_MASK; exynos_dp_enable_video_master()
1184 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; exynos_dp_enable_video_master()
1185 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); exynos_dp_enable_video_master()
1187 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); exynos_dp_enable_video_master()
1188 reg &= ~VIDEO_MODE_MASK; exynos_dp_enable_video_master()
1189 reg |= VIDEO_MODE_SLAVE_MODE; exynos_dp_enable_video_master()
1190 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); exynos_dp_enable_video_master()
1196 u32 reg; exynos_dp_start_video() local
1198 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); exynos_dp_start_video()
1199 reg |= VIDEO_EN; exynos_dp_start_video()
1200 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); exynos_dp_start_video()
1205 u32 reg; exynos_dp_is_video_stream_on() local
1207 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); exynos_dp_is_video_stream_on()
1208 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); exynos_dp_is_video_stream_on()
1210 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); exynos_dp_is_video_stream_on()
1211 if (!(reg & STRM_VALID)) { exynos_dp_is_video_stream_on()
1221 u32 reg; exynos_dp_config_video_slave_mode() local
1223 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1); exynos_dp_config_video_slave_mode()
1224 reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); exynos_dp_config_video_slave_mode()
1225 reg |= MASTER_VID_FUNC_EN_N; exynos_dp_config_video_slave_mode()
1226 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); exynos_dp_config_video_slave_mode()
1228 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_config_video_slave_mode()
1229 reg &= ~INTERACE_SCAN_CFG; exynos_dp_config_video_slave_mode()
1230 reg |= (dp->video_info->interlaced << 2); exynos_dp_config_video_slave_mode()
1231 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_config_video_slave_mode()
1233 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_config_video_slave_mode()
1234 reg &= ~VSYNC_POLARITY_CFG; exynos_dp_config_video_slave_mode()
1235 reg |= (dp->video_info->v_sync_polarity << 1); exynos_dp_config_video_slave_mode()
1236 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_config_video_slave_mode()
1238 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_config_video_slave_mode()
1239 reg &= ~HSYNC_POLARITY_CFG; exynos_dp_config_video_slave_mode()
1240 reg |= (dp->video_info->h_sync_polarity << 0); exynos_dp_config_video_slave_mode()
1241 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_config_video_slave_mode()
1243 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; exynos_dp_config_video_slave_mode()
1244 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); exynos_dp_config_video_slave_mode()
1249 u32 reg; exynos_dp_enable_scrambling() local
1251 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_enable_scrambling()
1252 reg &= ~SCRAMBLING_DISABLE; exynos_dp_enable_scrambling()
1253 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_enable_scrambling()
1258 u32 reg; exynos_dp_disable_scrambling() local
1260 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_disable_scrambling()
1261 reg |= SCRAMBLING_DISABLE; exynos_dp_disable_scrambling()
1262 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_disable_scrambling()
/linux-4.1.27/drivers/media/platform/s5p-jpeg/
H A Djpeg-hw-s5p.c22 unsigned long reg; s5p_jpeg_reset() local
25 reg = readl(regs + S5P_JPG_SW_RESET); s5p_jpeg_reset()
27 while (reg != 0) { s5p_jpeg_reset()
29 reg = readl(regs + S5P_JPG_SW_RESET); s5p_jpeg_reset()
40 unsigned long reg, m; s5p_jpeg_input_raw_mode() local
48 reg = readl(regs + S5P_JPGCMOD); s5p_jpeg_input_raw_mode()
49 reg &= ~S5P_MOD_SEL_MASK; s5p_jpeg_input_raw_mode()
50 reg |= m; s5p_jpeg_input_raw_mode()
51 writel(reg, regs + S5P_JPGCMOD); s5p_jpeg_input_raw_mode()
56 unsigned long reg, m; s5p_jpeg_proc_mode() local
63 reg = readl(regs + S5P_JPGMOD); s5p_jpeg_proc_mode()
64 reg &= ~S5P_PROC_MODE_MASK; s5p_jpeg_proc_mode()
65 reg |= m; s5p_jpeg_proc_mode()
66 writel(reg, regs + S5P_JPGMOD); s5p_jpeg_proc_mode()
71 unsigned long reg, m; s5p_jpeg_subsampling_mode() local
78 reg = readl(regs + S5P_JPGMOD); s5p_jpeg_subsampling_mode()
79 reg &= ~S5P_SUBSAMPLING_MODE_MASK; s5p_jpeg_subsampling_mode()
80 reg |= m; s5p_jpeg_subsampling_mode()
81 writel(reg, regs + S5P_JPGMOD); s5p_jpeg_subsampling_mode()
91 unsigned long reg; s5p_jpeg_dri() local
93 reg = readl(regs + S5P_JPGDRI_U); s5p_jpeg_dri()
94 reg &= ~0xff; s5p_jpeg_dri()
95 reg |= (dri >> 8) & 0xff; s5p_jpeg_dri()
96 writel(reg, regs + S5P_JPGDRI_U); s5p_jpeg_dri()
98 reg = readl(regs + S5P_JPGDRI_L); s5p_jpeg_dri()
99 reg &= ~0xff; s5p_jpeg_dri()
100 reg |= dri & 0xff; s5p_jpeg_dri()
101 writel(reg, regs + S5P_JPGDRI_L); s5p_jpeg_dri()
106 unsigned long reg; s5p_jpeg_qtbl() local
108 reg = readl(regs + S5P_JPG_QTBL); s5p_jpeg_qtbl()
109 reg &= ~S5P_QT_NUMt_MASK(t); s5p_jpeg_qtbl()
110 reg |= (n << S5P_QT_NUMt_SHIFT(t)) & S5P_QT_NUMt_MASK(t); s5p_jpeg_qtbl()
111 writel(reg, regs + S5P_JPG_QTBL); s5p_jpeg_qtbl()
116 unsigned long reg; s5p_jpeg_htbl_ac() local
118 reg = readl(regs + S5P_JPG_HTBL); s5p_jpeg_htbl_ac()
119 reg &= ~S5P_HT_NUMt_AC_MASK(t); s5p_jpeg_htbl_ac()
121 reg |= (0 << S5P_HT_NUMt_AC_SHIFT(t)) & S5P_HT_NUMt_AC_MASK(t); s5p_jpeg_htbl_ac()
122 writel(reg, regs + S5P_JPG_HTBL); s5p_jpeg_htbl_ac()
127 unsigned long reg; s5p_jpeg_htbl_dc() local
129 reg = readl(regs + S5P_JPG_HTBL); s5p_jpeg_htbl_dc()
130 reg &= ~S5P_HT_NUMt_DC_MASK(t); s5p_jpeg_htbl_dc()
132 reg |= (0 << S5P_HT_NUMt_DC_SHIFT(t)) & S5P_HT_NUMt_DC_MASK(t); s5p_jpeg_htbl_dc()
133 writel(reg, regs + S5P_JPG_HTBL); s5p_jpeg_htbl_dc()
138 unsigned long reg; s5p_jpeg_y() local
140 reg = readl(regs + S5P_JPGY_U); s5p_jpeg_y()
141 reg &= ~0xff; s5p_jpeg_y()
142 reg |= (y >> 8) & 0xff; s5p_jpeg_y()
143 writel(reg, regs + S5P_JPGY_U); s5p_jpeg_y()
145 reg = readl(regs + S5P_JPGY_L); s5p_jpeg_y()
146 reg &= ~0xff; s5p_jpeg_y()
147 reg |= y & 0xff; s5p_jpeg_y()
148 writel(reg, regs + S5P_JPGY_L); s5p_jpeg_y()
153 unsigned long reg; s5p_jpeg_x() local
155 reg = readl(regs + S5P_JPGX_U); s5p_jpeg_x()
156 reg &= ~0xff; s5p_jpeg_x()
157 reg |= (x >> 8) & 0xff; s5p_jpeg_x()
158 writel(reg, regs + S5P_JPGX_U); s5p_jpeg_x()
160 reg = readl(regs + S5P_JPGX_L); s5p_jpeg_x()
161 reg &= ~0xff; s5p_jpeg_x()
162 reg |= x & 0xff; s5p_jpeg_x()
163 writel(reg, regs + S5P_JPGX_L); s5p_jpeg_x()
168 unsigned long reg; s5p_jpeg_rst_int_enable() local
170 reg = readl(regs + S5P_JPGINTSE); s5p_jpeg_rst_int_enable()
171 reg &= ~S5P_RSTm_INT_EN_MASK; s5p_jpeg_rst_int_enable()
173 reg |= S5P_RSTm_INT_EN; s5p_jpeg_rst_int_enable()
174 writel(reg, regs + S5P_JPGINTSE); s5p_jpeg_rst_int_enable()
179 unsigned long reg; s5p_jpeg_data_num_int_enable() local
181 reg = readl(regs + S5P_JPGINTSE); s5p_jpeg_data_num_int_enable()
182 reg &= ~S5P_DATA_NUM_INT_EN_MASK; s5p_jpeg_data_num_int_enable()
184 reg |= S5P_DATA_NUM_INT_EN; s5p_jpeg_data_num_int_enable()
185 writel(reg, regs + S5P_JPGINTSE); s5p_jpeg_data_num_int_enable()
190 unsigned long reg; s5p_jpeg_final_mcu_num_int_enable() local
192 reg = readl(regs + S5P_JPGINTSE); s5p_jpeg_final_mcu_num_int_enable()
193 reg &= ~S5P_FINAL_MCU_NUM_INT_EN_MASK; s5p_jpeg_final_mcu_num_int_enable()
195 reg |= S5P_FINAL_MCU_NUM_INT_EN; s5p_jpeg_final_mcu_num_int_enable()
196 writel(reg, regs + S5P_JPGINTSE); s5p_jpeg_final_mcu_num_int_enable()
207 unsigned long reg; s5p_jpeg_clear_timer_stat() local
209 reg = readl(regs + S5P_JPG_TIMER_SE); s5p_jpeg_clear_timer_stat()
210 reg &= ~S5P_TIMER_INT_STAT_MASK; s5p_jpeg_clear_timer_stat()
211 writel(reg, regs + S5P_JPG_TIMER_SE); s5p_jpeg_clear_timer_stat()
216 unsigned long reg; s5p_jpeg_enc_stream_int() local
218 reg = readl(regs + S5P_JPG_ENC_STREAM_INTSE); s5p_jpeg_enc_stream_int()
219 reg &= ~S5P_ENC_STREAM_BOUND_MASK; s5p_jpeg_enc_stream_int()
220 reg |= S5P_ENC_STREAM_INT_EN; s5p_jpeg_enc_stream_int()
221 reg |= size & S5P_ENC_STREAM_BOUND_MASK; s5p_jpeg_enc_stream_int()
222 writel(reg, regs + S5P_JPG_ENC_STREAM_INTSE); s5p_jpeg_enc_stream_int()
233 unsigned long reg; s5p_jpeg_clear_enc_stream_stat() local
235 reg = readl(regs + S5P_JPG_ENC_STREAM_INTSE); s5p_jpeg_clear_enc_stream_stat()
236 reg &= ~S5P_ENC_STREAM_INT_MASK; s5p_jpeg_clear_enc_stream_stat()
237 writel(reg, regs + S5P_JPG_ENC_STREAM_INTSE); s5p_jpeg_clear_enc_stream_stat()
242 unsigned long reg, f; s5p_jpeg_outform_raw() local
249 reg = readl(regs + S5P_JPG_OUTFORM); s5p_jpeg_outform_raw()
250 reg &= ~S5P_DEC_OUT_FORMAT_MASK; s5p_jpeg_outform_raw()
251 reg |= f; s5p_jpeg_outform_raw()
252 writel(reg, regs + S5P_JPG_OUTFORM); s5p_jpeg_outform_raw()
268 unsigned long reg; s5p_jpeg_coef() local
270 reg = readl(regs + S5P_JPG_COEF(i)); s5p_jpeg_coef()
271 reg &= ~S5P_COEFn_MASK(j); s5p_jpeg_coef()
272 reg |= (coef << S5P_COEFn_SHIFT(j)) & S5P_COEFn_MASK(j); s5p_jpeg_coef()
273 writel(reg, regs + S5P_JPG_COEF(i)); s5p_jpeg_coef()
H A Djpeg-hw-exynos3250.c23 u32 reg = 1; exynos3250_jpeg_reset() local
28 while (reg != 0 && --count > 0) { exynos3250_jpeg_reset()
31 reg = readl(regs + EXYNOS3250_SW_RESET); exynos3250_jpeg_reset()
34 reg = 0; exynos3250_jpeg_reset()
37 while (reg != 1 && --count > 0) { exynos3250_jpeg_reset()
41 reg = readl(regs + EXYNOS3250_JPGDRI); exynos3250_jpeg_reset()
65 u32 reg; exynos3250_jpeg_clk_set() local
67 reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; exynos3250_jpeg_clk_set()
69 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); exynos3250_jpeg_clk_set()
74 u32 reg; exynos3250_jpeg_input_raw_fmt() local
76 reg = readl(regs + EXYNOS3250_JPGCMOD) & exynos3250_jpeg_input_raw_fmt()
81 reg |= EXYNOS3250_MODE_SEL_ARGB8888; exynos3250_jpeg_input_raw_fmt()
84 reg |= EXYNOS3250_MODE_SEL_ARGB8888 | EXYNOS3250_SRC_SWAP_RGB; exynos3250_jpeg_input_raw_fmt()
87 reg |= EXYNOS3250_MODE_SEL_RGB565; exynos3250_jpeg_input_raw_fmt()
90 reg |= EXYNOS3250_MODE_SEL_RGB565 | EXYNOS3250_SRC_SWAP_RGB; exynos3250_jpeg_input_raw_fmt()
93 reg |= EXYNOS3250_MODE_SEL_422_1P_LUM_CHR; exynos3250_jpeg_input_raw_fmt()
96 reg |= EXYNOS3250_MODE_SEL_422_1P_LUM_CHR | exynos3250_jpeg_input_raw_fmt()
100 reg |= EXYNOS3250_MODE_SEL_422_1P_CHR_LUM; exynos3250_jpeg_input_raw_fmt()
103 reg |= EXYNOS3250_MODE_SEL_422_1P_CHR_LUM | exynos3250_jpeg_input_raw_fmt()
107 reg |= EXYNOS3250_MODE_SEL_420_2P | EXYNOS3250_SRC_NV12; exynos3250_jpeg_input_raw_fmt()
110 reg |= EXYNOS3250_MODE_SEL_420_2P | EXYNOS3250_SRC_NV21; exynos3250_jpeg_input_raw_fmt()
113 reg |= EXYNOS3250_MODE_SEL_420_3P; exynos3250_jpeg_input_raw_fmt()
120 writel(reg, regs + EXYNOS3250_JPGCMOD); exynos3250_jpeg_input_raw_fmt()
125 u32 reg; exynos3250_jpeg_set_y16() local
127 reg = readl(regs + EXYNOS3250_JPGCMOD); exynos3250_jpeg_set_y16()
129 reg |= EXYNOS3250_MODE_Y16; exynos3250_jpeg_set_y16()
131 reg &= ~EXYNOS3250_MODE_Y16_MASK; exynos3250_jpeg_set_y16()
132 writel(reg, regs + EXYNOS3250_JPGCMOD); exynos3250_jpeg_set_y16()
137 u32 reg, m; exynos3250_jpeg_proc_mode() local
143 reg = readl(regs + EXYNOS3250_JPGMOD); exynos3250_jpeg_proc_mode()
144 reg &= ~EXYNOS3250_PROC_MODE_MASK; exynos3250_jpeg_proc_mode()
145 reg |= m; exynos3250_jpeg_proc_mode()
146 writel(reg, regs + EXYNOS3250_JPGMOD); exynos3250_jpeg_proc_mode()
151 u32 reg, m = 0; exynos3250_jpeg_subsampling_mode() local
165 reg = readl(regs + EXYNOS3250_JPGMOD); exynos3250_jpeg_subsampling_mode()
166 reg &= ~EXYNOS3250_SUBSAMPLING_MODE_MASK; exynos3250_jpeg_subsampling_mode()
167 reg |= m; exynos3250_jpeg_subsampling_mode()
168 writel(reg, regs + EXYNOS3250_JPGMOD); exynos3250_jpeg_subsampling_mode()
179 u32 reg; exynos3250_jpeg_dri() local
181 reg = dri & EXYNOS3250_JPGDRI_MASK; exynos3250_jpeg_dri()
182 writel(reg, regs + EXYNOS3250_JPGDRI); exynos3250_jpeg_dri()
187 unsigned long reg; exynos3250_jpeg_qtbl() local
189 reg = readl(regs + EXYNOS3250_QHTBL); exynos3250_jpeg_qtbl()
190 reg &= ~EXYNOS3250_QT_NUM_MASK(t); exynos3250_jpeg_qtbl()
191 reg |= (n << EXYNOS3250_QT_NUM_SHIFT(t)) & exynos3250_jpeg_qtbl()
193 writel(reg, regs + EXYNOS3250_QHTBL); exynos3250_jpeg_qtbl()
198 unsigned long reg; exynos3250_jpeg_htbl_ac() local
200 reg = readl(regs + EXYNOS3250_QHTBL); exynos3250_jpeg_htbl_ac()
201 reg &= ~EXYNOS3250_HT_NUM_AC_MASK(t); exynos3250_jpeg_htbl_ac()
203 reg |= (0 << EXYNOS3250_HT_NUM_AC_SHIFT(t)) & exynos3250_jpeg_htbl_ac()
205 writel(reg, regs + EXYNOS3250_QHTBL); exynos3250_jpeg_htbl_ac()
210 unsigned long reg; exynos3250_jpeg_htbl_dc() local
212 reg = readl(regs + EXYNOS3250_QHTBL); exynos3250_jpeg_htbl_dc()
213 reg &= ~EXYNOS3250_HT_NUM_DC_MASK(t); exynos3250_jpeg_htbl_dc()
215 reg |= (0 << EXYNOS3250_HT_NUM_DC_SHIFT(t)) & exynos3250_jpeg_htbl_dc()
217 writel(reg, regs + EXYNOS3250_QHTBL); exynos3250_jpeg_htbl_dc()
222 u32 reg; exynos3250_jpeg_set_y() local
224 reg = y & EXYNOS3250_JPGY_MASK; exynos3250_jpeg_set_y()
225 writel(reg, regs + EXYNOS3250_JPGY); exynos3250_jpeg_set_y()
230 u32 reg; exynos3250_jpeg_set_x() local
232 reg = x & EXYNOS3250_JPGX_MASK; exynos3250_jpeg_set_x()
233 writel(reg, regs + EXYNOS3250_JPGX); exynos3250_jpeg_set_x()
250 u32 reg; exynos3250_jpeg_interrupts_enable() local
252 reg = readl(regs + EXYNOS3250_JPGINTSE); exynos3250_jpeg_interrupts_enable()
253 reg |= (EXYNOS3250_JPEG_DONE_EN | exynos3250_jpeg_interrupts_enable()
260 writel(reg, regs + EXYNOS3250_JPGINTSE); exynos3250_jpeg_interrupts_enable()
265 u32 reg; exynos3250_jpeg_enc_stream_bound() local
267 reg = size & EXYNOS3250_ENC_STREAM_BOUND_MASK; exynos3250_jpeg_enc_stream_bound()
268 writel(reg, regs + EXYNOS3250_ENC_STREAM_BOUND); exynos3250_jpeg_enc_stream_bound()
273 u32 reg; exynos3250_jpeg_output_raw_fmt() local
277 reg = EXYNOS3250_OUT_FMT_ARGB8888; exynos3250_jpeg_output_raw_fmt()
280 reg = EXYNOS3250_OUT_FMT_ARGB8888 | EXYNOS3250_OUT_SWAP_RGB; exynos3250_jpeg_output_raw_fmt()
283 reg = EXYNOS3250_OUT_FMT_RGB565; exynos3250_jpeg_output_raw_fmt()
286 reg = EXYNOS3250_OUT_FMT_RGB565 | EXYNOS3250_OUT_SWAP_RGB; exynos3250_jpeg_output_raw_fmt()
289 reg = EXYNOS3250_OUT_FMT_422_1P_LUM_CHR; exynos3250_jpeg_output_raw_fmt()
292 reg = EXYNOS3250_OUT_FMT_422_1P_LUM_CHR | exynos3250_jpeg_output_raw_fmt()
296 reg = EXYNOS3250_OUT_FMT_422_1P_CHR_LUM; exynos3250_jpeg_output_raw_fmt()
299 reg = EXYNOS3250_OUT_FMT_422_1P_CHR_LUM | exynos3250_jpeg_output_raw_fmt()
303 reg = EXYNOS3250_OUT_FMT_420_2P | EXYNOS3250_OUT_NV12; exynos3250_jpeg_output_raw_fmt()
306 reg = EXYNOS3250_OUT_FMT_420_2P | EXYNOS3250_OUT_NV21; exynos3250_jpeg_output_raw_fmt()
309 reg = EXYNOS3250_OUT_FMT_420_3P; exynos3250_jpeg_output_raw_fmt()
312 reg = 0; exynos3250_jpeg_output_raw_fmt()
316 writel(reg, regs + EXYNOS3250_OUTFORM); exynos3250_jpeg_output_raw_fmt()
369 u32 reg; exynos3250_jpeg_offset() local
371 reg = (y_offset << EXYNOS3250_LUMA_YY_OFFSET_SHIFT) & exynos3250_jpeg_offset()
373 reg |= (x_offset << EXYNOS3250_LUMA_YX_OFFSET_SHIFT) & exynos3250_jpeg_offset()
376 writel(reg, regs + EXYNOS3250_LUMA_XY_OFFSET); exynos3250_jpeg_offset()
378 reg = (y_offset << EXYNOS3250_CHROMA_YY_OFFSET_SHIFT) & exynos3250_jpeg_offset()
380 reg |= (x_offset << EXYNOS3250_CHROMA_YX_OFFSET_SHIFT) & exynos3250_jpeg_offset()
383 writel(reg, regs + EXYNOS3250_CHROMA_XY_OFFSET); exynos3250_jpeg_offset()
385 reg = (y_offset << EXYNOS3250_CHROMA_CR_YY_OFFSET_SHIFT) & exynos3250_jpeg_offset()
387 reg |= (x_offset << EXYNOS3250_CHROMA_CR_YX_OFFSET_SHIFT) & exynos3250_jpeg_offset()
390 writel(reg, regs + EXYNOS3250_CHROMA_CR_XY_OFFSET); exynos3250_jpeg_offset()
H A Djpeg-hw-exynos4.c21 unsigned int reg; exynos4_jpeg_sw_reset() local
23 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_sw_reset()
24 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_sw_reset()
28 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_sw_reset()
33 unsigned int reg; exynos4_jpeg_set_enc_dec_mode() local
35 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_set_enc_dec_mode()
38 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | exynos4_jpeg_set_enc_dec_mode()
42 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | exynos4_jpeg_set_enc_dec_mode()
50 unsigned int reg; exynos4_jpeg_set_img_fmt() local
52 reg = readl(base + EXYNOS4_IMG_FMT_REG) & exynos4_jpeg_set_img_fmt()
57 reg = reg | EXYNOS4_ENC_GRAY_IMG | EXYNOS4_GRAY_IMG_IP; exynos4_jpeg_set_img_fmt()
60 reg = reg | EXYNOS4_ENC_RGB_IMG | exynos4_jpeg_set_img_fmt()
64 reg = reg | EXYNOS4_ENC_RGB_IMG | exynos4_jpeg_set_img_fmt()
68 reg = reg | EXYNOS4_ENC_YUV_444_IMG | exynos4_jpeg_set_img_fmt()
73 reg = reg | EXYNOS4_ENC_YUV_444_IMG | exynos4_jpeg_set_img_fmt()
78 reg = reg | EXYNOS4_DEC_YUV_422_IMG | exynos4_jpeg_set_img_fmt()
84 reg = reg | EXYNOS4_DEC_YUV_422_IMG | exynos4_jpeg_set_img_fmt()
89 reg = reg | EXYNOS4_DEC_YUV_422_IMG | exynos4_jpeg_set_img_fmt()
94 reg = reg | EXYNOS4_DEC_YUV_422_IMG | exynos4_jpeg_set_img_fmt()
99 reg = reg | EXYNOS4_DEC_YUV_420_IMG | exynos4_jpeg_set_img_fmt()
104 reg = reg | EXYNOS4_DEC_YUV_420_IMG | exynos4_jpeg_set_img_fmt()
109 reg = reg | EXYNOS4_DEC_YUV_420_IMG | exynos4_jpeg_set_img_fmt()
118 writel(reg, base + EXYNOS4_IMG_FMT_REG); exynos4_jpeg_set_img_fmt()
123 unsigned int reg; exynos4_jpeg_set_enc_out_fmt() local
125 reg = readl(base + EXYNOS4_IMG_FMT_REG) & exynos4_jpeg_set_enc_out_fmt()
130 reg = reg | EXYNOS4_ENC_FMT_GRAY; exynos4_jpeg_set_enc_out_fmt()
134 reg = reg | EXYNOS4_ENC_FMT_YUV_444; exynos4_jpeg_set_enc_out_fmt()
138 reg = reg | EXYNOS4_ENC_FMT_YUV_422; exynos4_jpeg_set_enc_out_fmt()
142 reg = reg | EXYNOS4_ENC_FMT_YUV_420; exynos4_jpeg_set_enc_out_fmt()
149 writel(reg, base + EXYNOS4_IMG_FMT_REG); exynos4_jpeg_set_enc_out_fmt()
177 unsigned int reg; exynos4_jpeg_set_huf_table_enable() local
179 reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~EXYNOS4_HUF_TBL_EN; exynos4_jpeg_set_huf_table_enable()
182 writel(reg | EXYNOS4_HUF_TBL_EN, exynos4_jpeg_set_huf_table_enable()
185 writel(reg & ~EXYNOS4_HUF_TBL_EN, exynos4_jpeg_set_huf_table_enable()
191 unsigned int reg; exynos4_jpeg_set_sys_int_enable() local
193 reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~(EXYNOS4_SYS_INT_EN); exynos4_jpeg_set_sys_int_enable()
196 writel(reg | EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_set_sys_int_enable()
198 writel(reg & ~EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_set_sys_int_enable()
226 unsigned int reg; exynos4_jpeg_set_encode_tbl_select() local
228 reg = EXYNOS4_Q_TBL_COMP1_0 | EXYNOS4_Q_TBL_COMP2_1 | exynos4_jpeg_set_encode_tbl_select()
234 writel(reg, base + EXYNOS4_TBL_SEL_REG); exynos4_jpeg_set_encode_tbl_select()
/linux-4.1.27/drivers/scsi/
H A Ddtc.h34 #define DTC_address(reg) (base + DTC_5380_OFFSET + reg)
36 #define dbNCR5380_read(reg) \
37 (rval=readb(DTC_address(reg)), \
39 , (reg), DTC_address(reg), rval)), rval ) )
41 #define dbNCR5380_write(reg, value) do { \
43 (value), (reg), DTC_address(reg)); \
44 writeb(value, DTC_address(reg));} while(0)
48 #define NCR5380_read(reg) (readb(DTC_address(reg)))
49 #define NCR5380_write(reg, value) (writeb(value, DTC_address(reg)))
51 #define NCR5380_read(reg) (readb(DTC_address(reg)))
52 #define xNCR5380_read(reg) \
54 , (reg), DTC_address(reg))), readb(DTC_address(reg)))
56 #define NCR5380_write(reg, value) do { \
58 (value), (reg), DTC_address(reg)); \
59 writeb(value, DTC_address(reg));} while(0)
H A Dnsp32_io.h119 unsigned int reg) nsp32_index_read1()
121 outb(reg, base + INDEX_REG); nsp32_index_read1()
126 unsigned int reg, nsp32_index_write1()
129 outb(reg, base + INDEX_REG ); nsp32_index_write1()
134 unsigned int reg) nsp32_index_read2()
136 outb(reg, base + INDEX_REG); nsp32_index_read2()
141 unsigned int reg, nsp32_index_write2()
144 outb(reg, base + INDEX_REG ); nsp32_index_write2()
149 unsigned int reg) nsp32_index_read4()
153 outb(reg, base + INDEX_REG); nsp32_index_read4()
161 unsigned int reg, nsp32_index_write4()
169 outb(reg, base + INDEX_REG ); nsp32_index_write4()
177 unsigned int reg) nsp32_mmio_index_read1()
184 writeb(reg, index_ptr); nsp32_mmio_index_read1()
189 unsigned int reg, nsp32_mmio_index_write1()
197 writeb(reg, index_ptr); nsp32_mmio_index_write1()
202 unsigned int reg) nsp32_mmio_index_read2()
209 writeb(reg, index_ptr); nsp32_mmio_index_read2()
214 unsigned int reg, nsp32_mmio_index_write2()
222 writeb(reg, index_ptr); nsp32_mmio_index_write2()
229 unsigned int reg, nsp32_multi_read4()
233 insl(base + reg, buf, count); nsp32_multi_read4()
244 unsigned int reg, nsp32_multi_write4()
248 outsl(base + reg, buf, count); nsp32_multi_write4()
118 nsp32_index_read1(unsigned int base, unsigned int reg) nsp32_index_read1() argument
125 nsp32_index_write1(unsigned int base, unsigned int reg, unsigned char val) nsp32_index_write1() argument
133 nsp32_index_read2(unsigned int base, unsigned int reg) nsp32_index_read2() argument
140 nsp32_index_write2(unsigned int base, unsigned int reg, unsigned short val) nsp32_index_write2() argument
148 nsp32_index_read4(unsigned int base, unsigned int reg) nsp32_index_read4() argument
160 nsp32_index_write4(unsigned int base, unsigned int reg, unsigned long val) nsp32_index_write4() argument
176 nsp32_mmio_index_read1(unsigned long base, unsigned int reg) nsp32_mmio_index_read1() argument
188 nsp32_mmio_index_write1(unsigned long base, unsigned int reg, unsigned char val) nsp32_mmio_index_write1() argument
201 nsp32_mmio_index_read2(unsigned long base, unsigned int reg) nsp32_mmio_index_read2() argument
213 nsp32_mmio_index_write2(unsigned long base, unsigned int reg, unsigned short val) nsp32_mmio_index_write2() argument
228 nsp32_multi_read4(unsigned int base, unsigned int reg, void *buf, unsigned long count) nsp32_multi_read4() argument
243 nsp32_multi_write4(unsigned int base, unsigned int reg, void *buf, unsigned long count) nsp32_multi_write4() argument
/linux-4.1.27/drivers/mfd/
H A Drtsx_pcr.h58 #define rtsx_vendor_setting_valid(reg) (!((reg) & 0x1000000))
59 #define rts5209_vendor_setting1_valid(reg) (!((reg) & 0x80))
60 #define rts5209_vendor_setting2_valid(reg) ((reg) & 0x80)
62 #define rtsx_reg_to_aspm(reg) (((reg) >> 28) & 0x03)
63 #define rtsx_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 26) & 0x03)
64 #define rtsx_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x03)
65 #define rtsx_reg_to_card_drive_sel(reg) ((((reg) >> 25) & 0x01) << 6)
66 #define rtsx_reg_check_reverse_socket(reg) ((reg) & 0x4000)
67 #define rts5209_reg_to_aspm(reg) (((reg) >> 5) & 0x03)
68 #define rts5209_reg_check_ms_pmos(reg) (!((reg) & 0x08))
69 #define rts5209_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 3) & 0x07)
70 #define rts5209_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x07)
71 #define rts5209_reg_to_card_drive_sel(reg) ((reg) >> 8)
72 #define rtl8411_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x07)
73 #define rtl8411b_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x03)
H A Dtps65912-core.c29 int tps65912_set_bits(struct tps65912 *tps65912, u8 reg, u8 mask) tps65912_set_bits() argument
36 err = tps65912->read(tps65912, reg, 1, &data); tps65912_set_bits()
38 dev_err(tps65912->dev, "Read from reg 0x%x failed\n", reg); tps65912_set_bits()
43 err = tps65912->write(tps65912, reg, 1, &data); tps65912_set_bits()
45 dev_err(tps65912->dev, "Write to reg 0x%x failed\n", reg); tps65912_set_bits()
53 int tps65912_clear_bits(struct tps65912 *tps65912, u8 reg, u8 mask) tps65912_clear_bits() argument
59 err = tps65912->read(tps65912, reg, 1, &data); tps65912_clear_bits()
61 dev_err(tps65912->dev, "Read from reg 0x%x failed\n", reg); tps65912_clear_bits()
66 err = tps65912->write(tps65912, reg, 1, &data); tps65912_clear_bits()
68 dev_err(tps65912->dev, "Write to reg 0x%x failed\n", reg); tps65912_clear_bits()
76 static inline int tps65912_read(struct tps65912 *tps65912, u8 reg) tps65912_read() argument
81 err = tps65912->read(tps65912, reg, 1, &val); tps65912_read()
88 static inline int tps65912_write(struct tps65912 *tps65912, u8 reg, u8 val) tps65912_write() argument
90 return tps65912->write(tps65912, reg, 1, &val); tps65912_write()
93 int tps65912_reg_read(struct tps65912 *tps65912, u8 reg) tps65912_reg_read() argument
99 data = tps65912_read(tps65912, reg); tps65912_reg_read()
101 dev_err(tps65912->dev, "Read from reg 0x%x failed\n", reg); tps65912_reg_read()
108 int tps65912_reg_write(struct tps65912 *tps65912, u8 reg, u8 val) tps65912_reg_write() argument
114 err = tps65912_write(tps65912, reg, val); tps65912_reg_write()
116 dev_err(tps65912->dev, "Write for reg 0x%x failed\n", reg); tps65912_reg_write()
H A Dwm8350-irq.c41 int reg; member in struct:wm8350_irq_data
49 .reg = WM8350_OVER_CURRENT_INT_OFFSET,
55 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
60 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
65 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
70 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
75 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
80 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
85 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
90 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
95 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
100 .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
105 .reg = WM8350_INT_OFFSET_1,
110 .reg = WM8350_INT_OFFSET_1,
115 .reg = WM8350_INT_OFFSET_1,
120 .reg = WM8350_INT_OFFSET_1,
125 .reg = WM8350_INT_OFFSET_1,
130 .reg = WM8350_INT_OFFSET_1,
135 .reg = WM8350_INT_OFFSET_1,
140 .reg = WM8350_INT_OFFSET_1,
145 .reg = WM8350_INT_OFFSET_1,
150 .reg = WM8350_INT_OFFSET_1,
155 .reg = WM8350_INT_OFFSET_1,
160 .reg = WM8350_INT_OFFSET_1,
165 .reg = WM8350_INT_OFFSET_1,
170 .reg = WM8350_INT_OFFSET_2,
175 .reg = WM8350_INT_OFFSET_2,
180 .reg = WM8350_INT_OFFSET_2,
185 .reg = WM8350_INT_OFFSET_2,
190 .reg = WM8350_INT_OFFSET_2,
195 .reg = WM8350_INT_OFFSET_2,
200 .reg = WM8350_INT_OFFSET_2,
205 .reg = WM8350_INT_OFFSET_2,
210 .reg = WM8350_INT_OFFSET_2,
215 .reg = WM8350_INT_OFFSET_2,
220 .reg = WM8350_INT_OFFSET_2,
225 .reg = WM8350_INT_OFFSET_2,
231 .reg = WM8350_COMPARATOR_INT_OFFSET,
236 .reg = WM8350_COMPARATOR_INT_OFFSET,
241 .reg = WM8350_COMPARATOR_INT_OFFSET,
246 .reg = WM8350_COMPARATOR_INT_OFFSET,
251 .reg = WM8350_COMPARATOR_INT_OFFSET,
256 .reg = WM8350_COMPARATOR_INT_OFFSET,
261 .reg = WM8350_COMPARATOR_INT_OFFSET,
266 .reg = WM8350_COMPARATOR_INT_OFFSET,
271 .reg = WM8350_COMPARATOR_INT_OFFSET,
276 .reg = WM8350_COMPARATOR_INT_OFFSET,
281 .reg = WM8350_COMPARATOR_INT_OFFSET,
286 .reg = WM8350_COMPARATOR_INT_OFFSET,
291 .reg = WM8350_COMPARATOR_INT_OFFSET,
296 .reg = WM8350_COMPARATOR_INT_OFFSET,
301 .reg = WM8350_GPIO_INT_OFFSET,
306 .reg = WM8350_GPIO_INT_OFFSET,
311 .reg = WM8350_GPIO_INT_OFFSET,
316 .reg = WM8350_GPIO_INT_OFFSET,
321 .reg = WM8350_GPIO_INT_OFFSET,
326 .reg = WM8350_GPIO_INT_OFFSET,
331 .reg = WM8350_GPIO_INT_OFFSET,
336 .reg = WM8350_GPIO_INT_OFFSET,
341 .reg = WM8350_GPIO_INT_OFFSET,
346 .reg = WM8350_GPIO_INT_OFFSET,
351 .reg = WM8350_GPIO_INT_OFFSET,
356 .reg = WM8350_GPIO_INT_OFFSET,
361 .reg = WM8350_GPIO_INT_OFFSET,
404 if (!read_done[data->reg]) { wm8350_irq()
405 sub_reg[data->reg] = wm8350_irq()
407 data->reg); wm8350_irq()
408 sub_reg[data->reg] &= ~wm8350->irq_masks[data->reg]; wm8350_irq()
409 read_done[data->reg] = 1; wm8350_irq()
412 if (sub_reg[data->reg] & data->mask) wm8350_irq()
448 wm8350->irq_masks[irq_data->reg] &= ~irq_data->mask; wm8350_irq_enable()
457 wm8350->irq_masks[irq_data->reg] |= irq_data->mask; wm8350_irq_disable()
H A Dtps65912-irq.c45 u8 reg; tps65912_irq() local
49 tps65912->read(tps65912, TPS65912_INT_STS, 1, &reg); tps65912_irq()
50 irq_sts = reg; tps65912_irq()
51 tps65912->read(tps65912, TPS65912_INT_STS2, 1, &reg); tps65912_irq()
52 irq_sts |= reg << 8; tps65912_irq()
53 tps65912->read(tps65912, TPS65912_INT_STS3, 1, &reg); tps65912_irq()
54 irq_sts |= reg << 16; tps65912_irq()
55 tps65912->read(tps65912, TPS65912_INT_STS4, 1, &reg); tps65912_irq()
56 irq_sts |= reg << 24; tps65912_irq()
58 tps65912->read(tps65912, TPS65912_INT_MSK, 1, &reg); tps65912_irq()
59 irq_mask = reg; tps65912_irq()
60 tps65912->read(tps65912, TPS65912_INT_MSK2, 1, &reg); tps65912_irq()
61 irq_mask |= reg << 8; tps65912_irq()
62 tps65912->read(tps65912, TPS65912_INT_MSK3, 1, &reg); tps65912_irq()
63 irq_mask |= reg << 16; tps65912_irq()
64 tps65912->read(tps65912, TPS65912_INT_MSK4, 1, &reg); tps65912_irq()
65 irq_mask |= reg << 24; tps65912_irq()
79 reg = irq_sts & 0xFF; tps65912_irq()
81 if (reg) tps65912_irq()
82 tps65912->write(tps65912, TPS65912_INT_STS, 1, &reg); tps65912_irq()
83 reg = irq_sts & 0xFF; tps65912_irq()
85 if (reg) tps65912_irq()
86 tps65912->write(tps65912, TPS65912_INT_STS2, 1, &reg); tps65912_irq()
87 reg = irq_sts & 0xFF; tps65912_irq()
89 if (reg) tps65912_irq()
90 tps65912->write(tps65912, TPS65912_INT_STS3, 1, &reg); tps65912_irq()
91 reg = irq_sts & 0xFF; tps65912_irq()
92 if (reg) tps65912_irq()
93 tps65912->write(tps65912, TPS65912_INT_STS4, 1, &reg); tps65912_irq()
109 u8 reg; tps65912_irq_sync_unlock() local
111 tps65912->read(tps65912, TPS65912_INT_MSK, 1, &reg); tps65912_irq_sync_unlock()
112 reg_mask = reg; tps65912_irq_sync_unlock()
113 tps65912->read(tps65912, TPS65912_INT_MSK2, 1, &reg); tps65912_irq_sync_unlock()
114 reg_mask |= reg << 8; tps65912_irq_sync_unlock()
115 tps65912->read(tps65912, TPS65912_INT_MSK3, 1, &reg); tps65912_irq_sync_unlock()
116 reg_mask |= reg << 16; tps65912_irq_sync_unlock()
117 tps65912->read(tps65912, TPS65912_INT_MSK4, 1, &reg); tps65912_irq_sync_unlock()
118 reg_mask |= reg << 24; tps65912_irq_sync_unlock()
121 reg = tps65912->irq_mask & 0xFF; tps65912_irq_sync_unlock()
122 tps65912->write(tps65912, TPS65912_INT_MSK, 1, &reg); tps65912_irq_sync_unlock()
123 reg = tps65912->irq_mask >> 8 & 0xFF; tps65912_irq_sync_unlock()
124 tps65912->write(tps65912, TPS65912_INT_MSK2, 1, &reg); tps65912_irq_sync_unlock()
125 reg = tps65912->irq_mask >> 16 & 0xFF; tps65912_irq_sync_unlock()
126 tps65912->write(tps65912, TPS65912_INT_MSK3, 1, &reg); tps65912_irq_sync_unlock()
127 reg = tps65912->irq_mask >> 24 & 0xFF; tps65912_irq_sync_unlock()
128 tps65912->write(tps65912, TPS65912_INT_MSK4, 1, &reg); tps65912_irq_sync_unlock()
161 u8 reg; tps65912_irq_init() local
174 tps65912->read(tps65912, TPS65912_INT_STS, 1, &reg); tps65912_irq_init()
175 tps65912->write(tps65912, TPS65912_INT_STS, 1, &reg); tps65912_irq_init()
176 tps65912->read(tps65912, TPS65912_INT_STS2, 1, &reg); tps65912_irq_init()
177 tps65912->write(tps65912, TPS65912_INT_STS2, 1, &reg); tps65912_irq_init()
178 tps65912->read(tps65912, TPS65912_INT_STS3, 1, &reg); tps65912_irq_init()
179 tps65912->write(tps65912, TPS65912_INT_STS3, 1, &reg); tps65912_irq_init()
180 tps65912->read(tps65912, TPS65912_INT_STS4, 1, &reg); tps65912_irq_init()
181 tps65912->write(tps65912, TPS65912_INT_STS4, 1, &reg); tps65912_irq_init()
H A Dwm831x-irq.c32 int reg; member in struct:wm831x_irq_data
39 .reg = 1,
44 .reg = 5,
49 .reg = 5,
54 .reg = 5,
59 .reg = 5,
64 .reg = 5,
69 .reg = 5,
74 .reg = 5,
79 .reg = 5,
84 .reg = 5,
89 .reg = 5,
94 .reg = 5,
99 .reg = 5,
104 .reg = 5,
109 .reg = 5,
114 .reg = 5,
119 .reg = 5,
124 .reg = 1,
129 .reg = 1,
134 .reg = 1,
139 .reg = 1,
144 .reg = 1,
149 .reg = 1,
154 .reg = 1,
159 .reg = 2,
164 .reg = 2,
169 .reg = 2,
174 .reg = 2,
179 .reg = 2,
184 .reg = 2,
189 .reg = 2,
194 .reg = 2,
199 .reg = 1,
204 .reg = 1,
209 .reg = 1,
214 .reg = 1,
219 .reg = 1,
224 .reg = 1,
229 .reg = 1,
234 .reg = 2,
239 .reg = 2,
244 .reg = 4,
249 .reg = 4,
254 .reg = 3,
259 .reg = 3,
264 .reg = 3,
269 .reg = 3,
274 .reg = 3,
279 .reg = 3,
284 .reg = 3,
289 .reg = 3,
294 .reg = 3,
299 .reg = 3,
304 .reg = 4,
309 .reg = 4,
314 .reg = 4,
319 .reg = 4,
326 return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg; irq_data_to_status_reg()
380 wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; wm831x_irq_enable()
389 wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; wm831x_irq_disable()
484 int offset = wm831x_irqs[i].reg - 1; wm831x_irq_thread()
H A Dpcf50633-gpio.c40 u8 reg; pcf50633_gpio_set() local
42 reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; pcf50633_gpio_set()
44 return pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val); pcf50633_gpio_set()
50 u8 reg, val; pcf50633_gpio_get() local
52 reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; pcf50633_gpio_get()
53 val = pcf50633_reg_read(pcf, reg) & 0x07; pcf50633_gpio_get()
61 u8 val, reg; pcf50633_gpio_invert_set() local
63 reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; pcf50633_gpio_invert_set()
66 return pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val); pcf50633_gpio_invert_set()
72 u8 reg, val; pcf50633_gpio_invert_get() local
74 reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; pcf50633_gpio_invert_get()
75 val = pcf50633_reg_read(pcf, reg); pcf50633_gpio_invert_get()
84 u8 reg, val, mask; pcf50633_gpio_power_supply_set() local
87 reg = pcf50633_regulator_registers[regulator] + 1; pcf50633_gpio_power_supply_set()
92 return pcf50633_reg_set_bit_mask(pcf, reg, mask, val); pcf50633_gpio_power_supply_set()
H A Dwm8350-gpio.c52 u16 reg; gpio_set_func() local
57 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) gpio_set_func()
60 reg | ((func & 0xf) << 0)); gpio_set_func()
63 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) gpio_set_func()
66 reg | ((func & 0xf) << 4)); gpio_set_func()
69 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) gpio_set_func()
72 reg | ((func & 0xf) << 8)); gpio_set_func()
75 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) gpio_set_func()
78 reg | ((func & 0xf) << 12)); gpio_set_func()
81 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2) gpio_set_func()
84 reg | ((func & 0xf) << 0)); gpio_set_func()
87 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2) gpio_set_func()
90 reg | ((func & 0xf) << 4)); gpio_set_func()
93 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2) gpio_set_func()
96 reg | ((func & 0xf) << 8)); gpio_set_func()
99 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2) gpio_set_func()
102 reg | ((func & 0xf) << 12)); gpio_set_func()
105 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3) gpio_set_func()
108 reg | ((func & 0xf) << 0)); gpio_set_func()
111 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3) gpio_set_func()
114 reg | ((func & 0xf) << 4)); gpio_set_func()
117 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3) gpio_set_func()
120 reg | ((func & 0xf) << 8)); gpio_set_func()
123 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3) gpio_set_func()
126 reg | ((func & 0xf) << 12)); gpio_set_func()
129 reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_4) gpio_set_func()
132 reg | ((func & 0xf) << 0)); gpio_set_func()
H A Dmax8998-irq.c21 int reg; member in struct:max8998_irq_data
27 .reg = 1,
31 .reg = 1,
35 .reg = 1,
39 .reg = 1,
43 .reg = 1,
47 .reg = 1,
51 .reg = 2,
55 .reg = 2,
59 .reg = 2,
63 .reg = 2,
67 .reg = 3,
71 .reg = 3,
75 .reg = 3,
79 .reg = 3,
83 .reg = 3,
87 .reg = 3,
91 .reg = 4,
95 .reg = 4,
140 max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; max8998_irq_unmask()
149 max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; max8998_irq_mask()
181 if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask) { max8998_irq_thread()
/linux-4.1.27/drivers/media/pci/cx23885/
H A Dcx23885-ioctl.c42 struct v4l2_dbg_register *reg) cx23417_g_register()
49 if ((reg->reg & 0x3) != 0 || reg->reg >= 0x10000) cx23417_g_register()
52 if (mc417_register_read(dev, (u16) reg->reg, &value)) cx23417_g_register()
55 reg->size = 4; cx23417_g_register()
56 reg->val = value; cx23417_g_register()
61 struct v4l2_dbg_register *reg) cx23885_g_register()
65 if (reg->match.addr > 1) cx23885_g_register()
67 if (reg->match.addr) cx23885_g_register()
68 return cx23417_g_register(dev, reg); cx23885_g_register()
70 if ((reg->reg & 0x3) != 0 || reg->reg >= pci_resource_len(dev->pci, 0)) cx23885_g_register()
73 reg->size = 4; cx23885_g_register()
74 reg->val = cx_read(reg->reg); cx23885_g_register()
79 const struct v4l2_dbg_register *reg) cx23417_s_register()
84 if ((reg->reg & 0x3) != 0 || reg->reg >= 0x10000) cx23417_s_register()
87 if (mc417_register_write(dev, (u16) reg->reg, (u32) reg->val)) cx23417_s_register()
93 const struct v4l2_dbg_register *reg) cx23885_s_register()
97 if (reg->match.addr > 1) cx23885_s_register()
99 if (reg->match.addr) cx23885_s_register()
100 return cx23417_s_register(dev, reg); cx23885_s_register()
102 if ((reg->reg & 0x3) != 0 || reg->reg >= pci_resource_len(dev->pci, 0)) cx23885_s_register()
105 cx_write(reg->reg, reg->val); cx23885_s_register()
41 cx23417_g_register(struct cx23885_dev *dev, struct v4l2_dbg_register *reg) cx23417_g_register() argument
60 cx23885_g_register(struct file *file, void *fh, struct v4l2_dbg_register *reg) cx23885_g_register() argument
78 cx23417_s_register(struct cx23885_dev *dev, const struct v4l2_dbg_register *reg) cx23417_s_register() argument
92 cx23885_s_register(struct file *file, void *fh, const struct v4l2_dbg_register *reg) cx23885_s_register() argument
H A Dnetup-init.c25 static void i2c_av_write(struct i2c_adapter *i2c, u16 reg, u8 val) i2c_av_write() argument
36 buf[0] = reg >> 8; i2c_av_write()
37 buf[1] = reg & 0xff; i2c_av_write()
46 static void i2c_av_write4(struct i2c_adapter *i2c, u16 reg, u32 val) i2c_av_write4() argument
57 buf[0] = reg >> 8; i2c_av_write4()
58 buf[1] = reg & 0xff; i2c_av_write4()
70 static u8 i2c_av_read(struct i2c_adapter *i2c, u16 reg) i2c_av_read() argument
81 buf[0] = reg >> 8; i2c_av_read()
82 buf[1] = reg & 0xff; i2c_av_read()
100 static void i2c_av_and_or(struct i2c_adapter *i2c, u16 reg, unsigned and_mask, i2c_av_and_or() argument
103 i2c_av_write(i2c, reg, (i2c_av_read(i2c, reg) & and_mask) | or_value); i2c_av_and_or()
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/iop/
H A Diop_version_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Diop_fifo_in_extra_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Diop_fifo_out_extra_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Diop_scrc_in_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Diop_scrc_out_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Diop_trigger_grp_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Diop_crc_par_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Diop_fifo_in_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Diop_mpu_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Diop_sap_in_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Diop_timer_grp_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/
H A Dirq_nmi_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Dstrcop_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Dconfig_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Drt_trace_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Data_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Dbif_slave_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Dmarb_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
277 #define REG_RD( scope, inst, reg ) \
278 REG_READ( reg_##scope##_##reg, \
279 (inst) + REG_RD_ADDR_##scope##_##reg )
283 #define REG_WR( scope, inst, reg, val ) \
284 REG_WRITE( reg_##scope##_##reg, \
285 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
289 #define REG_RD_VECT( scope, inst, reg, index ) \
290 REG_READ( reg_##scope##_##reg, \
291 (inst) + REG_RD_ADDR_##scope##_##reg + \
292 (index) * STRIDE_##scope##_##reg )
296 #define REG_WR_VECT( scope, inst, reg, index, val ) \
297 REG_WRITE( reg_##scope##_##reg, \
298 (inst) + REG_WR_ADDR_##scope##_##reg + \
299 (index) * STRIDE_##scope##_##reg, (val) )
303 #define REG_RD_INT( scope, inst, reg ) \
304 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
308 #define REG_WR_INT( scope, inst, reg, val ) \
309 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
313 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
314 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
315 (index) * STRIDE_##scope##_##reg )
319 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
320 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
321 (index) * STRIDE_##scope##_##reg, (val) )
334 #define REG_ADDR( scope, inst, reg ) \
335 ( (inst) + REG_RD_ADDR_##scope##_##reg )
339 #define REG_ADDR_VECT( scope, inst, reg, index ) \
340 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
341 (index) * STRIDE_##scope##_##reg )
H A Dmarb_bp_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
H A Dstrmux_defs.h15 #define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
H A Dclkgen_defs.h15 #define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
H A Dl2cache_defs.h15 #define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
H A Dmarb_bar_defs.h15 #define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )
299 #define REG_RD( scope, inst, reg ) \
300 REG_READ( reg_##scope##_##reg, \
301 (inst) + REG_RD_ADDR_##scope##_##reg )
305 #define REG_WR( scope, inst, reg, val ) \
306 REG_WRITE( reg_##scope##_##reg, \
307 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
311 #define REG_RD_VECT( scope, inst, reg, index ) \
312 REG_READ( reg_##scope##_##reg, \
313 (inst) + REG_RD_ADDR_##scope##_##reg + \
314 (index) * STRIDE_##scope##_##reg )
318 #define REG_WR_VECT( scope, inst, reg, index, val ) \
319 REG_WRITE( reg_##scope##_##reg, \
320 (inst) + REG_WR_ADDR_##scope##_##reg + \
321 (index) * STRIDE_##scope##_##reg, (val) )
325 #define REG_RD_INT( scope, inst, reg ) \
326 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
330 #define REG_WR_INT( scope, inst, reg, val ) \
331 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
335 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
336 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
337 (index) * STRIDE_##scope##_##reg )
341 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
342 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
343 (index) * STRIDE_##scope##_##reg, (val) )
356 #define REG_ADDR( scope, inst, reg ) \
357 ( (inst) + REG_RD_ADDR_##scope##_##reg )
361 #define REG_ADDR_VECT( scope, inst, reg, index ) \
362 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
363 (index) * STRIDE_##scope##_##reg )
/linux-4.1.27/drivers/video/fbdev/exynos/
H A Dexynos_mipi_dsi_lowlevel.c34 unsigned int reg; exynos_mipi_dsi_func_reset() local
36 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); exynos_mipi_dsi_func_reset()
38 reg |= DSIM_FUNCRST; exynos_mipi_dsi_func_reset()
40 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); exynos_mipi_dsi_func_reset()
45 unsigned int reg; exynos_mipi_dsi_sw_reset() local
47 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); exynos_mipi_dsi_sw_reset()
49 reg |= DSIM_SWRST; exynos_mipi_dsi_sw_reset()
51 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); exynos_mipi_dsi_sw_reset()
56 unsigned int reg; exynos_mipi_dsi_sw_reset_release() local
58 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_sw_reset_release()
60 reg |= INTSRC_SW_RST_RELEASE; exynos_mipi_dsi_sw_reset_release()
62 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_sw_reset_release()
73 unsigned int reg; exynos_mipi_dsi_read_interrupt_mask() local
75 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK); exynos_mipi_dsi_read_interrupt_mask()
77 return reg; exynos_mipi_dsi_read_interrupt_mask()
83 unsigned int reg = 0; exynos_mipi_dsi_set_interrupt_mask() local
86 reg |= mode; exynos_mipi_dsi_set_interrupt_mask()
88 reg &= ~mode; exynos_mipi_dsi_set_interrupt_mask()
90 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK); exynos_mipi_dsi_set_interrupt_mask()
96 unsigned int reg; exynos_mipi_dsi_init_fifo_pointer() local
98 reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); exynos_mipi_dsi_init_fifo_pointer()
100 writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); exynos_mipi_dsi_init_fifo_pointer()
102 reg |= cfg; exynos_mipi_dsi_init_fifo_pointer()
104 writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); exynos_mipi_dsi_init_fifo_pointer()
119 unsigned int reg; exynos_mipi_dsi_set_main_stand_by() local
121 reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL); exynos_mipi_dsi_set_main_stand_by()
123 reg &= ~DSIM_MAIN_STAND_BY; exynos_mipi_dsi_set_main_stand_by()
126 reg |= DSIM_MAIN_STAND_BY; exynos_mipi_dsi_set_main_stand_by()
128 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); exynos_mipi_dsi_set_main_stand_by()
134 unsigned int reg; exynos_mipi_dsi_set_main_disp_resol() local
137 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) & exynos_mipi_dsi_set_main_disp_resol()
139 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); exynos_mipi_dsi_set_main_disp_resol()
141 reg &= ~((0x7ff << 16) | (0x7ff << 0)); exynos_mipi_dsi_set_main_disp_resol()
142 reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol); exynos_mipi_dsi_set_main_disp_resol()
144 reg |= DSIM_MAIN_STAND_BY; exynos_mipi_dsi_set_main_disp_resol()
145 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); exynos_mipi_dsi_set_main_disp_resol()
151 unsigned int reg; exynos_mipi_dsi_set_main_disp_vporch() local
153 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) & exynos_mipi_dsi_set_main_disp_vporch()
157 reg |= (DSIM_CMD_ALLOW_SHIFT(cmd_allow & 0xf) | exynos_mipi_dsi_set_main_disp_vporch()
161 writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH); exynos_mipi_dsi_set_main_disp_vporch()
167 unsigned int reg; exynos_mipi_dsi_set_main_disp_hporch() local
169 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) & exynos_mipi_dsi_set_main_disp_hporch()
172 reg |= DSIM_MAIN_HFP_SHIFT(front) | DSIM_MAIN_HBP_SHIFT(back); exynos_mipi_dsi_set_main_disp_hporch()
174 writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH); exynos_mipi_dsi_set_main_disp_hporch()
180 unsigned int reg; exynos_mipi_dsi_set_main_disp_sync_area() local
182 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MSYNC)) & exynos_mipi_dsi_set_main_disp_sync_area()
185 reg |= (DSIM_MAIN_VSA_SHIFT(vert & 0x3ff) | exynos_mipi_dsi_set_main_disp_sync_area()
188 writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC); exynos_mipi_dsi_set_main_disp_sync_area()
194 unsigned int reg; exynos_mipi_dsi_set_sub_disp_resol() local
196 reg = (readl(dsim->reg_base + EXYNOS_DSIM_SDRESOL)) & exynos_mipi_dsi_set_sub_disp_resol()
199 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); exynos_mipi_dsi_set_sub_disp_resol()
201 reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK); exynos_mipi_dsi_set_sub_disp_resol()
202 reg |= (DSIM_SUB_VRESOL_SHIFT(vert & 0x7ff) | exynos_mipi_dsi_set_sub_disp_resol()
204 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); exynos_mipi_dsi_set_sub_disp_resol()
206 reg |= DSIM_SUB_STANDY_SHIFT(1); exynos_mipi_dsi_set_sub_disp_resol()
207 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); exynos_mipi_dsi_set_sub_disp_resol()
232 u32 reg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) & exynos_mipi_dsi_display_config() local
237 reg |= (1 << 25); exynos_mipi_dsi_display_config()
239 reg &= ~(1 << 25); exynos_mipi_dsi_display_config()
246 reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << 26 | exynos_mipi_dsi_display_config()
250 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG); exynos_mipi_dsi_display_config()
256 unsigned int reg; exynos_mipi_dsi_enable_lane() local
258 reg = readl(dsim->reg_base + EXYNOS_DSIM_CONFIG); exynos_mipi_dsi_enable_lane()
261 reg |= DSIM_LANE_ENx(lane); exynos_mipi_dsi_enable_lane()
263 reg &= ~DSIM_LANE_ENx(lane); exynos_mipi_dsi_enable_lane()
265 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG); exynos_mipi_dsi_enable_lane()
283 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR); exynos_mipi_dsi_enable_afc() local
286 reg |= (1 << 14); exynos_mipi_dsi_enable_afc()
287 reg &= ~(0x7 << 5); exynos_mipi_dsi_enable_afc()
288 reg |= (afc_code & 0x7) << 5; exynos_mipi_dsi_enable_afc()
290 reg &= ~(1 << 14); exynos_mipi_dsi_enable_afc()
292 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR); exynos_mipi_dsi_enable_afc()
298 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & exynos_mipi_dsi_enable_pll_bypass() local
301 reg |= DSIM_PLL_BYPASS_SHIFT(enable); exynos_mipi_dsi_enable_pll_bypass()
303 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_pll_bypass()
309 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_set_pll_pms() local
311 reg |= ((p & 0x3f) << 13) | ((m & 0x1ff) << 4) | ((s & 0x7) << 1); exynos_mipi_dsi_set_pll_pms()
313 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_set_pll_pms()
319 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & exynos_mipi_dsi_pll_freq_band() local
322 reg |= DSIM_FREQ_BAND_SHIFT(freq_band & 0x1f); exynos_mipi_dsi_pll_freq_band()
324 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_pll_freq_band()
331 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & exynos_mipi_dsi_pll_freq() local
334 reg |= (pre_divider & 0x3f) << 13 | (main_divider & 0x1ff) << 4 | exynos_mipi_dsi_pll_freq()
337 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_pll_freq()
348 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & exynos_mipi_dsi_enable_pll() local
351 reg |= DSIM_PLL_EN_SHIFT(enable & 0x1); exynos_mipi_dsi_enable_pll()
353 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_enable_pll()
359 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & exynos_mipi_dsi_set_byte_clock_src() local
362 reg |= (DSIM_BYTE_CLK_SRC_SHIFT(src)); exynos_mipi_dsi_set_byte_clock_src()
364 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_set_byte_clock_src()
370 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & exynos_mipi_dsi_enable_byte_clock() local
373 reg |= DSIM_BYTE_CLKEN_SHIFT(enable); exynos_mipi_dsi_enable_byte_clock()
375 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_byte_clock()
381 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & exynos_mipi_dsi_set_esc_clk_prs() local
384 reg |= DSIM_ESC_CLKEN_SHIFT(enable); exynos_mipi_dsi_set_esc_clk_prs()
386 reg |= prs_val; exynos_mipi_dsi_set_esc_clk_prs()
388 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_set_esc_clk_prs()
394 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_esc_clk_on_lane() local
397 reg |= DSIM_LANE_ESC_CLKEN(lane_sel); exynos_mipi_dsi_enable_esc_clk_on_lane()
400 reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel); exynos_mipi_dsi_enable_esc_clk_on_lane()
402 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_esc_clk_on_lane()
408 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) & exynos_mipi_dsi_force_dphy_stop_state() local
411 reg |= (DSIM_FORCE_STOP_STATE_SHIFT(enable & 0x1)); exynos_mipi_dsi_force_dphy_stop_state()
413 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_force_dphy_stop_state()
418 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS); exynos_mipi_dsi_is_lane_state() local
426 if ((reg & DSIM_STOP_STATE_DAT(0xf)) && exynos_mipi_dsi_is_lane_state()
427 ((reg & DSIM_STOP_STATE_CLK) || exynos_mipi_dsi_is_lane_state()
428 (reg & DSIM_TX_READY_HS_CLK))) exynos_mipi_dsi_is_lane_state()
437 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) & exynos_mipi_dsi_set_stop_state_counter() local
440 reg |= (DSIM_STOP_STATE_CNT_SHIFT(cnt_val & 0x7ff)); exynos_mipi_dsi_set_stop_state_counter()
442 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_set_stop_state_counter()
448 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) & exynos_mipi_dsi_set_bta_timeout() local
451 reg |= (DSIM_BTA_TOUT_SHIFT(timeout)); exynos_mipi_dsi_set_bta_timeout()
453 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT); exynos_mipi_dsi_set_bta_timeout()
459 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) & exynos_mipi_dsi_set_lpdr_timeout() local
462 reg |= (DSIM_LPDR_TOUT_SHIFT(timeout)); exynos_mipi_dsi_set_lpdr_timeout()
464 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT); exynos_mipi_dsi_set_lpdr_timeout()
470 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_set_cpu_transfer_mode() local
472 reg &= ~DSIM_CMD_LPDT_LP; exynos_mipi_dsi_set_cpu_transfer_mode()
475 reg |= DSIM_CMD_LPDT_LP; exynos_mipi_dsi_set_cpu_transfer_mode()
477 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_set_cpu_transfer_mode()
483 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_set_lcdc_transfer_mode() local
485 reg &= ~DSIM_TX_LPDT_LP; exynos_mipi_dsi_set_lcdc_transfer_mode()
488 reg |= DSIM_TX_LPDT_LP; exynos_mipi_dsi_set_lcdc_transfer_mode()
490 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_set_lcdc_transfer_mode()
496 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & exynos_mipi_dsi_enable_hs_clock() local
499 reg |= DSIM_TX_REQUEST_HSCLK_SHIFT(enable); exynos_mipi_dsi_enable_hs_clock()
501 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_hs_clock()
507 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR1); exynos_mipi_dsi_dp_dn_swap() local
509 reg &= ~(0x3 << 0); exynos_mipi_dsi_dp_dn_swap()
510 reg |= (swap_en & 0x3) << 0; exynos_mipi_dsi_dp_dn_swap()
512 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1); exynos_mipi_dsi_dp_dn_swap()
518 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & exynos_mipi_dsi_hs_zero_ctrl() local
521 reg |= ((hs_zero & 0xf) << 28); exynos_mipi_dsi_hs_zero_ctrl()
523 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_hs_zero_ctrl()
528 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & exynos_mipi_dsi_prep_ctrl() local
531 reg |= ((prep & 0x7) << 20); exynos_mipi_dsi_prep_ctrl()
533 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_prep_ctrl()
544 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_clear_interrupt() local
546 reg |= src; exynos_mipi_dsi_clear_interrupt()
548 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_clear_interrupt()
554 unsigned int reg = 0; exynos_mipi_dsi_set_interrupt() local
557 reg |= src; exynos_mipi_dsi_set_interrupt()
559 reg &= ~src; exynos_mipi_dsi_set_interrupt()
561 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_set_interrupt()
566 unsigned int reg; exynos_mipi_dsi_is_pll_stable() local
568 reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS); exynos_mipi_dsi_is_pll_stable()
570 return reg & (1 << 31) ? 1 : 0; exynos_mipi_dsi_is_pll_stable()
581 unsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0); exynos_mipi_dsi_wr_tx_header() local
583 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR); exynos_mipi_dsi_wr_tx_header()
589 unsigned int reg = (data0 << 8) | (di << 0); exynos_mipi_dsi_rd_tx_header() local
591 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR); exynos_mipi_dsi_rd_tx_header()
601 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); _exynos_mipi_dsi_get_frame_done_status() local
603 return (reg & INTSRC_FRAME_DONE) ? 1 : 0; _exynos_mipi_dsi_get_frame_done_status()
608 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); _exynos_mipi_dsi_clear_frame_done() local
610 writel(reg | INTSRC_FRAME_DONE, dsim->reg_base + _exynos_mipi_dsi_clear_frame_done()
/linux-4.1.27/drivers/scsi/qla2xxx/
H A Dqla_dbg.c121 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; qla27xx_dump_mpi_ram() local
128 WRT_REG_WORD(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM); qla27xx_dump_mpi_ram()
137 WRT_REG_WORD(&reg->mailbox1, LSW(addr)); qla27xx_dump_mpi_ram()
138 WRT_REG_WORD(&reg->mailbox8, MSW(addr)); qla27xx_dump_mpi_ram()
140 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma)); qla27xx_dump_mpi_ram()
141 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma)); qla27xx_dump_mpi_ram()
142 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma))); qla27xx_dump_mpi_ram()
143 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma))); qla27xx_dump_mpi_ram()
145 WRT_REG_WORD(&reg->mailbox4, MSW(dwords)); qla27xx_dump_mpi_ram()
146 WRT_REG_WORD(&reg->mailbox5, LSW(dwords)); qla27xx_dump_mpi_ram()
148 WRT_REG_WORD(&reg->mailbox9, 0); qla27xx_dump_mpi_ram()
149 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); qla27xx_dump_mpi_ram()
154 stat = RD_REG_DWORD(&reg->host_status); qla27xx_dump_mpi_ram()
163 mb0 = RD_REG_WORD(&reg->mailbox0); qla27xx_dump_mpi_ram()
164 mb1 = RD_REG_WORD(&reg->mailbox1); qla27xx_dump_mpi_ram()
166 WRT_REG_DWORD(&reg->hccr, qla27xx_dump_mpi_ram()
168 RD_REG_DWORD(&reg->hccr); qla27xx_dump_mpi_ram()
173 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); qla27xx_dump_mpi_ram()
174 RD_REG_DWORD(&reg->hccr); qla27xx_dump_mpi_ram()
201 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; qla24xx_dump_ram() local
208 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); qla24xx_dump_ram()
217 WRT_REG_WORD(&reg->mailbox1, LSW(addr)); qla24xx_dump_ram()
218 WRT_REG_WORD(&reg->mailbox8, MSW(addr)); qla24xx_dump_ram()
220 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma)); qla24xx_dump_ram()
221 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma)); qla24xx_dump_ram()
222 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma))); qla24xx_dump_ram()
223 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma))); qla24xx_dump_ram()
225 WRT_REG_WORD(&reg->mailbox4, MSW(dwords)); qla24xx_dump_ram()
226 WRT_REG_WORD(&reg->mailbox5, LSW(dwords)); qla24xx_dump_ram()
227 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); qla24xx_dump_ram()
232 stat = RD_REG_DWORD(&reg->host_status); qla24xx_dump_ram()
241 mb0 = RD_REG_WORD(&reg->mailbox0); qla24xx_dump_ram()
243 WRT_REG_DWORD(&reg->hccr, qla24xx_dump_ram()
245 RD_REG_DWORD(&reg->hccr); qla24xx_dump_ram()
250 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); qla24xx_dump_ram()
251 RD_REG_DWORD(&reg->hccr); qla24xx_dump_ram()
294 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, qla24xx_read_window() argument
299 WRT_REG_DWORD(&reg->iobase_addr, iobase); qla24xx_read_window()
300 dmp_reg = &reg->iobase_window; qla24xx_read_window()
308 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg, struct qla_hw_data *ha) qla24xx_pause_risc() argument
310 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE); qla24xx_pause_risc()
314 if (RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) qla24xx_pause_risc()
324 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; qla24xx_soft_reset() local
331 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); qla24xx_soft_reset()
333 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0) qla24xx_soft_reset()
338 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE)) qla24xx_soft_reset()
341 WRT_REG_DWORD(&reg->ctrl_status, qla24xx_soft_reset()
349 if ((RD_REG_DWORD(&reg->ctrl_status) & qla24xx_soft_reset()
355 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET)) qla24xx_soft_reset()
358 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET); qla24xx_soft_reset()
359 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */ qla24xx_soft_reset()
361 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 && qla24xx_soft_reset()
381 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; qla2xxx_dump_ram() local
388 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); qla2xxx_dump_ram()
397 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); qla2xxx_dump_ram()
398 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); qla2xxx_dump_ram()
400 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); qla2xxx_dump_ram()
401 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); qla2xxx_dump_ram()
402 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); qla2xxx_dump_ram()
403 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); qla2xxx_dump_ram()
405 WRT_MAILBOX_REG(ha, reg, 4, words); qla2xxx_dump_ram()
406 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT); qla2xxx_dump_ram()
410 stat = RD_REG_DWORD(&reg->u.isp2300.host_status); qla2xxx_dump_ram()
418 mb0 = RD_MAILBOX_REG(ha, reg, 0); qla2xxx_dump_ram()
421 WRT_REG_WORD(&reg->semaphore, 0); qla2xxx_dump_ram()
422 WRT_REG_WORD(&reg->hccr, qla2xxx_dump_ram()
424 RD_REG_WORD(&reg->hccr); qla2xxx_dump_ram()
430 mb0 = RD_MAILBOX_REG(ha, reg, 0); qla2xxx_dump_ram()
432 WRT_REG_WORD(&reg->hccr, qla2xxx_dump_ram()
434 RD_REG_WORD(&reg->hccr); qla2xxx_dump_ram()
439 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT); qla2xxx_dump_ram()
440 RD_REG_WORD(&reg->hccr); qla2xxx_dump_ram()
459 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, qla2xxx_read_window() argument
462 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd; qla2xxx_read_window()
630 device_reg_t __iomem *reg; qla25xx_copy_mq() local
644 reg = ISP_QUE_REG(ha, cnt); qla25xx_copy_mq()
647 htonl(RD_REG_DWORD(&reg->isp25mq.req_q_in)); qla25xx_copy_mq()
649 htonl(RD_REG_DWORD(&reg->isp25mq.req_q_out)); qla25xx_copy_mq()
651 htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_in)); qla25xx_copy_mq()
653 htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_out)); qla25xx_copy_mq()
689 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; qla2300_fw_dump() local
718 fw->hccr = htons(RD_REG_WORD(&reg->hccr)); qla2300_fw_dump()
721 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); qla2300_fw_dump()
724 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 && qla2300_fw_dump()
732 RD_REG_WORD(&reg->hccr); /* PCI Posting. */ qla2300_fw_dump()
737 dmp_reg = &reg->flash_address; qla2300_fw_dump()
741 dmp_reg = &reg->u.isp2300.req_q_in; qla2300_fw_dump()
745 dmp_reg = &reg->u.isp2300.mailbox0; qla2300_fw_dump()
749 WRT_REG_WORD(&reg->ctrl_status, 0x40); qla2300_fw_dump()
750 qla2xxx_read_window(reg, 32, fw->resp_dma_reg); qla2300_fw_dump()
752 WRT_REG_WORD(&reg->ctrl_status, 0x50); qla2300_fw_dump()
753 qla2xxx_read_window(reg, 48, fw->dma_reg); qla2300_fw_dump()
755 WRT_REG_WORD(&reg->ctrl_status, 0x00); qla2300_fw_dump()
756 dmp_reg = &reg->risc_hw; qla2300_fw_dump()
760 WRT_REG_WORD(&reg->pcr, 0x2000); qla2300_fw_dump()
761 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); qla2300_fw_dump()
763 WRT_REG_WORD(&reg->pcr, 0x2200); qla2300_fw_dump()
764 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); qla2300_fw_dump()
766 WRT_REG_WORD(&reg->pcr, 0x2400); qla2300_fw_dump()
767 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); qla2300_fw_dump()
769 WRT_REG_WORD(&reg->pcr, 0x2600); qla2300_fw_dump()
770 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); qla2300_fw_dump()
772 WRT_REG_WORD(&reg->pcr, 0x2800); qla2300_fw_dump()
773 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); qla2300_fw_dump()
775 WRT_REG_WORD(&reg->pcr, 0x2A00); qla2300_fw_dump()
776 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); qla2300_fw_dump()
778 WRT_REG_WORD(&reg->pcr, 0x2C00); qla2300_fw_dump()
779 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); qla2300_fw_dump()
781 WRT_REG_WORD(&reg->pcr, 0x2E00); qla2300_fw_dump()
782 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); qla2300_fw_dump()
784 WRT_REG_WORD(&reg->ctrl_status, 0x10); qla2300_fw_dump()
785 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); qla2300_fw_dump()
787 WRT_REG_WORD(&reg->ctrl_status, 0x20); qla2300_fw_dump()
788 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); qla2300_fw_dump()
790 WRT_REG_WORD(&reg->ctrl_status, 0x30); qla2300_fw_dump()
791 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); qla2300_fw_dump()
794 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET); qla2300_fw_dump()
796 if ((RD_REG_WORD(&reg->ctrl_status) & qla2300_fw_dump()
805 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && qla2300_fw_dump()
852 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; qla2100_fw_dump() local
882 fw->hccr = htons(RD_REG_WORD(&reg->hccr)); qla2100_fw_dump()
885 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); qla2100_fw_dump()
886 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 && qla2100_fw_dump()
894 dmp_reg = &reg->flash_address; qla2100_fw_dump()
898 dmp_reg = &reg->u.isp2100.mailbox0; qla2100_fw_dump()
901 dmp_reg = &reg->u_end.isp2200.mailbox8; qla2100_fw_dump()
906 dmp_reg = &reg->u.isp2100.unused_2[0]; qla2100_fw_dump()
910 WRT_REG_WORD(&reg->ctrl_status, 0x00); qla2100_fw_dump()
911 dmp_reg = &reg->risc_hw; qla2100_fw_dump()
915 WRT_REG_WORD(&reg->pcr, 0x2000); qla2100_fw_dump()
916 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); qla2100_fw_dump()
918 WRT_REG_WORD(&reg->pcr, 0x2100); qla2100_fw_dump()
919 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); qla2100_fw_dump()
921 WRT_REG_WORD(&reg->pcr, 0x2200); qla2100_fw_dump()
922 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); qla2100_fw_dump()
924 WRT_REG_WORD(&reg->pcr, 0x2300); qla2100_fw_dump()
925 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); qla2100_fw_dump()
927 WRT_REG_WORD(&reg->pcr, 0x2400); qla2100_fw_dump()
928 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); qla2100_fw_dump()
930 WRT_REG_WORD(&reg->pcr, 0x2500); qla2100_fw_dump()
931 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); qla2100_fw_dump()
933 WRT_REG_WORD(&reg->pcr, 0x2600); qla2100_fw_dump()
934 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); qla2100_fw_dump()
936 WRT_REG_WORD(&reg->pcr, 0x2700); qla2100_fw_dump()
937 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); qla2100_fw_dump()
939 WRT_REG_WORD(&reg->ctrl_status, 0x10); qla2100_fw_dump()
940 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); qla2100_fw_dump()
942 WRT_REG_WORD(&reg->ctrl_status, 0x20); qla2100_fw_dump()
943 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); qla2100_fw_dump()
945 WRT_REG_WORD(&reg->ctrl_status, 0x30); qla2100_fw_dump()
946 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); qla2100_fw_dump()
949 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET); qla2100_fw_dump()
952 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && qla2100_fw_dump()
962 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) { qla2100_fw_dump()
964 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC); qla2100_fw_dump()
966 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 && qla2100_fw_dump()
976 WRT_REG_WORD(&reg->mctr, 0xf1); qla2100_fw_dump()
978 WRT_REG_WORD(&reg->mctr, 0xf2); qla2100_fw_dump()
979 RD_REG_WORD(&reg->mctr); /* PCI Posting. */ qla2100_fw_dump()
982 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC); qla2100_fw_dump()
989 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); qla2100_fw_dump()
994 WRT_MAILBOX_REG(ha, reg, 1, risc_address); qla2100_fw_dump()
995 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT); qla2100_fw_dump()
999 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) { qla2100_fw_dump()
1000 if (RD_REG_WORD(&reg->semaphore) & BIT_0) { qla2100_fw_dump()
1004 mb0 = RD_MAILBOX_REG(ha, reg, 0); qla2100_fw_dump()
1005 mb2 = RD_MAILBOX_REG(ha, reg, 2); qla2100_fw_dump()
1007 WRT_REG_WORD(&reg->semaphore, 0); qla2100_fw_dump()
1008 WRT_REG_WORD(&reg->hccr, qla2100_fw_dump()
1010 RD_REG_WORD(&reg->hccr); qla2100_fw_dump()
1013 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT); qla2100_fw_dump()
1014 RD_REG_WORD(&reg->hccr); qla2100_fw_dump()
1044 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; qla24xx_fw_dump() local
1082 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status)); qla24xx_fw_dump()
1088 qla24xx_pause_risc(reg, ha); qla24xx_fw_dump()
1091 dmp_reg = &reg->flash_addr; qla24xx_fw_dump()
1096 WRT_REG_DWORD(&reg->ictrl, 0); qla24xx_fw_dump()
1097 RD_REG_DWORD(&reg->ictrl); qla24xx_fw_dump()
1100 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); qla24xx_fw_dump()
1101 RD_REG_DWORD(&reg->iobase_addr); qla24xx_fw_dump()
1102 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000); qla24xx_fw_dump()
1103 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla24xx_fw_dump()
1105 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000); qla24xx_fw_dump()
1106 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla24xx_fw_dump()
1108 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000); qla24xx_fw_dump()
1109 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla24xx_fw_dump()
1111 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000); qla24xx_fw_dump()
1112 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla24xx_fw_dump()
1114 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000); qla24xx_fw_dump()
1115 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla24xx_fw_dump()
1117 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000); qla24xx_fw_dump()
1118 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla24xx_fw_dump()
1120 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000); qla24xx_fw_dump()
1121 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla24xx_fw_dump()
1124 mbx_reg = &reg->mailbox0; qla24xx_fw_dump()
1130 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); qla24xx_fw_dump()
1131 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); qla24xx_fw_dump()
1132 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); qla24xx_fw_dump()
1133 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); qla24xx_fw_dump()
1134 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); qla24xx_fw_dump()
1135 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); qla24xx_fw_dump()
1136 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); qla24xx_fw_dump()
1137 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); qla24xx_fw_dump()
1139 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); qla24xx_fw_dump()
1140 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); qla24xx_fw_dump()
1144 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); qla24xx_fw_dump()
1145 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); qla24xx_fw_dump()
1146 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); qla24xx_fw_dump()
1147 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); qla24xx_fw_dump()
1148 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); qla24xx_fw_dump()
1149 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); qla24xx_fw_dump()
1150 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); qla24xx_fw_dump()
1151 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); qla24xx_fw_dump()
1153 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); qla24xx_fw_dump()
1154 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); qla24xx_fw_dump()
1155 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); qla24xx_fw_dump()
1158 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); qla24xx_fw_dump()
1162 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); qla24xx_fw_dump()
1163 dmp_reg = &reg->iobase_q; qla24xx_fw_dump()
1168 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); qla24xx_fw_dump()
1169 dmp_reg = &reg->iobase_q; qla24xx_fw_dump()
1174 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); qla24xx_fw_dump()
1175 dmp_reg = &reg->iobase_q; qla24xx_fw_dump()
1181 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); qla24xx_fw_dump()
1182 qla24xx_read_window(reg, 0x7610, 16, iter_reg); qla24xx_fw_dump()
1185 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); qla24xx_fw_dump()
1186 qla24xx_read_window(reg, 0x7630, 16, iter_reg); qla24xx_fw_dump()
1189 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); qla24xx_fw_dump()
1190 qla24xx_read_window(reg, 0x7650, 16, iter_reg); qla24xx_fw_dump()
1193 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); qla24xx_fw_dump()
1194 qla24xx_read_window(reg, 0x7670, 16, iter_reg); qla24xx_fw_dump()
1197 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); qla24xx_fw_dump()
1198 qla24xx_read_window(reg, 0x7690, 16, iter_reg); qla24xx_fw_dump()
1200 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); qla24xx_fw_dump()
1204 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); qla24xx_fw_dump()
1205 qla24xx_read_window(reg, 0x7710, 16, iter_reg); qla24xx_fw_dump()
1208 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); qla24xx_fw_dump()
1209 qla24xx_read_window(reg, 0x7730, 16, iter_reg); qla24xx_fw_dump()
1213 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); qla24xx_fw_dump()
1214 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); qla24xx_fw_dump()
1215 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); qla24xx_fw_dump()
1216 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); qla24xx_fw_dump()
1217 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); qla24xx_fw_dump()
1218 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); qla24xx_fw_dump()
1219 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); qla24xx_fw_dump()
1220 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); qla24xx_fw_dump()
1224 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); qla24xx_fw_dump()
1225 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); qla24xx_fw_dump()
1226 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); qla24xx_fw_dump()
1227 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); qla24xx_fw_dump()
1228 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); qla24xx_fw_dump()
1229 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); qla24xx_fw_dump()
1230 qla24xx_read_window(reg, 0x3060, 16, iter_reg); qla24xx_fw_dump()
1234 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); qla24xx_fw_dump()
1235 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); qla24xx_fw_dump()
1236 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); qla24xx_fw_dump()
1237 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); qla24xx_fw_dump()
1238 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); qla24xx_fw_dump()
1239 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); qla24xx_fw_dump()
1240 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); qla24xx_fw_dump()
1241 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); qla24xx_fw_dump()
1242 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); qla24xx_fw_dump()
1243 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); qla24xx_fw_dump()
1244 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); qla24xx_fw_dump()
1245 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); qla24xx_fw_dump()
1249 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); qla24xx_fw_dump()
1250 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); qla24xx_fw_dump()
1251 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); qla24xx_fw_dump()
1252 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); qla24xx_fw_dump()
1253 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); qla24xx_fw_dump()
1254 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); qla24xx_fw_dump()
1255 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); qla24xx_fw_dump()
1256 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); qla24xx_fw_dump()
1257 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); qla24xx_fw_dump()
1258 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); qla24xx_fw_dump()
1259 qla24xx_read_window(reg, 0x61B0, 16, iter_reg); qla24xx_fw_dump()
1299 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; qla25xx_fw_dump() local
1334 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status)); qla25xx_fw_dump()
1340 qla24xx_pause_risc(reg, ha); qla25xx_fw_dump()
1344 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); qla25xx_fw_dump()
1345 qla24xx_read_window(reg, 0x7010, 16, iter_reg); qla25xx_fw_dump()
1348 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00); qla25xx_fw_dump()
1349 RD_REG_DWORD(&reg->iobase_addr); qla25xx_fw_dump()
1350 WRT_REG_DWORD(&reg->iobase_window, 0x01); qla25xx_fw_dump()
1351 dmp_reg = &reg->iobase_c4; qla25xx_fw_dump()
1355 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window)); qla25xx_fw_dump()
1357 WRT_REG_DWORD(&reg->iobase_window, 0x00); qla25xx_fw_dump()
1358 RD_REG_DWORD(&reg->iobase_window); qla25xx_fw_dump()
1361 dmp_reg = &reg->flash_addr; qla25xx_fw_dump()
1366 WRT_REG_DWORD(&reg->ictrl, 0); qla25xx_fw_dump()
1367 RD_REG_DWORD(&reg->ictrl); qla25xx_fw_dump()
1370 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); qla25xx_fw_dump()
1371 RD_REG_DWORD(&reg->iobase_addr); qla25xx_fw_dump()
1372 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000); qla25xx_fw_dump()
1373 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla25xx_fw_dump()
1375 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000); qla25xx_fw_dump()
1376 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla25xx_fw_dump()
1378 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000); qla25xx_fw_dump()
1379 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla25xx_fw_dump()
1381 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000); qla25xx_fw_dump()
1382 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla25xx_fw_dump()
1384 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000); qla25xx_fw_dump()
1385 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla25xx_fw_dump()
1387 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000); qla25xx_fw_dump()
1388 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla25xx_fw_dump()
1390 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000); qla25xx_fw_dump()
1391 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla25xx_fw_dump()
1393 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000); qla25xx_fw_dump()
1394 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla25xx_fw_dump()
1396 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000); qla25xx_fw_dump()
1397 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla25xx_fw_dump()
1399 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000); qla25xx_fw_dump()
1400 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla25xx_fw_dump()
1402 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000); qla25xx_fw_dump()
1403 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla25xx_fw_dump()
1406 WRT_REG_DWORD(&reg->iobase_addr, 0x0010); qla25xx_fw_dump()
1407 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window)); qla25xx_fw_dump()
1410 mbx_reg = &reg->mailbox0; qla25xx_fw_dump()
1416 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); qla25xx_fw_dump()
1417 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); qla25xx_fw_dump()
1418 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); qla25xx_fw_dump()
1419 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); qla25xx_fw_dump()
1420 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); qla25xx_fw_dump()
1421 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); qla25xx_fw_dump()
1422 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); qla25xx_fw_dump()
1423 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); qla25xx_fw_dump()
1426 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); qla25xx_fw_dump()
1427 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); qla25xx_fw_dump()
1428 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); qla25xx_fw_dump()
1430 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); qla25xx_fw_dump()
1434 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); qla25xx_fw_dump()
1435 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); qla25xx_fw_dump()
1436 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); qla25xx_fw_dump()
1437 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); qla25xx_fw_dump()
1438 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); qla25xx_fw_dump()
1439 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); qla25xx_fw_dump()
1440 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); qla25xx_fw_dump()
1441 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); qla25xx_fw_dump()
1444 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); qla25xx_fw_dump()
1445 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); qla25xx_fw_dump()
1447 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); qla25xx_fw_dump()
1448 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); qla25xx_fw_dump()
1452 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); qla25xx_fw_dump()
1453 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); qla25xx_fw_dump()
1454 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); qla25xx_fw_dump()
1455 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); qla25xx_fw_dump()
1456 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); qla25xx_fw_dump()
1457 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); qla25xx_fw_dump()
1458 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); qla25xx_fw_dump()
1459 qla24xx_read_window(reg, 0xB070, 16, iter_reg); qla25xx_fw_dump()
1462 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); qla25xx_fw_dump()
1463 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); qla25xx_fw_dump()
1465 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); qla25xx_fw_dump()
1466 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); qla25xx_fw_dump()
1469 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); qla25xx_fw_dump()
1473 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); qla25xx_fw_dump()
1474 dmp_reg = &reg->iobase_q; qla25xx_fw_dump()
1479 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); qla25xx_fw_dump()
1480 dmp_reg = &reg->iobase_q; qla25xx_fw_dump()
1485 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); qla25xx_fw_dump()
1486 dmp_reg = &reg->iobase_q; qla25xx_fw_dump()
1492 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); qla25xx_fw_dump()
1493 qla24xx_read_window(reg, 0x7610, 16, iter_reg); qla25xx_fw_dump()
1496 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); qla25xx_fw_dump()
1497 qla24xx_read_window(reg, 0x7630, 16, iter_reg); qla25xx_fw_dump()
1500 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); qla25xx_fw_dump()
1501 qla24xx_read_window(reg, 0x7650, 16, iter_reg); qla25xx_fw_dump()
1504 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); qla25xx_fw_dump()
1505 qla24xx_read_window(reg, 0x7670, 16, iter_reg); qla25xx_fw_dump()
1508 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); qla25xx_fw_dump()
1509 qla24xx_read_window(reg, 0x7690, 16, iter_reg); qla25xx_fw_dump()
1511 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); qla25xx_fw_dump()
1515 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); qla25xx_fw_dump()
1516 qla24xx_read_window(reg, 0x7710, 16, iter_reg); qla25xx_fw_dump()
1519 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); qla25xx_fw_dump()
1520 qla24xx_read_window(reg, 0x7730, 16, iter_reg); qla25xx_fw_dump()
1524 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); qla25xx_fw_dump()
1525 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); qla25xx_fw_dump()
1526 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); qla25xx_fw_dump()
1527 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); qla25xx_fw_dump()
1528 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); qla25xx_fw_dump()
1529 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); qla25xx_fw_dump()
1530 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); qla25xx_fw_dump()
1531 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); qla25xx_fw_dump()
1535 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); qla25xx_fw_dump()
1536 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); qla25xx_fw_dump()
1537 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); qla25xx_fw_dump()
1538 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); qla25xx_fw_dump()
1539 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); qla25xx_fw_dump()
1540 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); qla25xx_fw_dump()
1541 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); qla25xx_fw_dump()
1542 qla24xx_read_window(reg, 0x3070, 16, iter_reg); qla25xx_fw_dump()
1546 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); qla25xx_fw_dump()
1547 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); qla25xx_fw_dump()
1548 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); qla25xx_fw_dump()
1549 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); qla25xx_fw_dump()
1550 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); qla25xx_fw_dump()
1551 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); qla25xx_fw_dump()
1552 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); qla25xx_fw_dump()
1553 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); qla25xx_fw_dump()
1554 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); qla25xx_fw_dump()
1555 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); qla25xx_fw_dump()
1556 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); qla25xx_fw_dump()
1557 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); qla25xx_fw_dump()
1561 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); qla25xx_fw_dump()
1562 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); qla25xx_fw_dump()
1563 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); qla25xx_fw_dump()
1564 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); qla25xx_fw_dump()
1565 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); qla25xx_fw_dump()
1566 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); qla25xx_fw_dump()
1567 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); qla25xx_fw_dump()
1568 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); qla25xx_fw_dump()
1569 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); qla25xx_fw_dump()
1570 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); qla25xx_fw_dump()
1571 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); qla25xx_fw_dump()
1572 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); qla25xx_fw_dump()
1618 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; qla81xx_fw_dump() local
1652 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status)); qla81xx_fw_dump()
1658 qla24xx_pause_risc(reg, ha); qla81xx_fw_dump()
1662 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); qla81xx_fw_dump()
1663 qla24xx_read_window(reg, 0x7010, 16, iter_reg); qla81xx_fw_dump()
1666 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00); qla81xx_fw_dump()
1667 RD_REG_DWORD(&reg->iobase_addr); qla81xx_fw_dump()
1668 WRT_REG_DWORD(&reg->iobase_window, 0x01); qla81xx_fw_dump()
1669 dmp_reg = &reg->iobase_c4; qla81xx_fw_dump()
1673 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window)); qla81xx_fw_dump()
1675 WRT_REG_DWORD(&reg->iobase_window, 0x00); qla81xx_fw_dump()
1676 RD_REG_DWORD(&reg->iobase_window); qla81xx_fw_dump()
1679 dmp_reg = &reg->flash_addr; qla81xx_fw_dump()
1684 WRT_REG_DWORD(&reg->ictrl, 0); qla81xx_fw_dump()
1685 RD_REG_DWORD(&reg->ictrl); qla81xx_fw_dump()
1688 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); qla81xx_fw_dump()
1689 RD_REG_DWORD(&reg->iobase_addr); qla81xx_fw_dump()
1690 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000); qla81xx_fw_dump()
1691 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla81xx_fw_dump()
1693 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000); qla81xx_fw_dump()
1694 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla81xx_fw_dump()
1696 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000); qla81xx_fw_dump()
1697 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla81xx_fw_dump()
1699 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000); qla81xx_fw_dump()
1700 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla81xx_fw_dump()
1702 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000); qla81xx_fw_dump()
1703 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla81xx_fw_dump()
1705 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000); qla81xx_fw_dump()
1706 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla81xx_fw_dump()
1708 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000); qla81xx_fw_dump()
1709 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla81xx_fw_dump()
1711 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000); qla81xx_fw_dump()
1712 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla81xx_fw_dump()
1714 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000); qla81xx_fw_dump()
1715 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla81xx_fw_dump()
1717 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000); qla81xx_fw_dump()
1718 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla81xx_fw_dump()
1720 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000); qla81xx_fw_dump()
1721 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla81xx_fw_dump()
1724 WRT_REG_DWORD(&reg->iobase_addr, 0x0010); qla81xx_fw_dump()
1725 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window)); qla81xx_fw_dump()
1728 mbx_reg = &reg->mailbox0; qla81xx_fw_dump()
1734 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); qla81xx_fw_dump()
1735 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); qla81xx_fw_dump()
1736 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); qla81xx_fw_dump()
1737 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); qla81xx_fw_dump()
1738 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); qla81xx_fw_dump()
1739 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); qla81xx_fw_dump()
1740 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); qla81xx_fw_dump()
1741 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); qla81xx_fw_dump()
1744 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); qla81xx_fw_dump()
1745 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); qla81xx_fw_dump()
1746 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); qla81xx_fw_dump()
1748 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); qla81xx_fw_dump()
1752 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); qla81xx_fw_dump()
1753 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); qla81xx_fw_dump()
1754 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); qla81xx_fw_dump()
1755 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); qla81xx_fw_dump()
1756 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); qla81xx_fw_dump()
1757 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); qla81xx_fw_dump()
1758 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); qla81xx_fw_dump()
1759 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); qla81xx_fw_dump()
1762 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); qla81xx_fw_dump()
1763 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); qla81xx_fw_dump()
1765 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); qla81xx_fw_dump()
1766 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); qla81xx_fw_dump()
1770 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); qla81xx_fw_dump()
1771 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); qla81xx_fw_dump()
1772 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); qla81xx_fw_dump()
1773 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); qla81xx_fw_dump()
1774 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); qla81xx_fw_dump()
1775 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); qla81xx_fw_dump()
1776 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); qla81xx_fw_dump()
1777 qla24xx_read_window(reg, 0xB070, 16, iter_reg); qla81xx_fw_dump()
1780 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); qla81xx_fw_dump()
1781 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); qla81xx_fw_dump()
1783 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); qla81xx_fw_dump()
1784 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); qla81xx_fw_dump()
1787 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); qla81xx_fw_dump()
1791 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); qla81xx_fw_dump()
1792 dmp_reg = &reg->iobase_q; qla81xx_fw_dump()
1797 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); qla81xx_fw_dump()
1798 dmp_reg = &reg->iobase_q; qla81xx_fw_dump()
1803 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); qla81xx_fw_dump()
1804 dmp_reg = &reg->iobase_q; qla81xx_fw_dump()
1810 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); qla81xx_fw_dump()
1811 qla24xx_read_window(reg, 0x7610, 16, iter_reg); qla81xx_fw_dump()
1814 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); qla81xx_fw_dump()
1815 qla24xx_read_window(reg, 0x7630, 16, iter_reg); qla81xx_fw_dump()
1818 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); qla81xx_fw_dump()
1819 qla24xx_read_window(reg, 0x7650, 16, iter_reg); qla81xx_fw_dump()
1822 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); qla81xx_fw_dump()
1823 qla24xx_read_window(reg, 0x7670, 16, iter_reg); qla81xx_fw_dump()
1826 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); qla81xx_fw_dump()
1827 qla24xx_read_window(reg, 0x7690, 16, iter_reg); qla81xx_fw_dump()
1829 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); qla81xx_fw_dump()
1833 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); qla81xx_fw_dump()
1834 qla24xx_read_window(reg, 0x7710, 16, iter_reg); qla81xx_fw_dump()
1837 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); qla81xx_fw_dump()
1838 qla24xx_read_window(reg, 0x7730, 16, iter_reg); qla81xx_fw_dump()
1842 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); qla81xx_fw_dump()
1843 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); qla81xx_fw_dump()
1844 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); qla81xx_fw_dump()
1845 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); qla81xx_fw_dump()
1846 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); qla81xx_fw_dump()
1847 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); qla81xx_fw_dump()
1848 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); qla81xx_fw_dump()
1849 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); qla81xx_fw_dump()
1853 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); qla81xx_fw_dump()
1854 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); qla81xx_fw_dump()
1855 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); qla81xx_fw_dump()
1856 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); qla81xx_fw_dump()
1857 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); qla81xx_fw_dump()
1858 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); qla81xx_fw_dump()
1859 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); qla81xx_fw_dump()
1860 qla24xx_read_window(reg, 0x3070, 16, iter_reg); qla81xx_fw_dump()
1864 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); qla81xx_fw_dump()
1865 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); qla81xx_fw_dump()
1866 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); qla81xx_fw_dump()
1867 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); qla81xx_fw_dump()
1868 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); qla81xx_fw_dump()
1869 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); qla81xx_fw_dump()
1870 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); qla81xx_fw_dump()
1871 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); qla81xx_fw_dump()
1872 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); qla81xx_fw_dump()
1873 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); qla81xx_fw_dump()
1874 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); qla81xx_fw_dump()
1875 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); qla81xx_fw_dump()
1876 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); qla81xx_fw_dump()
1877 qla24xx_read_window(reg, 0x40D0, 16, iter_reg); qla81xx_fw_dump()
1881 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); qla81xx_fw_dump()
1882 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); qla81xx_fw_dump()
1883 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); qla81xx_fw_dump()
1884 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); qla81xx_fw_dump()
1885 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); qla81xx_fw_dump()
1886 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); qla81xx_fw_dump()
1887 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); qla81xx_fw_dump()
1888 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); qla81xx_fw_dump()
1889 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); qla81xx_fw_dump()
1890 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); qla81xx_fw_dump()
1891 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); qla81xx_fw_dump()
1892 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); qla81xx_fw_dump()
1893 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); qla81xx_fw_dump()
1939 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; qla83xx_fw_dump() local
1972 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status)); qla83xx_fw_dump()
1978 qla24xx_pause_risc(reg, ha); qla83xx_fw_dump()
1980 WRT_REG_DWORD(&reg->iobase_addr, 0x6000); qla83xx_fw_dump()
1981 dmp_reg = &reg->iobase_window; qla83xx_fw_dump()
1985 dmp_reg = &reg->unused_4_1[0]; qla83xx_fw_dump()
1989 WRT_REG_DWORD(&reg->iobase_addr, 0x6010); qla83xx_fw_dump()
1990 dmp_reg = &reg->unused_4_1[2]; qla83xx_fw_dump()
1995 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); qla83xx_fw_dump()
1996 RD_REG_DWORD(&reg->iobase_addr); qla83xx_fw_dump()
1997 WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */ qla83xx_fw_dump()
2001 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); qla83xx_fw_dump()
2002 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg); qla83xx_fw_dump()
2003 qla24xx_read_window(reg, 0x7040, 16, iter_reg); qla83xx_fw_dump()
2006 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00); qla83xx_fw_dump()
2007 RD_REG_DWORD(&reg->iobase_addr); qla83xx_fw_dump()
2008 WRT_REG_DWORD(&reg->iobase_window, 0x01); qla83xx_fw_dump()
2009 dmp_reg = &reg->iobase_c4; qla83xx_fw_dump()
2013 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window)); qla83xx_fw_dump()
2015 WRT_REG_DWORD(&reg->iobase_window, 0x00); qla83xx_fw_dump()
2016 RD_REG_DWORD(&reg->iobase_window); qla83xx_fw_dump()
2019 dmp_reg = &reg->flash_addr; qla83xx_fw_dump()
2024 WRT_REG_DWORD(&reg->ictrl, 0); qla83xx_fw_dump()
2025 RD_REG_DWORD(&reg->ictrl); qla83xx_fw_dump()
2028 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); qla83xx_fw_dump()
2029 RD_REG_DWORD(&reg->iobase_addr); qla83xx_fw_dump()
2030 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000); qla83xx_fw_dump()
2031 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla83xx_fw_dump()
2033 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000); qla83xx_fw_dump()
2034 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla83xx_fw_dump()
2036 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000); qla83xx_fw_dump()
2037 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla83xx_fw_dump()
2039 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000); qla83xx_fw_dump()
2040 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla83xx_fw_dump()
2042 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000); qla83xx_fw_dump()
2043 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla83xx_fw_dump()
2045 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000); qla83xx_fw_dump()
2046 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla83xx_fw_dump()
2048 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000); qla83xx_fw_dump()
2049 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla83xx_fw_dump()
2051 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000); qla83xx_fw_dump()
2052 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla83xx_fw_dump()
2054 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000); qla83xx_fw_dump()
2055 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla83xx_fw_dump()
2057 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000); qla83xx_fw_dump()
2058 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla83xx_fw_dump()
2060 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000); qla83xx_fw_dump()
2061 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); qla83xx_fw_dump()
2064 WRT_REG_DWORD(&reg->iobase_addr, 0x0010); qla83xx_fw_dump()
2065 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window)); qla83xx_fw_dump()
2068 mbx_reg = &reg->mailbox0; qla83xx_fw_dump()
2074 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg); qla83xx_fw_dump()
2075 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg); qla83xx_fw_dump()
2076 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg); qla83xx_fw_dump()
2077 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg); qla83xx_fw_dump()
2078 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg); qla83xx_fw_dump()
2079 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg); qla83xx_fw_dump()
2080 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg); qla83xx_fw_dump()
2081 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg); qla83xx_fw_dump()
2082 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); qla83xx_fw_dump()
2083 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); qla83xx_fw_dump()
2084 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); qla83xx_fw_dump()
2085 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); qla83xx_fw_dump()
2086 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); qla83xx_fw_dump()
2087 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); qla83xx_fw_dump()
2088 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); qla83xx_fw_dump()
2089 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); qla83xx_fw_dump()
2092 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); qla83xx_fw_dump()
2093 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); qla83xx_fw_dump()
2094 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); qla83xx_fw_dump()
2096 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); qla83xx_fw_dump()
2098 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg); qla83xx_fw_dump()
2102 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg); qla83xx_fw_dump()
2103 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg); qla83xx_fw_dump()
2104 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg); qla83xx_fw_dump()
2105 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg); qla83xx_fw_dump()
2106 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg); qla83xx_fw_dump()
2107 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg); qla83xx_fw_dump()
2108 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg); qla83xx_fw_dump()
2109 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg); qla83xx_fw_dump()
2110 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); qla83xx_fw_dump()
2111 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); qla83xx_fw_dump()
2112 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); qla83xx_fw_dump()
2113 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); qla83xx_fw_dump()
2114 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); qla83xx_fw_dump()
2115 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); qla83xx_fw_dump()
2116 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); qla83xx_fw_dump()
2117 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); qla83xx_fw_dump()
2120 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); qla83xx_fw_dump()
2121 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); qla83xx_fw_dump()
2123 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); qla83xx_fw_dump()
2124 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); qla83xx_fw_dump()
2125 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg); qla83xx_fw_dump()
2129 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); qla83xx_fw_dump()
2130 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); qla83xx_fw_dump()
2131 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); qla83xx_fw_dump()
2132 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); qla83xx_fw_dump()
2133 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); qla83xx_fw_dump()
2134 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); qla83xx_fw_dump()
2135 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); qla83xx_fw_dump()
2136 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg); qla83xx_fw_dump()
2137 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg); qla83xx_fw_dump()
2138 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg); qla83xx_fw_dump()
2139 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg); qla83xx_fw_dump()
2140 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg); qla83xx_fw_dump()
2141 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg); qla83xx_fw_dump()
2142 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg); qla83xx_fw_dump()
2143 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg); qla83xx_fw_dump()
2144 qla24xx_read_window(reg, 0xB170, 16, iter_reg); qla83xx_fw_dump()
2147 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); qla83xx_fw_dump()
2148 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); qla83xx_fw_dump()
2150 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); qla83xx_fw_dump()
2151 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); qla83xx_fw_dump()
2152 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg); qla83xx_fw_dump()
2156 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg); qla83xx_fw_dump()
2157 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg); qla83xx_fw_dump()
2158 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg); qla83xx_fw_dump()
2159 qla24xx_read_window(reg, 0x71F0, 16, iter_reg); qla83xx_fw_dump()
2163 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); qla83xx_fw_dump()
2164 dmp_reg = &reg->iobase_q; qla83xx_fw_dump()
2169 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); qla83xx_fw_dump()
2170 dmp_reg = &reg->iobase_q; qla83xx_fw_dump()
2175 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); qla83xx_fw_dump()
2176 dmp_reg = &reg->iobase_q; qla83xx_fw_dump()
2182 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); qla83xx_fw_dump()
2183 qla24xx_read_window(reg, 0x7610, 16, iter_reg); qla83xx_fw_dump()
2186 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); qla83xx_fw_dump()
2187 qla24xx_read_window(reg, 0x7630, 16, iter_reg); qla83xx_fw_dump()
2190 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); qla83xx_fw_dump()
2191 qla24xx_read_window(reg, 0x7650, 16, iter_reg); qla83xx_fw_dump()
2194 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); qla83xx_fw_dump()
2195 qla24xx_read_window(reg, 0x7670, 16, iter_reg); qla83xx_fw_dump()
2198 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); qla83xx_fw_dump()
2199 qla24xx_read_window(reg, 0x7690, 16, iter_reg); qla83xx_fw_dump()
2201 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); qla83xx_fw_dump()
2205 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); qla83xx_fw_dump()
2206 qla24xx_read_window(reg, 0x7710, 16, iter_reg); qla83xx_fw_dump()
2209 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); qla83xx_fw_dump()
2210 qla24xx_read_window(reg, 0x7730, 16, iter_reg); qla83xx_fw_dump()
2214 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); qla83xx_fw_dump()
2215 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); qla83xx_fw_dump()
2216 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); qla83xx_fw_dump()
2217 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); qla83xx_fw_dump()
2218 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); qla83xx_fw_dump()
2219 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); qla83xx_fw_dump()
2220 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); qla83xx_fw_dump()
2221 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); qla83xx_fw_dump()
2225 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); qla83xx_fw_dump()
2226 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); qla83xx_fw_dump()
2227 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); qla83xx_fw_dump()
2228 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); qla83xx_fw_dump()
2229 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); qla83xx_fw_dump()
2230 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); qla83xx_fw_dump()
2231 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); qla83xx_fw_dump()
2232 qla24xx_read_window(reg, 0x3070, 16, iter_reg); qla83xx_fw_dump()
2236 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); qla83xx_fw_dump()
2237 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); qla83xx_fw_dump()
2238 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); qla83xx_fw_dump()
2239 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); qla83xx_fw_dump()
2240 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); qla83xx_fw_dump()
2241 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); qla83xx_fw_dump()
2242 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); qla83xx_fw_dump()
2243 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); qla83xx_fw_dump()
2244 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); qla83xx_fw_dump()
2245 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); qla83xx_fw_dump()
2246 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); qla83xx_fw_dump()
2247 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); qla83xx_fw_dump()
2248 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); qla83xx_fw_dump()
2249 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg); qla83xx_fw_dump()
2250 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg); qla83xx_fw_dump()
2251 qla24xx_read_window(reg, 0x40F0, 16, iter_reg); qla83xx_fw_dump()
2255 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg); qla83xx_fw_dump()
2256 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg); qla83xx_fw_dump()
2257 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg); qla83xx_fw_dump()
2258 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg); qla83xx_fw_dump()
2259 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg); qla83xx_fw_dump()
2260 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg); qla83xx_fw_dump()
2261 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg); qla83xx_fw_dump()
2262 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg); qla83xx_fw_dump()
2263 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg); qla83xx_fw_dump()
2264 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg); qla83xx_fw_dump()
2265 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg); qla83xx_fw_dump()
2266 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg); qla83xx_fw_dump()
2267 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg); qla83xx_fw_dump()
2268 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg); qla83xx_fw_dump()
2269 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg); qla83xx_fw_dump()
2270 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg); qla83xx_fw_dump()
2274 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg); qla83xx_fw_dump()
2275 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg); qla83xx_fw_dump()
2276 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg); qla83xx_fw_dump()
2277 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg); qla83xx_fw_dump()
2278 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg); qla83xx_fw_dump()
2279 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg); qla83xx_fw_dump()
2280 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg); qla83xx_fw_dump()
2281 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg); qla83xx_fw_dump()
2282 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg); qla83xx_fw_dump()
2283 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg); qla83xx_fw_dump()
2284 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg); qla83xx_fw_dump()
2285 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg); qla83xx_fw_dump()
2286 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg); qla83xx_fw_dump()
2287 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg); qla83xx_fw_dump()
2288 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg); qla83xx_fw_dump()
2289 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg); qla83xx_fw_dump()
2293 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg); qla83xx_fw_dump()
2294 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg); qla83xx_fw_dump()
2295 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg); qla83xx_fw_dump()
2296 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg); qla83xx_fw_dump()
2297 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg); qla83xx_fw_dump()
2298 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg); qla83xx_fw_dump()
2299 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg); qla83xx_fw_dump()
2300 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg); qla83xx_fw_dump()
2301 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg); qla83xx_fw_dump()
2302 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg); qla83xx_fw_dump()
2303 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg); qla83xx_fw_dump()
2304 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg); qla83xx_fw_dump()
2305 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg); qla83xx_fw_dump()
2306 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg); qla83xx_fw_dump()
2307 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg); qla83xx_fw_dump()
2308 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg); qla83xx_fw_dump()
2312 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg); qla83xx_fw_dump()
2313 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg); qla83xx_fw_dump()
2314 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg); qla83xx_fw_dump()
2315 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg); qla83xx_fw_dump()
2316 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg); qla83xx_fw_dump()
2317 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg); qla83xx_fw_dump()
2318 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg); qla83xx_fw_dump()
2319 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg); qla83xx_fw_dump()
2320 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg); qla83xx_fw_dump()
2321 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg); qla83xx_fw_dump()
2322 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg); qla83xx_fw_dump()
2323 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg); qla83xx_fw_dump()
2324 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg); qla83xx_fw_dump()
2325 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg); qla83xx_fw_dump()
2326 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg); qla83xx_fw_dump()
2327 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg); qla83xx_fw_dump()
2330 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg); qla83xx_fw_dump()
2331 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg); qla83xx_fw_dump()
2332 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg); qla83xx_fw_dump()
2333 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg); qla83xx_fw_dump()
2334 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg); qla83xx_fw_dump()
2335 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg); qla83xx_fw_dump()
2336 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg); qla83xx_fw_dump()
2337 qla24xx_read_window(reg, 0x70F0, 16, iter_reg); qla83xx_fw_dump()
2340 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg); qla83xx_fw_dump()
2344 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); qla83xx_fw_dump()
2345 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); qla83xx_fw_dump()
2346 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); qla83xx_fw_dump()
2347 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); qla83xx_fw_dump()
2348 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); qla83xx_fw_dump()
2349 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg); qla83xx_fw_dump()
2350 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg); qla83xx_fw_dump()
2351 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); qla83xx_fw_dump()
2352 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); qla83xx_fw_dump()
2353 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); qla83xx_fw_dump()
2354 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); qla83xx_fw_dump()
2355 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); qla83xx_fw_dump()
2356 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); qla83xx_fw_dump()
2357 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); qla83xx_fw_dump()
2358 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg); qla83xx_fw_dump()
2359 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg); qla83xx_fw_dump()
2360 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg); qla83xx_fw_dump()
2361 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg); qla83xx_fw_dump()
2362 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg); qla83xx_fw_dump()
2363 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg); qla83xx_fw_dump()
2364 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg); qla83xx_fw_dump()
2365 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg); qla83xx_fw_dump()
2366 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg); qla83xx_fw_dump()
2367 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg); qla83xx_fw_dump()
2368 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg); qla83xx_fw_dump()
2369 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg); qla83xx_fw_dump()
2370 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); qla83xx_fw_dump()
2384 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET); qla83xx_fw_dump()
2385 RD_REG_DWORD(&reg->hccr); qla83xx_fw_dump()
2387 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE); qla83xx_fw_dump()
2388 RD_REG_DWORD(&reg->hccr); qla83xx_fw_dump()
2390 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET); qla83xx_fw_dump()
2391 RD_REG_DWORD(&reg->hccr); qla83xx_fw_dump()
2393 for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--) qla83xx_fw_dump()
2647 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; ql_dump_regs() local
2660 mbx_reg = MAILBOX_REG(ha, reg, 0); ql_dump_regs()
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Dni_labpc_regs.h11 #define STAT1_REG 0x00 /* R: Status 1 reg */
18 #define CMD1_REG 0x00 /* W: Command 1 reg */
23 #define CMD2_REG 0x01 /* W: Command 2 reg */
31 #define CMD3_REG 0x02 /* W: Command 3 reg */
38 #define ADC_START_CONVERT_REG 0x03 /* W: Start Convert reg */
39 #define DAC_LSB_REG(x) (0x04 + 2 * (x)) /* W: DAC0/1 LSB reg */
40 #define DAC_MSB_REG(x) (0x05 + 2 * (x)) /* W: DAC0/1 MSB reg */
41 #define ADC_FIFO_CLEAR_REG 0x08 /* W: A/D FIFO Clear reg */
42 #define ADC_FIFO_REG 0x0a /* R: A/D FIFO reg */
43 #define DMATC_CLEAR_REG 0x0a /* W: DMA Interrupt Clear reg */
44 #define TIMER_CLEAR_REG 0x0c /* W: Timer Interrupt Clear reg */
45 #define CMD6_REG 0x0e /* W: Command 6 reg */
52 #define CMD4_REG 0x0f /* W: Command 3 reg */
58 #define DIO_BASE_REG 0x10 /* R/W: 8255 DIO base reg */
59 #define COUNTER_A_BASE_REG 0x14 /* R/W: 8253 Counter A base reg */
60 #define COUNTER_B_BASE_REG 0x18 /* R/W: 8253 Counter B base reg */
61 #define CMD5_REG 0x1c /* W: Command 5 reg */
68 #define STAT2_REG 0x1d /* R: Status 2 reg */
72 #define INTERVAL_COUNT_REG 0x1e /* W: Interval Counter Data reg */
73 #define INTERVAL_STROBE_REG 0x1f /* W: Interval Counter Strobe reg */
/linux-4.1.27/drivers/video/fbdev/riva/
H A Dnvreg.h44 #define DEVICE_ACCESS(device,reg) \
45 nvCONTROL[(NV_##device##_##reg)/4]
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value)
48 #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg)
49 #define DEVICE_PRINT(device,reg) \
50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value)
57 #define PDAC_Read(reg) DEVICE_READ(PDAC,reg)
58 #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg)
63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value)
64 #define PFB_Read(reg) DEVICE_READ(PFB,reg)
65 #define PFB_Print(reg) DEVICE_PRINT(PFB,reg)
70 #define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value)
71 #define PRM_Read(reg) DEVICE_READ(PRM,reg)
72 #define PRM_Print(reg) DEVICE_PRINT(PRM,reg)
77 #define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value)
78 #define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg)
79 #define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg)
84 #define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value)
85 #define PDMA_Read(reg) DEVICE_READ(PDMA,reg)
86 #define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg)
91 #define PTIMER_Write(reg,value) DEVICE_WRITE(PTIMER,reg,value)
92 #define PTIMER_Read(reg) DEVICE_READ(PTIMER,reg)
93 #define PTIMER_Print(reg) DEVICE_PRINT(PTIMER,reg)
98 #define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value)
99 #define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg)
100 #define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg)
105 #define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value)
106 #define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg)
107 #define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg)
112 #define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value)
113 #define PRAM_Read(reg) DEVICE_READ(PRAM,reg)
114 #define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg)
119 #define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value)
120 #define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg)
121 #define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg)
126 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
127 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
128 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
133 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
134 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
135 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
141 #define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value)
142 #define PBUS_Read(reg) DEVICE_READ(PBUS,reg)
143 #define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg)
149 #define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value)
150 #define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg)
151 #define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg)
157 #define PDAC_ReadExt(reg) \
158 ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
159 (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
162 #define PDAC_WriteExt(reg,value)\
163 ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
164 (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
/linux-4.1.27/arch/m68k/include/asm/
H A Dm5206sim.h24 #define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
25 #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
26 #define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
27 #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
28 #define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
29 #define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
30 #define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
31 #define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
32 #define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */
33 #define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */
34 #define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */
35 #define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */
36 #define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */
37 #define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */
39 #define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */
40 #define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */
52 #define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
53 #define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
54 #define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
55 #define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
56 #define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
57 #define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
58 #define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
59 #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
61 #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
62 #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
63 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
64 #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
65 #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
66 #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
67 #define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
68 #define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */
69 #define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
70 #define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */
71 #define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */
72 #define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
73 #define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */
74 #define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */
75 #define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
76 #define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */
77 #define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */
78 #define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */
79 #define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */
80 #define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */
81 #define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */
82 #define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */
83 #define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */
84 #define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */
H A Dm5407sim.h37 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
38 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
39 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
40 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
41 #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
42 #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
43 #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
44 #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
45 #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
46 #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
47 #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
48 #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
50 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
51 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
52 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
53 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
54 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
55 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
57 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
58 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
59 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
60 #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
61 #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
62 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
63 #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
64 #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
65 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
66 #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
67 #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
68 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
69 #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
70 #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
71 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
72 #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
73 #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
74 #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
H A Dm5307sim.h26 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
37 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
38 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
39 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
40 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
41 #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
42 #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
43 #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
44 #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
45 #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
46 #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
47 #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
48 #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
50 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
51 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
52 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
53 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
54 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
55 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
60 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */
61 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
62 #define MCFSIM_CSMR3 (MCF_MBAR + 0xaa) /* CS 3 Mask reg */
63 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
64 #define MCFSIM_CSMR4 (MCF_MBAR + 0xb6) /* CS 4 Mask reg */
65 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
66 #define MCFSIM_CSMR5 (MCF_MBAR + 0xc2) /* CS 5 Mask reg */
67 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
68 #define MCFSIM_CSMR6 (MCF_MBAR + 0xce) /* CS 6 Mask reg */
69 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
70 #define MCFSIM_CSMR7 (MCF_MBAR + 0xda) /* CS 7 Mask reg */
71 #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
73 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
74 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
75 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
76 #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
77 #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
78 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
79 #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
80 #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
81 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
82 #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
83 #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
84 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
85 #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
86 #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
87 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
88 #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
89 #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
90 #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
H A Dm68360_quicc.h95 volatile unsigned long sim_mcr; /* module configuration reg */
98 volatile unsigned char sim_avr; /* auto vector reg */
99 volatile unsigned char sim_rsr; /* reset status reg */
111 volatile unsigned short sim_picr; /* periodic interrupt control reg */
113 volatile unsigned short sim_pitr; /* periodic interrupt timing reg */
156 volatile unsigned short idma_iccr; /* channel configuration reg*/
158 volatile unsigned short idma1_cmr; /* dma mode reg */
162 volatile unsigned long idma1_bcr; /* dma byte count reg */
163 volatile unsigned char idma1_fcr; /* function code reg */
165 volatile unsigned char idma1_cmar; /* channel mask reg */
167 volatile unsigned char idma1_csr; /* channel status reg */
170 volatile unsigned char sdma_sdsr; /* status reg */
172 volatile unsigned short sdma_sdcr; /* configuration reg */
173 volatile unsigned long sdma_sdar; /* address reg */
176 volatile unsigned short idma2_cmr; /* dma mode reg */
179 volatile unsigned long idma2_bcr; /* dma byte count reg */
180 volatile unsigned char idma2_fcr; /* function code reg */
182 volatile unsigned char idma2_cmar; /* channel mask reg */
184 volatile unsigned char idma2_csr; /* channel status reg */
187 volatile unsigned long intr_cicr; /* CP interrupt configuration reg*/
188 volatile unsigned long intr_cipr; /* CP interrupt pending reg */
189 volatile unsigned long intr_cimr; /* CP interrupt mask reg */
190 volatile unsigned long intr_cisr; /* CP interrupt in service reg*/
192 volatile unsigned short pio_padir; /* port A data direction reg */
193 volatile unsigned short pio_papar; /* port A pin assignment reg */
194 volatile unsigned short pio_paodr; /* port A open drain reg */
197 volatile unsigned short pio_pcdir; /* port C data direction reg*/
198 volatile unsigned short pio_pcpar; /* port C pin assignment reg*/
201 volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */
204 volatile unsigned short timer_tgcr; /* timer global configuration reg */
206 volatile unsigned short timer_tmr1; /* timer 1 mode reg */
207 volatile unsigned short timer_tmr2; /* timer 2 mode reg */
208 volatile unsigned short timer_trr1; /* timer 1 referance reg */
209 volatile unsigned short timer_trr2; /* timer 2 referance reg */
210 volatile unsigned short timer_tcr1; /* timer 1 capture reg */
211 volatile unsigned short timer_tcr2; /* timer 2 capture reg */
212 volatile unsigned short timer_tcn1; /* timer 1 counter reg */
213 volatile unsigned short timer_tcn2; /* timer 2 counter reg */
214 volatile unsigned short timer_tmr3; /* timer 3 mode reg */
215 volatile unsigned short timer_tmr4; /* timer 4 mode reg */
216 volatile unsigned short timer_trr3; /* timer 3 referance reg */
217 volatile unsigned short timer_trr4; /* timer 4 referance reg */
218 volatile unsigned short timer_tcr3; /* timer 3 capture reg */
219 volatile unsigned short timer_tcr4; /* timer 4 capture reg */
220 volatile unsigned short timer_tcn3; /* timer 3 counter reg */
221 volatile unsigned short timer_tcn4; /* timer 4 counter reg */
222 volatile unsigned short timer_ter1; /* timer 1 event reg */
223 volatile unsigned short timer_ter2; /* timer 2 event reg */
224 volatile unsigned short timer_ter3; /* timer 3 event reg */
225 volatile unsigned short timer_ter4; /* timer 4 event reg */
230 volatile unsigned short cp_rccr; /* main configuration reg */
232 volatile unsigned char cp_rmds; /* development support status reg */
233 volatile unsigned long cp_rmdr; /* development support control reg */
239 volatile unsigned short cp_rter; /* RISC timers event reg */
241 volatile unsigned short cp_rtmr; /* RISC timers mask reg */
301 } scc_gsmr; /* SCC general mode reg */
302 volatile unsigned short scc_psmr; /* protocol specific mode reg */
305 volatile unsigned short scc_dsr; /* SCC data sync reg */
306 volatile unsigned short scc_scce; /* SCC event reg */
308 volatile unsigned short scc_sccm; /* SCC mask reg */
310 volatile unsigned char scc_sccs; /* SCC status reg */
316 volatile unsigned short smc_smcmr; /* SMC mode reg */
318 volatile unsigned char smc_smce; /* SMC event reg */
320 volatile unsigned char smc_smcm; /* SMC mask reg */
324 volatile unsigned short spi_spmode; /* SPI mode reg */
326 volatile unsigned char spi_spie; /* SPI event reg */
328 volatile unsigned char spi_spim; /* SPI mask reg */
330 volatile unsigned char spi_spcom; /* SPI command reg */
333 volatile unsigned short pip_pipc; /* pip configuration reg */
335 volatile unsigned short pip_ptpr; /* pip timing parameters reg */
336 volatile unsigned long pip_pbdir; /* port b data direction reg */
337 volatile unsigned long pip_pbpar; /* port b pin assignment reg */
338 volatile unsigned long pip_pbodr; /* port b open drain reg */
339 volatile unsigned long pip_pbdat; /* port b data reg */
/linux-4.1.27/drivers/net/ethernet/intel/e1000/
H A De1000_osdep.h54 #define er32(reg) \
56 ? E1000_##reg : E1000_82542_##reg)))
58 #define ew32(reg, value) \
60 ? E1000_##reg : E1000_82542_##reg))))
62 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
64 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
67 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
69 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
75 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
77 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
80 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
82 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
85 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
87 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
90 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
92 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
97 #define E1000_WRITE_ICH_FLASH_REG(a, reg, value) ( \
98 writel((value), ((a)->flash_address + reg)))
100 #define E1000_READ_ICH_FLASH_REG(a, reg) ( \
101 readl((a)->flash_address + reg))
103 #define E1000_WRITE_ICH_FLASH_REG16(a, reg, value) ( \
104 writew((value), ((a)->flash_address + reg)))
106 #define E1000_READ_ICH_FLASH_REG16(a, reg) ( \
107 readw((a)->flash_address + reg))
/linux-4.1.27/arch/x86/include/asm/
H A Dprocessor-cyrix.h20 static inline u8 getCx86(u8 reg) getCx86() argument
22 outb(reg, 0x22); getCx86()
26 static inline void setCx86(u8 reg, u8 data) setCx86() argument
28 outb(reg, 0x22); setCx86()
32 #define getCx86_old(reg) ({ outb((reg), 0x22); inb(0x23); })
34 #define setCx86_old(reg, data) do { \
35 outb((reg), 0x22); \
H A Ddwarf2.h84 .macro pushq_cfi reg
85 pushq \reg
89 .macro pushq_cfi_reg reg
90 pushq %\reg
92 CFI_REL_OFFSET \reg, 0
95 .macro popq_cfi reg
96 popq \reg
100 .macro popq_cfi_reg reg
101 popq %\reg
103 CFI_RESTORE \reg
116 .macro movq_cfi reg offset=0
117 movq %\reg, \offset(%rsp)
118 CFI_REL_OFFSET \reg, \offset variable
121 .macro movq_cfi_restore offset reg
122 movq \offset(%rsp), %\reg
123 CFI_RESTORE \reg
126 .macro pushl_cfi reg
127 pushl \reg
131 .macro pushl_cfi_reg reg
132 pushl %\reg
134 CFI_REL_OFFSET \reg, 0
137 .macro popl_cfi reg
138 popl \reg
142 .macro popl_cfi_reg reg
143 popl %\reg
145 CFI_RESTORE \reg
158 .macro movl_cfi reg offset=0
159 movl %\reg, \offset(%esp)
160 CFI_REL_OFFSET \reg, \offset
163 .macro movl_cfi_restore offset reg
164 movl \offset(%esp), %\reg
165 CFI_RESTORE \reg
H A Dxor_avx.h43 #define BLOCK(i, reg) \ xor_avx_2()
45 asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p1[i / sizeof(*p1)])); \ xor_avx_2()
46 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ xor_avx_2()
48 asm volatile("vmovdqa %%ymm" #reg ", %0" : \ xor_avx_2()
70 #define BLOCK(i, reg) \ xor_avx_3()
72 asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p2[i / sizeof(*p2)])); \ xor_avx_3()
73 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ xor_avx_3()
75 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ xor_avx_3()
77 asm volatile("vmovdqa %%ymm" #reg ", %0" : \ xor_avx_3()
100 #define BLOCK(i, reg) \ xor_avx_4()
102 asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p3[i / sizeof(*p3)])); \ xor_avx_4()
103 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ xor_avx_4()
105 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ xor_avx_4()
107 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ xor_avx_4()
109 asm volatile("vmovdqa %%ymm" #reg ", %0" : \ xor_avx_4()
133 #define BLOCK(i, reg) \ xor_avx_5()
135 asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p4[i / sizeof(*p4)])); \ xor_avx_5()
136 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ xor_avx_5()
138 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ xor_avx_5()
140 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ xor_avx_5()
142 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ xor_avx_5()
144 asm volatile("vmovdqa %%ymm" #reg ", %0" : \ xor_avx_5()
H A Dintel_mid_vrtc.h4 extern unsigned char vrtc_cmos_read(unsigned char reg);
5 extern void vrtc_cmos_write(unsigned char val, unsigned char reg);
/linux-4.1.27/arch/x86/boot/
H A Dregs.c22 void initregs(struct biosregs *reg) initregs() argument
24 memset(reg, 0, sizeof *reg); initregs()
25 reg->eflags |= X86_EFLAGS_CF; initregs()
26 reg->ds = ds(); initregs()
27 reg->es = ds(); initregs()
28 reg->fs = fs(); initregs()
29 reg->gs = gs(); initregs()
/linux-4.1.27/arch/metag/include/asm/
H A Dcore_reg.h6 extern void core_reg_write(int unit, int reg, int thread, unsigned int val);
7 extern unsigned int core_reg_read(int unit, int reg, int thread);
14 #define __core_reg_get(reg) ({ \
16 asm volatile("MOV %0," #reg \
21 #define __core_reg_set(reg, value) do { \
23 asm volatile("MOV " #reg ",%0" \
28 #define __core_reg_swap(reg, value) do { \
30 asm volatile("SWAP " #reg ",%0" \
H A Dsyscall.h72 unsigned int reg, j; syscall_get_arguments() local
75 for (j = i, reg = 6 - i; j < (i + n); j++, reg--) { syscall_get_arguments()
76 if (reg % 2) syscall_get_arguments()
77 args[j] = regs->ctx.DX[(reg + 1) / 2].U0; syscall_get_arguments()
79 args[j] = regs->ctx.DX[reg / 2].U1; syscall_get_arguments()
88 unsigned int reg; syscall_set_arguments() local
91 for (reg = 6 - i; i < (i + n); i++, reg--) { syscall_set_arguments()
92 if (reg % 2) syscall_set_arguments()
93 regs->ctx.DX[(reg + 1) / 2].U0 = args[i]; syscall_set_arguments()
95 regs->ctx.DX[reg / 2].U1 = args[i]; syscall_set_arguments()
/linux-4.1.27/drivers/staging/sm750fb/
H A Dsm750_help.h41 #define FIELD_GET(x, reg, field) \
43 _F_NORMALIZE((x), reg ## _ ## field) \
46 #define FIELD_SET(x, reg, field, value) \
48 (x & ~_F_MASK(reg ## _ ## field)) \
49 | _F_DENORMALIZE(reg ## _ ## field ## _ ## value, reg ## _ ## field) \
52 #define FIELD_VALUE(x, reg, field, value) \
54 (x & ~_F_MASK(reg ## _ ## field)) \
55 | _F_DENORMALIZE(value, reg ## _ ## field) \
58 #define FIELD_CLEAR(reg, field) \
60 ~ _F_MASK(reg ## _ ## field) \
74 #define FIELD_NORMALIZE(reg, field) (((reg) & FIELD_MASK(field)) >> FIELD_START(field))
77 #define FIELD_INIT(reg, field, value) FIELD_DENORMALIZE(reg ## _ ## field, \
78 reg ## _ ## field ## _ ## value)
79 #define FIELD_INIT_VAL(reg, field, value) \
80 (FIELD_DENORMALIZE(reg ## _ ## field, value))
/linux-4.1.27/arch/sh/include/mach-common/mach/
H A Dmagicpanelr2.h22 #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg)
23 #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg)
24 #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg)
25 #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg)
26 #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg)
27 #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg)
/linux-4.1.27/drivers/clk/
H A Dclk-highbank.c50 void __iomem *reg; member in struct:hb_clk
58 u32 reg; clk_pll_prepare() local
60 reg = readl(hbclk->reg); clk_pll_prepare()
61 reg &= ~HB_PLL_RESET; clk_pll_prepare()
62 writel(reg, hbclk->reg); clk_pll_prepare()
64 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) clk_pll_prepare()
66 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) clk_pll_prepare()
75 u32 reg; clk_pll_unprepare() local
77 reg = readl(hbclk->reg); clk_pll_unprepare()
78 reg |= HB_PLL_RESET; clk_pll_unprepare()
79 writel(reg, hbclk->reg); clk_pll_unprepare()
85 u32 reg; clk_pll_enable() local
87 reg = readl(hbclk->reg); clk_pll_enable()
88 reg |= HB_PLL_EXT_ENA; clk_pll_enable()
89 writel(reg, hbclk->reg); clk_pll_enable()
97 u32 reg; clk_pll_disable() local
99 reg = readl(hbclk->reg); clk_pll_disable()
100 reg &= ~HB_PLL_EXT_ENA; clk_pll_disable()
101 writel(reg, hbclk->reg); clk_pll_disable()
108 unsigned long divf, divq, vco_freq, reg; clk_pll_recalc_rate() local
110 reg = readl(hbclk->reg); clk_pll_recalc_rate()
111 if (reg & HB_PLL_EXT_BYPASS) clk_pll_recalc_rate()
114 divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT; clk_pll_recalc_rate()
115 divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT; clk_pll_recalc_rate()
161 u32 reg; clk_pll_set_rate() local
165 reg = readl(hbclk->reg); clk_pll_set_rate()
166 if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) { clk_pll_set_rate()
168 reg |= HB_PLL_EXT_BYPASS; clk_pll_set_rate()
169 writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); clk_pll_set_rate()
171 writel(reg | HB_PLL_RESET, hbclk->reg); clk_pll_set_rate()
172 reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK); clk_pll_set_rate()
173 reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT); clk_pll_set_rate()
174 writel(reg | HB_PLL_RESET, hbclk->reg); clk_pll_set_rate()
175 writel(reg, hbclk->reg); clk_pll_set_rate()
177 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) clk_pll_set_rate()
179 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) clk_pll_set_rate()
181 reg |= HB_PLL_EXT_ENA; clk_pll_set_rate()
182 reg &= ~HB_PLL_EXT_BYPASS; clk_pll_set_rate()
184 writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); clk_pll_set_rate()
185 reg &= ~HB_PLL_DIVQ_MASK; clk_pll_set_rate()
186 reg |= divq << HB_PLL_DIVQ_SHIFT; clk_pll_set_rate()
187 writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); clk_pll_set_rate()
189 writel(reg, hbclk->reg); clk_pll_set_rate()
208 u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4; clk_cpu_periphclk_recalc_rate()
220 u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT; clk_cpu_a9bclk_recalc_rate()
235 div = readl(hbclk->reg) & 0x1f; clk_periclk_recalc_rate()
264 writel(div >> 1, hbclk->reg); clk_periclk_set_rate()
276 u32 reg; hb_clk_init() local
285 rc = of_property_read_u32(node, "reg", &reg); hb_clk_init()
295 hb_clk->reg = of_iomap(srnp, 0); hb_clk_init()
296 BUG_ON(!hb_clk->reg); hb_clk_init()
297 hb_clk->reg += reg; hb_clk_init()
/linux-4.1.27/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_dcb_82598.c46 u32 reg = 0; ixgbe_dcb_config_rx_arbiter_82598() local
51 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; ixgbe_dcb_config_rx_arbiter_82598()
52 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); ixgbe_dcb_config_rx_arbiter_82598()
54 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); ixgbe_dcb_config_rx_arbiter_82598()
56 reg &= ~IXGBE_RMCS_ARBDIS; ixgbe_dcb_config_rx_arbiter_82598()
58 reg |= IXGBE_RMCS_RRM; ixgbe_dcb_config_rx_arbiter_82598()
60 reg |= IXGBE_RMCS_DFP; ixgbe_dcb_config_rx_arbiter_82598()
62 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); ixgbe_dcb_config_rx_arbiter_82598()
69 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); ixgbe_dcb_config_rx_arbiter_82598()
72 reg |= IXGBE_RT2CR_LSP; ixgbe_dcb_config_rx_arbiter_82598()
74 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); ixgbe_dcb_config_rx_arbiter_82598()
77 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); ixgbe_dcb_config_rx_arbiter_82598()
78 reg |= IXGBE_RDRXCTL_RDMTS_1_2; ixgbe_dcb_config_rx_arbiter_82598()
79 reg |= IXGBE_RDRXCTL_MPBEN; ixgbe_dcb_config_rx_arbiter_82598()
80 reg |= IXGBE_RDRXCTL_MCEN; ixgbe_dcb_config_rx_arbiter_82598()
81 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); ixgbe_dcb_config_rx_arbiter_82598()
83 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); ixgbe_dcb_config_rx_arbiter_82598()
85 reg &= ~IXGBE_RXCTRL_DMBYPS; ixgbe_dcb_config_rx_arbiter_82598()
86 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); ixgbe_dcb_config_rx_arbiter_82598()
104 u32 reg, max_credits; ixgbe_dcb_config_tx_desc_arbiter_82598() local
107 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); ixgbe_dcb_config_tx_desc_arbiter_82598()
110 reg &= ~IXGBE_DPMCS_ARBDIS; ixgbe_dcb_config_tx_desc_arbiter_82598()
111 reg |= IXGBE_DPMCS_TSOEF; ixgbe_dcb_config_tx_desc_arbiter_82598()
114 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); ixgbe_dcb_config_tx_desc_arbiter_82598()
116 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); ixgbe_dcb_config_tx_desc_arbiter_82598()
121 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; ixgbe_dcb_config_tx_desc_arbiter_82598()
122 reg |= refill[i]; ixgbe_dcb_config_tx_desc_arbiter_82598()
123 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT; ixgbe_dcb_config_tx_desc_arbiter_82598()
126 reg |= IXGBE_TDTQ2TCCR_GSP; ixgbe_dcb_config_tx_desc_arbiter_82598()
129 reg |= IXGBE_TDTQ2TCCR_LSP; ixgbe_dcb_config_tx_desc_arbiter_82598()
131 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); ixgbe_dcb_config_tx_desc_arbiter_82598()
150 u32 reg; ixgbe_dcb_config_tx_data_arbiter_82598() local
153 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); ixgbe_dcb_config_tx_data_arbiter_82598()
155 reg &= ~IXGBE_PDPMCS_ARBDIS; ixgbe_dcb_config_tx_data_arbiter_82598()
157 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM); ixgbe_dcb_config_tx_data_arbiter_82598()
159 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); ixgbe_dcb_config_tx_data_arbiter_82598()
163 reg = refill[i]; ixgbe_dcb_config_tx_data_arbiter_82598()
164 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT; ixgbe_dcb_config_tx_data_arbiter_82598()
165 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT; ixgbe_dcb_config_tx_data_arbiter_82598()
168 reg |= IXGBE_TDPT2TCCR_GSP; ixgbe_dcb_config_tx_data_arbiter_82598()
171 reg |= IXGBE_TDPT2TCCR_LSP; ixgbe_dcb_config_tx_data_arbiter_82598()
173 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); ixgbe_dcb_config_tx_data_arbiter_82598()
177 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); ixgbe_dcb_config_tx_data_arbiter_82598()
178 reg |= IXGBE_DTXCTL_ENDBUBD; ixgbe_dcb_config_tx_data_arbiter_82598()
179 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); ixgbe_dcb_config_tx_data_arbiter_82598()
193 u32 fcrtl, reg; ixgbe_dcb_config_pfc_82598() local
197 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); ixgbe_dcb_config_pfc_82598()
198 reg &= ~IXGBE_RMCS_TFCE_802_3X; ixgbe_dcb_config_pfc_82598()
199 reg |= IXGBE_RMCS_TFCE_PRIORITY; ixgbe_dcb_config_pfc_82598()
200 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); ixgbe_dcb_config_pfc_82598()
203 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); ixgbe_dcb_config_pfc_82598()
204 reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE); ixgbe_dcb_config_pfc_82598()
207 reg |= IXGBE_FCTRL_RPFCE; ixgbe_dcb_config_pfc_82598()
209 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); ixgbe_dcb_config_pfc_82598()
220 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; ixgbe_dcb_config_pfc_82598()
222 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); ixgbe_dcb_config_pfc_82598()
226 reg = hw->fc.pause_time * 0x00010001; ixgbe_dcb_config_pfc_82598()
228 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); ixgbe_dcb_config_pfc_82598()
246 u32 reg = 0; ixgbe_dcb_config_tc_stats_82598() local
250 /* Receive Queues stats setting - 8 queues per statistics reg */ ixgbe_dcb_config_tc_stats_82598()
252 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); ixgbe_dcb_config_tc_stats_82598()
253 reg |= ((0x1010101) * j); ixgbe_dcb_config_tc_stats_82598()
254 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); ixgbe_dcb_config_tc_stats_82598()
255 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); ixgbe_dcb_config_tc_stats_82598()
256 reg |= ((0x1010101) * j); ixgbe_dcb_config_tc_stats_82598()
257 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); ixgbe_dcb_config_tc_stats_82598()
259 /* Transmit Queues stats setting - 4 queues per statistics reg */ ixgbe_dcb_config_tc_stats_82598()
261 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); ixgbe_dcb_config_tc_stats_82598()
262 reg |= ((0x1010101) * i); ixgbe_dcb_config_tc_stats_82598()
263 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); ixgbe_dcb_config_tc_stats_82598()
H A Dixgbe_dcb_82599.c51 u32 reg = 0; ixgbe_dcb_config_rx_arbiter_82599() local
60 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; ixgbe_dcb_config_rx_arbiter_82599()
61 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); ixgbe_dcb_config_rx_arbiter_82599()
64 reg = 0; ixgbe_dcb_config_rx_arbiter_82599()
66 reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); ixgbe_dcb_config_rx_arbiter_82599()
67 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); ixgbe_dcb_config_rx_arbiter_82599()
73 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); ixgbe_dcb_config_rx_arbiter_82599()
75 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; ixgbe_dcb_config_rx_arbiter_82599()
78 reg |= IXGBE_RTRPT4C_LSP; ixgbe_dcb_config_rx_arbiter_82599()
80 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); ixgbe_dcb_config_rx_arbiter_82599()
87 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC; ixgbe_dcb_config_rx_arbiter_82599()
88 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); ixgbe_dcb_config_rx_arbiter_82599()
109 u32 reg, max_credits; ixgbe_dcb_config_tx_desc_arbiter_82599() local
121 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT; ixgbe_dcb_config_tx_desc_arbiter_82599()
122 reg |= refill[i]; ixgbe_dcb_config_tx_desc_arbiter_82599()
123 reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT; ixgbe_dcb_config_tx_desc_arbiter_82599()
126 reg |= IXGBE_RTTDT2C_GSP; ixgbe_dcb_config_tx_desc_arbiter_82599()
129 reg |= IXGBE_RTTDT2C_LSP; ixgbe_dcb_config_tx_desc_arbiter_82599()
131 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg); ixgbe_dcb_config_tx_desc_arbiter_82599()
138 reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM; ixgbe_dcb_config_tx_desc_arbiter_82599()
139 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); ixgbe_dcb_config_tx_desc_arbiter_82599()
161 u32 reg; ixgbe_dcb_config_tx_data_arbiter_82599() local
168 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | ixgbe_dcb_config_tx_data_arbiter_82599()
171 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); ixgbe_dcb_config_tx_data_arbiter_82599()
174 reg = 0; ixgbe_dcb_config_tx_data_arbiter_82599()
176 reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT)); ixgbe_dcb_config_tx_data_arbiter_82599()
177 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); ixgbe_dcb_config_tx_data_arbiter_82599()
181 reg = refill[i]; ixgbe_dcb_config_tx_data_arbiter_82599()
182 reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT; ixgbe_dcb_config_tx_data_arbiter_82599()
183 reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT; ixgbe_dcb_config_tx_data_arbiter_82599()
186 reg |= IXGBE_RTTPT2C_GSP; ixgbe_dcb_config_tx_data_arbiter_82599()
189 reg |= IXGBE_RTTPT2C_LSP; ixgbe_dcb_config_tx_data_arbiter_82599()
191 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg); ixgbe_dcb_config_tx_data_arbiter_82599()
198 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | ixgbe_dcb_config_tx_data_arbiter_82599()
200 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); ixgbe_dcb_config_tx_data_arbiter_82599()
215 u32 i, j, fcrtl, reg; ixgbe_dcb_config_pfc_82599() local
222 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); ixgbe_dcb_config_pfc_82599()
223 reg |= IXGBE_MFLCN_DPF; ixgbe_dcb_config_pfc_82599()
230 reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); ixgbe_dcb_config_pfc_82599()
233 reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT; ixgbe_dcb_config_pfc_82599()
236 reg |= IXGBE_MFLCN_RPFCE; ixgbe_dcb_config_pfc_82599()
238 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); ixgbe_dcb_config_pfc_82599()
258 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; ixgbe_dcb_config_pfc_82599()
262 reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32; ixgbe_dcb_config_pfc_82599()
266 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); ixgbe_dcb_config_pfc_82599()
275 reg = hw->fc.pause_time * 0x00010001; ixgbe_dcb_config_pfc_82599()
277 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); ixgbe_dcb_config_pfc_82599()
294 u32 reg = 0; ixgbe_dcb_config_tc_stats_82599() local
304 reg = 0x01010101 * (i / 4); ixgbe_dcb_config_tc_stats_82599()
305 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); ixgbe_dcb_config_tc_stats_82599()
317 reg = 0x00000000; ixgbe_dcb_config_tc_stats_82599()
319 reg = 0x01010101; ixgbe_dcb_config_tc_stats_82599()
321 reg = 0x02020202; ixgbe_dcb_config_tc_stats_82599()
323 reg = 0x03030303; ixgbe_dcb_config_tc_stats_82599()
325 reg = 0x04040404; ixgbe_dcb_config_tc_stats_82599()
327 reg = 0x05050505; ixgbe_dcb_config_tc_stats_82599()
329 reg = 0x06060606; ixgbe_dcb_config_tc_stats_82599()
331 reg = 0x07070707; ixgbe_dcb_config_tc_stats_82599()
332 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg); ixgbe_dcb_config_tc_stats_82599()
/linux-4.1.27/drivers/acpi/pmic/
H A Dintel_pmic_crc.c30 .reg = 0x66,
35 .reg = 0x5d,
43 .reg = 0x75
47 .reg = 0x95
51 .reg = 0x97
55 .reg = 0x77
59 .reg = 0x9a
63 .reg = 0x9c
67 .reg = 0x79
71 .reg = 0x9f
75 .reg = 0xa1
79 .reg = 0x94
83 .reg = 0x99
87 .reg = 0x9e
91 static int intel_crc_pmic_get_power(struct regmap *regmap, int reg, intel_crc_pmic_get_power() argument
96 if (regmap_read(regmap, reg, &data)) intel_crc_pmic_get_power()
103 static int intel_crc_pmic_update_power(struct regmap *regmap, int reg, intel_crc_pmic_update_power() argument
108 if (regmap_read(regmap, reg, &data)) intel_crc_pmic_update_power()
118 if (regmap_write(regmap, reg, data)) intel_crc_pmic_update_power()
123 static int intel_crc_pmic_get_raw_temp(struct regmap *regmap, int reg) intel_crc_pmic_get_raw_temp() argument
128 * Raw temperature value is 10bits: 8bits in reg intel_crc_pmic_get_raw_temp()
129 * and 2bits in reg-1: bit0,1 intel_crc_pmic_get_raw_temp()
131 if (regmap_read(regmap, reg, &temp_l) || intel_crc_pmic_get_raw_temp()
132 regmap_read(regmap, reg - 1, &temp_h)) intel_crc_pmic_get_raw_temp()
138 static int intel_crc_pmic_update_aux(struct regmap *regmap, int reg, int raw) intel_crc_pmic_update_aux() argument
140 return regmap_write(regmap, reg, raw) || intel_crc_pmic_update_aux()
141 regmap_update_bits(regmap, reg - 1, 0x3, raw >> 8) ? -EIO : 0; intel_crc_pmic_update_aux()
144 static int intel_crc_pmic_get_policy(struct regmap *regmap, int reg, u64 *value) intel_crc_pmic_get_policy() argument
148 if (regmap_read(regmap, reg, &pen)) intel_crc_pmic_get_policy()
155 int reg, int enable) intel_crc_pmic_update_policy()
166 if (regmap_update_bits(regmap, reg, 0x80, enable << 7)) intel_crc_pmic_update_policy()
154 intel_crc_pmic_update_policy(struct regmap *regmap, int reg, int enable) intel_crc_pmic_update_policy() argument
H A Dintel_pmic.h6 int reg; /* corresponding thermal register */ member in struct:pmic_table
11 int (*get_power)(struct regmap *r, int reg, int bit, u64 *value);
12 int (*update_power)(struct regmap *r, int reg, int bit, bool on);
13 int (*get_raw_temp)(struct regmap *r, int reg);
14 int (*update_aux)(struct regmap *r, int reg, int raw_temp);
15 int (*get_policy)(struct regmap *r, int reg, u64 *value);
16 int (*update_policy)(struct regmap *r, int reg, int enable);
H A Dintel_pmic_xpower.c29 .reg = 0x13,
34 .reg = 0x13,
39 .reg = 0x13,
44 .reg = 0x12,
49 .reg = 0x12,
54 .reg = 0x12,
59 .reg = 0x12,
64 .reg = 0x12,
69 .reg = 0x12,
74 .reg = 0x12,
79 .reg = 0x13,
84 .reg = 0x13,
89 .reg = 0x13,
94 .reg = 0x10,
99 .reg = 0x10,
104 .reg = 0x10,
109 .reg = 0x10,
114 .reg = 0x10,
119 .reg = 0x10,
128 .reg = XPOWER_GPADC_LOW
132 .reg = XPOWER_GPADC_LOW
136 .reg = XPOWER_GPADC_LOW
140 .reg = XPOWER_GPADC_LOW
144 .reg = XPOWER_GPADC_LOW
148 .reg = XPOWER_GPADC_LOW
152 static int intel_xpower_pmic_get_power(struct regmap *regmap, int reg, intel_xpower_pmic_get_power() argument
157 if (regmap_read(regmap, reg, &data)) intel_xpower_pmic_get_power()
164 static int intel_xpower_pmic_update_power(struct regmap *regmap, int reg, intel_xpower_pmic_update_power() argument
169 if (regmap_read(regmap, reg, &data)) intel_xpower_pmic_update_power()
177 if (regmap_write(regmap, reg, data)) intel_xpower_pmic_update_power()
187 * @reg: register to get the reading
196 static int intel_xpower_pmic_get_raw_temp(struct regmap *regmap, int reg) intel_xpower_pmic_get_raw_temp() argument
H A Dintel_pmic.c33 int count, int *reg, int *bit) pmic_get_reg_bit()
39 *reg = table[i].reg; pmic_get_reg_bit()
55 int reg, bit, result; intel_pmic_power_handler() local
64 d->power_table_count, &reg, &bit); intel_pmic_power_handler()
71 d->get_power(regmap, reg, bit, value64) : intel_pmic_power_handler()
72 d->update_power(regmap, reg, bit, *value64 == 1); intel_pmic_power_handler()
80 int reg, u64 *value) pmic_read_temp()
87 raw_temp = opregion->data->get_raw_temp(opregion->regmap, reg); pmic_read_temp()
104 static int pmic_thermal_temp(struct intel_pmic_opregion *opregion, int reg, pmic_thermal_temp() argument
108 pmic_read_temp(opregion, reg, value) : -EINVAL; pmic_thermal_temp()
111 static int pmic_thermal_aux(struct intel_pmic_opregion *opregion, int reg, pmic_thermal_aux() argument
117 return pmic_read_temp(opregion, reg, value); pmic_thermal_aux()
130 return opregion->data->update_aux(opregion->regmap, reg, raw_temp); pmic_thermal_aux()
133 static int pmic_thermal_pen(struct intel_pmic_opregion *opregion, int reg, pmic_thermal_pen() argument
143 return d->get_policy(regmap, reg, value); pmic_thermal_pen()
148 return d->update_policy(regmap, reg, *value); pmic_thermal_pen()
173 int reg, result; intel_pmic_thermal_handler() local
179 d->thermal_table_count, &reg, NULL); intel_pmic_thermal_handler()
186 result = pmic_thermal_temp(opregion, reg, function, value64); intel_pmic_thermal_handler()
188 result = pmic_thermal_aux(opregion, reg, function, value64); intel_pmic_thermal_handler()
190 result = pmic_thermal_pen(opregion, reg, function, value64); intel_pmic_thermal_handler()
32 pmic_get_reg_bit(int address, struct pmic_table *table, int count, int *reg, int *bit) pmic_get_reg_bit() argument
79 pmic_read_temp(struct intel_pmic_opregion *opregion, int reg, u64 *value) pmic_read_temp() argument
/linux-4.1.27/arch/mips/include/asm/mach-ralink/
H A Dralink_regs.h19 static inline void rt_sysc_w32(u32 val, unsigned reg) rt_sysc_w32() argument
21 __raw_writel(val, rt_sysc_membase + reg); rt_sysc_w32()
24 static inline u32 rt_sysc_r32(unsigned reg) rt_sysc_r32() argument
26 return __raw_readl(rt_sysc_membase + reg); rt_sysc_r32()
29 static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg) rt_sysc_m32() argument
31 u32 val = rt_sysc_r32(reg) & ~clr; rt_sysc_m32()
33 __raw_writel(val | set, rt_sysc_membase + reg); rt_sysc_m32()
36 static inline void rt_memc_w32(u32 val, unsigned reg) rt_memc_w32() argument
38 __raw_writel(val, rt_memc_membase + reg); rt_memc_w32()
41 static inline u32 rt_memc_r32(unsigned reg) rt_memc_r32() argument
43 return __raw_readl(rt_memc_membase + reg); rt_memc_r32()
/linux-4.1.27/drivers/media/platform/s5p-g2d/
H A Dg2d-regs.h14 #define SOFT_RESET_REG 0x0000 /* Software reset reg */
15 #define INTEN_REG 0x0004 /* Interrupt Enable reg */
16 #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */
17 #define FIFO_STAT_REG 0x0010 /* Command FIFO Status reg */
18 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
19 #define CACHECTL_REG 0x0018 /* Cache & Buffer clear reg */
20 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
23 #define BITBLT_START_REG 0x0100 /* BitBLT Start reg */
24 #define BITBLT_COMMAND_REG 0x0104 /* Command reg for BitBLT */
27 #define ROTATE_REG 0x0200 /* Rotation reg */
28 #define SRC_MSK_DIRECT_REG 0x0204 /* Src and Mask Direction reg */
29 #define DST_PAT_DIRECT_REG 0x0208 /* Dest and Pattern Direction reg */
32 #define SRC_SELECT_REG 0x0300 /* Src Image Selection reg */
33 #define SRC_BASE_ADDR_REG 0x0304 /* Src Image Base Address reg */
34 #define SRC_STRIDE_REG 0x0308 /* Src Stride reg */
35 #define SRC_COLOR_MODE_REG 0x030C /* Src Image Color Mode reg */
36 #define SRC_LEFT_TOP_REG 0x0310 /* Src Left Top Coordinate reg */
37 #define SRC_RIGHT_BOTTOM_REG 0x0314 /* Src Right Bottom Coordinate reg */
43 #define DST_SELECT_REG 0x0400 /* Dest Image Selection reg */
44 #define DST_BASE_ADDR_REG 0x0404 /* Dest Image Base Address reg */
45 #define DST_STRIDE_REG 0x0408 /* Dest Stride reg */
46 #define DST_COLOR_MODE_REG 0x040C /* Dest Image Color Mode reg */
47 #define DST_LEFT_TOP_REG 0x0410 /* Dest Left Top Coordinate reg */
48 #define DST_RIGHT_BOTTOM_REG 0x0414 /* Dest Right Bottom Coordinate reg */
51 #define PAT_BASE_ADDR_REG 0x0500 /* Pattern Image Base Address reg */
52 #define PAT_SIZE_REG 0x0504 /* Pattern Image Size reg */
53 #define PAT_COLOR_MODE_REG 0x0508 /* Pattern Image Color Mode reg */
54 #define PAT_OFFSET_REG 0x050C /* Pattern Left Top Coordinate reg */
55 #define PAT_STRIDE_REG 0x0510 /* Pattern Stride reg */
58 #define MASK_BASE_ADDR_REG 0x0520 /* Mask Base Address reg */
59 #define MASK_STRIDE_REG 0x0524 /* Mask Stride reg */
67 #define THIRD_OPERAND_REG 0x0610 /* Third Operand Selection reg */
68 #define ROP4_REG 0x0614 /* Raster Operation reg */
72 #define FG_COLOR_REG 0x0700 /* Foreground Color reg */
73 #define BG_COLOR_REG 0x0704 /* Background Color reg */
74 #define BS_COLOR_REG 0x0708 /* Blue Screen Color reg */
77 #define SRC_COLORKEY_CTRL_REG 0x0710 /* Src Colorkey control reg */
79 Min reg */
81 Max reg */
82 #define DST_COLORKEY_CTRL_REG 0x071C /* Dest Colorkey control reg */
84 Min reg */
86 Max reg */
/linux-4.1.27/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
H A Dconfig_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Dstrmux_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Dbif_slave_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Dintr_vect_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
H A Dmarb_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
277 #define REG_RD( scope, inst, reg ) \
278 REG_READ( reg_##scope##_##reg, \
279 (inst) + REG_RD_ADDR_##scope##_##reg )
283 #define REG_WR( scope, inst, reg, val ) \
284 REG_WRITE( reg_##scope##_##reg, \
285 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
289 #define REG_RD_VECT( scope, inst, reg, index ) \
290 REG_READ( reg_##scope##_##reg, \
291 (inst) + REG_RD_ADDR_##scope##_##reg + \
292 (index) * STRIDE_##scope##_##reg )
296 #define REG_WR_VECT( scope, inst, reg, index, val ) \
297 REG_WRITE( reg_##scope##_##reg, \
298 (inst) + REG_WR_ADDR_##scope##_##reg + \
299 (index) * STRIDE_##scope##_##reg, (val) )
303 #define REG_RD_INT( scope, inst, reg ) \
304 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
308 #define REG_WR_INT( scope, inst, reg, val ) \
309 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
313 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
314 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
315 (index) * STRIDE_##scope##_##reg )
319 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
320 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
321 (index) * STRIDE_##scope##_##reg, (val) )
334 #define REG_ADDR( scope, inst, reg ) \
335 ( (inst) + REG_RD_ADDR_##scope##_##reg )
339 #define REG_ADDR_VECT( scope, inst, reg, index ) \
340 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
341 (index) * STRIDE_##scope##_##reg )
H A Dmarb_bp_defs.h18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
/linux-4.1.27/arch/arm/mach-cns3xxx/
H A Dpm.c20 u32 reg = __raw_readl(PM_CLK_GATE_REG); cns3xxx_pwr_clk_en() local
22 reg |= (block & PM_CLK_GATE_REG_MASK); cns3xxx_pwr_clk_en()
23 __raw_writel(reg, PM_CLK_GATE_REG); cns3xxx_pwr_clk_en()
29 u32 reg = __raw_readl(PM_CLK_GATE_REG); cns3xxx_pwr_clk_dis() local
31 reg &= ~(block & PM_CLK_GATE_REG_MASK); cns3xxx_pwr_clk_dis()
32 __raw_writel(reg, PM_CLK_GATE_REG); cns3xxx_pwr_clk_dis()
38 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); cns3xxx_pwr_power_up() local
40 reg &= ~(block & CNS3XXX_PWR_PLL_ALL); cns3xxx_pwr_power_up()
41 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); cns3xxx_pwr_power_up()
50 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); cns3xxx_pwr_power_down() local
53 reg |= (block & CNS3XXX_PWR_PLL_ALL); cns3xxx_pwr_power_down()
54 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); cns3xxx_pwr_power_down()
60 u32 reg = __raw_readl(PM_SOFT_RST_REG); cns3xxx_pwr_soft_rst_force() local
67 reg &= ~(block & PM_SOFT_RST_REG_MASK); cns3xxx_pwr_soft_rst_force()
69 reg &= ~(block & PM_SOFT_RST_REG_MASK); cns3xxx_pwr_soft_rst_force()
70 __raw_writel(reg, PM_SOFT_RST_REG); cns3xxx_pwr_soft_rst_force()
71 reg |= (block & PM_SOFT_RST_REG_MASK); cns3xxx_pwr_soft_rst_force()
74 __raw_writel(reg, PM_SOFT_RST_REG); cns3xxx_pwr_soft_rst_force()
108 u32 reg = __raw_readl(PM_CLK_CTRL_REG); cns3xxx_cpu_clock() local
113 cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf; cns3xxx_cpu_clock()
114 div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; cns3xxx_cpu_clock()
/linux-4.1.27/arch/ia64/include/asm/native/
H A Dinst.h51 #define MOV_FROM_IFA(reg) \
52 mov reg = cr.ifa
54 #define MOV_FROM_ITIR(reg) \
55 mov reg = cr.itir
57 #define MOV_FROM_ISR(reg) \
58 mov reg = cr.isr
60 #define MOV_FROM_IHA(reg) \
61 mov reg = cr.iha
63 #define MOV_FROM_IPSR(pred, reg) \
64 (pred) mov reg = cr.ipsr
66 #define MOV_FROM_IIM(reg) \
67 mov reg = cr.iim
69 #define MOV_FROM_IIP(reg) \
70 mov reg = cr.iip
72 #define MOV_FROM_IVR(reg, clob) \
73 mov reg = cr.ivr \
76 #define MOV_FROM_PSR(pred, reg, clob) \
77 (pred) mov reg = psr \
80 #define MOV_FROM_ITC(pred, pred_clob, reg, clob) \
81 (pred) mov reg = ar.itc \
85 #define MOV_TO_IFA(reg, clob) \
86 mov cr.ifa = reg \
89 #define MOV_TO_ITIR(pred, reg, clob) \
90 (pred) mov cr.itir = reg \
93 #define MOV_TO_IHA(pred, reg, clob) \
94 (pred) mov cr.iha = reg \
97 #define MOV_TO_IPSR(pred, reg, clob) \
98 (pred) mov cr.ipsr = reg \
101 #define MOV_TO_IFS(pred, reg, clob) \
102 (pred) mov cr.ifs = reg \
105 #define MOV_TO_IIP(reg, clob) \
106 mov cr.iip = reg \
109 #define MOV_TO_KR(kr, reg, clob0, clob1) \
110 mov IA64_KR(kr) = reg \
114 #define ITC_I(pred, reg, clob) \
115 (pred) itc.i reg \
118 #define ITC_D(pred, reg, clob) \
119 (pred) itc.d reg \
122 #define ITC_I_AND_D(pred_i, pred_d, reg, clob) \
123 (pred_i) itc.i reg; \
124 (pred_d) itc.d reg \
H A Dpvchk_inst.h126 /* check whether reg is a regular register */
127 .macro is_rreg_in reg
128 .ifc "\reg", "r0"
133 mov \reg = r0 variable
136 #define IS_RREG_IN(reg) is_rreg_in reg ;
138 #define IS_RREG_OUT(reg) \
140 mov reg = r0 \
143 #define IS_RREG_CLOB(reg) IS_RREG_OUT(reg)
161 #define MOV_FROM_IFA(reg) \
162 IS_RREG_OUT(reg)
163 #define MOV_FROM_ITIR(reg) \
164 IS_RREG_OUT(reg)
165 #define MOV_FROM_ISR(reg) \
166 IS_RREG_OUT(reg)
167 #define MOV_FROM_IHA(reg) \
168 IS_RREG_OUT(reg)
169 #define MOV_FROM_IPSR(pred, reg) \
171 IS_RREG_OUT(reg)
172 #define MOV_FROM_IIM(reg) \
173 IS_RREG_OUT(reg)
174 #define MOV_FROM_IIP(reg) \
175 IS_RREG_OUT(reg)
176 #define MOV_FROM_IVR(reg, clob) \
177 IS_RREG_OUT(reg) \
179 #define MOV_FROM_PSR(pred, reg, clob) \
181 IS_RREG_OUT(reg) \
183 #define MOV_FROM_ITC(pred, pred_clob, reg, clob) \
186 IS_RREG_OUT(reg) \
188 #define MOV_TO_IFA(reg, clob) \
189 IS_RREG_IN(reg) \
191 #define MOV_TO_ITIR(pred, reg, clob) \
193 IS_RREG_IN(reg) \
195 #define MOV_TO_IHA(pred, reg, clob) \
197 IS_RREG_IN(reg) \
199 #define MOV_TO_IPSR(pred, reg, clob) \
201 IS_RREG_IN(reg) \
203 #define MOV_TO_IFS(pred, reg, clob) \
205 IS_RREG_IN(reg) \
207 #define MOV_TO_IIP(reg, clob) \
208 IS_RREG_IN(reg) \
210 #define MOV_TO_KR(kr, reg, clob0, clob1) \
211 IS_RREG_IN(reg) \
214 #define ITC_I(pred, reg, clob) \
216 IS_RREG_IN(reg) \
218 #define ITC_D(pred, reg, clob) \
220 IS_RREG_IN(reg) \
222 #define ITC_I_AND_D(pred_i, pred_d, reg, clob) \
225 IS_RREG_IN(reg) \
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/asm/
H A Dirq_nmi_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
H A Dstrcop_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
H A Dstrmux_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
H A Dconfig_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
H A Dcris_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
H A Drt_trace_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/iop/asm/
H A Diop_version_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
H A Diop_scrc_out_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
H A Diop_fifo_in_extra_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
H A Diop_fifo_out_extra_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
H A Diop_scrc_in_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
H A Diop_trigger_grp_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/
H A Diop_version_defs_asm.h15 #define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
21 #define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
27 #define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
33 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
46 #define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
H A Diop_sap_in_defs_asm.h15 #define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
21 #define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
27 #define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
33 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
46 #define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
/linux-4.1.27/arch/mips/ath79/
H A Dcommon.c43 void ath79_ddr_wb_flush(u32 reg) ath79_ddr_wb_flush() argument
45 void __iomem *flush_reg = ath79_ddr_base + reg; ath79_ddr_wb_flush()
62 u32 reg; ath79_device_reset_set() local
66 reg = AR71XX_RESET_REG_RESET_MODULE; ath79_device_reset_set()
68 reg = AR724X_RESET_REG_RESET_MODULE; ath79_device_reset_set()
70 reg = AR913X_RESET_REG_RESET_MODULE; ath79_device_reset_set()
72 reg = AR933X_RESET_REG_RESET_MODULE; ath79_device_reset_set()
74 reg = AR934X_RESET_REG_RESET_MODULE; ath79_device_reset_set()
76 reg = QCA955X_RESET_REG_RESET_MODULE; ath79_device_reset_set()
81 t = ath79_reset_rr(reg); ath79_device_reset_set()
82 ath79_reset_wr(reg, t | mask); ath79_device_reset_set()
90 u32 reg; ath79_device_reset_clear() local
94 reg = AR71XX_RESET_REG_RESET_MODULE; ath79_device_reset_clear()
96 reg = AR724X_RESET_REG_RESET_MODULE; ath79_device_reset_clear()
98 reg = AR913X_RESET_REG_RESET_MODULE; ath79_device_reset_clear()
100 reg = AR933X_RESET_REG_RESET_MODULE; ath79_device_reset_clear()
102 reg = AR934X_RESET_REG_RESET_MODULE; ath79_device_reset_clear()
104 reg = QCA955X_RESET_REG_RESET_MODULE; ath79_device_reset_clear()
109 t = ath79_reset_rr(reg); ath79_device_reset_clear()
110 ath79_reset_wr(reg, t & ~mask); ath79_device_reset_clear()
/linux-4.1.27/arch/mips/bcm63xx/
H A Dtimer.c58 u32 reg; bcm63xx_timer_enable() local
66 reg = bcm_timer_readl(TIMER_CTLx_REG(id)); bcm63xx_timer_enable()
67 reg |= TIMER_CTL_ENABLE_MASK; bcm63xx_timer_enable()
68 bcm_timer_writel(reg, TIMER_CTLx_REG(id)); bcm63xx_timer_enable()
70 reg = bcm_timer_readl(TIMER_IRQSTAT_REG); bcm63xx_timer_enable()
71 reg |= TIMER_IRQSTAT_TIMER_IR_EN(id); bcm63xx_timer_enable()
72 bcm_timer_writel(reg, TIMER_IRQSTAT_REG); bcm63xx_timer_enable()
82 u32 reg; bcm63xx_timer_disable() local
90 reg = bcm_timer_readl(TIMER_CTLx_REG(id)); bcm63xx_timer_disable()
91 reg &= ~TIMER_CTL_ENABLE_MASK; bcm63xx_timer_disable()
92 bcm_timer_writel(reg, TIMER_CTLx_REG(id)); bcm63xx_timer_disable()
94 reg = bcm_timer_readl(TIMER_IRQSTAT_REG); bcm63xx_timer_disable()
95 reg &= ~TIMER_IRQSTAT_TIMER_IR_EN(id); bcm63xx_timer_disable()
96 bcm_timer_writel(reg, TIMER_IRQSTAT_REG); bcm63xx_timer_disable()
152 u32 reg, countdown; bcm63xx_timer_set() local
163 reg = bcm_timer_readl(TIMER_CTLx_REG(id)); bcm63xx_timer_set()
166 reg &= ~TIMER_CTL_MONOTONIC_MASK; bcm63xx_timer_set()
168 reg |= TIMER_CTL_MONOTONIC_MASK; bcm63xx_timer_set()
170 reg &= ~TIMER_CTL_COUNTDOWN_MASK; bcm63xx_timer_set()
171 reg |= countdown; bcm63xx_timer_set()
172 bcm_timer_writel(reg, TIMER_CTLx_REG(id)); bcm63xx_timer_set()
183 u32 reg; bcm63xx_timer_init() local
185 reg = bcm_timer_readl(TIMER_IRQSTAT_REG); bcm63xx_timer_init()
186 reg &= ~TIMER_IRQSTAT_TIMER0_IR_EN; bcm63xx_timer_init()
187 reg &= ~TIMER_IRQSTAT_TIMER1_IR_EN; bcm63xx_timer_init()
188 reg &= ~TIMER_IRQSTAT_TIMER2_IR_EN; bcm63xx_timer_init()
189 bcm_timer_writel(reg, TIMER_IRQSTAT_REG); bcm63xx_timer_init()
H A Dsetup.c34 u32 reg; bcm6348_a1_reboot() local
38 reg = bcm_perf_readl(PERF_SOFTRESET_REG); bcm6348_a1_reboot()
39 reg &= ~SOFTRESET_6348_ALL; bcm6348_a1_reboot()
40 bcm_perf_writel(reg, PERF_SOFTRESET_REG); bcm6348_a1_reboot()
43 reg = bcm_perf_readl(PERF_SOFTRESET_REG); bcm6348_a1_reboot()
44 reg |= SOFTRESET_6348_ALL; bcm6348_a1_reboot()
45 bcm_perf_writel(reg, PERF_SOFTRESET_REG); bcm6348_a1_reboot()
67 u32 reg, perf_regs[2] = { 0, 0 }; bcm63xx_machine_reboot() local
99 reg = bcm_perf_readl(perf_regs[i]); bcm63xx_machine_reboot()
101 reg &= ~EXTIRQ_CFG_MASK_ALL_6348; bcm63xx_machine_reboot()
102 reg |= EXTIRQ_CFG_CLEAR_ALL_6348; bcm63xx_machine_reboot()
104 reg &= ~EXTIRQ_CFG_MASK_ALL; bcm63xx_machine_reboot()
105 reg |= EXTIRQ_CFG_CLEAR_ALL; bcm63xx_machine_reboot()
107 bcm_perf_writel(reg, perf_regs[i]); bcm63xx_machine_reboot()
117 reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); bcm63xx_machine_reboot()
118 reg |= SYS_PLL_SOFT_RESET; bcm63xx_machine_reboot()
119 bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG); bcm63xx_machine_reboot()
H A Dgpio.c41 u32 reg; bcm63xx_gpio_set() local
50 reg = gpio_out_low_reg; bcm63xx_gpio_set()
54 reg = GPIO_DATA_HI_REG; bcm63xx_gpio_set()
64 bcm_gpio_writel(*v, reg); bcm63xx_gpio_set()
70 u32 reg; bcm63xx_gpio_get() local
77 reg = gpio_out_low_reg; bcm63xx_gpio_get()
80 reg = GPIO_DATA_HI_REG; bcm63xx_gpio_get()
84 return !!(bcm_gpio_readl(reg) & mask); bcm63xx_gpio_get()
90 u32 reg; bcm63xx_gpio_set_direction() local
99 reg = GPIO_CTL_LO_REG; bcm63xx_gpio_set_direction()
102 reg = GPIO_CTL_HI_REG; bcm63xx_gpio_set_direction()
107 tmp = bcm_gpio_readl(reg); bcm63xx_gpio_set_direction()
112 bcm_gpio_writel(tmp, reg); bcm63xx_gpio_set_direction()
/linux-4.1.27/drivers/media/tuners/
H A Dfc0012.c24 static int fc0012_writereg(struct fc0012_priv *priv, u8 reg, u8 val) fc0012_writereg() argument
26 u8 buf[2] = {reg, val}; fc0012_writereg()
33 "%s: I2C write reg failed, reg: %02x, val: %02x\n", fc0012_writereg()
34 KBUILD_MODNAME, reg, val); fc0012_writereg()
40 static int fc0012_readreg(struct fc0012_priv *priv, u8 reg, u8 *val) fc0012_readreg() argument
44 .buf = &reg, .len = 1 }, fc0012_readreg()
51 "%s: I2C read reg failed, reg: %02x\n", fc0012_readreg()
52 KBUILD_MODNAME, reg); fc0012_readreg()
69 unsigned char reg[] = { fc0012_init() local
70 0x00, /* dummy reg. 0 */ fc0012_init()
71 0x05, /* reg. 0x01 */ fc0012_init()
72 0x10, /* reg. 0x02 */ fc0012_init()
73 0x00, /* reg. 0x03 */ fc0012_init()
74 0x00, /* reg. 0x04 */ fc0012_init()
75 0x0f, /* reg. 0x05: may also be 0x0a */ fc0012_init()
76 0x00, /* reg. 0x06: divider 2, VCO slow */ fc0012_init()
77 0x00, /* reg. 0x07: may also be 0x0f */ fc0012_init()
78 0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256, fc0012_init()
80 0x6e, /* reg. 0x09: Disable LoopThrough, Enable LoopThrough: 0x6f */ fc0012_init()
81 0xb8, /* reg. 0x0a: Disable LO Test Buffer */ fc0012_init()
82 0x82, /* reg. 0x0b: Output Clock is same as clock frequency, fc0012_init()
84 0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */ fc0012_init()
85 0x02, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, 0x02 for DVB-T */ fc0012_init()
86 0x00, /* reg. 0x0e */ fc0012_init()
87 0x00, /* reg. 0x0f */ fc0012_init()
88 0x00, /* reg. 0x10: may also be 0x0d */ fc0012_init()
89 0x00, /* reg. 0x11 */ fc0012_init()
90 0x1f, /* reg. 0x12: Set to maximum gain */ fc0012_init()
91 0x08, /* reg. 0x13: Set to Middle Gain: 0x08, fc0012_init()
93 0x00, /* reg. 0x14 */ fc0012_init()
94 0x04, /* reg. 0x15: Enable LNA COMPS */ fc0012_init()
100 reg[0x07] |= 0x20; fc0012_init()
108 reg[0x0c] |= 0x02; fc0012_init()
111 reg[0x09] |= 0x01; fc0012_init()
116 for (i = 1; i < sizeof(reg); i++) { fc0012_init()
117 ret = fc0012_writereg(priv, i, reg[i]); fc0012_init()
139 unsigned char reg[7], am, pm, multi, tmp; fc0012_set_params() local
167 reg[5] = 0x82; fc0012_set_params()
168 reg[6] = 0x00; fc0012_set_params()
171 reg[5] = 0x82; fc0012_set_params()
172 reg[6] = 0x02; fc0012_set_params()
175 reg[5] = 0x42; fc0012_set_params()
176 reg[6] = 0x00; fc0012_set_params()
179 reg[5] = 0x42; fc0012_set_params()
180 reg[6] = 0x02; fc0012_set_params()
183 reg[5] = 0x22; fc0012_set_params()
184 reg[6] = 0x00; fc0012_set_params()
187 reg[5] = 0x22; fc0012_set_params()
188 reg[6] = 0x02; fc0012_set_params()
191 reg[5] = 0x12; fc0012_set_params()
192 reg[6] = 0x00; fc0012_set_params()
195 reg[5] = 0x12; fc0012_set_params()
196 reg[6] = 0x02; fc0012_set_params()
199 reg[5] = 0x0a; fc0012_set_params()
200 reg[6] = 0x00; fc0012_set_params()
203 reg[5] = 0x0a; fc0012_set_params()
204 reg[6] = 0x02; fc0012_set_params()
210 reg[6] |= 0x08; fc0012_set_params()
224 reg[1] = am + 8; fc0012_set_params()
225 reg[2] = pm - 1; fc0012_set_params()
227 reg[1] = am; fc0012_set_params()
228 reg[2] = pm; fc0012_set_params()
232 reg[1] = 0x06; fc0012_set_params()
233 reg[2] = 0x11; fc0012_set_params()
237 reg[6] |= 0x20; fc0012_set_params()
246 reg[3] = xin >> 8; /* xin with 9 bit resolution */ fc0012_set_params()
247 reg[4] = xin & 0xff; fc0012_set_params()
250 reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */ fc0012_set_params()
253 reg[6] |= 0x80; fc0012_set_params()
256 reg[6] |= 0x40; fc0012_set_params()
269 reg[5] |= 0x07; fc0012_set_params()
275 ret = fc0012_writereg(priv, i, reg[i]); fc0012_set_params()
301 reg[6] &= ~0x08; fc0012_set_params()
302 ret = fc0012_writereg(priv, 0x06, reg[6]); fc0012_set_params()
310 reg[6] |= 0x08; fc0012_set_params()
311 ret = fc0012_writereg(priv, 0x06, reg[6]); fc0012_set_params()
H A Dfc0013.c27 static int fc0013_writereg(struct fc0013_priv *priv, u8 reg, u8 val) fc0013_writereg() argument
29 u8 buf[2] = {reg, val}; fc0013_writereg()
35 err("I2C write reg failed, reg: %02x, val: %02x", reg, val); fc0013_writereg()
41 static int fc0013_readreg(struct fc0013_priv *priv, u8 reg, u8 *val) fc0013_readreg() argument
44 { .addr = priv->addr, .flags = 0, .buf = &reg, .len = 1 }, fc0013_readreg()
49 err("I2C read reg failed, reg: %02x", reg); fc0013_readreg()
66 unsigned char reg[] = { fc0013_init() local
67 0x00, /* reg. 0x00: dummy */ fc0013_init()
68 0x09, /* reg. 0x01 */ fc0013_init()
69 0x16, /* reg. 0x02 */ fc0013_init()
70 0x00, /* reg. 0x03 */ fc0013_init()
71 0x00, /* reg. 0x04 */ fc0013_init()
72 0x17, /* reg. 0x05 */ fc0013_init()
73 0x02, /* reg. 0x06 */ fc0013_init()
74 0x0a, /* reg. 0x07: CHECK */ fc0013_init()
75 0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256, fc0013_init()
77 0x6f, /* reg. 0x09: enable LoopThrough */ fc0013_init()
78 0xb8, /* reg. 0x0a: Disable LO Test Buffer */ fc0013_init()
79 0x82, /* reg. 0x0b: CHECK */ fc0013_init()
80 0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */ fc0013_init()
81 0x01, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, may need 0x02 */ fc0013_init()
82 0x00, /* reg. 0x0e */ fc0013_init()
83 0x00, /* reg. 0x0f */ fc0013_init()
84 0x00, /* reg. 0x10 */ fc0013_init()
85 0x00, /* reg. 0x11 */ fc0013_init()
86 0x00, /* reg. 0x12 */ fc0013_init()
87 0x00, /* reg. 0x13 */ fc0013_init()
88 0x50, /* reg. 0x14: DVB-t High Gain, UHF. fc0013_init()
90 0x01, /* reg. 0x15 */ fc0013_init()
96 reg[0x07] |= 0x20; fc0013_init()
104 reg[0x0c] |= 0x02; fc0013_init()
109 for (i = 1; i < sizeof(reg); i++) { fc0013_init()
110 ret = fc0013_writereg(priv, i, reg[i]); fc0013_init()
233 unsigned char reg[7], am, pm, multi, tmp; fc0013_set_params() local
319 reg[5] = 0x82; fc0013_set_params()
320 reg[6] = 0x00; fc0013_set_params()
323 reg[5] = 0x02; fc0013_set_params()
324 reg[6] = 0x02; fc0013_set_params()
327 reg[5] = 0x42; fc0013_set_params()
328 reg[6] = 0x00; fc0013_set_params()
331 reg[5] = 0x82; fc0013_set_params()
332 reg[6] = 0x02; fc0013_set_params()
335 reg[5] = 0x22; fc0013_set_params()
336 reg[6] = 0x00; fc0013_set_params()
339 reg[5] = 0x42; fc0013_set_params()
340 reg[6] = 0x02; fc0013_set_params()
343 reg[5] = 0x12; fc0013_set_params()
344 reg[6] = 0x00; fc0013_set_params()
347 reg[5] = 0x22; fc0013_set_params()
348 reg[6] = 0x02; fc0013_set_params()
351 reg[5] = 0x0a; fc0013_set_params()
352 reg[6] = 0x00; fc0013_set_params()
355 reg[5] = 0x12; fc0013_set_params()
356 reg[6] = 0x02; fc0013_set_params()
359 reg[5] = 0x0a; fc0013_set_params()
360 reg[6] = 0x02; fc0013_set_params()
366 reg[6] |= 0x08; fc0013_set_params()
380 reg[1] = am + 8; fc0013_set_params()
381 reg[2] = pm - 1; fc0013_set_params()
383 reg[1] = am; fc0013_set_params()
384 reg[2] = pm; fc0013_set_params()
388 reg[1] = 0x06; fc0013_set_params()
389 reg[2] = 0x11; fc0013_set_params()
393 reg[6] |= 0x20; fc0013_set_params()
402 reg[3] = xin >> 8; fc0013_set_params()
403 reg[4] = xin & 0xff; fc0013_set_params()
406 reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */ fc0013_set_params()
409 reg[6] |= 0x80; fc0013_set_params()
412 reg[6] |= 0x40; fc0013_set_params()
424 reg[5] |= 0x07; fc0013_set_params()
427 ret = fc0013_writereg(priv, i, reg[i]); fc0013_set_params()
463 reg[6] &= ~0x08; fc0013_set_params()
464 ret = fc0013_writereg(priv, 0x06, reg[6]); fc0013_set_params()
472 reg[6] |= 0x08; fc0013_set_params()
473 ret = fc0013_writereg(priv, 0x06, reg[6]); fc0013_set_params()
/linux-4.1.27/drivers/net/wireless/rt2x00/
H A Drt2400pci.c59 u32 reg; rt2400pci_bbp_write() local
67 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { rt2400pci_bbp_write()
68 reg = 0; rt2400pci_bbp_write()
69 rt2x00_set_field32(&reg, BBPCSR_VALUE, value); rt2400pci_bbp_write()
70 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word); rt2400pci_bbp_write()
71 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1); rt2400pci_bbp_write()
72 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1); rt2400pci_bbp_write()
74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); rt2400pci_bbp_write()
83 u32 reg; rt2400pci_bbp_read() local
92 * doesn't become available in time, reg will be 0xffffffff rt2400pci_bbp_read()
95 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { rt2400pci_bbp_read()
96 reg = 0; rt2400pci_bbp_read()
97 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word); rt2400pci_bbp_read()
98 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1); rt2400pci_bbp_read()
99 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0); rt2400pci_bbp_read()
101 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); rt2400pci_bbp_read()
103 WAIT_FOR_BBP(rt2x00dev, &reg); rt2400pci_bbp_read()
106 *value = rt2x00_get_field32(reg, BBPCSR_VALUE); rt2400pci_bbp_read()
114 u32 reg; rt2400pci_rf_write() local
122 if (WAIT_FOR_RF(rt2x00dev, &reg)) { rt2400pci_rf_write()
123 reg = 0; rt2400pci_rf_write()
124 rt2x00_set_field32(&reg, RFCSR_VALUE, value); rt2400pci_rf_write()
125 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20); rt2400pci_rf_write()
126 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0); rt2400pci_rf_write()
127 rt2x00_set_field32(&reg, RFCSR_BUSY, 1); rt2400pci_rf_write()
129 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); rt2400pci_rf_write()
139 u32 reg; rt2400pci_eepromregister_read() local
141 rt2x00mmio_register_read(rt2x00dev, CSR21, &reg); rt2400pci_eepromregister_read()
143 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); rt2400pci_eepromregister_read()
144 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); rt2400pci_eepromregister_read()
146 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); rt2400pci_eepromregister_read()
148 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); rt2400pci_eepromregister_read()
154 u32 reg = 0; rt2400pci_eepromregister_write() local
156 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); rt2400pci_eepromregister_write()
157 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); rt2400pci_eepromregister_write()
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK, rt2400pci_eepromregister_write()
160 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT, rt2400pci_eepromregister_write()
163 rt2x00mmio_register_write(rt2x00dev, CSR21, reg); rt2400pci_eepromregister_write()
203 u32 reg; rt2400pci_rfkill_poll() local
205 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg); rt2400pci_rfkill_poll()
206 return rt2x00_get_field32(reg, GPIOCSR_VAL0); rt2400pci_rfkill_poll()
216 u32 reg; rt2400pci_brightness_set() local
218 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg); rt2400pci_brightness_set()
221 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled); rt2400pci_brightness_set()
223 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled); rt2400pci_brightness_set()
225 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); rt2400pci_brightness_set()
234 u32 reg; rt2400pci_blink_set() local
236 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg); rt2400pci_blink_set()
237 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on); rt2400pci_blink_set()
238 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off); rt2400pci_blink_set()
239 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); rt2400pci_blink_set()
262 u32 reg; rt2400pci_config_filter() local
269 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg); rt2400pci_config_filter()
270 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC, rt2400pci_config_filter()
272 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, rt2400pci_config_filter()
274 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, rt2400pci_config_filter()
276 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME, rt2400pci_config_filter()
278 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, rt2400pci_config_filter()
281 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1); rt2400pci_config_filter()
282 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); rt2400pci_config_filter()
291 u32 reg; rt2400pci_config_intf() local
298 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, &reg); rt2400pci_config_intf()
299 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload); rt2400pci_config_intf()
300 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); rt2400pci_config_intf()
305 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg); rt2400pci_config_intf()
306 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync); rt2400pci_config_intf()
307 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); rt2400pci_config_intf()
325 u32 reg; rt2400pci_config_erp() local
333 rt2x00mmio_register_read(rt2x00dev, TXCSR1, &reg); rt2400pci_config_erp()
334 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff); rt2400pci_config_erp()
335 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a); rt2400pci_config_erp()
336 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); rt2400pci_config_erp()
337 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1); rt2400pci_config_erp()
338 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); rt2400pci_config_erp()
340 rt2x00mmio_register_read(rt2x00dev, ARCSR2, &reg); rt2400pci_config_erp()
341 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00); rt2400pci_config_erp()
342 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04); rt2400pci_config_erp()
343 rt2x00_set_field32(&reg, ARCSR2_LENGTH, rt2400pci_config_erp()
345 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); rt2400pci_config_erp()
347 rt2x00mmio_register_read(rt2x00dev, ARCSR3, &reg); rt2400pci_config_erp()
348 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask); rt2400pci_config_erp()
349 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04); rt2400pci_config_erp()
350 rt2x00_set_field32(&reg, ARCSR2_LENGTH, rt2400pci_config_erp()
352 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); rt2400pci_config_erp()
354 rt2x00mmio_register_read(rt2x00dev, ARCSR4, &reg); rt2400pci_config_erp()
355 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask); rt2400pci_config_erp()
356 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04); rt2400pci_config_erp()
357 rt2x00_set_field32(&reg, ARCSR2_LENGTH, rt2400pci_config_erp()
359 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); rt2400pci_config_erp()
361 rt2x00mmio_register_read(rt2x00dev, ARCSR5, &reg); rt2400pci_config_erp()
362 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask); rt2400pci_config_erp()
363 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84); rt2400pci_config_erp()
364 rt2x00_set_field32(&reg, ARCSR2_LENGTH, rt2400pci_config_erp()
366 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); rt2400pci_config_erp()
373 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg); rt2400pci_config_erp()
374 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time); rt2400pci_config_erp()
375 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); rt2400pci_config_erp()
377 rt2x00mmio_register_read(rt2x00dev, CSR18, &reg); rt2400pci_config_erp()
378 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs); rt2400pci_config_erp()
379 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs); rt2400pci_config_erp()
380 rt2x00mmio_register_write(rt2x00dev, CSR18, reg); rt2400pci_config_erp()
382 rt2x00mmio_register_read(rt2x00dev, CSR19, &reg); rt2400pci_config_erp()
383 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs); rt2400pci_config_erp()
384 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs); rt2400pci_config_erp()
385 rt2x00mmio_register_write(rt2x00dev, CSR19, reg); rt2400pci_config_erp()
389 rt2x00mmio_register_read(rt2x00dev, CSR12, &reg); rt2400pci_config_erp()
390 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, rt2400pci_config_erp()
392 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, rt2400pci_config_erp()
394 rt2x00mmio_register_write(rt2x00dev, CSR12, reg); rt2400pci_config_erp()
509 u32 reg; rt2400pci_config_retry_limit() local
511 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg); rt2400pci_config_retry_limit()
512 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, rt2400pci_config_retry_limit()
514 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, rt2400pci_config_retry_limit()
516 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); rt2400pci_config_retry_limit()
525 u32 reg; rt2400pci_config_ps() local
528 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg); rt2400pci_config_ps()
529 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN, rt2400pci_config_ps()
531 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP, rt2400pci_config_ps()
535 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0); rt2400pci_config_ps()
536 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); rt2400pci_config_ps()
538 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1); rt2400pci_config_ps()
539 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); rt2400pci_config_ps()
541 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg); rt2400pci_config_ps()
542 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0); rt2400pci_config_ps()
543 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); rt2400pci_config_ps()
567 u32 reg; rt2400pci_config_cw() local
569 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg); rt2400pci_config_cw()
570 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min); rt2400pci_config_cw()
571 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max); rt2400pci_config_cw()
572 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); rt2400pci_config_cw()
581 u32 reg; rt2400pci_link_stats() local
587 rt2x00mmio_register_read(rt2x00dev, CNT0, &reg); rt2400pci_link_stats()
588 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); rt2400pci_link_stats()
638 u32 reg; rt2400pci_start_queue() local
642 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg); rt2400pci_start_queue()
643 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0); rt2400pci_start_queue()
644 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); rt2400pci_start_queue()
647 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg); rt2400pci_start_queue()
648 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1); rt2400pci_start_queue()
649 rt2x00_set_field32(&reg, CSR14_TBCN, 1); rt2400pci_start_queue()
650 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1); rt2400pci_start_queue()
651 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); rt2400pci_start_queue()
661 u32 reg; rt2400pci_kick_queue() local
665 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg); rt2400pci_kick_queue()
666 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1); rt2400pci_kick_queue()
667 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); rt2400pci_kick_queue()
670 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg); rt2400pci_kick_queue()
671 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1); rt2400pci_kick_queue()
672 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); rt2400pci_kick_queue()
675 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg); rt2400pci_kick_queue()
676 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1); rt2400pci_kick_queue()
677 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); rt2400pci_kick_queue()
687 u32 reg; rt2400pci_stop_queue() local
693 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg); rt2400pci_stop_queue()
694 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1); rt2400pci_stop_queue()
695 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); rt2400pci_stop_queue()
698 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg); rt2400pci_stop_queue()
699 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1); rt2400pci_stop_queue()
700 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); rt2400pci_stop_queue()
703 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg); rt2400pci_stop_queue()
704 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0); rt2400pci_stop_queue()
705 rt2x00_set_field32(&reg, CSR14_TBCN, 0); rt2400pci_stop_queue()
706 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); rt2400pci_stop_queue()
707 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); rt2400pci_stop_queue()
768 u32 reg; rt2400pci_init_queues() local
773 rt2x00mmio_register_read(rt2x00dev, TXCSR2, &reg); rt2400pci_init_queues()
774 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); rt2400pci_init_queues()
775 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); rt2400pci_init_queues()
776 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); rt2400pci_init_queues()
777 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); rt2400pci_init_queues()
778 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); rt2400pci_init_queues()
781 rt2x00mmio_register_read(rt2x00dev, TXCSR3, &reg); rt2400pci_init_queues()
782 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, rt2400pci_init_queues()
784 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); rt2400pci_init_queues()
787 rt2x00mmio_register_read(rt2x00dev, TXCSR5, &reg); rt2400pci_init_queues()
788 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, rt2400pci_init_queues()
790 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); rt2400pci_init_queues()
793 rt2x00mmio_register_read(rt2x00dev, TXCSR4, &reg); rt2400pci_init_queues()
794 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, rt2400pci_init_queues()
796 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); rt2400pci_init_queues()
799 rt2x00mmio_register_read(rt2x00dev, TXCSR6, &reg); rt2400pci_init_queues()
800 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, rt2400pci_init_queues()
802 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); rt2400pci_init_queues()
804 rt2x00mmio_register_read(rt2x00dev, RXCSR1, &reg); rt2400pci_init_queues()
805 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); rt2400pci_init_queues()
806 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); rt2400pci_init_queues()
807 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); rt2400pci_init_queues()
810 rt2x00mmio_register_read(rt2x00dev, RXCSR2, &reg); rt2400pci_init_queues()
811 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, rt2400pci_init_queues()
813 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); rt2400pci_init_queues()
820 u32 reg; rt2400pci_init_registers() local
827 rt2x00mmio_register_read(rt2x00dev, TIMECSR, &reg); rt2400pci_init_registers()
828 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33); rt2400pci_init_registers()
829 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63); rt2400pci_init_registers()
830 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0); rt2400pci_init_registers()
831 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); rt2400pci_init_registers()
833 rt2x00mmio_register_read(rt2x00dev, CSR9, &reg); rt2400pci_init_registers()
834 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT, rt2400pci_init_registers()
836 rt2x00mmio_register_write(rt2x00dev, CSR9, reg); rt2400pci_init_registers()
838 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg); rt2400pci_init_registers()
839 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0); rt2400pci_init_registers()
840 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0); rt2400pci_init_registers()
841 rt2x00_set_field32(&reg, CSR14_TBCN, 0); rt2400pci_init_registers()
842 rt2x00_set_field32(&reg, CSR14_TCFP, 0); rt2400pci_init_registers()
843 rt2x00_set_field32(&reg, CSR14_TATIMW, 0); rt2400pci_init_registers()
844 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); rt2400pci_init_registers()
845 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0); rt2400pci_init_registers()
846 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0); rt2400pci_init_registers()
847 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); rt2400pci_init_registers()
851 rt2x00mmio_register_read(rt2x00dev, ARCSR0, &reg); rt2400pci_init_registers()
852 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133); rt2400pci_init_registers()
853 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134); rt2400pci_init_registers()
854 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136); rt2400pci_init_registers()
855 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135); rt2400pci_init_registers()
856 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg); rt2400pci_init_registers()
858 rt2x00mmio_register_read(rt2x00dev, RXCSR3, &reg); rt2400pci_init_registers()
859 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/ rt2400pci_init_registers()
860 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1); rt2400pci_init_registers()
861 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */ rt2400pci_init_registers()
862 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1); rt2400pci_init_registers()
863 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */ rt2400pci_init_registers()
864 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1); rt2400pci_init_registers()
865 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); rt2400pci_init_registers()
875 rt2x00mmio_register_read(rt2x00dev, MACCSR2, &reg); rt2400pci_init_registers()
876 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64); rt2400pci_init_registers()
877 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); rt2400pci_init_registers()
879 rt2x00mmio_register_read(rt2x00dev, RALINKCSR, &reg); rt2400pci_init_registers()
880 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17); rt2400pci_init_registers()
881 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154); rt2400pci_init_registers()
882 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0); rt2400pci_init_registers()
883 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154); rt2400pci_init_registers()
884 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); rt2400pci_init_registers()
886 rt2x00mmio_register_read(rt2x00dev, CSR1, &reg); rt2400pci_init_registers()
887 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1); rt2400pci_init_registers()
888 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0); rt2400pci_init_registers()
889 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0); rt2400pci_init_registers()
890 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); rt2400pci_init_registers()
892 rt2x00mmio_register_read(rt2x00dev, CSR1, &reg); rt2400pci_init_registers()
893 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0); rt2400pci_init_registers()
894 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1); rt2400pci_init_registers()
895 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); rt2400pci_init_registers()
902 rt2x00mmio_register_read(rt2x00dev, CNT0, &reg); rt2400pci_init_registers()
903 rt2x00mmio_register_read(rt2x00dev, CNT4, &reg); rt2400pci_init_registers()
969 u32 reg; rt2400pci_toggle_irq() local
977 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg); rt2400pci_toggle_irq()
978 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); rt2400pci_toggle_irq()
987 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); rt2400pci_toggle_irq()
988 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask); rt2400pci_toggle_irq()
989 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask); rt2400pci_toggle_irq()
990 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask); rt2400pci_toggle_irq()
991 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask); rt2400pci_toggle_irq()
992 rt2x00_set_field32(&reg, CSR8_RXDONE, mask); rt2400pci_toggle_irq()
993 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); rt2400pci_toggle_irq()
1032 u32 reg, reg2; rt2400pci_set_state() local
1040 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg); rt2400pci_set_state()
1041 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1); rt2400pci_set_state()
1042 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state); rt2400pci_set_state()
1043 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state); rt2400pci_set_state()
1044 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); rt2400pci_set_state()
1045 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); rt2400pci_set_state()
1058 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); rt2400pci_set_state()
1177 u32 reg; rt2400pci_write_beacon() local
1183 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg); rt2400pci_write_beacon()
1184 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); rt2400pci_write_beacon()
1185 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); rt2400pci_write_beacon()
1194 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1); rt2400pci_write_beacon()
1208 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1); rt2400pci_write_beacon()
1209 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); rt2400pci_write_beacon()
1315 u32 reg; rt2400pci_enable_interrupt() local
1323 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); rt2400pci_enable_interrupt()
1324 rt2x00_set_field32(&reg, irq_field, 0); rt2400pci_enable_interrupt()
1325 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); rt2400pci_enable_interrupt()
1333 u32 reg; rt2400pci_txstatus_tasklet() local
1348 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); rt2400pci_txstatus_tasklet()
1349 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0); rt2400pci_txstatus_tasklet()
1350 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0); rt2400pci_txstatus_tasklet()
1351 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0); rt2400pci_txstatus_tasklet()
1352 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); rt2400pci_txstatus_tasklet()
1378 u32 reg, mask; rt2400pci_interrupt() local
1384 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg); rt2400pci_interrupt()
1385 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); rt2400pci_interrupt()
1387 if (!reg) rt2400pci_interrupt()
1393 mask = reg; rt2400pci_interrupt()
1398 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) rt2400pci_interrupt()
1401 if (rt2x00_get_field32(reg, CSR7_RXDONE)) rt2400pci_interrupt()
1404 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || rt2400pci_interrupt()
1405 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || rt2400pci_interrupt()
1406 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { rt2400pci_interrupt()
1422 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); rt2400pci_interrupt()
1423 reg |= mask; rt2400pci_interrupt()
1424 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); rt2400pci_interrupt()
1439 u32 reg; rt2400pci_validate_eeprom() local
1443 rt2x00mmio_register_read(rt2x00dev, CSR21, &reg); rt2400pci_validate_eeprom()
1448 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? rt2400pci_validate_eeprom()
1478 u32 reg; rt2400pci_init_eeprom() local
1491 rt2x00mmio_register_read(rt2x00dev, CSR0, &reg); rt2400pci_init_eeprom()
1493 rt2x00_get_field32(reg, CSR0_REVISION)); rt2400pci_init_eeprom()
1619 u32 reg; rt2400pci_probe_hw() local
1636 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg); rt2400pci_probe_hw()
1637 rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1); rt2400pci_probe_hw()
1638 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); rt2400pci_probe_hw()
1696 u32 reg; rt2400pci_get_tsf() local
1698 rt2x00mmio_register_read(rt2x00dev, CSR17, &reg); rt2400pci_get_tsf()
1699 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; rt2400pci_get_tsf()
1700 rt2x00mmio_register_read(rt2x00dev, CSR16, &reg); rt2400pci_get_tsf()
1701 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); rt2400pci_get_tsf()
1709 u32 reg; rt2400pci_tx_last_beacon() local
1711 rt2x00mmio_register_read(rt2x00dev, CSR15, &reg); rt2400pci_tx_last_beacon()
1712 return rt2x00_get_field32(reg, CSR15_BEACON_SENT); rt2400pci_tx_last_beacon()
H A Drt2500pci.c59 u32 reg; rt2500pci_bbp_write() local
67 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { rt2500pci_bbp_write()
68 reg = 0; rt2500pci_bbp_write()
69 rt2x00_set_field32(&reg, BBPCSR_VALUE, value); rt2500pci_bbp_write()
70 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word); rt2500pci_bbp_write()
71 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1); rt2500pci_bbp_write()
72 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1); rt2500pci_bbp_write()
74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); rt2500pci_bbp_write()
83 u32 reg; rt2500pci_bbp_read() local
92 * doesn't become available in time, reg will be 0xffffffff rt2500pci_bbp_read()
95 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { rt2500pci_bbp_read()
96 reg = 0; rt2500pci_bbp_read()
97 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word); rt2500pci_bbp_read()
98 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1); rt2500pci_bbp_read()
99 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0); rt2500pci_bbp_read()
101 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); rt2500pci_bbp_read()
103 WAIT_FOR_BBP(rt2x00dev, &reg); rt2500pci_bbp_read()
106 *value = rt2x00_get_field32(reg, BBPCSR_VALUE); rt2500pci_bbp_read()
114 u32 reg; rt2500pci_rf_write() local
122 if (WAIT_FOR_RF(rt2x00dev, &reg)) { rt2500pci_rf_write()
123 reg = 0; rt2500pci_rf_write()
124 rt2x00_set_field32(&reg, RFCSR_VALUE, value); rt2500pci_rf_write()
125 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20); rt2500pci_rf_write()
126 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0); rt2500pci_rf_write()
127 rt2x00_set_field32(&reg, RFCSR_BUSY, 1); rt2500pci_rf_write()
129 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); rt2500pci_rf_write()
139 u32 reg; rt2500pci_eepromregister_read() local
141 rt2x00mmio_register_read(rt2x00dev, CSR21, &reg); rt2500pci_eepromregister_read()
143 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); rt2500pci_eepromregister_read()
144 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); rt2500pci_eepromregister_read()
146 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); rt2500pci_eepromregister_read()
148 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); rt2500pci_eepromregister_read()
154 u32 reg = 0; rt2500pci_eepromregister_write() local
156 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); rt2500pci_eepromregister_write()
157 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); rt2500pci_eepromregister_write()
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK, rt2500pci_eepromregister_write()
160 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT, rt2500pci_eepromregister_write()
163 rt2x00mmio_register_write(rt2x00dev, CSR21, reg); rt2500pci_eepromregister_write()
203 u32 reg; rt2500pci_rfkill_poll() local
205 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg); rt2500pci_rfkill_poll()
206 return rt2x00_get_field32(reg, GPIOCSR_VAL0); rt2500pci_rfkill_poll()
216 u32 reg; rt2500pci_brightness_set() local
218 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg); rt2500pci_brightness_set()
221 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled); rt2500pci_brightness_set()
223 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled); rt2500pci_brightness_set()
225 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); rt2500pci_brightness_set()
234 u32 reg; rt2500pci_blink_set() local
236 rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg); rt2500pci_blink_set()
237 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on); rt2500pci_blink_set()
238 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off); rt2500pci_blink_set()
239 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); rt2500pci_blink_set()
262 u32 reg; rt2500pci_config_filter() local
270 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg); rt2500pci_config_filter()
271 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC, rt2500pci_config_filter()
273 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, rt2500pci_config_filter()
275 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, rt2500pci_config_filter()
277 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME, rt2500pci_config_filter()
279 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, rt2500pci_config_filter()
282 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1); rt2500pci_config_filter()
283 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST, rt2500pci_config_filter()
285 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0); rt2500pci_config_filter()
286 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); rt2500pci_config_filter()
296 u32 reg; rt2500pci_config_intf() local
303 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, &reg); rt2500pci_config_intf()
304 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload); rt2500pci_config_intf()
305 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min); rt2500pci_config_intf()
306 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); rt2500pci_config_intf()
311 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg); rt2500pci_config_intf()
312 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync); rt2500pci_config_intf()
313 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); rt2500pci_config_intf()
330 u32 reg; rt2500pci_config_erp() local
338 rt2x00mmio_register_read(rt2x00dev, TXCSR1, &reg); rt2500pci_config_erp()
339 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162); rt2500pci_config_erp()
340 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2); rt2500pci_config_erp()
341 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); rt2500pci_config_erp()
342 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1); rt2500pci_config_erp()
343 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); rt2500pci_config_erp()
345 rt2x00mmio_register_read(rt2x00dev, ARCSR2, &reg); rt2500pci_config_erp()
346 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00); rt2500pci_config_erp()
347 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04); rt2500pci_config_erp()
348 rt2x00_set_field32(&reg, ARCSR2_LENGTH, rt2500pci_config_erp()
350 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); rt2500pci_config_erp()
352 rt2x00mmio_register_read(rt2x00dev, ARCSR3, &reg); rt2500pci_config_erp()
353 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask); rt2500pci_config_erp()
354 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04); rt2500pci_config_erp()
355 rt2x00_set_field32(&reg, ARCSR2_LENGTH, rt2500pci_config_erp()
357 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); rt2500pci_config_erp()
359 rt2x00mmio_register_read(rt2x00dev, ARCSR4, &reg); rt2500pci_config_erp()
360 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask); rt2500pci_config_erp()
361 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04); rt2500pci_config_erp()
362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, rt2500pci_config_erp()
364 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); rt2500pci_config_erp()
366 rt2x00mmio_register_read(rt2x00dev, ARCSR5, &reg); rt2500pci_config_erp()
367 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask); rt2500pci_config_erp()
368 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84); rt2500pci_config_erp()
369 rt2x00_set_field32(&reg, ARCSR2_LENGTH, rt2500pci_config_erp()
371 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); rt2500pci_config_erp()
378 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg); rt2500pci_config_erp()
379 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time); rt2500pci_config_erp()
380 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); rt2500pci_config_erp()
382 rt2x00mmio_register_read(rt2x00dev, CSR18, &reg); rt2500pci_config_erp()
383 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs); rt2500pci_config_erp()
384 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs); rt2500pci_config_erp()
385 rt2x00mmio_register_write(rt2x00dev, CSR18, reg); rt2500pci_config_erp()
387 rt2x00mmio_register_read(rt2x00dev, CSR19, &reg); rt2500pci_config_erp()
388 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs); rt2500pci_config_erp()
389 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs); rt2500pci_config_erp()
390 rt2x00mmio_register_write(rt2x00dev, CSR19, reg); rt2500pci_config_erp()
394 rt2x00mmio_register_read(rt2x00dev, CSR12, &reg); rt2500pci_config_erp()
395 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, rt2500pci_config_erp()
397 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, rt2500pci_config_erp()
399 rt2x00mmio_register_write(rt2x00dev, CSR12, reg); rt2500pci_config_erp()
407 u32 reg; rt2500pci_config_ant() local
418 rt2x00mmio_register_read(rt2x00dev, BBPCSR1, &reg); rt2500pci_config_ant()
428 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0); rt2500pci_config_ant()
429 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0); rt2500pci_config_ant()
434 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2); rt2500pci_config_ant()
435 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2); rt2500pci_config_ant()
457 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1); rt2500pci_config_ant()
458 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1); rt2500pci_config_ant()
466 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0); rt2500pci_config_ant()
467 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0); rt2500pci_config_ant()
470 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg); rt2500pci_config_ant()
557 u32 reg; rt2500pci_config_retry_limit() local
559 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg); rt2500pci_config_retry_limit()
560 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, rt2500pci_config_retry_limit()
562 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, rt2500pci_config_retry_limit()
564 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); rt2500pci_config_retry_limit()
573 u32 reg; rt2500pci_config_ps() local
576 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg); rt2500pci_config_ps()
577 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN, rt2500pci_config_ps()
579 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP, rt2500pci_config_ps()
583 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0); rt2500pci_config_ps()
584 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); rt2500pci_config_ps()
586 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1); rt2500pci_config_ps()
587 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); rt2500pci_config_ps()
589 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg); rt2500pci_config_ps()
590 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0); rt2500pci_config_ps()
591 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); rt2500pci_config_ps()
620 u32 reg; rt2500pci_link_stats() local
625 rt2x00mmio_register_read(rt2x00dev, CNT0, &reg); rt2500pci_link_stats()
626 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); rt2500pci_link_stats()
631 rt2x00mmio_register_read(rt2x00dev, CNT3, &reg); rt2500pci_link_stats()
632 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA); rt2500pci_link_stats()
727 u32 reg; rt2500pci_start_queue() local
731 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg); rt2500pci_start_queue()
732 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0); rt2500pci_start_queue()
733 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); rt2500pci_start_queue()
736 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg); rt2500pci_start_queue()
737 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1); rt2500pci_start_queue()
738 rt2x00_set_field32(&reg, CSR14_TBCN, 1); rt2500pci_start_queue()
739 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1); rt2500pci_start_queue()
740 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); rt2500pci_start_queue()
750 u32 reg; rt2500pci_kick_queue() local
754 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg); rt2500pci_kick_queue()
755 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1); rt2500pci_kick_queue()
756 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); rt2500pci_kick_queue()
759 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg); rt2500pci_kick_queue()
760 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1); rt2500pci_kick_queue()
761 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); rt2500pci_kick_queue()
764 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg); rt2500pci_kick_queue()
765 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1); rt2500pci_kick_queue()
766 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); rt2500pci_kick_queue()
776 u32 reg; rt2500pci_stop_queue() local
782 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg); rt2500pci_stop_queue()
783 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1); rt2500pci_stop_queue()
784 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); rt2500pci_stop_queue()
787 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg); rt2500pci_stop_queue()
788 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1); rt2500pci_stop_queue()
789 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); rt2500pci_stop_queue()
792 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg); rt2500pci_stop_queue()
793 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0); rt2500pci_stop_queue()
794 rt2x00_set_field32(&reg, CSR14_TBCN, 0); rt2500pci_stop_queue()
795 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); rt2500pci_stop_queue()
796 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); rt2500pci_stop_queue()
853 u32 reg; rt2500pci_init_queues() local
858 rt2x00mmio_register_read(rt2x00dev, TXCSR2, &reg); rt2500pci_init_queues()
859 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); rt2500pci_init_queues()
860 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); rt2500pci_init_queues()
861 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); rt2500pci_init_queues()
862 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); rt2500pci_init_queues()
863 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); rt2500pci_init_queues()
866 rt2x00mmio_register_read(rt2x00dev, TXCSR3, &reg); rt2500pci_init_queues()
867 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, rt2500pci_init_queues()
869 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); rt2500pci_init_queues()
872 rt2x00mmio_register_read(rt2x00dev, TXCSR5, &reg); rt2500pci_init_queues()
873 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, rt2500pci_init_queues()
875 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); rt2500pci_init_queues()
878 rt2x00mmio_register_read(rt2x00dev, TXCSR4, &reg); rt2500pci_init_queues()
879 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, rt2500pci_init_queues()
881 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); rt2500pci_init_queues()
884 rt2x00mmio_register_read(rt2x00dev, TXCSR6, &reg); rt2500pci_init_queues()
885 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, rt2500pci_init_queues()
887 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); rt2500pci_init_queues()
889 rt2x00mmio_register_read(rt2x00dev, RXCSR1, &reg); rt2500pci_init_queues()
890 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); rt2500pci_init_queues()
891 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); rt2500pci_init_queues()
892 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); rt2500pci_init_queues()
895 rt2x00mmio_register_read(rt2x00dev, RXCSR2, &reg); rt2500pci_init_queues()
896 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, rt2500pci_init_queues()
898 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); rt2500pci_init_queues()
905 u32 reg; rt2500pci_init_registers() local
912 rt2x00mmio_register_read(rt2x00dev, TIMECSR, &reg); rt2500pci_init_registers()
913 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33); rt2500pci_init_registers()
914 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63); rt2500pci_init_registers()
915 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0); rt2500pci_init_registers()
916 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); rt2500pci_init_registers()
918 rt2x00mmio_register_read(rt2x00dev, CSR9, &reg); rt2500pci_init_registers()
919 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT, rt2500pci_init_registers()
921 rt2x00mmio_register_write(rt2x00dev, CSR9, reg); rt2500pci_init_registers()
926 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg); rt2500pci_init_registers()
927 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0); rt2500pci_init_registers()
928 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); rt2500pci_init_registers()
930 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg); rt2500pci_init_registers()
931 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0); rt2500pci_init_registers()
932 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0); rt2500pci_init_registers()
933 rt2x00_set_field32(&reg, CSR14_TBCN, 0); rt2500pci_init_registers()
934 rt2x00_set_field32(&reg, CSR14_TCFP, 0); rt2500pci_init_registers()
935 rt2x00_set_field32(&reg, CSR14_TATIMW, 0); rt2500pci_init_registers()
936 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); rt2500pci_init_registers()
937 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0); rt2500pci_init_registers()
938 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0); rt2500pci_init_registers()
939 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); rt2500pci_init_registers()
943 rt2x00mmio_register_read(rt2x00dev, TXCSR8, &reg); rt2500pci_init_registers()
944 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10); rt2500pci_init_registers()
945 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1); rt2500pci_init_registers()
946 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11); rt2500pci_init_registers()
947 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1); rt2500pci_init_registers()
948 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13); rt2500pci_init_registers()
949 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1); rt2500pci_init_registers()
950 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12); rt2500pci_init_registers()
951 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1); rt2500pci_init_registers()
952 rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg); rt2500pci_init_registers()
954 rt2x00mmio_register_read(rt2x00dev, ARTCSR0, &reg); rt2500pci_init_registers()
955 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112); rt2500pci_init_registers()
956 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56); rt2500pci_init_registers()
957 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20); rt2500pci_init_registers()
958 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10); rt2500pci_init_registers()
959 rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg); rt2500pci_init_registers()
961 rt2x00mmio_register_read(rt2x00dev, ARTCSR1, &reg); rt2500pci_init_registers()
962 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45); rt2500pci_init_registers()
963 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37); rt2500pci_init_registers()
964 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33); rt2500pci_init_registers()
965 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29); rt2500pci_init_registers()
966 rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg); rt2500pci_init_registers()
968 rt2x00mmio_register_read(rt2x00dev, ARTCSR2, &reg); rt2500pci_init_registers()
969 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29); rt2500pci_init_registers()
970 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25); rt2500pci_init_registers()
971 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25); rt2500pci_init_registers()
972 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25); rt2500pci_init_registers()
973 rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg); rt2500pci_init_registers()
975 rt2x00mmio_register_read(rt2x00dev, RXCSR3, &reg); rt2500pci_init_registers()
976 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */ rt2500pci_init_registers()
977 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1); rt2500pci_init_registers()
978 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */ rt2500pci_init_registers()
979 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1); rt2500pci_init_registers()
980 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */ rt2500pci_init_registers()
981 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1); rt2500pci_init_registers()
982 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */ rt2500pci_init_registers()
983 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1); rt2500pci_init_registers()
984 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); rt2500pci_init_registers()
986 rt2x00mmio_register_read(rt2x00dev, PCICSR, &reg); rt2500pci_init_registers()
987 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0); rt2500pci_init_registers()
988 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0); rt2500pci_init_registers()
989 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3); rt2500pci_init_registers()
990 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1); rt2500pci_init_registers()
991 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1); rt2500pci_init_registers()
992 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1); rt2500pci_init_registers()
993 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1); rt2500pci_init_registers()
994 rt2x00mmio_register_write(rt2x00dev, PCICSR, reg); rt2500pci_init_registers()
1007 rt2x00mmio_register_read(rt2x00dev, MACCSR2, &reg); rt2500pci_init_registers()
1008 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64); rt2500pci_init_registers()
1009 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); rt2500pci_init_registers()
1011 rt2x00mmio_register_read(rt2x00dev, RALINKCSR, &reg); rt2500pci_init_registers()
1012 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17); rt2500pci_init_registers()
1013 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26); rt2500pci_init_registers()
1014 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1); rt2500pci_init_registers()
1015 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0); rt2500pci_init_registers()
1016 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26); rt2500pci_init_registers()
1017 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1); rt2500pci_init_registers()
1018 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); rt2500pci_init_registers()
1024 rt2x00mmio_register_read(rt2x00dev, CSR1, &reg); rt2500pci_init_registers()
1025 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1); rt2500pci_init_registers()
1026 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0); rt2500pci_init_registers()
1027 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0); rt2500pci_init_registers()
1028 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); rt2500pci_init_registers()
1030 rt2x00mmio_register_read(rt2x00dev, CSR1, &reg); rt2500pci_init_registers()
1031 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0); rt2500pci_init_registers()
1032 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1); rt2500pci_init_registers()
1033 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); rt2500pci_init_registers()
1040 rt2x00mmio_register_read(rt2x00dev, CNT0, &reg); rt2500pci_init_registers()
1041 rt2x00mmio_register_read(rt2x00dev, CNT4, &reg); rt2500pci_init_registers()
1123 u32 reg; rt2500pci_toggle_irq() local
1131 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg); rt2500pci_toggle_irq()
1132 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); rt2500pci_toggle_irq()
1141 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); rt2500pci_toggle_irq()
1142 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask); rt2500pci_toggle_irq()
1143 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask); rt2500pci_toggle_irq()
1144 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask); rt2500pci_toggle_irq()
1145 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask); rt2500pci_toggle_irq()
1146 rt2x00_set_field32(&reg, CSR8_RXDONE, mask); rt2500pci_toggle_irq()
1147 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); rt2500pci_toggle_irq()
1185 u32 reg, reg2; rt2500pci_set_state() local
1193 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg); rt2500pci_set_state()
1194 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1); rt2500pci_set_state()
1195 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state); rt2500pci_set_state()
1196 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state); rt2500pci_set_state()
1197 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); rt2500pci_set_state()
1198 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); rt2500pci_set_state()
1211 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); rt2500pci_set_state()
1329 u32 reg; rt2500pci_write_beacon() local
1335 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg); rt2500pci_write_beacon()
1336 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); rt2500pci_write_beacon()
1337 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); rt2500pci_write_beacon()
1357 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1); rt2500pci_write_beacon()
1358 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); rt2500pci_write_beacon()
1443 u32 reg; rt2500pci_enable_interrupt() local
1451 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); rt2500pci_enable_interrupt()
1452 rt2x00_set_field32(&reg, irq_field, 0); rt2500pci_enable_interrupt()
1453 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); rt2500pci_enable_interrupt()
1461 u32 reg; rt2500pci_txstatus_tasklet() local
1476 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); rt2500pci_txstatus_tasklet()
1477 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0); rt2500pci_txstatus_tasklet()
1478 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0); rt2500pci_txstatus_tasklet()
1479 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0); rt2500pci_txstatus_tasklet()
1480 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); rt2500pci_txstatus_tasklet()
1506 u32 reg, mask; rt2500pci_interrupt() local
1512 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg); rt2500pci_interrupt()
1513 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); rt2500pci_interrupt()
1515 if (!reg) rt2500pci_interrupt()
1521 mask = reg; rt2500pci_interrupt()
1526 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) rt2500pci_interrupt()
1529 if (rt2x00_get_field32(reg, CSR7_RXDONE)) rt2500pci_interrupt()
1532 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || rt2500pci_interrupt()
1533 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || rt2500pci_interrupt()
1534 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { rt2500pci_interrupt()
1550 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg); rt2500pci_interrupt()
1551 reg |= mask; rt2500pci_interrupt()
1552 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); rt2500pci_interrupt()
1565 u32 reg; rt2500pci_validate_eeprom() local
1569 rt2x00mmio_register_read(rt2x00dev, CSR21, &reg); rt2500pci_validate_eeprom()
1574 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? rt2500pci_validate_eeprom()
1632 u32 reg; rt2500pci_init_eeprom() local
1645 rt2x00mmio_register_read(rt2x00dev, CSR0, &reg); rt2500pci_init_eeprom()
1647 rt2x00_get_field32(reg, CSR0_REVISION)); rt2500pci_init_eeprom()
1944 u32 reg; rt2500pci_probe_hw() local
1961 rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg); rt2500pci_probe_hw()
1962 rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1); rt2500pci_probe_hw()
1963 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); rt2500pci_probe_hw()
1995 u32 reg; rt2500pci_get_tsf() local
1997 rt2x00mmio_register_read(rt2x00dev, CSR17, &reg); rt2500pci_get_tsf()
1998 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; rt2500pci_get_tsf()
1999 rt2x00mmio_register_read(rt2x00dev, CSR16, &reg); rt2500pci_get_tsf()
2000 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); rt2500pci_get_tsf()
2008 u32 reg; rt2500pci_tx_last_beacon() local
2010 rt2x00mmio_register_read(rt2x00dev, CSR15, &reg); rt2500pci_tx_last_beacon()
2011 return rt2x00_get_field32(reg, CSR15_BEACON_SENT); rt2500pci_tx_last_beacon()
H A Drt2500usb.c62 __le16 reg; rt2500usb_register_read() local
65 &reg, sizeof(reg)); rt2500usb_register_read()
66 *value = le16_to_cpu(reg); rt2500usb_register_read()
73 __le16 reg; rt2500usb_register_read_lock() local
76 &reg, sizeof(reg), REGISTER_TIMEOUT); rt2500usb_register_read_lock()
77 *value = le16_to_cpu(reg); rt2500usb_register_read_lock()
93 __le16 reg = cpu_to_le16(value); rt2500usb_register_write() local
96 &reg, sizeof(reg)); rt2500usb_register_write()
103 __le16 reg = cpu_to_le16(value); rt2500usb_register_write_lock() local
106 &reg, sizeof(reg), REGISTER_TIMEOUT); rt2500usb_register_write_lock()
121 u16 *reg) rt2500usb_regbusy_read()
126 rt2500usb_register_read_lock(rt2x00dev, offset, reg); rt2500usb_regbusy_read()
127 if (!rt2x00_get_field16(*reg, field)) rt2500usb_regbusy_read()
133 offset, *reg); rt2500usb_regbusy_read()
134 *reg = ~0; rt2500usb_regbusy_read()
147 u16 reg; rt2500usb_bbp_write() local
155 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { rt2500usb_bbp_write()
156 reg = 0; rt2500usb_bbp_write()
157 rt2x00_set_field16(&reg, PHY_CSR7_DATA, value); rt2500usb_bbp_write()
158 rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word); rt2500usb_bbp_write()
159 rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 0); rt2500usb_bbp_write()
161 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg); rt2500usb_bbp_write()
170 u16 reg; rt2500usb_bbp_read() local
179 * doesn't become available in time, reg will be 0xffffffff rt2500usb_bbp_read()
182 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { rt2500usb_bbp_read()
183 reg = 0; rt2500usb_bbp_read()
184 rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word); rt2500usb_bbp_read()
185 rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 1); rt2500usb_bbp_read()
187 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg); rt2500usb_bbp_read()
189 if (WAIT_FOR_BBP(rt2x00dev, &reg)) rt2500usb_bbp_read()
190 rt2500usb_register_read_lock(rt2x00dev, PHY_CSR7, &reg); rt2500usb_bbp_read()
193 *value = rt2x00_get_field16(reg, PHY_CSR7_DATA); rt2500usb_bbp_read()
201 u16 reg; rt2500usb_rf_write() local
209 if (WAIT_FOR_RF(rt2x00dev, &reg)) { rt2500usb_rf_write()
210 reg = 0; rt2500usb_rf_write()
211 rt2x00_set_field16(&reg, PHY_CSR9_RF_VALUE, value); rt2500usb_rf_write()
212 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR9, reg); rt2500usb_rf_write()
214 reg = 0; rt2500usb_rf_write()
215 rt2x00_set_field16(&reg, PHY_CSR10_RF_VALUE, value >> 16); rt2500usb_rf_write()
216 rt2x00_set_field16(&reg, PHY_CSR10_RF_NUMBER_OF_BITS, 20); rt2500usb_rf_write()
217 rt2x00_set_field16(&reg, PHY_CSR10_RF_IF_SELECT, 0); rt2500usb_rf_write()
218 rt2x00_set_field16(&reg, PHY_CSR10_RF_BUSY, 1); rt2500usb_rf_write()
220 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR10, reg); rt2500usb_rf_write()
278 u16 reg; rt2500usb_rfkill_poll() local
280 rt2500usb_register_read(rt2x00dev, MAC_CSR19, &reg); rt2500usb_rfkill_poll()
281 return rt2x00_get_field16(reg, MAC_CSR19_VAL7); rt2500usb_rfkill_poll()
291 u16 reg; rt2500usb_brightness_set() local
293 rt2500usb_register_read(led->rt2x00dev, MAC_CSR20, &reg); rt2500usb_brightness_set()
296 rt2x00_set_field16(&reg, MAC_CSR20_LINK, enabled); rt2500usb_brightness_set()
298 rt2x00_set_field16(&reg, MAC_CSR20_ACTIVITY, enabled); rt2500usb_brightness_set()
300 rt2500usb_register_write(led->rt2x00dev, MAC_CSR20, reg); rt2500usb_brightness_set()
309 u16 reg; rt2500usb_blink_set() local
311 rt2500usb_register_read(led->rt2x00dev, MAC_CSR21, &reg); rt2500usb_blink_set()
312 rt2x00_set_field16(&reg, MAC_CSR21_ON_PERIOD, *delay_on); rt2500usb_blink_set()
313 rt2x00_set_field16(&reg, MAC_CSR21_OFF_PERIOD, *delay_off); rt2500usb_blink_set()
314 rt2500usb_register_write(led->rt2x00dev, MAC_CSR21, reg); rt2500usb_blink_set()
344 u16 reg; rt2500usb_config_key() local
365 rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg); rt2500usb_config_key()
366 curr_cipher = rt2x00_get_field16(reg, TXRX_CSR0_ALGORITHM); rt2500usb_config_key()
367 reg &= mask; rt2500usb_config_key()
369 if (reg && reg == mask) rt2500usb_config_key()
372 reg = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID); rt2500usb_config_key()
374 key->hw_key_idx += reg ? ffz(reg) : 0; rt2500usb_config_key()
404 rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg); rt2500usb_config_key()
405 rt2x00_set_field16(&reg, TXRX_CSR0_ALGORITHM, crypto->cipher); rt2500usb_config_key()
406 rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER); rt2500usb_config_key()
408 mask = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID); rt2500usb_config_key()
413 rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, mask); rt2500usb_config_key()
414 rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg); rt2500usb_config_key()
422 u16 reg; rt2500usb_config_filter() local
430 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg); rt2500usb_config_filter()
431 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CRC, rt2500usb_config_filter()
433 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_PHYSICAL, rt2500usb_config_filter()
435 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CONTROL, rt2500usb_config_filter()
437 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_NOT_TO_ME, rt2500usb_config_filter()
439 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_TODS, rt2500usb_config_filter()
442 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_VERSION_ERROR, 1); rt2500usb_config_filter()
443 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_MULTICAST, rt2500usb_config_filter()
445 rt2x00_set_field16(&reg, TXRX_CSR2_DROP_BROADCAST, 0); rt2500usb_config_filter()
446 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg); rt2500usb_config_filter()
455 u16 reg; rt2500usb_config_intf() local
462 rt2500usb_register_read(rt2x00dev, TXRX_CSR20, &reg); rt2500usb_config_intf()
463 rt2x00_set_field16(&reg, TXRX_CSR20_OFFSET, bcn_preload >> 6); rt2500usb_config_intf()
464 rt2x00_set_field16(&reg, TXRX_CSR20_BCN_EXPECT_WINDOW, rt2500usb_config_intf()
466 rt2500usb_register_write(rt2x00dev, TXRX_CSR20, reg); rt2500usb_config_intf()
471 rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg); rt2500usb_config_intf()
472 rt2x00_set_field16(&reg, TXRX_CSR18_OFFSET, 0); rt2500usb_config_intf()
473 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg); rt2500usb_config_intf()
475 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg); rt2500usb_config_intf()
476 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, conf->sync); rt2500usb_config_intf()
477 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); rt2500usb_config_intf()
493 u16 reg; rt2500usb_config_erp() local
496 rt2500usb_register_read(rt2x00dev, TXRX_CSR10, &reg); rt2500usb_config_erp()
497 rt2x00_set_field16(&reg, TXRX_CSR10_AUTORESPOND_PREAMBLE, rt2500usb_config_erp()
499 rt2500usb_register_write(rt2x00dev, TXRX_CSR10, reg); rt2500usb_config_erp()
507 rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg); rt2500usb_config_erp()
508 rt2x00_set_field16(&reg, TXRX_CSR18_INTERVAL, rt2500usb_config_erp()
510 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg); rt2500usb_config_erp()
649 u16 reg; rt2500usb_config_ps() local
652 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg); rt2500usb_config_ps()
653 rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON, rt2500usb_config_ps()
655 rt2x00_set_field16(&reg, MAC_CSR18_BEACONS_BEFORE_WAKEUP, rt2500usb_config_ps()
659 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 0); rt2500usb_config_ps()
660 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg); rt2500usb_config_ps()
662 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 1); rt2500usb_config_ps()
663 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg); rt2500usb_config_ps()
665 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg); rt2500usb_config_ps()
666 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 0); rt2500usb_config_ps()
667 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg); rt2500usb_config_ps()
694 u16 reg; rt2500usb_link_stats() local
699 rt2500usb_register_read(rt2x00dev, STA_CSR0, &reg); rt2500usb_link_stats()
700 qual->rx_failed = rt2x00_get_field16(reg, STA_CSR0_FCS_ERROR); rt2500usb_link_stats()
705 rt2500usb_register_read(rt2x00dev, STA_CSR3, &reg); rt2500usb_link_stats()
706 qual->false_cca = rt2x00_get_field16(reg, STA_CSR3_FALSE_CCA_ERROR); rt2500usb_link_stats()
740 u16 reg; rt2500usb_start_queue() local
744 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg); rt2500usb_start_queue()
745 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 0); rt2500usb_start_queue()
746 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg); rt2500usb_start_queue()
749 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg); rt2500usb_start_queue()
750 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1); rt2500usb_start_queue()
751 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1); rt2500usb_start_queue()
752 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1); rt2500usb_start_queue()
753 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); rt2500usb_start_queue()
763 u16 reg; rt2500usb_stop_queue() local
767 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg); rt2500usb_stop_queue()
768 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 1); rt2500usb_stop_queue()
769 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg); rt2500usb_stop_queue()
772 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg); rt2500usb_stop_queue()
773 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 0); rt2500usb_stop_queue()
774 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 0); rt2500usb_stop_queue()
775 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0); rt2500usb_stop_queue()
776 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); rt2500usb_stop_queue()
788 u16 reg; rt2500usb_init_registers() local
795 rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg); rt2500usb_init_registers()
796 rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 1); rt2500usb_init_registers()
797 rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg); rt2500usb_init_registers()
802 rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg); rt2500usb_init_registers()
803 rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 1); rt2500usb_init_registers()
804 rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 1); rt2500usb_init_registers()
805 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0); rt2500usb_init_registers()
806 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg); rt2500usb_init_registers()
808 rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg); rt2500usb_init_registers()
809 rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0); rt2500usb_init_registers()
810 rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0); rt2500usb_init_registers()
811 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0); rt2500usb_init_registers()
812 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg); rt2500usb_init_registers()
814 rt2500usb_register_read(rt2x00dev, TXRX_CSR5, &reg); rt2500usb_init_registers()
815 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0, 13); rt2500usb_init_registers()
816 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0_VALID, 1); rt2500usb_init_registers()
817 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1, 12); rt2500usb_init_registers()
818 rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1_VALID, 1); rt2500usb_init_registers()
819 rt2500usb_register_write(rt2x00dev, TXRX_CSR5, reg); rt2500usb_init_registers()
821 rt2500usb_register_read(rt2x00dev, TXRX_CSR6, &reg); rt2500usb_init_registers()
822 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0, 10); rt2500usb_init_registers()
823 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0_VALID, 1); rt2500usb_init_registers()
824 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1, 11); rt2500usb_init_registers()
825 rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1_VALID, 1); rt2500usb_init_registers()
826 rt2500usb_register_write(rt2x00dev, TXRX_CSR6, reg); rt2500usb_init_registers()
828 rt2500usb_register_read(rt2x00dev, TXRX_CSR7, &reg); rt2500usb_init_registers()
829 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0, 7); rt2500usb_init_registers()
830 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0_VALID, 1); rt2500usb_init_registers()
831 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1, 6); rt2500usb_init_registers()
832 rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1_VALID, 1); rt2500usb_init_registers()
833 rt2500usb_register_write(rt2x00dev, TXRX_CSR7, reg); rt2500usb_init_registers()
835 rt2500usb_register_read(rt2x00dev, TXRX_CSR8, &reg); rt2500usb_init_registers()
836 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0, 5); rt2500usb_init_registers()
837 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0_VALID, 1); rt2500usb_init_registers()
838 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1, 0); rt2500usb_init_registers()
839 rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1_VALID, 0); rt2500usb_init_registers()
840 rt2500usb_register_write(rt2x00dev, TXRX_CSR8, reg); rt2500usb_init_registers()
842 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg); rt2500usb_init_registers()
843 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 0); rt2500usb_init_registers()
844 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, 0); rt2500usb_init_registers()
845 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 0); rt2500usb_init_registers()
846 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0); rt2500usb_init_registers()
847 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); rt2500usb_init_registers()
855 rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg); rt2500usb_init_registers()
856 rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0); rt2500usb_init_registers()
857 rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0); rt2500usb_init_registers()
858 rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 1); rt2500usb_init_registers()
859 rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg); rt2500usb_init_registers()
862 rt2500usb_register_read(rt2x00dev, PHY_CSR2, &reg); rt2500usb_init_registers()
863 rt2x00_set_field16(&reg, PHY_CSR2_LNA, 0); rt2500usb_init_registers()
865 reg = 0; rt2500usb_init_registers()
866 rt2x00_set_field16(&reg, PHY_CSR2_LNA, 1); rt2500usb_init_registers()
867 rt2x00_set_field16(&reg, PHY_CSR2_LNA_MODE, 3); rt2500usb_init_registers()
869 rt2500usb_register_write(rt2x00dev, PHY_CSR2, reg); rt2500usb_init_registers()
876 rt2500usb_register_read(rt2x00dev, MAC_CSR8, &reg); rt2500usb_init_registers()
877 rt2x00_set_field16(&reg, MAC_CSR8_MAX_FRAME_UNIT, rt2500usb_init_registers()
879 rt2500usb_register_write(rt2x00dev, MAC_CSR8, reg); rt2500usb_init_registers()
881 rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg); rt2500usb_init_registers()
882 rt2x00_set_field16(&reg, TXRX_CSR0_ALGORITHM, CIPHER_NONE); rt2500usb_init_registers()
883 rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER); rt2500usb_init_registers()
884 rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, 0); rt2500usb_init_registers()
885 rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg); rt2500usb_init_registers()
887 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg); rt2500usb_init_registers()
888 rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON, 90); rt2500usb_init_registers()
889 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg); rt2500usb_init_registers()
891 rt2500usb_register_read(rt2x00dev, PHY_CSR4, &reg); rt2500usb_init_registers()
892 rt2x00_set_field16(&reg, PHY_CSR4_LOW_RF_LE, 1); rt2500usb_init_registers()
893 rt2500usb_register_write(rt2x00dev, PHY_CSR4, reg); rt2500usb_init_registers()
895 rt2500usb_register_read(rt2x00dev, TXRX_CSR1, &reg); rt2500usb_init_registers()
896 rt2x00_set_field16(&reg, TXRX_CSR1_AUTO_SEQUENCE, 1); rt2500usb_init_registers()
897 rt2500usb_register_write(rt2x00dev, TXRX_CSR1, reg); rt2500usb_init_registers()
1004 u16 reg; rt2500usb_set_state() local
1013 reg = 0; rt2500usb_set_state()
1014 rt2x00_set_field16(&reg, MAC_CSR17_BBP_DESIRE_STATE, state); rt2500usb_set_state()
1015 rt2x00_set_field16(&reg, MAC_CSR17_RF_DESIRE_STATE, state); rt2500usb_set_state()
1016 rt2x00_set_field16(&reg, MAC_CSR17_PUT_TO_SLEEP, put_to_sleep); rt2500usb_set_state()
1017 rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg); rt2500usb_set_state()
1018 rt2x00_set_field16(&reg, MAC_CSR17_SET_STATE, 1); rt2500usb_set_state()
1019 rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg); rt2500usb_set_state()
1032 rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg); rt2500usb_set_state()
1146 u16 reg, reg0; rt2500usb_write_beacon() local
1152 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg); rt2500usb_write_beacon()
1153 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0); rt2500usb_write_beacon()
1154 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); rt2500usb_write_beacon()
1201 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1); rt2500usb_write_beacon()
1202 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1); rt2500usb_write_beacon()
1203 reg0 = reg; rt2500usb_write_beacon()
1204 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1); rt2500usb_write_beacon()
1208 * register several times (reg0 is the same as reg rt2500usb_write_beacon()
1210 * and 1 in reg). rt2500usb_write_beacon()
1212 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); rt2500usb_write_beacon()
1214 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); rt2500usb_write_beacon()
1216 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); rt2500usb_write_beacon()
1450 u16 reg; rt2500usb_init_eeprom() local
1463 rt2500usb_register_read(rt2x00dev, MAC_CSR0, &reg); rt2500usb_init_eeprom()
1464 rt2x00_set_chip(rt2x00dev, RT2570, value, reg); rt2500usb_init_eeprom()
1466 if (((reg & 0xfff0) != 0) || ((reg & 0x0000000f) == 0)) { rt2500usb_init_eeprom()
1772 u16 reg; rt2500usb_probe_hw() local
1789 rt2500usb_register_read(rt2x00dev, MAC_CSR19, &reg); rt2500usb_probe_hw()
1790 rt2x00_set_field16(&reg, MAC_CSR19_DIR0, 0); rt2500usb_probe_hw()
1791 rt2500usb_register_write(rt2x00dev, MAC_CSR19, reg); rt2500usb_probe_hw()
118 rt2500usb_regbusy_read(struct rt2x00_dev *rt2x00dev, const unsigned int offset, struct rt2x00_field16 field, u16 *reg) rt2500usb_regbusy_read() argument
H A Drt61pci.c68 u32 reg; rt61pci_bbp_write() local
76 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { rt61pci_bbp_write()
77 reg = 0; rt61pci_bbp_write()
78 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value); rt61pci_bbp_write()
79 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word); rt61pci_bbp_write()
80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); rt61pci_bbp_write()
81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0); rt61pci_bbp_write()
83 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); rt61pci_bbp_write()
92 u32 reg; rt61pci_bbp_read() local
101 * doesn't become available in time, reg will be 0xffffffff rt61pci_bbp_read()
104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { rt61pci_bbp_read()
105 reg = 0; rt61pci_bbp_read()
106 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word); rt61pci_bbp_read()
107 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); rt61pci_bbp_read()
108 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1); rt61pci_bbp_read()
110 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); rt61pci_bbp_read()
112 WAIT_FOR_BBP(rt2x00dev, &reg); rt61pci_bbp_read()
115 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); rt61pci_bbp_read()
123 u32 reg; rt61pci_rf_write() local
131 if (WAIT_FOR_RF(rt2x00dev, &reg)) { rt61pci_rf_write()
132 reg = 0; rt61pci_rf_write()
133 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value); rt61pci_rf_write()
134 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21); rt61pci_rf_write()
135 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0); rt61pci_rf_write()
136 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1); rt61pci_rf_write()
138 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg); rt61pci_rf_write()
149 u32 reg; rt61pci_mcu_request() local
157 if (WAIT_FOR_MCU(rt2x00dev, &reg)) { rt61pci_mcu_request()
158 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1); rt61pci_mcu_request()
159 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token); rt61pci_mcu_request()
160 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0); rt61pci_mcu_request()
161 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1); rt61pci_mcu_request()
162 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); rt61pci_mcu_request()
164 rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR, &reg); rt61pci_mcu_request()
165 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command); rt61pci_mcu_request()
166 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1); rt61pci_mcu_request()
167 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg); rt61pci_mcu_request()
177 u32 reg; rt61pci_eepromregister_read() local
179 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg); rt61pci_eepromregister_read()
181 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); rt61pci_eepromregister_read()
182 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); rt61pci_eepromregister_read()
184 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); rt61pci_eepromregister_read()
186 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); rt61pci_eepromregister_read()
192 u32 reg = 0; rt61pci_eepromregister_write() local
194 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); rt61pci_eepromregister_write()
195 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); rt61pci_eepromregister_write()
196 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, rt61pci_eepromregister_write()
198 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT, rt61pci_eepromregister_write()
201 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); rt61pci_eepromregister_write()
241 u32 reg; rt61pci_rfkill_poll() local
243 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg); rt61pci_rfkill_poll()
244 return rt2x00_get_field32(reg, MAC_CSR13_VAL5); rt61pci_rfkill_poll()
292 u32 reg; rt61pci_blink_set() local
294 rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14, &reg); rt61pci_blink_set()
295 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on); rt61pci_blink_set()
296 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off); rt61pci_blink_set()
297 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg); rt61pci_blink_set()
324 u32 reg; rt61pci_config_shared_key() local
339 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, &reg); rt61pci_config_shared_key()
340 reg &= mask; rt61pci_config_shared_key()
342 if (reg && reg == mask) rt61pci_config_shared_key()
345 key->hw_key_idx += reg ? ffz(reg) : 0; rt61pci_config_shared_key()
357 reg = SHARED_KEY_ENTRY(key->hw_key_idx); rt61pci_config_shared_key()
358 rt2x00mmio_register_multiwrite(rt2x00dev, reg, rt61pci_config_shared_key()
372 rt2x00mmio_register_read(rt2x00dev, SEC_CSR1, &reg); rt61pci_config_shared_key()
373 rt2x00_set_field32(&reg, field, crypto->cipher); rt61pci_config_shared_key()
374 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg); rt61pci_config_shared_key()
379 rt2x00mmio_register_read(rt2x00dev, SEC_CSR5, &reg); rt61pci_config_shared_key()
380 rt2x00_set_field32(&reg, field, crypto->cipher); rt61pci_config_shared_key()
381 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg); rt61pci_config_shared_key()
404 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, &reg); rt61pci_config_shared_key()
406 reg |= mask; rt61pci_config_shared_key()
408 reg &= ~mask; rt61pci_config_shared_key()
409 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, reg); rt61pci_config_shared_key()
421 u32 reg; rt61pci_config_pairwise_key() local
433 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, &reg); rt61pci_config_pairwise_key()
434 if (reg && reg == ~0) { rt61pci_config_pairwise_key()
436 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, &reg); rt61pci_config_pairwise_key()
437 if (reg && reg == ~0) rt61pci_config_pairwise_key()
441 key->hw_key_idx += reg ? ffz(reg) : 0; rt61pci_config_pairwise_key()
457 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); rt61pci_config_pairwise_key()
458 rt2x00mmio_register_multiwrite(rt2x00dev, reg, rt61pci_config_pairwise_key()
461 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); rt61pci_config_pairwise_key()
462 rt2x00mmio_register_multiwrite(rt2x00dev, reg, rt61pci_config_pairwise_key()
470 rt2x00mmio_register_read(rt2x00dev, SEC_CSR4, &reg); rt61pci_config_pairwise_key()
471 reg |= (1 << crypto->bssidx); rt61pci_config_pairwise_key()
472 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg); rt61pci_config_pairwise_key()
495 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, &reg); rt61pci_config_pairwise_key()
497 reg |= mask; rt61pci_config_pairwise_key()
499 reg &= ~mask; rt61pci_config_pairwise_key()
500 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg); rt61pci_config_pairwise_key()
504 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, &reg); rt61pci_config_pairwise_key()
506 reg |= mask; rt61pci_config_pairwise_key()
508 reg &= ~mask; rt61pci_config_pairwise_key()
509 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg); rt61pci_config_pairwise_key()
518 u32 reg; rt61pci_config_filter() local
526 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg); rt61pci_config_filter()
527 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC, rt61pci_config_filter()
529 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL, rt61pci_config_filter()
531 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL, rt61pci_config_filter()
533 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME, rt61pci_config_filter()
535 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS, rt61pci_config_filter()
538 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1); rt61pci_config_filter()
539 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST, rt61pci_config_filter()
541 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0); rt61pci_config_filter()
542 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, rt61pci_config_filter()
544 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); rt61pci_config_filter()
552 u32 reg; rt61pci_config_intf() local
558 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg); rt61pci_config_intf()
559 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync); rt61pci_config_intf()
560 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); rt61pci_config_intf()
564 reg = le32_to_cpu(conf->mac[1]); rt61pci_config_intf()
565 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); rt61pci_config_intf()
566 conf->mac[1] = cpu_to_le32(reg); rt61pci_config_intf()
573 reg = le32_to_cpu(conf->bssid[1]); rt61pci_config_intf()
574 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3); rt61pci_config_intf()
575 conf->bssid[1] = cpu_to_le32(reg); rt61pci_config_intf()
587 u32 reg; rt61pci_config_erp() local
589 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg); rt61pci_config_erp()
590 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); rt61pci_config_erp()
591 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); rt61pci_config_erp()
592 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); rt61pci_config_erp()
595 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, &reg); rt61pci_config_erp()
596 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1); rt61pci_config_erp()
597 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, rt61pci_config_erp()
599 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); rt61pci_config_erp()
607 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg); rt61pci_config_erp()
608 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, rt61pci_config_erp()
610 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); rt61pci_config_erp()
614 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, &reg); rt61pci_config_erp()
615 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time); rt61pci_config_erp()
616 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); rt61pci_config_erp()
618 rt2x00mmio_register_read(rt2x00dev, MAC_CSR8, &reg); rt61pci_config_erp()
619 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs); rt61pci_config_erp()
620 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); rt61pci_config_erp()
621 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs); rt61pci_config_erp()
622 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg); rt61pci_config_erp()
713 u32 reg; rt61pci_config_antenna_2529_rx() local
715 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg); rt61pci_config_antenna_2529_rx()
717 rt2x00_set_field32(&reg, MAC_CSR13_DIR4, 0); rt61pci_config_antenna_2529_rx()
718 rt2x00_set_field32(&reg, MAC_CSR13_VAL4, p1); rt61pci_config_antenna_2529_rx()
720 rt2x00_set_field32(&reg, MAC_CSR13_DIR3, 0); rt61pci_config_antenna_2529_rx()
721 rt2x00_set_field32(&reg, MAC_CSR13_VAL3, !p2); rt61pci_config_antenna_2529_rx()
723 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); rt61pci_config_antenna_2529_rx()
802 u32 reg; rt61pci_config_ant() local
822 rt2x00mmio_register_read(rt2x00dev, PHY_CSR0, &reg); rt61pci_config_ant()
824 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, rt61pci_config_ant()
826 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, rt61pci_config_ant()
829 rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg); rt61pci_config_ant()
927 u32 reg; rt61pci_config_retry_limit() local
929 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, &reg); rt61pci_config_retry_limit()
930 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); rt61pci_config_retry_limit()
931 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); rt61pci_config_retry_limit()
932 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); rt61pci_config_retry_limit()
933 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, rt61pci_config_retry_limit()
935 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, rt61pci_config_retry_limit()
937 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); rt61pci_config_retry_limit()
946 u32 reg; rt61pci_config_ps() local
949 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, &reg); rt61pci_config_ps()
950 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, rt61pci_config_ps()
952 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, rt61pci_config_ps()
954 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5); rt61pci_config_ps()
957 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0); rt61pci_config_ps()
958 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); rt61pci_config_ps()
960 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1); rt61pci_config_ps()
961 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); rt61pci_config_ps()
970 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, &reg); rt61pci_config_ps()
971 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0); rt61pci_config_ps()
972 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); rt61pci_config_ps()
973 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0); rt61pci_config_ps()
974 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0); rt61pci_config_ps()
975 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); rt61pci_config_ps()
1011 u32 reg; rt61pci_link_stats() local
1016 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, &reg); rt61pci_link_stats()
1017 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); rt61pci_link_stats()
1022 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, &reg); rt61pci_link_stats()
1023 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); rt61pci_link_stats()
1137 u32 reg; rt61pci_start_queue() local
1141 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg); rt61pci_start_queue()
1142 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0); rt61pci_start_queue()
1143 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); rt61pci_start_queue()
1146 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg); rt61pci_start_queue()
1147 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1); rt61pci_start_queue()
1148 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1); rt61pci_start_queue()
1149 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); rt61pci_start_queue()
1150 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); rt61pci_start_queue()
1160 u32 reg; rt61pci_kick_queue() local
1164 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg); rt61pci_kick_queue()
1165 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1); rt61pci_kick_queue()
1166 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); rt61pci_kick_queue()
1169 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg); rt61pci_kick_queue()
1170 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1); rt61pci_kick_queue()
1171 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); rt61pci_kick_queue()
1174 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg); rt61pci_kick_queue()
1175 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1); rt61pci_kick_queue()
1176 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); rt61pci_kick_queue()
1179 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg); rt61pci_kick_queue()
1180 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1); rt61pci_kick_queue()
1181 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); rt61pci_kick_queue()
1191 u32 reg; rt61pci_stop_queue() local
1195 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg); rt61pci_stop_queue()
1196 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1); rt61pci_stop_queue()
1197 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); rt61pci_stop_queue()
1200 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg); rt61pci_stop_queue()
1201 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1); rt61pci_stop_queue()
1202 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); rt61pci_stop_queue()
1205 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg); rt61pci_stop_queue()
1206 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1); rt61pci_stop_queue()
1207 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); rt61pci_stop_queue()
1210 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg); rt61pci_stop_queue()
1211 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1); rt61pci_stop_queue()
1212 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); rt61pci_stop_queue()
1215 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg); rt61pci_stop_queue()
1216 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1); rt61pci_stop_queue()
1217 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); rt61pci_stop_queue()
1220 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg); rt61pci_stop_queue()
1221 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0); rt61pci_stop_queue()
1222 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0); rt61pci_stop_queue()
1223 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); rt61pci_stop_queue()
1224 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); rt61pci_stop_queue()
1296 u32 reg; rt61pci_load_firmware() local
1302 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, &reg); rt61pci_load_firmware()
1303 if (reg) rt61pci_load_firmware()
1308 if (!reg) { rt61pci_load_firmware()
1316 reg = 0; rt61pci_load_firmware()
1317 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1); rt61pci_load_firmware()
1318 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); rt61pci_load_firmware()
1326 reg = 0; rt61pci_load_firmware()
1327 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1); rt61pci_load_firmware()
1328 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1); rt61pci_load_firmware()
1329 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); rt61pci_load_firmware()
1334 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0); rt61pci_load_firmware()
1335 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); rt61pci_load_firmware()
1337 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0); rt61pci_load_firmware()
1338 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); rt61pci_load_firmware()
1341 rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR, &reg); rt61pci_load_firmware()
1342 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY)) rt61pci_load_firmware()
1360 reg = 0; rt61pci_load_firmware()
1361 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1); rt61pci_load_firmware()
1362 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1); rt61pci_load_firmware()
1363 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); rt61pci_load_firmware()
1365 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg); rt61pci_load_firmware()
1366 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0); rt61pci_load_firmware()
1367 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0); rt61pci_load_firmware()
1368 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); rt61pci_load_firmware()
1370 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg); rt61pci_load_firmware()
1371 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1); rt61pci_load_firmware()
1372 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); rt61pci_load_firmware()
1423 u32 reg; rt61pci_init_queues() local
1428 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0, &reg); rt61pci_init_queues()
1429 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE, rt61pci_init_queues()
1431 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE, rt61pci_init_queues()
1433 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE, rt61pci_init_queues()
1435 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE, rt61pci_init_queues()
1437 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg); rt61pci_init_queues()
1439 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1, &reg); rt61pci_init_queues()
1440 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE, rt61pci_init_queues()
1442 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg); rt61pci_init_queues()
1445 rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR, &reg); rt61pci_init_queues()
1446 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER, rt61pci_init_queues()
1448 rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg); rt61pci_init_queues()
1451 rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR, &reg); rt61pci_init_queues()
1452 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER, rt61pci_init_queues()
1454 rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg); rt61pci_init_queues()
1457 rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR, &reg); rt61pci_init_queues()
1458 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER, rt61pci_init_queues()
1460 rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg); rt61pci_init_queues()
1463 rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR, &reg); rt61pci_init_queues()
1464 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER, rt61pci_init_queues()
1466 rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg); rt61pci_init_queues()
1468 rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR, &reg); rt61pci_init_queues()
1469 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); rt61pci_init_queues()
1470 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE, rt61pci_init_queues()
1472 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); rt61pci_init_queues()
1473 rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg); rt61pci_init_queues()
1476 rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR, &reg); rt61pci_init_queues()
1477 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER, rt61pci_init_queues()
1479 rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg); rt61pci_init_queues()
1481 rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg); rt61pci_init_queues()
1482 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2); rt61pci_init_queues()
1483 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2); rt61pci_init_queues()
1484 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2); rt61pci_init_queues()
1485 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2); rt61pci_init_queues()
1486 rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); rt61pci_init_queues()
1488 rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg); rt61pci_init_queues()
1489 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); rt61pci_init_queues()
1490 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); rt61pci_init_queues()
1491 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); rt61pci_init_queues()
1492 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); rt61pci_init_queues()
1493 rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); rt61pci_init_queues()
1495 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, &reg); rt61pci_init_queues()
1496 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1); rt61pci_init_queues()
1497 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); rt61pci_init_queues()
1504 u32 reg; rt61pci_init_registers() local
1506 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg); rt61pci_init_registers()
1507 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1); rt61pci_init_registers()
1508 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0); rt61pci_init_registers()
1509 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0); rt61pci_init_registers()
1510 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); rt61pci_init_registers()
1512 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1, &reg); rt61pci_init_registers()
1513 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ rt61pci_init_registers()
1514 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1); rt61pci_init_registers()
1515 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ rt61pci_init_registers()
1516 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1); rt61pci_init_registers()
1517 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ rt61pci_init_registers()
1518 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1); rt61pci_init_registers()
1519 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ rt61pci_init_registers()
1520 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1); rt61pci_init_registers()
1521 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg); rt61pci_init_registers()
1526 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2, &reg); rt61pci_init_registers()
1527 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13); rt61pci_init_registers()
1528 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1); rt61pci_init_registers()
1529 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12); rt61pci_init_registers()
1530 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1); rt61pci_init_registers()
1531 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11); rt61pci_init_registers()
1532 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1); rt61pci_init_registers()
1533 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10); rt61pci_init_registers()
1534 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1); rt61pci_init_registers()
1535 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg); rt61pci_init_registers()
1540 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3, &reg); rt61pci_init_registers()
1541 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7); rt61pci_init_registers()
1542 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1); rt61pci_init_registers()
1543 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6); rt61pci_init_registers()
1544 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1); rt61pci_init_registers()
1545 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5); rt61pci_init_registers()
1546 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1); rt61pci_init_registers()
1547 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg); rt61pci_init_registers()
1549 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7, &reg); rt61pci_init_registers()
1550 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59); rt61pci_init_registers()
1551 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53); rt61pci_init_registers()
1552 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49); rt61pci_init_registers()
1553 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46); rt61pci_init_registers()
1554 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg); rt61pci_init_registers()
1556 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8, &reg); rt61pci_init_registers()
1557 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44); rt61pci_init_registers()
1558 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42); rt61pci_init_registers()
1559 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42); rt61pci_init_registers()
1560 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42); rt61pci_init_registers()
1561 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg); rt61pci_init_registers()
1563 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg); rt61pci_init_registers()
1564 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0); rt61pci_init_registers()
1565 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0); rt61pci_init_registers()
1566 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0); rt61pci_init_registers()
1567 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0); rt61pci_init_registers()
1568 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); rt61pci_init_registers()
1569 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); rt61pci_init_registers()
1570 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); rt61pci_init_registers()
1576 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, &reg); rt61pci_init_registers()
1577 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0); rt61pci_init_registers()
1578 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); rt61pci_init_registers()
1622 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, &reg); rt61pci_init_registers()
1623 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, &reg); rt61pci_init_registers()
1624 rt2x00mmio_register_read(rt2x00dev, STA_CSR2, &reg); rt61pci_init_registers()
1629 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg); rt61pci_init_registers()
1630 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1); rt61pci_init_registers()
1631 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1); rt61pci_init_registers()
1632 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); rt61pci_init_registers()
1634 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg); rt61pci_init_registers()
1635 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0); rt61pci_init_registers()
1636 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0); rt61pci_init_registers()
1637 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); rt61pci_init_registers()
1639 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg); rt61pci_init_registers()
1640 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1); rt61pci_init_registers()
1641 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); rt61pci_init_registers()
1717 u32 reg; rt61pci_toggle_irq() local
1725 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); rt61pci_toggle_irq()
1726 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); rt61pci_toggle_irq()
1728 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg); rt61pci_toggle_irq()
1729 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); rt61pci_toggle_irq()
1738 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg); rt61pci_toggle_irq()
1739 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask); rt61pci_toggle_irq()
1740 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask); rt61pci_toggle_irq()
1741 rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask); rt61pci_toggle_irq()
1742 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask); rt61pci_toggle_irq()
1743 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); rt61pci_toggle_irq()
1744 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); rt61pci_toggle_irq()
1746 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg); rt61pci_toggle_irq()
1747 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask); rt61pci_toggle_irq()
1748 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask); rt61pci_toggle_irq()
1749 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask); rt61pci_toggle_irq()
1750 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask); rt61pci_toggle_irq()
1751 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask); rt61pci_toggle_irq()
1752 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask); rt61pci_toggle_irq()
1753 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask); rt61pci_toggle_irq()
1754 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask); rt61pci_toggle_irq()
1755 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask); rt61pci_toggle_irq()
1756 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); rt61pci_toggle_irq()
1773 u32 reg; rt61pci_enable_radio() local
1786 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, &reg); rt61pci_enable_radio()
1787 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1); rt61pci_enable_radio()
1788 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); rt61pci_enable_radio()
1803 u32 reg, reg2; rt61pci_set_state() local
1809 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, &reg); rt61pci_set_state()
1810 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); rt61pci_set_state()
1811 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); rt61pci_set_state()
1812 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); rt61pci_set_state()
1824 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); rt61pci_set_state()
1973 u32 orig_reg, reg; rt61pci_write_beacon() local
1979 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg); rt61pci_write_beacon()
1980 orig_reg = reg; rt61pci_write_beacon()
1981 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); rt61pci_write_beacon()
1982 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); rt61pci_write_beacon()
2021 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); rt61pci_write_beacon()
2022 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); rt61pci_write_beacon()
2034 u32 orig_reg, reg; rt61pci_clear_beacon() local
2041 reg = orig_reg; rt61pci_clear_beacon()
2042 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); rt61pci_clear_beacon()
2043 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); rt61pci_clear_beacon()
2161 u32 reg; rt61pci_txdone() local
2176 rt2x00mmio_register_read(rt2x00dev, STA_CSR4, &reg); rt61pci_txdone()
2177 if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) rt61pci_txdone()
2184 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); rt61pci_txdone()
2193 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE); rt61pci_txdone()
2221 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) { rt61pci_txdone()
2231 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); rt61pci_txdone()
2254 u32 reg; rt61pci_enable_interrupt() local
2262 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg); rt61pci_enable_interrupt()
2263 rt2x00_set_field32(&reg, irq_field, 0); rt61pci_enable_interrupt()
2264 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); rt61pci_enable_interrupt()
2272 u32 reg; rt61pci_enable_mcu_interrupt() local
2280 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg); rt61pci_enable_mcu_interrupt()
2281 rt2x00_set_field32(&reg, irq_field, 0); rt61pci_enable_mcu_interrupt()
2282 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); rt61pci_enable_mcu_interrupt()
2326 u32 reg, mask; rt61pci_interrupt() local
2335 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); rt61pci_interrupt()
2336 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); rt61pci_interrupt()
2338 if (!reg && !reg_mcu) rt61pci_interrupt()
2347 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE)) rt61pci_interrupt()
2350 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE)) rt61pci_interrupt()
2353 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE)) rt61pci_interrupt()
2364 mask = reg; rt61pci_interrupt()
2373 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg); rt61pci_interrupt()
2374 reg |= mask; rt61pci_interrupt()
2375 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); rt61pci_interrupt()
2377 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg); rt61pci_interrupt()
2378 reg |= mask_mcu; rt61pci_interrupt()
2379 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); rt61pci_interrupt()
2392 u32 reg; rt61pci_validate_eeprom() local
2397 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg); rt61pci_validate_eeprom()
2402 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ? rt61pci_validate_eeprom()
2502 u32 reg; rt61pci_init_eeprom() local
2515 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, &reg); rt61pci_init_eeprom()
2516 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), rt61pci_init_eeprom()
2517 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); rt61pci_init_eeprom()
2836 u32 reg; rt61pci_probe_hw() local
2858 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg); rt61pci_probe_hw()
2859 rt2x00_set_field32(&reg, MAC_CSR13_DIR5, 1); rt61pci_probe_hw()
2860 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); rt61pci_probe_hw()
2903 u32 reg; rt61pci_conf_tx() local
2930 rt2x00mmio_register_read(rt2x00dev, offset, &reg); rt61pci_conf_tx()
2931 rt2x00_set_field32(&reg, field, queue->txop); rt61pci_conf_tx()
2932 rt2x00mmio_register_write(rt2x00dev, offset, reg); rt61pci_conf_tx()
2938 rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR, &reg); rt61pci_conf_tx()
2939 rt2x00_set_field32(&reg, field, queue->aifs); rt61pci_conf_tx()
2940 rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg); rt61pci_conf_tx()
2942 rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR, &reg); rt61pci_conf_tx()
2943 rt2x00_set_field32(&reg, field, queue->cw_min); rt61pci_conf_tx()
2944 rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg); rt61pci_conf_tx()
2946 rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR, &reg); rt61pci_conf_tx()
2947 rt2x00_set_field32(&reg, field, queue->cw_max); rt61pci_conf_tx()
2948 rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg); rt61pci_conf_tx()
2957 u32 reg; rt61pci_get_tsf() local
2959 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13, &reg); rt61pci_get_tsf()
2960 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; rt61pci_get_tsf()
2961 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12, &reg); rt61pci_get_tsf()
2962 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); rt61pci_get_tsf()
H A Drt73usb.c66 u32 reg; rt73usb_bbp_write() local
74 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { rt73usb_bbp_write()
75 reg = 0; rt73usb_bbp_write()
76 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value); rt73usb_bbp_write()
77 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word); rt73usb_bbp_write()
78 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); rt73usb_bbp_write()
79 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0); rt73usb_bbp_write()
81 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); rt73usb_bbp_write()
90 u32 reg; rt73usb_bbp_read() local
99 * doesn't become available in time, reg will be 0xffffffff rt73usb_bbp_read()
102 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { rt73usb_bbp_read()
103 reg = 0; rt73usb_bbp_read()
104 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word); rt73usb_bbp_read()
105 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); rt73usb_bbp_read()
106 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1); rt73usb_bbp_read()
108 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); rt73usb_bbp_read()
110 WAIT_FOR_BBP(rt2x00dev, &reg); rt73usb_bbp_read()
113 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); rt73usb_bbp_read()
121 u32 reg; rt73usb_rf_write() local
129 if (WAIT_FOR_RF(rt2x00dev, &reg)) { rt73usb_rf_write()
130 reg = 0; rt73usb_rf_write()
131 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value); rt73usb_rf_write()
136 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, rt73usb_rf_write()
139 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0); rt73usb_rf_write()
140 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1); rt73usb_rf_write()
142 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg); rt73usb_rf_write()
186 u32 reg; rt73usb_rfkill_poll() local
188 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg); rt73usb_rfkill_poll()
189 return rt2x00_get_field32(reg, MAC_CSR13_VAL7); rt73usb_rfkill_poll()
239 u32 reg; rt73usb_blink_set() local
241 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg); rt73usb_blink_set()
242 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on); rt73usb_blink_set()
243 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off); rt73usb_blink_set()
244 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg); rt73usb_blink_set()
271 u32 reg; rt73usb_config_shared_key() local
286 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg); rt73usb_config_shared_key()
287 reg &= mask; rt73usb_config_shared_key()
289 if (reg && reg == mask) rt73usb_config_shared_key()
292 key->hw_key_idx += reg ? ffz(reg) : 0; rt73usb_config_shared_key()
304 reg = SHARED_KEY_ENTRY(key->hw_key_idx); rt73usb_config_shared_key()
305 rt2x00usb_register_multiwrite(rt2x00dev, reg, rt73usb_config_shared_key()
319 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg); rt73usb_config_shared_key()
320 rt2x00_set_field32(&reg, field, crypto->cipher); rt73usb_config_shared_key()
321 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg); rt73usb_config_shared_key()
326 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg); rt73usb_config_shared_key()
327 rt2x00_set_field32(&reg, field, crypto->cipher); rt73usb_config_shared_key()
328 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg); rt73usb_config_shared_key()
351 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg); rt73usb_config_shared_key()
353 reg |= mask; rt73usb_config_shared_key()
355 reg &= ~mask; rt73usb_config_shared_key()
356 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg); rt73usb_config_shared_key()
368 u32 reg; rt73usb_config_pairwise_key() local
380 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg); rt73usb_config_pairwise_key()
381 if (reg && reg == ~0) { rt73usb_config_pairwise_key()
383 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg); rt73usb_config_pairwise_key()
384 if (reg && reg == ~0) rt73usb_config_pairwise_key()
388 key->hw_key_idx += reg ? ffz(reg) : 0; rt73usb_config_pairwise_key()
400 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); rt73usb_config_pairwise_key()
401 rt2x00usb_register_multiwrite(rt2x00dev, reg, rt73usb_config_pairwise_key()
411 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); rt73usb_config_pairwise_key()
412 rt2x00usb_register_multiwrite(rt2x00dev, reg, rt73usb_config_pairwise_key()
420 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg); rt73usb_config_pairwise_key()
421 reg |= (1 << crypto->bssidx); rt73usb_config_pairwise_key()
422 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg); rt73usb_config_pairwise_key()
445 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg); rt73usb_config_pairwise_key()
447 reg |= mask; rt73usb_config_pairwise_key()
449 reg &= ~mask; rt73usb_config_pairwise_key()
450 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg); rt73usb_config_pairwise_key()
454 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg); rt73usb_config_pairwise_key()
456 reg |= mask; rt73usb_config_pairwise_key()
458 reg &= ~mask; rt73usb_config_pairwise_key()
459 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg); rt73usb_config_pairwise_key()
468 u32 reg; rt73usb_config_filter() local
476 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg); rt73usb_config_filter()
477 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC, rt73usb_config_filter()
479 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL, rt73usb_config_filter()
481 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL, rt73usb_config_filter()
483 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME, rt73usb_config_filter()
485 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS, rt73usb_config_filter()
488 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1); rt73usb_config_filter()
489 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST, rt73usb_config_filter()
491 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0); rt73usb_config_filter()
492 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, rt73usb_config_filter()
494 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); rt73usb_config_filter()
502 u32 reg; rt73usb_config_intf() local
508 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg); rt73usb_config_intf()
509 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync); rt73usb_config_intf()
510 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); rt73usb_config_intf()
514 reg = le32_to_cpu(conf->mac[1]); rt73usb_config_intf()
515 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); rt73usb_config_intf()
516 conf->mac[1] = cpu_to_le32(reg); rt73usb_config_intf()
523 reg = le32_to_cpu(conf->bssid[1]); rt73usb_config_intf()
524 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3); rt73usb_config_intf()
525 conf->bssid[1] = cpu_to_le32(reg); rt73usb_config_intf()
536 u32 reg; rt73usb_config_erp() local
538 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg); rt73usb_config_erp()
539 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); rt73usb_config_erp()
540 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); rt73usb_config_erp()
541 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); rt73usb_config_erp()
544 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg); rt73usb_config_erp()
545 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1); rt73usb_config_erp()
546 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, rt73usb_config_erp()
548 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); rt73usb_config_erp()
556 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg); rt73usb_config_erp()
557 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, rt73usb_config_erp()
559 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); rt73usb_config_erp()
563 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg); rt73usb_config_erp()
564 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time); rt73usb_config_erp()
565 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); rt73usb_config_erp()
567 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg); rt73usb_config_erp()
568 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs); rt73usb_config_erp()
569 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); rt73usb_config_erp()
570 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs); rt73usb_config_erp()
571 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg); rt73usb_config_erp()
698 u32 reg; rt73usb_config_ant() local
718 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg); rt73usb_config_ant()
720 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, rt73usb_config_ant()
722 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, rt73usb_config_ant()
725 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg); rt73usb_config_ant()
810 u32 reg; rt73usb_config_retry_limit() local
812 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg); rt73usb_config_retry_limit()
813 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); rt73usb_config_retry_limit()
814 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); rt73usb_config_retry_limit()
815 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); rt73usb_config_retry_limit()
816 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, rt73usb_config_retry_limit()
818 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, rt73usb_config_retry_limit()
820 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); rt73usb_config_retry_limit()
829 u32 reg; rt73usb_config_ps() local
832 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg); rt73usb_config_ps()
833 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, rt73usb_config_ps()
835 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, rt73usb_config_ps()
837 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5); rt73usb_config_ps()
840 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0); rt73usb_config_ps()
841 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); rt73usb_config_ps()
843 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1); rt73usb_config_ps()
844 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); rt73usb_config_ps()
849 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg); rt73usb_config_ps()
850 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0); rt73usb_config_ps()
851 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); rt73usb_config_ps()
852 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0); rt73usb_config_ps()
853 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0); rt73usb_config_ps()
854 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); rt73usb_config_ps()
886 u32 reg; rt73usb_link_stats() local
891 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg); rt73usb_link_stats()
892 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); rt73usb_link_stats()
897 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg); rt73usb_link_stats()
898 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); rt73usb_link_stats()
1024 u32 reg; rt73usb_start_queue() local
1028 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg); rt73usb_start_queue()
1029 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0); rt73usb_start_queue()
1030 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); rt73usb_start_queue()
1033 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg); rt73usb_start_queue()
1034 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1); rt73usb_start_queue()
1035 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1); rt73usb_start_queue()
1036 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); rt73usb_start_queue()
1037 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); rt73usb_start_queue()
1047 u32 reg; rt73usb_stop_queue() local
1051 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg); rt73usb_stop_queue()
1052 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1); rt73usb_stop_queue()
1053 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); rt73usb_stop_queue()
1056 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg); rt73usb_stop_queue()
1057 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0); rt73usb_stop_queue()
1058 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0); rt73usb_stop_queue()
1059 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); rt73usb_stop_queue()
1060 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); rt73usb_stop_queue()
1109 u32 reg; rt73usb_load_firmware() local
1115 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg); rt73usb_load_firmware()
1116 if (reg) rt73usb_load_firmware()
1121 if (!reg) { rt73usb_load_firmware()
1151 u32 reg; rt73usb_init_registers() local
1153 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg); rt73usb_init_registers()
1154 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1); rt73usb_init_registers()
1155 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0); rt73usb_init_registers()
1156 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0); rt73usb_init_registers()
1157 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); rt73usb_init_registers()
1159 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg); rt73usb_init_registers()
1160 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ rt73usb_init_registers()
1161 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1); rt73usb_init_registers()
1162 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ rt73usb_init_registers()
1163 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1); rt73usb_init_registers()
1164 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ rt73usb_init_registers()
1165 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1); rt73usb_init_registers()
1166 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ rt73usb_init_registers()
1167 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1); rt73usb_init_registers()
1168 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg); rt73usb_init_registers()
1173 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg); rt73usb_init_registers()
1174 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13); rt73usb_init_registers()
1175 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1); rt73usb_init_registers()
1176 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12); rt73usb_init_registers()
1177 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1); rt73usb_init_registers()
1178 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11); rt73usb_init_registers()
1179 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1); rt73usb_init_registers()
1180 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10); rt73usb_init_registers()
1181 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1); rt73usb_init_registers()
1182 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg); rt73usb_init_registers()
1187 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg); rt73usb_init_registers()
1188 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7); rt73usb_init_registers()
1189 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1); rt73usb_init_registers()
1190 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6); rt73usb_init_registers()
1191 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1); rt73usb_init_registers()
1192 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5); rt73usb_init_registers()
1193 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1); rt73usb_init_registers()
1194 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg); rt73usb_init_registers()
1196 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg); rt73usb_init_registers()
1197 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59); rt73usb_init_registers()
1198 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53); rt73usb_init_registers()
1199 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49); rt73usb_init_registers()
1200 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46); rt73usb_init_registers()
1201 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg); rt73usb_init_registers()
1203 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg); rt73usb_init_registers()
1204 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44); rt73usb_init_registers()
1205 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42); rt73usb_init_registers()
1206 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42); rt73usb_init_registers()
1207 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42); rt73usb_init_registers()
1208 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg); rt73usb_init_registers()
1210 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg); rt73usb_init_registers()
1211 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0); rt73usb_init_registers()
1212 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0); rt73usb_init_registers()
1213 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0); rt73usb_init_registers()
1214 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0); rt73usb_init_registers()
1215 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); rt73usb_init_registers()
1216 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); rt73usb_init_registers()
1217 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); rt73usb_init_registers()
1221 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg); rt73usb_init_registers()
1222 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff); rt73usb_init_registers()
1223 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg); rt73usb_init_registers()
1240 reg = 0x000023b0; rt73usb_init_registers()
1242 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1); rt73usb_init_registers()
1243 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg); rt73usb_init_registers()
1249 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg); rt73usb_init_registers()
1250 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0); rt73usb_init_registers()
1251 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); rt73usb_init_registers()
1269 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg); rt73usb_init_registers()
1270 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg); rt73usb_init_registers()
1271 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg); rt73usb_init_registers()
1276 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg); rt73usb_init_registers()
1277 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1); rt73usb_init_registers()
1278 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1); rt73usb_init_registers()
1279 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); rt73usb_init_registers()
1281 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg); rt73usb_init_registers()
1282 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0); rt73usb_init_registers()
1283 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0); rt73usb_init_registers()
1284 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); rt73usb_init_registers()
1286 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg); rt73usb_init_registers()
1287 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1); rt73usb_init_registers()
1288 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); rt73usb_init_registers()
1387 u32 reg, reg2; rt73usb_set_state() local
1393 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg); rt73usb_set_state()
1394 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); rt73usb_set_state()
1395 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); rt73usb_set_state()
1396 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg); rt73usb_set_state()
1408 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg); rt73usb_set_state()
1535 u32 orig_reg, reg; rt73usb_write_beacon() local
1541 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg); rt73usb_write_beacon()
1542 orig_reg = reg; rt73usb_write_beacon()
1543 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); rt73usb_write_beacon()
1544 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); rt73usb_write_beacon()
1586 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); rt73usb_write_beacon()
1587 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); rt73usb_write_beacon()
1600 u32 orig_reg, reg; rt73usb_clear_beacon() local
1607 reg = orig_reg; rt73usb_clear_beacon()
1608 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); rt73usb_clear_beacon()
1609 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); rt73usb_clear_beacon()
1857 u32 reg; rt73usb_init_eeprom() local
1870 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg); rt73usb_init_eeprom()
1871 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), rt73usb_init_eeprom()
1872 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); rt73usb_init_eeprom()
2178 u32 reg; rt73usb_probe_hw() local
2195 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg); rt73usb_probe_hw()
2196 rt2x00_set_field32(&reg, MAC_CSR13_DIR7, 0); rt73usb_probe_hw()
2197 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, reg); rt73usb_probe_hw()
2240 u32 reg; rt73usb_conf_tx() local
2267 rt2x00usb_register_read(rt2x00dev, offset, &reg); rt73usb_conf_tx()
2268 rt2x00_set_field32(&reg, field, queue->txop); rt73usb_conf_tx()
2269 rt2x00usb_register_write(rt2x00dev, offset, reg); rt73usb_conf_tx()
2275 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg); rt73usb_conf_tx()
2276 rt2x00_set_field32(&reg, field, queue->aifs); rt73usb_conf_tx()
2277 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg); rt73usb_conf_tx()
2279 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg); rt73usb_conf_tx()
2280 rt2x00_set_field32(&reg, field, queue->cw_min); rt73usb_conf_tx()
2281 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg); rt73usb_conf_tx()
2283 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg); rt73usb_conf_tx()
2284 rt2x00_set_field32(&reg, field, queue->cw_max); rt73usb_conf_tx()
2285 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg); rt73usb_conf_tx()
2294 u32 reg; rt73usb_get_tsf() local
2296 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg); rt73usb_get_tsf()
2297 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; rt73usb_get_tsf()
2298 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg); rt73usb_get_tsf()
2299 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); rt73usb_get_tsf()
H A Drt2800lib.c88 u32 reg; rt2800_bbp_write() local
96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { rt2800_bbp_write()
97 reg = 0; rt2800_bbp_write()
98 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value); rt2800_bbp_write()
99 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word); rt2800_bbp_write()
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1); rt2800_bbp_write()
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0); rt2800_bbp_write()
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1); rt2800_bbp_write()
104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); rt2800_bbp_write()
113 u32 reg; rt2800_bbp_read() local
122 * doesn't become available in time, reg will be 0xffffffff rt2800_bbp_read()
125 if (WAIT_FOR_BBP(rt2x00dev, &reg)) { rt2800_bbp_read()
126 reg = 0; rt2800_bbp_read()
127 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word); rt2800_bbp_read()
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1); rt2800_bbp_read()
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1); rt2800_bbp_read()
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1); rt2800_bbp_read()
132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); rt2800_bbp_read()
134 WAIT_FOR_BBP(rt2x00dev, &reg); rt2800_bbp_read()
137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); rt2800_bbp_read()
145 u32 reg; rt2800_rfcsr_write() local
153 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) { rt2800_rfcsr_write()
154 reg = 0; rt2800_rfcsr_write()
155 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value); rt2800_rfcsr_write()
156 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word); rt2800_rfcsr_write()
157 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1); rt2800_rfcsr_write()
158 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1); rt2800_rfcsr_write()
160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); rt2800_rfcsr_write()
169 u32 reg; rt2800_rfcsr_read() local
178 * doesn't become available in time, reg will be 0xffffffff rt2800_rfcsr_read()
181 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) { rt2800_rfcsr_read()
182 reg = 0; rt2800_rfcsr_read()
183 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word); rt2800_rfcsr_read()
184 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0); rt2800_rfcsr_read()
185 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1); rt2800_rfcsr_read()
187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); rt2800_rfcsr_read()
189 WAIT_FOR_RFCSR(rt2x00dev, &reg); rt2800_rfcsr_read()
192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); rt2800_rfcsr_read()
200 u32 reg; rt2800_rf_write() local
208 if (WAIT_FOR_RF(rt2x00dev, &reg)) { rt2800_rf_write()
209 reg = 0; rt2800_rf_write()
210 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value); rt2800_rf_write()
211 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0); rt2800_rf_write()
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0); rt2800_rf_write()
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1); rt2800_rf_write()
215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); rt2800_rf_write()
372 u32 reg; rt2800_enable_wlan_rt3290() local
375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg); rt2800_enable_wlan_rt3290()
376 if (rt2x00_get_field32(reg, WLAN_EN)) rt2800_enable_wlan_rt3290()
379 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); rt2800_enable_wlan_rt3290()
380 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1); rt2800_enable_wlan_rt3290()
381 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0); rt2800_enable_wlan_rt3290()
382 rt2x00_set_field32(&reg, WLAN_EN, 1); rt2800_enable_wlan_rt3290()
383 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); rt2800_enable_wlan_rt3290()
393 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg); rt2800_enable_wlan_rt3290()
394 if (rt2x00_get_field32(reg, PLL_LD) && rt2800_enable_wlan_rt3290()
395 rt2x00_get_field32(reg, XTAL_RDY)) rt2800_enable_wlan_rt3290()
416 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg); rt2800_enable_wlan_rt3290()
417 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0); rt2800_enable_wlan_rt3290()
418 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1); rt2800_enable_wlan_rt3290()
419 rt2x00_set_field32(&reg, WLAN_RESET, 1); rt2800_enable_wlan_rt3290()
420 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); rt2800_enable_wlan_rt3290()
422 rt2x00_set_field32(&reg, WLAN_RESET, 0); rt2800_enable_wlan_rt3290()
423 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); rt2800_enable_wlan_rt3290()
435 u32 reg; rt2800_mcu_request() local
449 if (WAIT_FOR_MCU(rt2x00dev, &reg)) { rt2800_mcu_request()
450 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1); rt2800_mcu_request()
451 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token); rt2800_mcu_request()
452 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0); rt2800_mcu_request()
453 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1); rt2800_mcu_request()
454 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); rt2800_mcu_request()
456 reg = 0; rt2800_mcu_request()
457 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command); rt2800_mcu_request()
458 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); rt2800_mcu_request()
468 u32 reg; rt2800_wait_csr_ready() local
471 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg); rt2800_wait_csr_ready()
472 if (reg && reg != ~0) rt2800_wait_csr_ready()
485 u32 reg; rt2800_wait_wpdma_ready() local
492 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); rt2800_wait_wpdma_ready()
493 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && rt2800_wait_wpdma_ready()
494 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) rt2800_wait_wpdma_ready()
500 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); rt2800_wait_wpdma_ready()
507 u32 reg; rt2800_disable_wpdma() local
509 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); rt2800_disable_wpdma()
510 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); rt2800_disable_wpdma()
511 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); rt2800_disable_wpdma()
512 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); rt2800_disable_wpdma()
513 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); rt2800_disable_wpdma()
514 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); rt2800_disable_wpdma()
515 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); rt2800_disable_wpdma()
632 u32 reg; rt2800_load_firmware() local
658 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg); rt2800_load_firmware()
659 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1); rt2800_load_firmware()
660 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1); rt2800_load_firmware()
661 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); rt2800_load_firmware()
677 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); rt2800_load_firmware()
678 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) rt2800_load_firmware()
955 u64 off, reg = 0; rt2800_update_beacons_setup() local
966 reg |= off << (8 * bcn_num); rt2800_update_beacons_setup()
972 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); rt2800_update_beacons_setup()
973 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); rt2800_update_beacons_setup()
990 u32 orig_reg, reg; rt2800_write_beacon() local
997 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); rt2800_write_beacon()
998 orig_reg = reg; rt2800_write_beacon()
999 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); rt2800_write_beacon()
1000 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); rt2800_write_beacon()
1081 u32 orig_reg, reg; rt2800_clear_beacon() local
1088 reg = orig_reg; rt2800_clear_beacon()
1089 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); rt2800_clear_beacon()
1090 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); rt2800_clear_beacon()
1157 u32 reg; rt2800_rfkill_poll() local
1160 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg); rt2800_rfkill_poll()
1161 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); rt2800_rfkill_poll()
1163 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg); rt2800_rfkill_poll()
1164 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); rt2800_rfkill_poll()
1184 u32 reg; rt2800_brightness_set() local
1188 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg); rt2800_brightness_set()
1191 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity); rt2800_brightness_set()
1195 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, rt2800_brightness_set()
1198 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, rt2800_brightness_set()
1201 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, rt2800_brightness_set()
1205 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); rt2800_brightness_set()
1271 u32 reg; rt2800_config_wcid_attr_bssidx() local
1277 rt2800_register_read(rt2x00dev, offset, &reg); rt2800_config_wcid_attr_bssidx()
1278 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); rt2800_config_wcid_attr_bssidx()
1279 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, rt2800_config_wcid_attr_bssidx()
1281 rt2800_register_write(rt2x00dev, offset, reg); rt2800_config_wcid_attr_bssidx()
1290 u32 reg; rt2800_config_wcid_attr_cipher() local
1295 rt2800_register_read(rt2x00dev, offset, &reg); rt2800_config_wcid_attr_cipher()
1296 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, rt2800_config_wcid_attr_cipher()
1303 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, rt2800_config_wcid_attr_cipher()
1305 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, rt2800_config_wcid_attr_cipher()
1307 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); rt2800_config_wcid_attr_cipher()
1308 rt2800_register_write(rt2x00dev, offset, reg); rt2800_config_wcid_attr_cipher()
1311 rt2800_register_read(rt2x00dev, offset, &reg); rt2800_config_wcid_attr_cipher()
1312 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0); rt2800_config_wcid_attr_cipher()
1313 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0); rt2800_config_wcid_attr_cipher()
1314 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); rt2800_config_wcid_attr_cipher()
1315 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); rt2800_config_wcid_attr_cipher()
1316 rt2800_register_write(rt2x00dev, offset, reg); rt2800_config_wcid_attr_cipher()
1338 u32 reg; rt2800_config_shared_key() local
1367 rt2800_register_read(rt2x00dev, offset, &reg); rt2800_config_shared_key()
1368 rt2x00_set_field32(&reg, field, rt2800_config_shared_key()
1370 rt2800_register_write(rt2x00dev, offset, reg); rt2800_config_shared_key()
1503 u32 reg; rt2800_config_filter() local
1511 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg); rt2800_config_filter()
1512 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR, rt2800_config_filter()
1514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR, rt2800_config_filter()
1516 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME, rt2800_config_filter()
1518 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); rt2800_config_filter()
1519 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1); rt2800_config_filter()
1520 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST, rt2800_config_filter()
1522 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0); rt2800_config_filter()
1523 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1); rt2800_config_filter()
1524 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK, rt2800_config_filter()
1526 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END, rt2800_config_filter()
1528 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK, rt2800_config_filter()
1530 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS, rt2800_config_filter()
1532 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS, rt2800_config_filter()
1534 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL, rt2800_config_filter()
1536 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0); rt2800_config_filter()
1537 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, rt2800_config_filter()
1539 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL, rt2800_config_filter()
1541 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); rt2800_config_filter()
1548 u32 reg; rt2800_config_intf() local
1555 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); rt2800_config_intf()
1556 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync); rt2800_config_intf()
1557 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); rt2800_config_intf()
1563 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg); rt2800_config_intf()
1564 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0); rt2800_config_intf()
1565 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1); rt2800_config_intf()
1566 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); rt2800_config_intf()
1567 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0); rt2800_config_intf()
1568 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); rt2800_config_intf()
1570 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg); rt2800_config_intf()
1571 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4); rt2800_config_intf()
1572 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2); rt2800_config_intf()
1573 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); rt2800_config_intf()
1574 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16); rt2800_config_intf()
1575 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); rt2800_config_intf()
1591 reg = le32_to_cpu(conf->mac[1]); rt2800_config_intf()
1592 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); rt2800_config_intf()
1593 conf->mac[1] = cpu_to_le32(reg); rt2800_config_intf()
1602 reg = le32_to_cpu(conf->bssid[1]); rt2800_config_intf()
1603 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3); rt2800_config_intf()
1604 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0); rt2800_config_intf()
1605 conf->bssid[1] = cpu_to_le32(reg); rt2800_config_intf()
1622 u32 reg; rt2800_config_ht_opmode() local
1689 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg); rt2800_config_ht_opmode()
1690 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); rt2800_config_ht_opmode()
1691 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); rt2800_config_ht_opmode()
1692 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); rt2800_config_ht_opmode()
1694 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg); rt2800_config_ht_opmode()
1695 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); rt2800_config_ht_opmode()
1696 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); rt2800_config_ht_opmode()
1697 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); rt2800_config_ht_opmode()
1699 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg); rt2800_config_ht_opmode()
1700 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); rt2800_config_ht_opmode()
1701 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); rt2800_config_ht_opmode()
1702 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); rt2800_config_ht_opmode()
1704 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg); rt2800_config_ht_opmode()
1705 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); rt2800_config_ht_opmode()
1706 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); rt2800_config_ht_opmode()
1707 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); rt2800_config_ht_opmode()
1713 u32 reg; rt2800_config_erp() local
1716 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg); rt2800_config_erp()
1717 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, rt2800_config_erp()
1719 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, rt2800_config_erp()
1721 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); rt2800_config_erp()
1725 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); rt2800_config_erp()
1726 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, rt2800_config_erp()
1728 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); rt2800_config_erp()
1738 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg); rt2800_config_erp()
1739 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, rt2800_config_erp()
1741 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); rt2800_config_erp()
1743 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg); rt2800_config_erp()
1744 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs); rt2800_config_erp()
1745 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); rt2800_config_erp()
1749 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); rt2800_config_erp()
1750 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, rt2800_config_erp()
1752 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); rt2800_config_erp()
1762 u32 reg; rt2800_config_3572bt_ant() local
1766 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg); rt2800_config_3572bt_ant()
1768 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1); rt2800_config_3572bt_ant()
1769 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1); rt2800_config_3572bt_ant()
1771 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0); rt2800_config_3572bt_ant()
1772 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0); rt2800_config_3572bt_ant()
1774 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); rt2800_config_3572bt_ant()
1776 rt2800_register_read(rt2x00dev, LED_CFG, &reg); rt2800_config_3572bt_ant()
1777 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; rt2800_config_3572bt_ant()
1778 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; rt2800_config_3572bt_ant()
1779 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || rt2800_config_3572bt_ant()
1780 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { rt2800_config_3572bt_ant()
1784 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode); rt2800_config_3572bt_ant()
1785 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode); rt2800_config_3572bt_ant()
1786 rt2800_register_write(rt2x00dev, LED_CFG, reg); rt2800_config_3572bt_ant()
1797 u32 reg; rt2800_set_ant_diversity() local
1802 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg); rt2800_set_ant_diversity()
1803 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin); rt2800_set_ant_diversity()
1804 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); rt2800_set_ant_diversity()
1809 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg); rt2800_set_ant_diversity()
1810 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0); rt2800_set_ant_diversity()
1811 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3); rt2800_set_ant_diversity()
1812 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); rt2800_set_ant_diversity()
2115 u32 reg; rt2800_config_channel_rf3052() local
2265 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg); rt2800_config_channel_rf3052()
2266 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0); rt2800_config_channel_rf3052()
2268 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1); rt2800_config_channel_rf3052()
2270 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0); rt2800_config_channel_rf3052()
2271 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); rt2800_config_channel_rf3052()
2762 u32 reg; rt2800_config_channel_rf55xx() local
2769 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg); rt2800_config_channel_rf55xx()
2770 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, rt2800_config_channel_rf55xx()
2772 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); rt2800_config_channel_rf55xx()
3035 u8 chain, reg; rt2800_bbp_write_with_rx_chain() local
3038 rt2800_bbp_read(rt2x00dev, 27, &reg); rt2800_bbp_write_with_rx_chain()
3039 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain); rt2800_bbp_write_with_rx_chain()
3040 rt2800_bbp_write(rt2x00dev, 27, reg); rt2800_bbp_write_with_rx_chain()
3154 u32 reg; rt2800_config_channel() local
3288 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg); rt2800_config_channel()
3289 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); rt2800_config_channel()
3290 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14); rt2800_config_channel()
3291 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14); rt2800_config_channel()
3292 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); rt2800_config_channel()
3354 reg = 0x1c + (2 * rt2x00dev->lna_gain); rt2800_config_channel()
3356 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); rt2800_config_channel()
3358 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); rt2800_config_channel()
3362 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg); rt2800_config_channel()
3368 rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0); rt2800_config_channel()
3370 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1); rt2800_config_channel()
3372 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0); rt2800_config_channel()
3380 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0); rt2800_config_channel()
3381 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0); rt2800_config_channel()
3383 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1); rt2800_config_channel()
3384 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1); rt2800_config_channel()
3387 rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0); rt2800_config_channel()
3388 rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1); rt2800_config_channel()
3391 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); rt2800_config_channel()
3395 reg = 0x1c + 2 * rt2x00dev->lna_gain; rt2800_config_channel()
3397 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); rt2800_config_channel()
3399 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); rt2800_config_channel()
3409 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain; rt2800_config_channel()
3410 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); rt2800_config_channel()
3440 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg); rt2800_config_channel()
3441 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg); rt2800_config_channel()
3442 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg); rt2800_config_channel()
4105 u32 reg, offset; rt2800_config_txpower_rt28xx() local
4173 rt2800_register_read(rt2x00dev, offset, &reg); rt2800_config_txpower_rt28xx()
4189 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower); rt2800_config_txpower_rt28xx()
4200 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower); rt2800_config_txpower_rt28xx()
4211 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower); rt2800_config_txpower_rt28xx()
4222 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower); rt2800_config_txpower_rt28xx()
4238 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower); rt2800_config_txpower_rt28xx()
4249 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower); rt2800_config_txpower_rt28xx()
4260 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower); rt2800_config_txpower_rt28xx()
4271 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower); rt2800_config_txpower_rt28xx()
4273 rt2800_register_write(rt2x00dev, offset, reg); rt2800_config_txpower_rt28xx()
4380 u32 reg; rt2800_config_retry_limit() local
4382 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg); rt2800_config_retry_limit()
4383 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, rt2800_config_retry_limit()
4385 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, rt2800_config_retry_limit()
4387 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); rt2800_config_retry_limit()
4396 u32 reg; rt2800_config_ps() local
4401 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg); rt2800_config_ps()
4402 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); rt2800_config_ps()
4403 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, rt2800_config_ps()
4405 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1); rt2800_config_ps()
4406 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); rt2800_config_ps()
4410 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg); rt2800_config_ps()
4411 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); rt2800_config_ps()
4412 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); rt2800_config_ps()
4413 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0); rt2800_config_ps()
4414 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); rt2800_config_ps()
4448 u32 reg; rt2800_link_stats() local
4453 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg); rt2800_link_stats()
4454 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); rt2800_link_stats()
4564 u32 reg; rt2800_init_registers() local
4580 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); rt2800_init_registers()
4581 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600); rt2800_init_registers()
4582 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0); rt2800_init_registers()
4583 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0); rt2800_init_registers()
4584 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0); rt2800_init_registers()
4585 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); rt2800_init_registers()
4586 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); rt2800_init_registers()
4587 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); rt2800_init_registers()
4591 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg); rt2800_init_registers()
4592 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9); rt2800_init_registers()
4593 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); rt2800_init_registers()
4594 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); rt2800_init_registers()
4597 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg); rt2800_init_registers()
4598 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { rt2800_init_registers()
4599 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1); rt2800_init_registers()
4600 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); rt2800_init_registers()
4603 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg); rt2800_init_registers()
4604 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { rt2800_init_registers()
4605 rt2x00_set_field32(&reg, LDO0_EN, 1); rt2800_init_registers()
4606 rt2x00_set_field32(&reg, LDO_BGSEL, 3); rt2800_init_registers()
4607 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); rt2800_init_registers()
4610 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg); rt2800_init_registers()
4611 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1); rt2800_init_registers()
4612 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1); rt2800_init_registers()
4613 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27); rt2800_init_registers()
4614 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); rt2800_init_registers()
4616 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg); rt2800_init_registers()
4617 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e); rt2800_init_registers()
4618 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); rt2800_init_registers()
4620 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg); rt2800_init_registers()
4621 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00); rt2800_init_registers()
4622 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17); rt2800_init_registers()
4623 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93); rt2800_init_registers()
4624 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f); rt2800_init_registers()
4625 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); rt2800_init_registers()
4627 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg); rt2800_init_registers()
4628 rt2x00_set_field32(&reg, PLL_CONTROL, 1); rt2800_init_registers()
4629 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); rt2800_init_registers()
4708 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg); rt2800_init_registers()
4709 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); rt2800_init_registers()
4710 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0); rt2800_init_registers()
4711 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); rt2800_init_registers()
4712 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0); rt2800_init_registers()
4713 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0); rt2800_init_registers()
4714 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1); rt2800_init_registers()
4715 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0); rt2800_init_registers()
4716 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0); rt2800_init_registers()
4717 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); rt2800_init_registers()
4719 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg); rt2800_init_registers()
4720 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); rt2800_init_registers()
4721 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); rt2800_init_registers()
4722 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); rt2800_init_registers()
4723 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); rt2800_init_registers()
4725 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg); rt2800_init_registers()
4726 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); rt2800_init_registers()
4730 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2); rt2800_init_registers()
4732 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1); rt2800_init_registers()
4733 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0); rt2800_init_registers()
4734 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0); rt2800_init_registers()
4735 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); rt2800_init_registers()
4737 rt2800_register_read(rt2x00dev, LED_CFG, &reg); rt2800_init_registers()
4738 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70); rt2800_init_registers()
4739 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30); rt2800_init_registers()
4740 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3); rt2800_init_registers()
4741 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3); rt2800_init_registers()
4742 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3); rt2800_init_registers()
4743 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3); rt2800_init_registers()
4744 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1); rt2800_init_registers()
4745 rt2800_register_write(rt2x00dev, LED_CFG, reg); rt2800_init_registers()
4749 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg); rt2800_init_registers()
4750 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15); rt2800_init_registers()
4751 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31); rt2800_init_registers()
4752 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000); rt2800_init_registers()
4753 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); rt2800_init_registers()
4754 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0); rt2800_init_registers()
4755 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); rt2800_init_registers()
4756 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); rt2800_init_registers()
4758 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg); rt2800_init_registers()
4759 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1); rt2800_init_registers()
4760 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); rt2800_init_registers()
4761 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0); rt2800_init_registers()
4762 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0); rt2800_init_registers()
4763 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1); rt2800_init_registers()
4764 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0); rt2800_init_registers()
4765 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); rt2800_init_registers()
4766 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); rt2800_init_registers()
4768 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg); rt2800_init_registers()
4769 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3); rt2800_init_registers()
4770 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0); rt2800_init_registers()
4771 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); rt2800_init_registers()
4772 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); rt2800_init_registers()
4773 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); rt2800_init_registers()
4774 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); rt2800_init_registers()
4775 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); rt2800_init_registers()
4776 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); rt2800_init_registers()
4777 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); rt2800_init_registers()
4778 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1); rt2800_init_registers()
4779 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); rt2800_init_registers()
4781 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); rt2800_init_registers()
4782 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3); rt2800_init_registers()
4783 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0); rt2800_init_registers()
4784 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); rt2800_init_registers()
4785 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); rt2800_init_registers()
4786 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); rt2800_init_registers()
4787 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); rt2800_init_registers()
4788 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); rt2800_init_registers()
4789 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); rt2800_init_registers()
4790 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); rt2800_init_registers()
4791 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1); rt2800_init_registers()
4792 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); rt2800_init_registers()
4794 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg); rt2800_init_registers()
4795 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004); rt2800_init_registers()
4796 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0); rt2800_init_registers()
4797 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); rt2800_init_registers()
4798 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); rt2800_init_registers()
4799 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); rt2800_init_registers()
4800 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); rt2800_init_registers()
4801 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); rt2800_init_registers()
4802 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); rt2800_init_registers()
4803 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); rt2800_init_registers()
4804 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0); rt2800_init_registers()
4805 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); rt2800_init_registers()
4807 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg); rt2800_init_registers()
4808 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084); rt2800_init_registers()
4809 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0); rt2800_init_registers()
4810 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); rt2800_init_registers()
4811 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); rt2800_init_registers()
4812 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); rt2800_init_registers()
4813 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); rt2800_init_registers()
4814 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); rt2800_init_registers()
4815 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); rt2800_init_registers()
4816 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); rt2800_init_registers()
4817 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0); rt2800_init_registers()
4818 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); rt2800_init_registers()
4820 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg); rt2800_init_registers()
4821 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004); rt2800_init_registers()
4822 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0); rt2800_init_registers()
4823 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); rt2800_init_registers()
4824 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); rt2800_init_registers()
4825 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); rt2800_init_registers()
4826 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); rt2800_init_registers()
4827 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); rt2800_init_registers()
4828 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); rt2800_init_registers()
4829 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); rt2800_init_registers()
4830 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0); rt2800_init_registers()
4831 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); rt2800_init_registers()
4833 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg); rt2800_init_registers()
4834 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084); rt2800_init_registers()
4835 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0); rt2800_init_registers()
4836 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); rt2800_init_registers()
4837 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); rt2800_init_registers()
4838 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); rt2800_init_registers()
4839 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); rt2800_init_registers()
4840 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); rt2800_init_registers()
4841 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); rt2800_init_registers()
4842 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); rt2800_init_registers()
4843 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0); rt2800_init_registers()
4844 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); rt2800_init_registers()
4849 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); rt2800_init_registers()
4850 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); rt2800_init_registers()
4851 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); rt2800_init_registers()
4852 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); rt2800_init_registers()
4853 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); rt2800_init_registers()
4854 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); rt2800_init_registers()
4855 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); rt2800_init_registers()
4856 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0); rt2800_init_registers()
4857 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); rt2800_init_registers()
4858 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); rt2800_init_registers()
4859 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); rt2800_init_registers()
4866 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg); rt2800_init_registers()
4867 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); rt2800_init_registers()
4868 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1); rt2800_init_registers()
4869 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); rt2800_init_registers()
4870 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); rt2800_init_registers()
4871 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); rt2800_init_registers()
4872 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); rt2800_init_registers()
4873 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); rt2800_init_registers()
4874 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0); rt2800_init_registers()
4875 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); rt2800_init_registers()
4876 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0); rt2800_init_registers()
4877 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); rt2800_init_registers()
4879 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; rt2800_init_registers()
4880 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); rt2800_init_registers()
4882 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg); rt2800_init_registers()
4883 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); rt2800_init_registers()
4884 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, rt2800_init_registers()
4886 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0); rt2800_init_registers()
4887 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); rt2800_init_registers()
4898 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg); rt2800_init_registers()
4899 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); rt2800_init_registers()
4900 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); rt2800_init_registers()
4901 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); rt2800_init_registers()
4902 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314); rt2800_init_registers()
4903 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); rt2800_init_registers()
4904 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); rt2800_init_registers()
4928 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg); rt2800_init_registers()
4929 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30); rt2800_init_registers()
4930 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); rt2800_init_registers()
4932 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg); rt2800_init_registers()
4933 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125); rt2800_init_registers()
4934 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); rt2800_init_registers()
4937 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg); rt2800_init_registers()
4938 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0); rt2800_init_registers()
4939 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0); rt2800_init_registers()
4940 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1); rt2800_init_registers()
4941 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2); rt2800_init_registers()
4942 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3); rt2800_init_registers()
4943 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4); rt2800_init_registers()
4944 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5); rt2800_init_registers()
4945 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6); rt2800_init_registers()
4946 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); rt2800_init_registers()
4948 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg); rt2800_init_registers()
4949 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8); rt2800_init_registers()
4950 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8); rt2800_init_registers()
4951 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9); rt2800_init_registers()
4952 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10); rt2800_init_registers()
4953 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11); rt2800_init_registers()
4954 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12); rt2800_init_registers()
4955 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13); rt2800_init_registers()
4956 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14); rt2800_init_registers()
4957 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); rt2800_init_registers()
4959 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg); rt2800_init_registers()
4960 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8); rt2800_init_registers()
4961 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8); rt2800_init_registers()
4962 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9); rt2800_init_registers()
4963 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10); rt2800_init_registers()
4964 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11); rt2800_init_registers()
4965 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12); rt2800_init_registers()
4966 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13); rt2800_init_registers()
4967 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14); rt2800_init_registers()
4968 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); rt2800_init_registers()
4970 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg); rt2800_init_registers()
4971 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0); rt2800_init_registers()
4972 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0); rt2800_init_registers()
4973 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1); rt2800_init_registers()
4974 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2); rt2800_init_registers()
4975 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); rt2800_init_registers()
4980 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg); rt2800_init_registers()
4981 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); rt2800_init_registers()
4982 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); rt2800_init_registers()
4983 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); rt2800_init_registers()
4990 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg); rt2800_init_registers()
4991 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg); rt2800_init_registers()
4992 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg); rt2800_init_registers()
4993 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg); rt2800_init_registers()
4994 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg); rt2800_init_registers()
4995 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg); rt2800_init_registers()
5000 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg); rt2800_init_registers()
5001 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); rt2800_init_registers()
5002 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); rt2800_init_registers()
5007 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg); rt2800_init_registers()
5008 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1); rt2800_init_registers()
5009 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1); rt2800_init_registers()
5010 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1); rt2800_init_registers()
5011 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1); rt2800_init_registers()
5012 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1); rt2800_init_registers()
5013 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); rt2800_init_registers()
5021 u32 reg; rt2800_wait_bbp_rf_ready() local
5024 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg); rt2800_wait_bbp_rf_ready()
5025 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) rt2800_wait_bbp_rf_ready()
5557 u32 reg; rt2800_init_bbp_53xx() local
5559 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg); rt2800_init_bbp_53xx()
5560 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0); rt2800_init_bbp_53xx()
5561 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0); rt2800_init_bbp_53xx()
5562 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0); rt2800_init_bbp_53xx()
5563 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0); rt2800_init_bbp_53xx()
5565 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1); rt2800_init_bbp_53xx()
5567 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1); rt2800_init_bbp_53xx()
5568 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); rt2800_init_bbp_53xx()
5721 u32 reg; rt2800_led_open_drain_enable() local
5723 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg); rt2800_led_open_drain_enable()
5724 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1); rt2800_led_open_drain_enable()
5725 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); rt2800_led_open_drain_enable()
5961 u8 reg; rt2800_normal_mode_setup_5xxx() local
5965 rt2800_bbp_read(rt2x00dev, 138, &reg); rt2800_normal_mode_setup_5xxx()
5968 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0); rt2800_normal_mode_setup_5xxx()
5970 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1); rt2800_normal_mode_setup_5xxx()
5971 rt2800_bbp_write(rt2x00dev, 138, reg); rt2800_normal_mode_setup_5xxx()
5973 rt2800_rfcsr_read(rt2x00dev, 38, &reg); rt2800_normal_mode_setup_5xxx()
5974 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0); rt2800_normal_mode_setup_5xxx()
5975 rt2800_rfcsr_write(rt2x00dev, 38, reg); rt2800_normal_mode_setup_5xxx()
5977 rt2800_rfcsr_read(rt2x00dev, 39, &reg); rt2800_normal_mode_setup_5xxx()
5978 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0); rt2800_normal_mode_setup_5xxx()
5979 rt2800_rfcsr_write(rt2x00dev, 39, reg); rt2800_normal_mode_setup_5xxx()
5983 rt2800_rfcsr_read(rt2x00dev, 30, &reg); rt2800_normal_mode_setup_5xxx()
5984 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2); rt2800_normal_mode_setup_5xxx()
5985 rt2800_rfcsr_write(rt2x00dev, 30, reg); rt2800_normal_mode_setup_5xxx()
6030 u32 reg; rt2800_init_rfcsr_30xx() local
6056 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg); rt2800_init_rfcsr_30xx()
6057 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1); rt2800_init_rfcsr_30xx()
6058 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3); rt2800_init_rfcsr_30xx()
6059 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); rt2800_init_rfcsr_30xx()
6068 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg); rt2800_init_rfcsr_30xx()
6069 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1); rt2800_init_rfcsr_30xx()
6075 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3); rt2800_init_rfcsr_30xx()
6077 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0); rt2800_init_rfcsr_30xx()
6079 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); rt2800_init_rfcsr_30xx()
6081 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg); rt2800_init_rfcsr_30xx()
6082 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0); rt2800_init_rfcsr_30xx()
6083 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); rt2800_init_rfcsr_30xx()
6233 u32 reg; rt2800_init_rfcsr_3390() local
6270 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg); rt2800_init_rfcsr_3390()
6271 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0); rt2800_init_rfcsr_3390()
6272 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); rt2800_init_rfcsr_3390()
6286 u32 reg; rt2800_init_rfcsr_3572() local
6326 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg); rt2800_init_rfcsr_3572()
6327 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3); rt2800_init_rfcsr_3572()
6328 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1); rt2800_init_rfcsr_3572()
6329 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); rt2800_init_rfcsr_3572()
6331 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg); rt2800_init_rfcsr_3572()
6332 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0); rt2800_init_rfcsr_3572()
6333 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1); rt2800_init_rfcsr_3572()
6334 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); rt2800_init_rfcsr_3572()
6391 u32 reg; rt2800_init_rfcsr_3593() local
6395 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg); rt2800_init_rfcsr_3593()
6396 rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0); rt2800_init_rfcsr_3593()
6397 rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0); rt2800_init_rfcsr_3593()
6398 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); rt2800_init_rfcsr_3593()
6446 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg); rt2800_init_rfcsr_3593()
6447 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3); rt2800_init_rfcsr_3593()
6448 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1); rt2800_init_rfcsr_3593()
6449 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); rt2800_init_rfcsr_3593()
6451 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg); rt2800_init_rfcsr_3593()
6452 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0); rt2800_init_rfcsr_3593()
6453 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); rt2800_init_rfcsr_3593()
6722 u32 reg; rt2800_enable_radio() local
6772 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); rt2800_enable_radio()
6773 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); rt2800_enable_radio()
6774 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0); rt2800_enable_radio()
6775 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); rt2800_enable_radio()
6779 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); rt2800_enable_radio()
6780 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); rt2800_enable_radio()
6781 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); rt2800_enable_radio()
6782 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2); rt2800_enable_radio()
6783 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); rt2800_enable_radio()
6784 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); rt2800_enable_radio()
6786 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); rt2800_enable_radio()
6787 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); rt2800_enable_radio()
6788 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1); rt2800_enable_radio()
6789 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); rt2800_enable_radio()
6812 u32 reg; rt2800_disable_radio() local
6819 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); rt2800_disable_radio()
6820 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0); rt2800_disable_radio()
6821 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0); rt2800_disable_radio()
6822 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); rt2800_disable_radio()
6828 u32 reg; rt2800_efuse_detect() local
6836 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg); rt2800_efuse_detect()
6837 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); rt2800_efuse_detect()
6843 u32 reg; rt2800_efuse_read() local
6865 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg); rt2800_efuse_read()
6866 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i); rt2800_efuse_read()
6867 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0); rt2800_efuse_read()
6868 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1); rt2800_efuse_read()
6869 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); rt2800_efuse_read()
6872 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg); rt2800_efuse_read()
6874 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg); rt2800_efuse_read()
6876 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); rt2800_efuse_read()
6877 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg); rt2800_efuse_read()
6878 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); rt2800_efuse_read()
6879 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg); rt2800_efuse_read()
6880 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); rt2800_efuse_read()
6881 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg); rt2800_efuse_read()
6882 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); rt2800_efuse_read()
7491 u32 reg; rt2800_probe_hw_mode() local
7581 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg); rt2800_probe_hw_mode()
7582 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { rt2800_probe_hw_mode()
7709 u32 reg; rt2800_probe_rt() local
7714 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg); rt2800_probe_rt()
7716 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg); rt2800_probe_rt()
7718 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); rt2800_probe_rt()
7719 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); rt2800_probe_rt()
7751 u32 reg; rt2800_probe_hw() local
7772 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg); rt2800_probe_hw()
7773 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1); rt2800_probe_hw()
7774 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); rt2800_probe_hw()
7840 u32 reg; rt2800_set_rts_threshold() local
7843 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg); rt2800_set_rts_threshold()
7844 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value); rt2800_set_rts_threshold()
7845 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); rt2800_set_rts_threshold()
7847 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg); rt2800_set_rts_threshold()
7848 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled); rt2800_set_rts_threshold()
7849 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); rt2800_set_rts_threshold()
7851 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); rt2800_set_rts_threshold()
7852 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled); rt2800_set_rts_threshold()
7853 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); rt2800_set_rts_threshold()
7855 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg); rt2800_set_rts_threshold()
7856 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled); rt2800_set_rts_threshold()
7857 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); rt2800_set_rts_threshold()
7859 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg); rt2800_set_rts_threshold()
7860 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled); rt2800_set_rts_threshold()
7861 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); rt2800_set_rts_threshold()
7863 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg); rt2800_set_rts_threshold()
7864 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled); rt2800_set_rts_threshold()
7865 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); rt2800_set_rts_threshold()
7867 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg); rt2800_set_rts_threshold()
7868 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled); rt2800_set_rts_threshold()
7869 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); rt2800_set_rts_threshold()
7883 u32 reg; rt2800_conf_tx() local
7910 rt2800_register_read(rt2x00dev, offset, &reg); rt2800_conf_tx()
7911 rt2x00_set_field32(&reg, field, queue->txop); rt2800_conf_tx()
7912 rt2800_register_write(rt2x00dev, offset, reg); rt2800_conf_tx()
7918 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg); rt2800_conf_tx()
7919 rt2x00_set_field32(&reg, field, queue->aifs); rt2800_conf_tx()
7920 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); rt2800_conf_tx()
7922 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg); rt2800_conf_tx()
7923 rt2x00_set_field32(&reg, field, queue->cw_min); rt2800_conf_tx()
7924 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); rt2800_conf_tx()
7926 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg); rt2800_conf_tx()
7927 rt2x00_set_field32(&reg, field, queue->cw_max); rt2800_conf_tx()
7928 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); rt2800_conf_tx()
7933 rt2800_register_read(rt2x00dev, offset, &reg); rt2800_conf_tx()
7934 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop); rt2800_conf_tx()
7935 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs); rt2800_conf_tx()
7936 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min); rt2800_conf_tx()
7937 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max); rt2800_conf_tx()
7938 rt2800_register_write(rt2x00dev, offset, reg); rt2800_conf_tx()
7948 u32 reg; rt2800_get_tsf() local
7950 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg); rt2800_get_tsf()
7951 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; rt2800_get_tsf()
7952 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg); rt2800_get_tsf()
7953 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); rt2800_get_tsf()
/linux-4.1.27/arch/arm/mach-tegra/
H A Dflowctrl.c76 unsigned int reg; flowctrl_cpu_suspend_enter() local
79 reg = flowctrl_read_cpu_csr(cpuid); flowctrl_cpu_suspend_enter()
83 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; flowctrl_cpu_suspend_enter()
85 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; flowctrl_cpu_suspend_enter()
87 reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; flowctrl_cpu_suspend_enter()
93 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; flowctrl_cpu_suspend_enter()
95 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; flowctrl_cpu_suspend_enter()
97 reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; flowctrl_cpu_suspend_enter()
100 reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ flowctrl_cpu_suspend_enter()
101 reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ flowctrl_cpu_suspend_enter()
102 reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ flowctrl_cpu_suspend_enter()
103 flowctrl_write_cpu_csr(cpuid, reg); flowctrl_cpu_suspend_enter()
108 reg = flowctrl_read_cpu_csr(i); flowctrl_cpu_suspend_enter()
109 reg |= FLOW_CTRL_CSR_EVENT_FLAG; flowctrl_cpu_suspend_enter()
110 reg |= FLOW_CTRL_CSR_INTR_FLAG; flowctrl_cpu_suspend_enter()
111 flowctrl_write_cpu_csr(i, reg); flowctrl_cpu_suspend_enter()
117 unsigned int reg; flowctrl_cpu_suspend_exit() local
120 reg = flowctrl_read_cpu_csr(cpuid); flowctrl_cpu_suspend_exit()
124 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; flowctrl_cpu_suspend_exit()
126 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; flowctrl_cpu_suspend_exit()
132 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; flowctrl_cpu_suspend_exit()
134 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; flowctrl_cpu_suspend_exit()
137 reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */ flowctrl_cpu_suspend_exit()
138 reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */ flowctrl_cpu_suspend_exit()
139 reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ flowctrl_cpu_suspend_exit()
140 flowctrl_write_cpu_csr(cpuid, reg); flowctrl_cpu_suspend_exit()
/linux-4.1.27/drivers/net/phy/
H A Dbcm63xx.c25 int reg, err; bcm63xx_config_init() local
27 reg = phy_read(phydev, MII_BCM63XX_IR); bcm63xx_config_init()
28 if (reg < 0) bcm63xx_config_init()
29 return reg; bcm63xx_config_init()
32 reg |= MII_BCM63XX_IR_GMASK; bcm63xx_config_init()
33 err = phy_write(phydev, MII_BCM63XX_IR, reg); bcm63xx_config_init()
38 reg = ~(MII_BCM63XX_IR_DUPLEX | bcm63xx_config_init()
42 return phy_write(phydev, MII_BCM63XX_IR, reg); bcm63xx_config_init()
47 int reg; bcm63xx_ack_interrupt() local
50 reg = phy_read(phydev, MII_BCM63XX_IR); bcm63xx_ack_interrupt()
51 if (reg < 0) bcm63xx_ack_interrupt()
52 return reg; bcm63xx_ack_interrupt()
59 int reg, err; bcm63xx_config_intr() local
61 reg = phy_read(phydev, MII_BCM63XX_IR); bcm63xx_config_intr()
62 if (reg < 0) bcm63xx_config_intr()
63 return reg; bcm63xx_config_intr()
66 reg &= ~MII_BCM63XX_IR_GMASK; bcm63xx_config_intr()
68 reg |= MII_BCM63XX_IR_GMASK; bcm63xx_config_intr()
70 err = phy_write(phydev, MII_BCM63XX_IR, reg); bcm63xx_config_intr()
H A Dbroadcom.c212 int reg, err; bcm54xx_config_init() local
214 reg = phy_read(phydev, MII_BCM54XX_ECR); bcm54xx_config_init()
215 if (reg < 0) bcm54xx_config_init()
216 return reg; bcm54xx_config_init()
219 reg |= MII_BCM54XX_ECR_IM; bcm54xx_config_init()
220 err = phy_write(phydev, MII_BCM54XX_ECR, reg); bcm54xx_config_init()
225 reg = ~(MII_BCM54XX_INT_DUPLEX | bcm54xx_config_init()
228 err = phy_write(phydev, MII_BCM54XX_IMR, reg); bcm54xx_config_init()
249 int err, reg; bcm5482_config_init() local
257 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_SSD); bcm5482_config_init()
259 reg | bcm5482_config_init()
266 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD; bcm5482_config_init()
267 err = bcm54xx_exp_read(phydev, reg); bcm5482_config_init()
270 err = bcm54xx_exp_write(phydev, reg, err | bcm5482_config_init()
279 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD; bcm5482_config_init()
280 err = bcm54xx_exp_read(phydev, reg); bcm5482_config_init()
283 err = bcm54xx_exp_write(phydev, reg, bcm5482_config_init()
291 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_MODE); bcm5482_config_init()
293 reg | BCM5482_SHD_MODE_1000BX); bcm5482_config_init()
339 int reg; bcm54xx_ack_interrupt() local
342 reg = phy_read(phydev, MII_BCM54XX_ISR); bcm54xx_ack_interrupt()
343 if (reg < 0) bcm54xx_ack_interrupt()
344 return reg; bcm54xx_ack_interrupt()
351 int reg, err; bcm54xx_config_intr() local
353 reg = phy_read(phydev, MII_BCM54XX_ECR); bcm54xx_config_intr()
354 if (reg < 0) bcm54xx_config_intr()
355 return reg; bcm54xx_config_intr()
358 reg &= ~MII_BCM54XX_ECR_IM; bcm54xx_config_intr()
360 reg |= MII_BCM54XX_ECR_IM; bcm54xx_config_intr()
362 err = phy_write(phydev, MII_BCM54XX_ECR, reg); bcm54xx_config_intr()
375 u16 reg; bcm5481_config_aneg() local
387 reg = 0x7 | (0x7 << 12); bcm5481_config_aneg()
388 phy_write(phydev, 0x18, reg); bcm5481_config_aneg()
390 reg = phy_read(phydev, 0x18); bcm5481_config_aneg()
392 reg |= (1 << 8); bcm5481_config_aneg()
394 reg |= (1 << 15); bcm5481_config_aneg()
395 phy_write(phydev, 0x18, reg); bcm5481_config_aneg()
401 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set) brcm_phy_setbits() argument
405 val = phy_read(phydev, reg); brcm_phy_setbits()
409 return phy_write(phydev, reg, val | set); brcm_phy_setbits()
414 int reg, err, err2, brcmtest; brcm_fet_config_init() local
421 reg = phy_read(phydev, MII_BRCM_FET_INTREG); brcm_fet_config_init()
422 if (reg < 0) brcm_fet_config_init()
423 return reg; brcm_fet_config_init()
426 reg = MII_BRCM_FET_IR_DUPLEX_EN | brcm_fet_config_init()
432 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); brcm_fet_config_init()
441 reg = brcmtest | MII_BRCM_FET_BT_SRE; brcm_fet_config_init()
443 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); brcm_fet_config_init()
448 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4); brcm_fet_config_init()
449 if (reg < 0) { brcm_fet_config_init()
450 err = reg; brcm_fet_config_init()
454 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK; brcm_fet_config_init()
455 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1; brcm_fet_config_init()
457 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); brcm_fet_config_init()
484 int reg; brcm_fet_ack_interrupt() local
487 reg = phy_read(phydev, MII_BRCM_FET_INTREG); brcm_fet_ack_interrupt()
488 if (reg < 0) brcm_fet_ack_interrupt()
489 return reg; brcm_fet_ack_interrupt()
496 int reg, err; brcm_fet_config_intr() local
498 reg = phy_read(phydev, MII_BRCM_FET_INTREG); brcm_fet_config_intr()
499 if (reg < 0) brcm_fet_config_intr()
500 return reg; brcm_fet_config_intr()
503 reg &= ~MII_BRCM_FET_IR_MASK; brcm_fet_config_intr()
505 reg |= MII_BRCM_FET_IR_MASK; brcm_fet_config_intr()
507 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); brcm_fet_config_intr()
/linux-4.1.27/arch/arm/mach-imx/
H A Dclk-gate2.c32 void __iomem *reg; member in struct:clk_gate2
44 u32 reg; clk_gate2_enable() local
52 reg = readl(gate->reg); clk_gate2_enable()
53 reg |= 3 << gate->bit_idx; clk_gate2_enable()
54 writel(reg, gate->reg); clk_gate2_enable()
65 u32 reg; clk_gate2_disable() local
77 reg = readl(gate->reg); clk_gate2_disable()
78 reg &= ~(3 << gate->bit_idx); clk_gate2_disable()
79 writel(reg, gate->reg); clk_gate2_disable()
85 static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx) clk_gate2_reg_is_enabled() argument
87 u32 val = readl(reg); clk_gate2_reg_is_enabled()
99 return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); clk_gate2_is_enabled()
106 u32 reg; clk_gate2_disable_unused() local
111 reg = readl(gate->reg); clk_gate2_disable_unused()
112 reg &= ~(3 << gate->bit_idx); clk_gate2_disable_unused()
113 writel(reg, gate->reg); clk_gate2_disable_unused()
128 void __iomem *reg, u8 bit_idx, clk_register_gate2()
141 gate->reg = reg; clk_register_gate2()
126 clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate2_flags, spinlock_t *lock, unsigned int *share_count) clk_register_gate2() argument
H A Dclk.h33 void __iomem *reg, u8 bit_idx,
41 void __iomem *reg, u8 shift, u32 exclusive_mask);
44 void __iomem *reg, u8 shift) imx_clk_gate2()
46 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, imx_clk_gate2()
51 const char *parent, void __iomem *reg, u8 shift, imx_clk_gate2_shared()
54 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, imx_clk_gate2_shared()
59 void __iomem *reg, u8 idx);
62 void __iomem *reg, u8 shift, u8 width,
65 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
70 void __iomem *reg, u8 shift, u8 width,
73 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
83 void __iomem *reg, u8 shift, u8 width) imx_clk_divider()
86 reg, shift, width, 0, &imx_ccm_lock); imx_clk_divider()
90 const char *parent, void __iomem *reg, u8 shift, u8 width, imx_clk_divider_flags()
94 reg, shift, width, 0, &imx_ccm_lock); imx_clk_divider_flags()
98 void __iomem *reg, u8 shift) imx_clk_gate()
100 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, imx_clk_gate()
105 void __iomem *reg, u8 shift) imx_clk_gate_dis()
107 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, imx_clk_gate_dis()
111 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, imx_clk_mux() argument
115 CLK_SET_RATE_NO_REPARENT, reg, shift, imx_clk_mux()
120 void __iomem *reg, u8 shift, u8 width, const char **parents, imx_clk_mux_flags()
124 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, imx_clk_mux_flags()
43 imx_clk_gate2(const char *name, const char *parent, void __iomem *reg, u8 shift) imx_clk_gate2() argument
50 imx_clk_gate2_shared(const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned int *share_count) imx_clk_gate2_shared() argument
82 imx_clk_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width) imx_clk_divider() argument
89 imx_clk_divider_flags(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, unsigned long flags) imx_clk_divider_flags() argument
97 imx_clk_gate(const char *name, const char *parent, void __iomem *reg, u8 shift) imx_clk_gate() argument
104 imx_clk_gate_dis(const char *name, const char *parent, void __iomem *reg, u8 shift) imx_clk_gate_dis() argument
119 imx_clk_mux_flags(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents, unsigned long flags) imx_clk_mux_flags() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
H A Dhwsq.h86 hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg) hwsq_rd32() argument
88 if (reg->sequence != ram->sequence) hwsq_rd32()
89 reg->data = nv_rd32(ram->subdev, reg->addr); hwsq_rd32()
90 return reg->data; hwsq_rd32()
94 hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data) hwsq_wr32() argument
98 reg->sequence = ram->sequence; hwsq_wr32()
99 reg->data = data; hwsq_wr32()
101 for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) { hwsq_wr32()
103 nvkm_hwsq_wr32(ram->hwsq, reg->addr+off, reg->data); hwsq_wr32()
105 off += reg->stride; hwsq_wr32()
110 hwsq_nuke(struct hwsq *ram, struct hwsq_reg *reg) hwsq_nuke() argument
112 reg->force = true; hwsq_nuke()
116 hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data) hwsq_mask() argument
118 u32 temp = hwsq_rd32(ram, reg); hwsq_mask()
119 if (temp != ((temp & ~mask) | data) || reg->force) hwsq_mask()
120 hwsq_wr32(ram, reg, (temp & ~mask) | data); hwsq_mask()
/linux-4.1.27/sound/hda/
H A Dhdac_regmap.c32 #define get_verb(reg) (((reg) >> 8) & 0xfff)
34 static bool hda_volatile_reg(struct device *dev, unsigned int reg) hda_volatile_reg() argument
37 unsigned int verb = get_verb(reg); hda_volatile_reg()
61 static bool hda_writeable_reg(struct device *dev, unsigned int reg) hda_writeable_reg() argument
64 unsigned int verb = get_verb(reg); hda_writeable_reg()
110 static bool hda_readable_reg(struct device *dev, unsigned int reg) hda_readable_reg() argument
113 unsigned int verb = get_verb(reg); hda_readable_reg()
132 return hda_writeable_reg(dev, reg); hda_readable_reg()
143 static bool is_stereo_amp_verb(unsigned int reg) is_stereo_amp_verb() argument
145 if (((reg >> 8) & 0x700) != AC_VERB_SET_AMP_GAIN_MUTE) is_stereo_amp_verb()
147 return (reg & (AC_AMP_SET_LEFT | AC_AMP_SET_RIGHT)) == is_stereo_amp_verb()
153 unsigned int reg, unsigned int *val) hda_reg_read_stereo_amp()
158 reg &= ~(AC_AMP_SET_LEFT | AC_AMP_SET_RIGHT); hda_reg_read_stereo_amp()
159 err = snd_hdac_exec_verb(codec, reg | AC_AMP_GET_LEFT, 0, &left); hda_reg_read_stereo_amp()
162 err = snd_hdac_exec_verb(codec, reg | AC_AMP_GET_RIGHT, 0, &right); hda_reg_read_stereo_amp()
171 unsigned int reg, unsigned int val) hda_reg_write_stereo_amp()
177 if (reg & AC_AMP_GET_OUTPUT) hda_reg_write_stereo_amp()
180 verb |= AC_AMP_SET_INPUT | ((reg & 0xf) << 8); hda_reg_write_stereo_amp()
181 reg = (reg & ~0xfffff) | verb; hda_reg_write_stereo_amp()
186 reg |= AC_AMP_SET_LEFT | AC_AMP_SET_RIGHT; hda_reg_write_stereo_amp()
187 return snd_hdac_exec_verb(codec, reg | left, 0, NULL); hda_reg_write_stereo_amp()
190 err = snd_hdac_exec_verb(codec, reg | AC_AMP_SET_LEFT | left, 0, NULL); hda_reg_write_stereo_amp()
193 err = snd_hdac_exec_verb(codec, reg | AC_AMP_SET_RIGHT | right, 0, NULL); hda_reg_write_stereo_amp()
200 static int hda_reg_read_coef(struct hdac_device *codec, unsigned int reg, hda_reg_read_coef() argument
209 verb = (reg & ~0xfff00) | (AC_VERB_SET_COEF_INDEX << 8); hda_reg_read_coef()
213 verb = (reg & ~0xfffff) | (AC_VERB_GET_COEF_INDEX << 8); hda_reg_read_coef()
218 static int hda_reg_write_coef(struct hdac_device *codec, unsigned int reg, hda_reg_write_coef() argument
227 verb = (reg & ~0xfff00) | (AC_VERB_SET_COEF_INDEX << 8); hda_reg_write_coef()
231 verb = (reg & ~0xfffff) | (AC_VERB_GET_COEF_INDEX << 8) | hda_reg_write_coef()
236 static int hda_reg_read(void *context, unsigned int reg, unsigned int *val) hda_reg_read() argument
239 int verb = get_verb(reg); hda_reg_read()
244 reg |= (codec->addr << 28); hda_reg_read()
245 if (is_stereo_amp_verb(reg)) hda_reg_read()
246 return hda_reg_read_stereo_amp(codec, reg, val); hda_reg_read()
248 return hda_reg_read_coef(codec, reg, val); hda_reg_read()
250 reg &= ~AC_AMP_FAKE_MUTE; hda_reg_read()
252 err = snd_hdac_exec_verb(codec, reg, 0, val); hda_reg_read()
265 static int hda_reg_write(void *context, unsigned int reg, unsigned int val) hda_reg_write() argument
274 reg &= ~0x00080000U; /* drop GET bit */ hda_reg_write()
275 reg |= (codec->addr << 28); hda_reg_write()
276 verb = get_verb(reg); hda_reg_write()
281 if (is_stereo_amp_verb(reg)) hda_reg_write()
282 return hda_reg_write_stereo_amp(codec, reg, val); hda_reg_write()
285 return hda_reg_write_coef(codec, reg, val); hda_reg_write()
289 if ((reg & AC_AMP_FAKE_MUTE) && (val & AC_AMP_MUTE)) hda_reg_write()
292 if (reg & AC_AMP_GET_LEFT) hda_reg_write()
296 if (reg & AC_AMP_GET_OUTPUT) { hda_reg_write()
300 verb |= reg & 0xf; hda_reg_write()
318 reg &= ~0xfffff; hda_reg_write()
319 reg |= (verb + i) << 8 | ((val >> (8 * i)) & 0xff); hda_reg_write()
320 err = snd_hdac_exec_verb(codec, reg, 0, NULL); hda_reg_write()
389 static int reg_raw_write(struct hdac_device *codec, unsigned int reg, reg_raw_write() argument
393 return hda_reg_write(codec, reg, val); reg_raw_write()
395 return regmap_write(codec->regmap, reg, val); reg_raw_write()
401 * @reg: pseudo register
406 int snd_hdac_regmap_write_raw(struct hdac_device *codec, unsigned int reg, snd_hdac_regmap_write_raw() argument
411 err = reg_raw_write(codec, reg, val); snd_hdac_regmap_write_raw()
415 err = reg_raw_write(codec, reg, val); snd_hdac_regmap_write_raw()
422 static int reg_raw_read(struct hdac_device *codec, unsigned int reg, reg_raw_read() argument
426 return hda_reg_read(codec, reg, val); reg_raw_read()
428 return regmap_read(codec->regmap, reg, val); reg_raw_read()
434 * @reg: pseudo register
439 int snd_hdac_regmap_read_raw(struct hdac_device *codec, unsigned int reg, snd_hdac_regmap_read_raw() argument
444 err = reg_raw_read(codec, reg, val); snd_hdac_regmap_read_raw()
448 err = reg_raw_read(codec, reg, val); snd_hdac_regmap_read_raw()
458 * @reg: pseudo register
464 int snd_hdac_regmap_update_raw(struct hdac_device *codec, unsigned int reg, snd_hdac_regmap_update_raw() argument
471 err = snd_hdac_regmap_read_raw(codec, reg, &orig); snd_hdac_regmap_update_raw()
477 err = snd_hdac_regmap_write_raw(codec, reg, val); snd_hdac_regmap_update_raw()
152 hda_reg_read_stereo_amp(struct hdac_device *codec, unsigned int reg, unsigned int *val) hda_reg_read_stereo_amp() argument
170 hda_reg_write_stereo_amp(struct hdac_device *codec, unsigned int reg, unsigned int val) hda_reg_write_stereo_amp() argument
/linux-4.1.27/drivers/regulator/
H A Dvexpress.c34 struct vexpress_regulator *reg = rdev_get_drvdata(regdev); vexpress_regulator_get_voltage() local
36 int err = regmap_read(reg->regmap, 0, &uV); vexpress_regulator_get_voltage()
44 struct vexpress_regulator *reg = rdev_get_drvdata(regdev); vexpress_regulator_set_voltage() local
46 return regmap_write(reg->regmap, 0, min_uV); vexpress_regulator_set_voltage()
60 struct vexpress_regulator *reg; vexpress_regulator_probe() local
64 reg = devm_kzalloc(&pdev->dev, sizeof(*reg), GFP_KERNEL); vexpress_regulator_probe()
65 if (!reg) vexpress_regulator_probe()
68 reg->regmap = devm_regmap_init_vexpress_config(&pdev->dev); vexpress_regulator_probe()
69 if (IS_ERR(reg->regmap)) vexpress_regulator_probe()
70 return PTR_ERR(reg->regmap); vexpress_regulator_probe()
72 reg->desc.name = dev_name(&pdev->dev); vexpress_regulator_probe()
73 reg->desc.type = REGULATOR_VOLTAGE; vexpress_regulator_probe()
74 reg->desc.owner = THIS_MODULE; vexpress_regulator_probe()
75 reg->desc.continuous_voltage_range = true; vexpress_regulator_probe()
78 &reg->desc); vexpress_regulator_probe()
84 reg->desc.ops = &vexpress_regulator_ops; vexpress_regulator_probe()
86 reg->desc.ops = &vexpress_regulator_ops_ro; vexpress_regulator_probe()
90 config.driver_data = reg; vexpress_regulator_probe()
93 reg->regdev = devm_regulator_register(&pdev->dev, &reg->desc, &config); vexpress_regulator_probe()
94 if (IS_ERR(reg->regdev)) vexpress_regulator_probe()
95 return PTR_ERR(reg->regdev); vexpress_regulator_probe()
97 platform_set_drvdata(pdev, reg); vexpress_regulator_probe()
H A Dtps6507x-regulator.c122 static inline int tps6507x_pmic_read(struct tps6507x_pmic *tps, u8 reg) tps6507x_pmic_read() argument
127 err = tps->mfd->read_dev(tps->mfd, reg, 1, &val); tps6507x_pmic_read()
135 static inline int tps6507x_pmic_write(struct tps6507x_pmic *tps, u8 reg, u8 val) tps6507x_pmic_write() argument
137 return tps->mfd->write_dev(tps->mfd, reg, 1, &val); tps6507x_pmic_write()
140 static int tps6507x_pmic_set_bits(struct tps6507x_pmic *tps, u8 reg, u8 mask) tps6507x_pmic_set_bits() argument
146 data = tps6507x_pmic_read(tps, reg); tps6507x_pmic_set_bits()
148 dev_err(tps->mfd->dev, "Read from reg 0x%x failed\n", reg); tps6507x_pmic_set_bits()
154 err = tps6507x_pmic_write(tps, reg, data); tps6507x_pmic_set_bits()
156 dev_err(tps->mfd->dev, "Write for reg 0x%x failed\n", reg); tps6507x_pmic_set_bits()
163 static int tps6507x_pmic_clear_bits(struct tps6507x_pmic *tps, u8 reg, u8 mask) tps6507x_pmic_clear_bits() argument
169 data = tps6507x_pmic_read(tps, reg); tps6507x_pmic_clear_bits()
171 dev_err(tps->mfd->dev, "Read from reg 0x%x failed\n", reg); tps6507x_pmic_clear_bits()
177 err = tps6507x_pmic_write(tps, reg, data); tps6507x_pmic_clear_bits()
179 dev_err(tps->mfd->dev, "Write for reg 0x%x failed\n", reg); tps6507x_pmic_clear_bits()
186 static int tps6507x_pmic_reg_read(struct tps6507x_pmic *tps, u8 reg) tps6507x_pmic_reg_read() argument
192 data = tps6507x_pmic_read(tps, reg); tps6507x_pmic_reg_read()
194 dev_err(tps->mfd->dev, "Read from reg 0x%x failed\n", reg); tps6507x_pmic_reg_read()
200 static int tps6507x_pmic_reg_write(struct tps6507x_pmic *tps, u8 reg, u8 val) tps6507x_pmic_reg_write() argument
206 err = tps6507x_pmic_write(tps, reg, val); tps6507x_pmic_reg_write()
208 dev_err(tps->mfd->dev, "Write for reg 0x%x failed\n", reg); tps6507x_pmic_reg_write()
263 u8 reg, mask; tps6507x_pmic_get_voltage_sel() local
267 reg = TPS6507X_REG_DEFDCDC1; tps6507x_pmic_get_voltage_sel()
272 reg = TPS6507X_REG_DEFDCDC2_HIGH; tps6507x_pmic_get_voltage_sel()
274 reg = TPS6507X_REG_DEFDCDC2_LOW; tps6507x_pmic_get_voltage_sel()
279 reg = TPS6507X_REG_DEFDCDC3_HIGH; tps6507x_pmic_get_voltage_sel()
281 reg = TPS6507X_REG_DEFDCDC3_LOW; tps6507x_pmic_get_voltage_sel()
285 reg = TPS6507X_REG_LDO_CTRL1; tps6507x_pmic_get_voltage_sel()
289 reg = TPS6507X_REG_DEFLDO2; tps6507x_pmic_get_voltage_sel()
296 data = tps6507x_pmic_reg_read(tps, reg); tps6507x_pmic_get_voltage_sel()
309 u8 reg, mask; tps6507x_pmic_set_voltage_sel() local
313 reg = TPS6507X_REG_DEFDCDC1; tps6507x_pmic_set_voltage_sel()
318 reg = TPS6507X_REG_DEFDCDC2_HIGH; tps6507x_pmic_set_voltage_sel()
320 reg = TPS6507X_REG_DEFDCDC2_LOW; tps6507x_pmic_set_voltage_sel()
325 reg = TPS6507X_REG_DEFDCDC3_HIGH; tps6507x_pmic_set_voltage_sel()
327 reg = TPS6507X_REG_DEFDCDC3_LOW; tps6507x_pmic_set_voltage_sel()
331 reg = TPS6507X_REG_LDO_CTRL1; tps6507x_pmic_set_voltage_sel()
335 reg = TPS6507X_REG_DEFLDO2; tps6507x_pmic_set_voltage_sel()
342 data = tps6507x_pmic_reg_read(tps, reg); tps6507x_pmic_set_voltage_sel()
349 return tps6507x_pmic_reg_write(tps, reg, data); tps6507x_pmic_set_voltage_sel()
/linux-4.1.27/arch/cris/include/asm/
H A Detraxi2c.h16 #define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value))
17 #define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8))
29 i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val);
32 i2c_arg = I2C_READARG(STA013_READ_ADDR, reg);
/linux-4.1.27/drivers/net/ethernet/broadcom/genet/
H A Dbcmgenet_wol.c47 u32 reg; bcmgenet_get_wol() local
54 reg = bcmgenet_umac_readl(priv, UMAC_MPD_PW_MS); bcmgenet_get_wol()
55 put_unaligned_be16(reg, &wol->sopass[0]); bcmgenet_get_wol()
56 reg = bcmgenet_umac_readl(priv, UMAC_MPD_PW_LS); bcmgenet_get_wol()
57 put_unaligned_be32(reg, &wol->sopass[2]); bcmgenet_get_wol()
68 u32 reg; bcmgenet_set_wol() local
76 reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL); bcmgenet_set_wol()
82 reg |= MPD_PW_EN; bcmgenet_set_wol()
84 reg &= ~MPD_PW_EN; bcmgenet_set_wol()
86 bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL); bcmgenet_set_wol()
132 u32 reg; bcmgenet_wol_power_down_cfg() local
140 reg = bcmgenet_umac_readl(priv, UMAC_CMD); bcmgenet_wol_power_down_cfg()
141 reg &= ~CMD_RX_EN; bcmgenet_wol_power_down_cfg()
142 bcmgenet_umac_writel(priv, reg, UMAC_CMD); bcmgenet_wol_power_down_cfg()
145 reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL); bcmgenet_wol_power_down_cfg()
146 reg |= MPD_EN; bcmgenet_wol_power_down_cfg()
147 bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL); bcmgenet_wol_power_down_cfg()
152 reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL); bcmgenet_wol_power_down_cfg()
153 reg &= ~MPD_EN; bcmgenet_wol_power_down_cfg()
154 bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL); bcmgenet_wol_power_down_cfg()
162 reg = bcmgenet_umac_readl(priv, UMAC_CMD); bcmgenet_wol_power_down_cfg()
164 reg |= CMD_CRC_FWD; bcmgenet_wol_power_down_cfg()
167 reg |= CMD_RX_EN; bcmgenet_wol_power_down_cfg()
168 bcmgenet_umac_writel(priv, reg, UMAC_CMD); bcmgenet_wol_power_down_cfg()
171 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); bcmgenet_wol_power_down_cfg()
172 reg &= ~EXT_ENERGY_DET_MASK; bcmgenet_wol_power_down_cfg()
173 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); bcmgenet_wol_power_down_cfg()
188 u32 reg; bcmgenet_wol_power_up_cfg() local
195 reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL); bcmgenet_wol_power_up_cfg()
196 reg &= ~MPD_EN; bcmgenet_wol_power_up_cfg()
197 bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL); bcmgenet_wol_power_up_cfg()
200 reg = bcmgenet_umac_readl(priv, UMAC_CMD); bcmgenet_wol_power_up_cfg()
201 reg &= ~CMD_CRC_FWD; bcmgenet_wol_power_up_cfg()
202 bcmgenet_umac_writel(priv, reg, UMAC_CMD); bcmgenet_wol_power_up_cfg()
/linux-4.1.27/drivers/isdn/hisax/
H A Damd7930_fn.h19 #define rByteAMD(cs, reg) cs->readisac(cs, reg)
20 #define wByteAMD(cs, reg, val) cs->writeisac(cs, reg, val)
21 #define rWordAMD(cs, reg) ReadWordAmd7930(cs, reg)
22 #define wWordAMD(cs, reg, val) WriteWordAmd7930(cs, reg, val)
/linux-4.1.27/arch/mips/pci/
H A Dops-sni.c24 static int set_config_address(unsigned int busno, unsigned int devfn, int reg) set_config_address() argument
26 if ((devfn > 255) || (reg > 255)) set_config_address()
35 (reg & 0xfc); set_config_address()
40 static int pcimt_read(struct pci_bus *bus, unsigned int devfn, int reg, pcimt_read() argument
45 if ((res = set_config_address(bus->number, devfn, reg))) pcimt_read()
50 *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); pcimt_read()
53 *val = inw(PCIMT_CONFIG_DATA + (reg & 2)); pcimt_read()
63 static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg, pcimt_write() argument
68 if ((res = set_config_address(bus->number, devfn, reg))) pcimt_write()
73 outb(val, PCIMT_CONFIG_DATA + (reg & 3)); pcimt_write()
76 outw(val, PCIMT_CONFIG_DATA + (reg & 2)); pcimt_write()
91 static int pcit_set_config_address(unsigned int busno, unsigned int devfn, int reg) pcit_set_config_address() argument
93 if ((devfn > 255) || (reg > 255) || (busno > 255)) pcit_set_config_address()
96 outl((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8); pcit_set_config_address()
100 static int pcit_read(struct pci_bus *bus, unsigned int devfn, int reg, pcit_read() argument
120 if ((res = pcit_set_config_address(bus->number, devfn, reg))) pcit_read()
125 *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); pcit_read()
128 *val = inw(PCIMT_CONFIG_DATA + (reg & 2)); pcit_read()
137 static int pcit_write(struct pci_bus *bus, unsigned int devfn, int reg, pcit_write() argument
142 if ((res = pcit_set_config_address(bus->number, devfn, reg))) pcit_write()
147 outb(val, PCIMT_CONFIG_DATA + (reg & 3)); pcit_write()
150 outw(val, PCIMT_CONFIG_DATA + (reg & 2)); pcit_write()
H A Dops-mace.c32 unsigned int reg) mkaddr()
36 (reg & 0xfc); mkaddr()
42 int reg, int size, u32 *val) mace_pci_read_config()
48 mace->pci.config_addr = mkaddr(bus, devfn, reg); mace_pci_read_config()
51 *val = mace->pci.config_data.b[(reg & 3) ^ 3]; mace_pci_read_config()
54 *val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1]; mace_pci_read_config()
67 if (bus->number == 0 && reg == 0x40 && size == 4 && mace_pci_read_config()
71 DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val); mace_pci_read_config()
78 int reg, int size, u32 val) mace_pci_write_config()
80 mace->pci.config_addr = mkaddr(bus, devfn, reg); mace_pci_write_config()
83 mace->pci.config_data.b[(reg & 3) ^ 3] = val; mace_pci_write_config()
86 mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val; mace_pci_write_config()
93 DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val); mace_pci_write_config()
31 mkaddr(struct pci_bus *bus, unsigned int devfn, unsigned int reg) mkaddr() argument
41 mace_pci_read_config(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 *val) mace_pci_read_config() argument
77 mace_pci_write_config(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 val) mace_pci_write_config() argument
/linux-4.1.27/drivers/net/ethernet/sfc/
H A Dio.h83 unsigned int reg) _efx_writeq()
85 __raw_writeq((__force u64)value, efx->membase + reg); _efx_writeq()
87 static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg) _efx_readq() argument
89 return (__force __le64)__raw_readq(efx->membase + reg); _efx_readq()
94 unsigned int reg) _efx_writed()
96 __raw_writel((__force u32)value, efx->membase + reg); _efx_writed()
98 static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg) _efx_readd() argument
100 return (__force __le32)__raw_readl(efx->membase + reg); _efx_readd()
105 unsigned int reg) efx_writeo()
110 "writing register %x with " EFX_OWORD_FMT "\n", reg, efx_writeo()
115 _efx_writeq(efx, value->u64[0], reg + 0); efx_writeo()
116 _efx_writeq(efx, value->u64[1], reg + 8); efx_writeo()
118 _efx_writed(efx, value->u32[0], reg + 0); efx_writeo()
119 _efx_writed(efx, value->u32[1], reg + 4); efx_writeo()
120 _efx_writed(efx, value->u32[2], reg + 8); efx_writeo()
121 _efx_writed(efx, value->u32[3], reg + 12); efx_writeo()
151 unsigned int reg) efx_writed()
155 reg, EFX_DWORD_VAL(*value)); efx_writed()
158 _efx_writed(efx, value->u32[0], reg); efx_writed()
163 unsigned int reg) efx_reado()
168 value->u32[0] = _efx_readd(efx, reg + 0); efx_reado()
169 value->u32[1] = _efx_readd(efx, reg + 4); efx_reado()
170 value->u32[2] = _efx_readd(efx, reg + 8); efx_reado()
171 value->u32[3] = _efx_readd(efx, reg + 12); efx_reado()
175 "read from register %x, got " EFX_OWORD_FMT "\n", reg, efx_reado()
202 unsigned int reg) efx_readd()
204 value->u32[0] = _efx_readd(efx, reg); efx_readd()
207 reg, EFX_DWORD_VAL(*value)); efx_readd()
213 unsigned int reg, unsigned int index) efx_writeo_table()
215 efx_writeo(efx, value, reg + index * sizeof(efx_oword_t)); efx_writeo_table()
220 unsigned int reg, unsigned int index) efx_reado_table()
222 efx_reado(efx, value, reg + index * sizeof(efx_oword_t)); efx_reado_table()
229 #define EFX_PAGED_REG(page, reg) \
230 ((page) * EFX_VI_PAGE_SIZE + (reg))
234 unsigned int reg, unsigned int page) _efx_writeo_page()
236 reg = EFX_PAGED_REG(page, reg); _efx_writeo_page()
239 "writing register %x with " EFX_OWORD_FMT "\n", reg, _efx_writeo_page()
243 _efx_writeq(efx, value->u64[0], reg + 0); _efx_writeo_page()
244 _efx_writeq(efx, value->u64[1], reg + 8); _efx_writeo_page()
246 _efx_writed(efx, value->u32[0], reg + 0); _efx_writeo_page()
247 _efx_writed(efx, value->u32[1], reg + 4); _efx_writeo_page()
248 _efx_writed(efx, value->u32[2], reg + 8); _efx_writeo_page()
249 _efx_writed(efx, value->u32[3], reg + 12); _efx_writeo_page()
252 #define efx_writeo_page(efx, value, reg, page) \
254 reg + \
255 BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
263 unsigned int reg, unsigned int page) _efx_writed_page()
265 efx_writed(efx, value, EFX_PAGED_REG(page, reg)); _efx_writed_page()
267 #define efx_writed_page(efx, value, reg, page) \
269 reg + \
270 BUILD_BUG_ON_ZERO((reg) != 0x400 && \
271 (reg) != 0x420 && \
272 (reg) != 0x830 && \
273 (reg) != 0x83c && \
274 (reg) != 0xa18 && \
275 (reg) != 0xa1c), \
284 unsigned int reg, _efx_writed_page_locked()
291 efx_writed(efx, value, EFX_PAGED_REG(page, reg)); _efx_writed_page_locked()
294 efx_writed(efx, value, EFX_PAGED_REG(page, reg)); _efx_writed_page_locked()
297 #define efx_writed_page_locked(efx, value, reg, page) \
299 reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
82 _efx_writeq(struct efx_nic *efx, __le64 value, unsigned int reg) _efx_writeq() argument
93 _efx_writed(struct efx_nic *efx, __le32 value, unsigned int reg) _efx_writed() argument
104 efx_writeo(struct efx_nic *efx, const efx_oword_t *value, unsigned int reg) efx_writeo() argument
150 efx_writed(struct efx_nic *efx, const efx_dword_t *value, unsigned int reg) efx_writed() argument
162 efx_reado(struct efx_nic *efx, efx_oword_t *value, unsigned int reg) efx_reado() argument
201 efx_readd(struct efx_nic *efx, efx_dword_t *value, unsigned int reg) efx_readd() argument
212 efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value, unsigned int reg, unsigned int index) efx_writeo_table() argument
219 efx_reado_table(struct efx_nic *efx, efx_oword_t *value, unsigned int reg, unsigned int index) efx_reado_table() argument
233 _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value, unsigned int reg, unsigned int page) _efx_writeo_page() argument
262 _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value, unsigned int reg, unsigned int page) _efx_writed_page() argument
282 _efx_writed_page_locked(struct efx_nic *efx, const efx_dword_t *value, unsigned int reg, unsigned int page) _efx_writed_page_locked() argument
/linux-4.1.27/arch/xtensa/include/asm/
H A Dcurrent.h31 #define GET_CURRENT(reg,sp) \
32 GET_THREAD_INFO(reg,sp); \
33 l32i reg, reg, TI_TASK \
/linux-4.1.27/arch/mips/include/asm/mach-loongson/cs5536/
H A Dcs5536_vsm.h13 typedef void (*cs5536_pci_vsm_write)(int reg, u32 value);
14 typedef u32 (*cs5536_pci_vsm_read)(int reg);
17 extern void pci_##name##_write_reg(int reg, u32 value); \
18 extern u32 pci_##name##_read_reg(int reg);
/linux-4.1.27/drivers/phy/
H A Dphy-qcom-ipq806x-sata.c64 u32 reg; qcom_ipq806x_sata_phy_init() local
67 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3); qcom_ipq806x_sata_phy_init()
68 reg = reg | SATA_PHY_SSC_EN; qcom_ipq806x_sata_phy_init()
69 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3); qcom_ipq806x_sata_phy_init()
71 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) & qcom_ipq806x_sata_phy_init()
75 reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf); qcom_ipq806x_sata_phy_init()
76 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0); qcom_ipq806x_sata_phy_init()
78 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) & qcom_ipq806x_sata_phy_init()
82 reg |= SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(0x55) | qcom_ipq806x_sata_phy_init()
85 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1); qcom_ipq806x_sata_phy_init()
87 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) & qcom_ipq806x_sata_phy_init()
89 reg |= SATA_PHY_P0_PARAM2_RX_EQ(0x3); qcom_ipq806x_sata_phy_init()
90 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2); qcom_ipq806x_sata_phy_init()
93 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); qcom_ipq806x_sata_phy_init()
94 reg = reg | SATA_PHY_RESET; qcom_ipq806x_sata_phy_init()
95 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); qcom_ipq806x_sata_phy_init()
98 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); qcom_ipq806x_sata_phy_init()
99 reg = reg | SATA_PHY_REF_SSP_EN | SATA_PHY_RESET; qcom_ipq806x_sata_phy_init()
100 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); qcom_ipq806x_sata_phy_init()
109 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); qcom_ipq806x_sata_phy_init()
110 reg = reg & ~SATA_PHY_RESET; qcom_ipq806x_sata_phy_init()
111 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); qcom_ipq806x_sata_phy_init()
119 u32 reg; qcom_ipq806x_sata_phy_exit() local
122 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); qcom_ipq806x_sata_phy_exit()
123 reg = reg | SATA_PHY_RESET; qcom_ipq806x_sata_phy_exit()
124 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); qcom_ipq806x_sata_phy_exit()
/linux-4.1.27/arch/blackfin/kernel/
H A Dpseudodbg.c23 static const char *get_allreg_name(int grp, int reg) get_allreg_name() argument
25 return greg_names[(grp << 3) | reg]; get_allreg_name()
40 static bool fix_up_reg(struct pt_regs *fp, long *value, int grp, int reg) fix_up_reg() argument
47 (grp == 4 && (reg == 4 || reg == 5)) || fix_up_reg()
51 if (grp == 0 || (grp == 1 && reg < 6)) fix_up_reg()
52 val -= (reg + 8 * grp); fix_up_reg()
53 else if (grp == 1 && reg == 6) fix_up_reg()
55 else if (grp == 1 && reg == 7) fix_up_reg()
59 val -= reg; fix_up_reg()
60 } else if (grp == 3 && reg >= 4) { fix_up_reg()
62 val -= (reg - 4); fix_up_reg()
63 } else if (grp == 3 && reg < 4) { fix_up_reg()
65 val -= reg; fix_up_reg()
66 } else if (grp == 4 && reg < 4) { fix_up_reg()
68 val -= reg; fix_up_reg()
69 } else if (grp == 4 && reg == 6) fix_up_reg()
71 else if (grp == 4 && reg == 7) fix_up_reg()
73 else if (grp == 6 && reg < 6) { fix_up_reg()
75 val -= reg; fix_up_reg()
76 } else if (grp == 6 && reg == 6) { fix_up_reg()
79 } else if (grp == 6 && reg == 7) { fix_up_reg()
160 int grp, fn, reg; execute_pseudodbg() local
169 reg = ((opcode >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask); execute_pseudodbg()
171 if (fn == 3 && (reg == 0 || reg == 1)) { execute_pseudodbg()
172 if (!fix_up_reg(fp, &value, 4, 2 * reg)) execute_pseudodbg()
174 if (!fix_up_reg(fp, &value1, 4, 2 * reg + 1)) execute_pseudodbg()
177 pr_notice("DBG A%i = %02lx%08lx\n", reg, value & 0xFF, value1); execute_pseudodbg()
182 if (!fix_up_reg(fp, &value, grp, reg)) execute_pseudodbg()
185 pr_notice("DBG %s = %08lx\n", get_allreg_name(grp, reg), value); execute_pseudodbg()
/linux-4.1.27/arch/m32r/include/asm/
H A Dassembler.h49 #define LDIMM(reg,x) LDIMM reg x
50 .macro LDIMM reg x
51 seth \reg, #high(\x)
52 or3 \reg, \reg, #low(\x) variable
56 #define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg
57 .macro ENABLE_INTERRUPTS reg
62 #define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg
63 .macro DISABLE_INTERRUPTS reg
68 #define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg
69 .macro ENABLE_INTERRUPTS reg
70 mvfc \reg, psw
71 or3 \reg, \reg, #0x0040
72 mvtc \reg, psw
75 #define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg
76 .macro DISABLE_INTERRUPTS reg
77 mvfc \reg, psw
78 and3 \reg, \reg, #0xffbf
79 mvtc \reg, psw
193 #define GET_CURRENT(reg) get_current reg
194 .macro get_current reg
195 ldi \reg, #-8192
196 and \reg, sp
/linux-4.1.27/drivers/scsi/aic94xx/
H A Daic94xx_reg.c128 u32 reg) \
131 u32 map_offs = (reg - io_handle->ww##_base) + asd_mem_offs_##ww();\
137 u32 reg, type val) \
140 u32 map_offs = (reg - io_handle->ww##_base) + asd_mem_offs_##ww();\
186 * @reg: register desired to be within range of the new window
188 static void asd_move_swb(struct asd_ha_struct *asd_ha, u32 reg) asd_move_swb() argument
190 u32 base = reg & ~(MBAR0_SWB_SIZE-1); asd_move_swb()
195 static void __asd_write_reg_byte(struct asd_ha_struct *asd_ha, u32 reg, u8 val) __asd_write_reg_byte() argument
198 BUG_ON(reg >= 0xC0000000 || reg < ALL_BASE_ADDR); __asd_write_reg_byte()
199 if (io_handle->swa_base <= reg __asd_write_reg_byte()
200 && reg < io_handle->swa_base + MBAR0_SWA_SIZE) __asd_write_reg_byte()
201 asd_write_swa_byte (asd_ha, reg,val); __asd_write_reg_byte()
202 else if (io_handle->swb_base <= reg __asd_write_reg_byte()
203 && reg < io_handle->swb_base + MBAR0_SWB_SIZE) __asd_write_reg_byte()
204 asd_write_swb_byte (asd_ha, reg, val); __asd_write_reg_byte()
205 else if (io_handle->swc_base <= reg __asd_write_reg_byte()
206 && reg < io_handle->swc_base + MBAR0_SWC_SIZE) __asd_write_reg_byte()
207 asd_write_swc_byte (asd_ha, reg, val); __asd_write_reg_byte()
210 asd_move_swb(asd_ha, reg); __asd_write_reg_byte()
211 asd_write_swb_byte (asd_ha, reg, val); __asd_write_reg_byte()
216 void asd_write_reg_##ord (struct asd_ha_struct *asd_ha, u32 reg, type val)\
220 BUG_ON(reg >= 0xC0000000 || reg < ALL_BASE_ADDR); \
222 if (io_handle->swa_base <= reg \
223 && reg < io_handle->swa_base + MBAR0_SWA_SIZE) \
224 asd_write_swa_##ord (asd_ha, reg,val); \
225 else if (io_handle->swb_base <= reg \
226 && reg < io_handle->swb_base + MBAR0_SWB_SIZE) \
227 asd_write_swb_##ord (asd_ha, reg, val); \
228 else if (io_handle->swc_base <= reg \
229 && reg < io_handle->swc_base + MBAR0_SWC_SIZE) \
230 asd_write_swc_##ord (asd_ha, reg, val); \
233 asd_move_swb(asd_ha, reg); \
234 asd_write_swb_##ord (asd_ha, reg, val); \
243 static u8 __asd_read_reg_byte(struct asd_ha_struct *asd_ha, u32 reg) __asd_read_reg_byte() argument
247 BUG_ON(reg >= 0xC0000000 || reg < ALL_BASE_ADDR); __asd_read_reg_byte()
248 if (io_handle->swa_base <= reg __asd_read_reg_byte()
249 && reg < io_handle->swa_base + MBAR0_SWA_SIZE) __asd_read_reg_byte()
250 val = asd_read_swa_byte (asd_ha, reg); __asd_read_reg_byte()
251 else if (io_handle->swb_base <= reg __asd_read_reg_byte()
252 && reg < io_handle->swb_base + MBAR0_SWB_SIZE) __asd_read_reg_byte()
253 val = asd_read_swb_byte (asd_ha, reg); __asd_read_reg_byte()
254 else if (io_handle->swc_base <= reg __asd_read_reg_byte()
255 && reg < io_handle->swc_base + MBAR0_SWC_SIZE) __asd_read_reg_byte()
256 val = asd_read_swc_byte (asd_ha, reg); __asd_read_reg_byte()
259 asd_move_swb(asd_ha, reg); __asd_read_reg_byte()
260 val = asd_read_swb_byte (asd_ha, reg); __asd_read_reg_byte()
266 type asd_read_reg_##ord (struct asd_ha_struct *asd_ha, u32 reg) \
271 BUG_ON(reg >= 0xC0000000 || reg < ALL_BASE_ADDR); \
273 if (io_handle->swa_base <= reg \
274 && reg < io_handle->swa_base + MBAR0_SWA_SIZE) \
275 val = asd_read_swa_##ord (asd_ha, reg); \
276 else if (io_handle->swb_base <= reg \
277 && reg < io_handle->swb_base + MBAR0_SWB_SIZE) \
278 val = asd_read_swb_##ord (asd_ha, reg); \
279 else if (io_handle->swc_base <= reg \
280 && reg < io_handle->swc_base + MBAR0_SWC_SIZE) \
281 val = asd_read_swc_##ord (asd_ha, reg); \
284 asd_move_swb(asd_ha, reg); \
285 val = asd_read_swb_##ord (asd_ha, reg); \
/linux-4.1.27/drivers/misc/mei/
H A Dmei-trace.h30 TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val),
31 TP_ARGS(dev, reg, offs, val),
34 __field(const char *, reg)
40 __entry->reg = reg;
45 __get_str(dev), __entry->reg, __entry->offs, __entry->val)
49 TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val),
50 TP_ARGS(dev, reg, offs, val),
53 __field(const char *, reg)
59 __entry->reg = reg;
64 __get_str(dev), __entry->reg, __entry->offs, __entry->val)
/linux-4.1.27/arch/mips/include/asm/mach-lantiq/
H A Dlantiq.h15 /* generic reg access functions */
16 #define ltq_r32(reg) __raw_readl(reg)
17 #define ltq_w32(val, reg) __raw_writel(val, reg)
18 #define ltq_w32_mask(clear, set, reg) \
19 ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg)
20 #define ltq_r8(reg) __raw_readb(reg)
21 #define ltq_w8(val, reg) __raw_writeb(val, reg)
/linux-4.1.27/arch/m68k/math-emu/
H A Dmulti_arith.h22 static inline void fp_denormalize(struct fp_ext *reg, unsigned int cnt) fp_denormalize() argument
24 reg->exp += cnt; fp_denormalize()
28 reg->lowmant = reg->mant.m32[1] << (8 - cnt); fp_denormalize()
29 reg->mant.m32[1] = (reg->mant.m32[1] >> cnt) | fp_denormalize()
30 (reg->mant.m32[0] << (32 - cnt)); fp_denormalize()
31 reg->mant.m32[0] = reg->mant.m32[0] >> cnt; fp_denormalize()
34 reg->lowmant = reg->mant.m32[1] >> (cnt - 8); fp_denormalize()
35 if (reg->mant.m32[1] << (40 - cnt)) fp_denormalize()
36 reg->lowmant |= 1; fp_denormalize()
37 reg->mant.m32[1] = (reg->mant.m32[1] >> cnt) | fp_denormalize()
38 (reg->mant.m32[0] << (32 - cnt)); fp_denormalize()
39 reg->mant.m32[0] = reg->mant.m32[0] >> cnt; fp_denormalize()
42 asm volatile ("bfextu %1{%2,#8},%0" : "=d" (reg->lowmant) fp_denormalize()
43 : "m" (reg->mant.m32[0]), "d" (64 - cnt)); fp_denormalize()
44 if (reg->mant.m32[1] << (40 - cnt)) fp_denormalize()
45 reg->lowmant |= 1; fp_denormalize()
46 reg->mant.m32[1] = reg->mant.m32[0] >> (cnt - 32); fp_denormalize()
47 reg->mant.m32[0] = 0; fp_denormalize()
50 reg->lowmant = reg->mant.m32[0] >> (cnt - 40); fp_denormalize()
51 if ((reg->mant.m32[0] << (72 - cnt)) || reg->mant.m32[1]) fp_denormalize()
52 reg->lowmant |= 1; fp_denormalize()
53 reg->mant.m32[1] = reg->mant.m32[0] >> (cnt - 32); fp_denormalize()
54 reg->mant.m32[0] = 0; fp_denormalize()
57 reg->lowmant = reg->mant.m32[0] || reg->mant.m32[1]; fp_denormalize()
58 reg->mant.m32[0] = 0; fp_denormalize()
59 reg->mant.m32[1] = 0; fp_denormalize()
64 static inline int fp_overnormalize(struct fp_ext *reg) fp_overnormalize() argument
68 if (reg->mant.m32[0]) { fp_overnormalize()
69 asm ("bfffo %1{#0,#32},%0" : "=d" (shift) : "dm" (reg->mant.m32[0])); fp_overnormalize()
70 reg->mant.m32[0] = (reg->mant.m32[0] << shift) | (reg->mant.m32[1] >> (32 - shift)); fp_overnormalize()
71 reg->mant.m32[1] = (reg->mant.m32[1] << shift); fp_overnormalize()
73 asm ("bfffo %1{#0,#32},%0" : "=d" (shift) : "dm" (reg->mant.m32[1])); fp_overnormalize()
74 reg->mant.m32[0] = (reg->mant.m32[1] << shift); fp_overnormalize()
75 reg->mant.m32[1] = 0; fp_overnormalize()
98 static inline int fp_addcarry(struct fp_ext *reg) fp_addcarry() argument
100 if (++reg->exp == 0x7fff) { fp_addcarry()
101 if (reg->mant.m64) fp_addcarry()
103 reg->mant.m64 = 0; fp_addcarry()
107 reg->lowmant = (reg->mant.m32[1] << 7) | (reg->lowmant ? 1 : 0); fp_addcarry()
108 reg->mant.m32[1] = (reg->mant.m32[1] >> 1) | fp_addcarry()
109 (reg->mant.m32[0] << 31); fp_addcarry()
110 reg->mant.m32[0] = (reg->mant.m32[0] >> 1) | 0x80000000; fp_addcarry()
/linux-4.1.27/arch/mips/oprofile/
H A Dop_model_loongson2.c41 } reg; variable in typeref:struct:loongson2_register_config
56 reg.reset_counter1 = 0; loongson2_reg_setup()
57 reg.reset_counter2 = 0; loongson2_reg_setup()
65 reg.reset_counter1 = 0x80000000ULL - cfg[0].count; loongson2_reg_setup()
70 reg.reset_counter2 = 0x80000000ULL - cfg[1].count; loongson2_reg_setup()
81 reg.ctrl = ctrl; loongson2_reg_setup()
83 reg.cnt1_enabled = cfg[0].enabled; loongson2_reg_setup()
84 reg.cnt2_enabled = cfg[1].enabled; loongson2_reg_setup()
89 write_c0_perfcnt((reg.reset_counter2 << 32) | reg.reset_counter1); loongson2_cpu_setup()
95 if (reg.cnt1_enabled || reg.cnt2_enabled) loongson2_cpu_start()
96 write_c0_perfctrl(reg.ctrl); loongson2_cpu_start()
103 memset(&reg, 0, sizeof(reg)); loongson2_cpu_stop()
116 enabled = reg.cnt1_enabled | reg.cnt2_enabled; loongson2_perfcount_handler()
125 if (reg.cnt1_enabled) loongson2_perfcount_handler()
127 counter1 = reg.reset_counter1; loongson2_perfcount_handler()
130 if (reg.cnt2_enabled) loongson2_perfcount_handler()
132 counter2 = reg.reset_counter2; loongson2_perfcount_handler()
H A Dop_model_loongson3.c51 } reg; variable in typeref:struct:loongson3_register_config
67 reg.reset_counter1 = 0; loongson3_reg_setup()
68 reg.reset_counter2 = 0; loongson3_reg_setup()
78 reg.reset_counter1 = 0x8000000000000000ULL - ctr[0].count; loongson3_reg_setup()
88 reg.reset_counter2 = 0x8000000000000000ULL - ctr[1].count; loongson3_reg_setup()
96 reg.control1 = control1; loongson3_reg_setup()
97 reg.control2 = control2; loongson3_reg_setup()
98 reg.ctr1_enable = ctr[0].enabled; loongson3_reg_setup()
99 reg.ctr2_enable = ctr[1].enabled; loongson3_reg_setup()
107 perfcount1 = reg.reset_counter1; loongson3_cpu_setup()
108 perfcount2 = reg.reset_counter2; loongson3_cpu_setup()
116 reg.control1 |= (LOONGSON3_PERFCTRL_W|LOONGSON3_PERFCTRL_M); loongson3_cpu_start()
117 reg.control2 |= (LOONGSON3_PERFCTRL_W|LOONGSON3_PERFCTRL_M); loongson3_cpu_start()
119 if (reg.ctr1_enable) loongson3_cpu_start()
120 write_c0_perflo1(reg.control1); loongson3_cpu_start()
121 if (reg.ctr2_enable) loongson3_cpu_start()
122 write_c0_perflo2(reg.control2); loongson3_cpu_start()
130 memset(&reg, 0, sizeof(reg)); loongson3_cpu_stop()
150 if (reg.ctr1_enable) loongson3_perfcount_handler()
152 counter1 = reg.reset_counter1; loongson3_perfcount_handler()
155 if (reg.ctr2_enable) loongson3_perfcount_handler()
157 counter2 = reg.reset_counter2; loongson3_perfcount_handler()
177 write_c0_perflo1(reg.control1); loongson3_cpu_callback()
178 write_c0_perflo2(reg.control2); loongson3_cpu_callback()
/linux-4.1.27/drivers/base/regmap/
H A Dtrace.h17 TP_PROTO(struct regmap *map, unsigned int reg,
20 TP_ARGS(map, reg, val),
24 __field( unsigned int, reg )
30 __entry->reg = reg;
34 TP_printk("%s reg=%x val=%x", __get_str(name),
35 (unsigned int)__entry->reg,
41 TP_PROTO(struct regmap *map, unsigned int reg,
44 TP_ARGS(map, reg, val)
50 TP_PROTO(struct regmap *map, unsigned int reg,
53 TP_ARGS(map, reg, val)
59 TP_PROTO(struct regmap *map, unsigned int reg,
62 TP_ARGS(map, reg, val)
68 TP_PROTO(struct regmap *map, unsigned int reg, int count),
70 TP_ARGS(map, reg, count),
74 __field( unsigned int, reg )
80 __entry->reg = reg;
84 TP_printk("%s reg=%x count=%d", __get_str(name),
85 (unsigned int)__entry->reg,
91 TP_PROTO(struct regmap *map, unsigned int reg, int count),
93 TP_ARGS(map, reg, count)
98 TP_PROTO(struct regmap *map, unsigned int reg, int count),
100 TP_ARGS(map, reg, count)
105 TP_PROTO(struct regmap *map, unsigned int reg, int count),
107 TP_ARGS(map, reg, count)
112 TP_PROTO(struct regmap *map, unsigned int reg, int count),
114 TP_ARGS(map, reg, count)
196 TP_PROTO(struct regmap *map, unsigned int reg, int count),
198 TP_ARGS(map, reg, count)
/linux-4.1.27/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h123 * @reg: FAU atomic register to access. 0 <= reg < 2048.
129 static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) __cvmx_fau_store_address() argument
133 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); __cvmx_fau_store_address()
143 * @reg: FAU atomic register to access. 0 <= reg < 2048.
152 static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, __cvmx_fau_atomic_address() argument
158 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); __cvmx_fau_atomic_address()
164 * @reg: FAU atomic register to access. 0 <= reg < 2048.
170 static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, cvmx_fau_fetch_and_add64() argument
173 return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); cvmx_fau_fetch_and_add64()
179 * @reg: FAU atomic register to access. 0 <= reg < 2048.
185 static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, cvmx_fau_fetch_and_add32() argument
188 reg ^= SWIZZLE_32; cvmx_fau_fetch_and_add32()
189 return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); cvmx_fau_fetch_and_add32()
195 * @reg: FAU atomic register to access. 0 <= reg < 2048.
200 static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, cvmx_fau_fetch_and_add16() argument
203 reg ^= SWIZZLE_16; cvmx_fau_fetch_and_add16()
204 return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value)); cvmx_fau_fetch_and_add16()
210 * @reg: FAU atomic register to access. 0 <= reg < 2048.
214 static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) cvmx_fau_fetch_and_add8() argument
216 reg ^= SWIZZLE_8; cvmx_fau_fetch_and_add8()
217 return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value)); cvmx_fau_fetch_and_add8()
224 * @reg: FAU atomic register to access. 0 <= reg < 2048.
233 cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) cvmx_fau_tagwait_fetch_and_add64() argument
240 cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value)); cvmx_fau_tagwait_fetch_and_add64()
248 * @reg: FAU atomic register to access. 0 <= reg < 2048.
257 cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) cvmx_fau_tagwait_fetch_and_add32() argument
263 reg ^= SWIZZLE_32; cvmx_fau_tagwait_fetch_and_add32()
265 cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value)); cvmx_fau_tagwait_fetch_and_add32()
273 * @reg: FAU atomic register to access. 0 <= reg < 2048.
281 cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) cvmx_fau_tagwait_fetch_and_add16() argument
287 reg ^= SWIZZLE_16; cvmx_fau_tagwait_fetch_and_add16()
289 cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value)); cvmx_fau_tagwait_fetch_and_add16()
297 * @reg: FAU atomic register to access. 0 <= reg < 2048.
304 cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) cvmx_fau_tagwait_fetch_and_add8() argument
310 reg ^= SWIZZLE_8; cvmx_fau_tagwait_fetch_and_add8()
311 result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value)); cvmx_fau_tagwait_fetch_and_add8()
331 * @reg: FAU atomic register to access. 0 <= reg < 2048.
340 uint64_t reg) __cvmx_fau_iobdma_data()
348 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); __cvmx_fau_iobdma_data()
357 * @reg: FAU atomic register to access. 0 <= reg < 2048.
364 cvmx_fau_reg_64_t reg, cvmx_fau_async_fetch_and_add64()
368 (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg)); cvmx_fau_async_fetch_and_add64()
377 * @reg: FAU atomic register to access. 0 <= reg < 2048.
384 cvmx_fau_reg_32_t reg, cvmx_fau_async_fetch_and_add32()
388 (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg)); cvmx_fau_async_fetch_and_add32()
397 * @reg: FAU atomic register to access. 0 <= reg < 2048.
403 cvmx_fau_reg_16_t reg, cvmx_fau_async_fetch_and_add16()
407 (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg)); cvmx_fau_async_fetch_and_add16()
416 * @reg: FAU atomic register to access. 0 <= reg < 2048.
421 cvmx_fau_reg_8_t reg, cvmx_fau_async_fetch_and_add8()
425 (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg)); cvmx_fau_async_fetch_and_add8()
437 * @reg: FAU atomic register to access. 0 <= reg < 2048.
444 cvmx_fau_reg_64_t reg, cvmx_fau_async_tagwait_fetch_and_add64()
448 (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg)); cvmx_fau_async_tagwait_fetch_and_add64()
460 * @reg: FAU atomic register to access. 0 <= reg < 2048.
467 cvmx_fau_reg_32_t reg, cvmx_fau_async_tagwait_fetch_and_add32()
471 (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg)); cvmx_fau_async_tagwait_fetch_and_add32()
483 * @reg: FAU atomic register to access. 0 <= reg < 2048.
490 cvmx_fau_reg_16_t reg, cvmx_fau_async_tagwait_fetch_and_add16()
494 (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg)); cvmx_fau_async_tagwait_fetch_and_add16()
506 * @reg: FAU atomic register to access. 0 <= reg < 2048.
512 cvmx_fau_reg_8_t reg, cvmx_fau_async_tagwait_fetch_and_add8()
516 (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg)); cvmx_fau_async_tagwait_fetch_and_add8()
522 * @reg: FAU atomic register to access. 0 <= reg < 2048.
526 static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) cvmx_fau_atomic_add64() argument
528 cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value); cvmx_fau_atomic_add64()
534 * @reg: FAU atomic register to access. 0 <= reg < 2048.
538 static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) cvmx_fau_atomic_add32() argument
540 reg ^= SWIZZLE_32; cvmx_fau_atomic_add32()
541 cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value); cvmx_fau_atomic_add32()
547 * @reg: FAU atomic register to access. 0 <= reg < 2048.
551 static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value) cvmx_fau_atomic_add16() argument
553 reg ^= SWIZZLE_16; cvmx_fau_atomic_add16()
554 cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value); cvmx_fau_atomic_add16()
560 * @reg: FAU atomic register to access. 0 <= reg < 2048.
563 static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value) cvmx_fau_atomic_add8() argument
565 reg ^= SWIZZLE_8; cvmx_fau_atomic_add8()
566 cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value); cvmx_fau_atomic_add8()
572 * @reg: FAU atomic register to access. 0 <= reg < 2048.
576 static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) cvmx_fau_atomic_write64() argument
578 cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value); cvmx_fau_atomic_write64()
584 * @reg: FAU atomic register to access. 0 <= reg < 2048.
588 static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) cvmx_fau_atomic_write32() argument
590 reg ^= SWIZZLE_32; cvmx_fau_atomic_write32()
591 cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value); cvmx_fau_atomic_write32()
597 * @reg: FAU atomic register to access. 0 <= reg < 2048.
601 static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value) cvmx_fau_atomic_write16() argument
603 reg ^= SWIZZLE_16; cvmx_fau_atomic_write16()
604 cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value); cvmx_fau_atomic_write16()
610 * @reg: FAU atomic register to access. 0 <= reg < 2048.
613 static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value) cvmx_fau_atomic_write8() argument
615 reg ^= SWIZZLE_8; cvmx_fau_atomic_write8()
616 cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value); cvmx_fau_atomic_write8()
337 __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, uint64_t tagwait, cvmx_fau_op_size_t size, uint64_t reg) __cvmx_fau_iobdma_data() argument
363 cvmx_fau_async_fetch_and_add64(uint64_t scraddr, cvmx_fau_reg_64_t reg, int64_t value) cvmx_fau_async_fetch_and_add64() argument
383 cvmx_fau_async_fetch_and_add32(uint64_t scraddr, cvmx_fau_reg_32_t reg, int32_t value) cvmx_fau_async_fetch_and_add32() argument
402 cvmx_fau_async_fetch_and_add16(uint64_t scraddr, cvmx_fau_reg_16_t reg, int16_t value) cvmx_fau_async_fetch_and_add16() argument
420 cvmx_fau_async_fetch_and_add8(uint64_t scraddr, cvmx_fau_reg_8_t reg, int8_t value) cvmx_fau_async_fetch_and_add8() argument
443 cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, cvmx_fau_reg_64_t reg, int64_t value) cvmx_fau_async_tagwait_fetch_and_add64() argument
466 cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, cvmx_fau_reg_32_t reg, int32_t value) cvmx_fau_async_tagwait_fetch_and_add32() argument
489 cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr, cvmx_fau_reg_16_t reg, int16_t value) cvmx_fau_async_tagwait_fetch_and_add16() argument
511 cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr, cvmx_fau_reg_8_t reg, int8_t value) cvmx_fau_async_tagwait_fetch_and_add8() argument
/linux-4.1.27/arch/cris/include/uapi/arch-v10/arch/
H A Dsv_addr_ag.h4 *! IO_MASK(reg,field)
5 *! IO_STATE(reg,field,state)
6 *! IO_EXTRACT(reg,field,val)
7 *! IO_STATE_VALUE(reg,field,state)
8 *! IO_BITNR(reg,field)
9 *! IO_WIDTH(reg,field)
10 *! IO_FIELD(reg,field,val)
11 *! IO_RD(reg)
28 #define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_)
34 #define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state)
40 #define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val)
46 #define IO_STATE_VALUE(reg, field, state) \
47 IO_STATE_VALUE_ (reg##_, field##_, _##state)
52 #define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val)
57 #define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_)
61 #define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_)
67 #define IO_RD(reg) (*(volatile u32*)(reg))
68 #define IO_RD_B(reg) (*(volatile u8*)(reg))
69 #define IO_RD_W(reg) (*(volatile u16*)(reg))
70 #define IO_RD_D(reg) (*(volatile u32*)(reg))
/linux-4.1.27/drivers/clk/berlin/
H A Dberlin2-avpll.c45 /* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */
127 u32 reg; berlin2_avpll_vco_is_enabled() local
129 reg = readl_relaxed(vco->base + VCO_CTRL0); berlin2_avpll_vco_is_enabled()
131 reg >>= 4; berlin2_avpll_vco_is_enabled()
133 return !!(reg & VCO_POWERUP); berlin2_avpll_vco_is_enabled()
139 u32 reg; berlin2_avpll_vco_enable() local
141 reg = readl_relaxed(vco->base + VCO_CTRL0); berlin2_avpll_vco_enable()
143 reg |= VCO_POWERUP << 4; berlin2_avpll_vco_enable()
145 reg |= VCO_POWERUP; berlin2_avpll_vco_enable()
146 writel_relaxed(reg, vco->base + VCO_CTRL0); berlin2_avpll_vco_enable()
154 u32 reg; berlin2_avpll_vco_disable() local
156 reg = readl_relaxed(vco->base + VCO_CTRL0); berlin2_avpll_vco_disable()
158 reg &= ~(VCO_POWERUP << 4); berlin2_avpll_vco_disable()
160 reg &= ~VCO_POWERUP; berlin2_avpll_vco_disable()
161 writel_relaxed(reg, vco->base + VCO_CTRL0); berlin2_avpll_vco_disable()
170 u32 reg, refdiv, fbdiv; berlin2_avpll_vco_recalc_rate() local
174 reg = readl_relaxed(vco->base + VCO_CTRL1); berlin2_avpll_vco_recalc_rate()
175 refdiv = (reg & VCO_REFDIV_MASK) >> VCO_REFDIV_SHIFT; berlin2_avpll_vco_recalc_rate()
177 fbdiv = (reg & VCO_FBDIV_MASK) >> VCO_FBDIV_SHIFT; berlin2_avpll_vco_recalc_rate()
226 u32 reg; berlin2_avpll_channel_is_enabled() local
231 reg = readl_relaxed(ch->base + VCO_CTRL10); berlin2_avpll_channel_is_enabled()
232 reg &= VCO_POWERUP_CH1 << ch->index; berlin2_avpll_channel_is_enabled()
234 return !!reg; berlin2_avpll_channel_is_enabled()
240 u32 reg; berlin2_avpll_channel_enable() local
242 reg = readl_relaxed(ch->base + VCO_CTRL10); berlin2_avpll_channel_enable()
243 reg |= VCO_POWERUP_CH1 << ch->index; berlin2_avpll_channel_enable()
244 writel_relaxed(reg, ch->base + VCO_CTRL10); berlin2_avpll_channel_enable()
252 u32 reg; berlin2_avpll_channel_disable() local
254 reg = readl_relaxed(ch->base + VCO_CTRL10); berlin2_avpll_channel_disable()
255 reg &= ~(VCO_POWERUP_CH1 << ch->index); berlin2_avpll_channel_disable()
256 writel_relaxed(reg, ch->base + VCO_CTRL10); berlin2_avpll_channel_disable()
266 u32 reg, div_av2, div_av3, divider = 1; berlin2_avpll_channel_recalc_rate() local
269 reg = readl_relaxed(ch->base + VCO_CTRL30); berlin2_avpll_channel_recalc_rate()
270 if ((reg & (VCO_DPLL_CH1_ENABLE << ch->index)) == 0) berlin2_avpll_channel_recalc_rate()
278 reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index)); berlin2_avpll_channel_recalc_rate()
279 /* BG2/BG2CDs SYNC1 reg on AVPLL_B channel 1 is shifted by 4 */ berlin2_avpll_channel_recalc_rate()
281 reg >>= 4; berlin2_avpll_channel_recalc_rate()
282 divider = reg & VCO_SYNC1_MASK; berlin2_avpll_channel_recalc_rate()
284 reg = readl_relaxed(ch->base + VCO_SYNC2n(ch->index)); berlin2_avpll_channel_recalc_rate()
285 freq *= reg & VCO_SYNC2_MASK; berlin2_avpll_channel_recalc_rate()
295 reg = readl_relaxed(ch->base + VCO_CTRL11) >> 7; berlin2_avpll_channel_recalc_rate()
296 reg = (reg >> (ch->index * 3)); berlin2_avpll_channel_recalc_rate()
297 if (reg & BIT(2)) berlin2_avpll_channel_recalc_rate()
298 divider *= div_hdmi[reg & 0x3]; berlin2_avpll_channel_recalc_rate()
305 reg = readl_relaxed(ch->base + VCO_CTRL11); berlin2_avpll_channel_recalc_rate()
306 reg >>= 28; berlin2_avpll_channel_recalc_rate()
308 reg = readl_relaxed(ch->base + VCO_CTRL12); berlin2_avpll_channel_recalc_rate()
309 reg >>= (ch->index-1) * 3; berlin2_avpll_channel_recalc_rate()
311 if (reg & BIT(2)) berlin2_avpll_channel_recalc_rate()
312 divider *= div_av1[reg & 0x3]; berlin2_avpll_channel_recalc_rate()
319 reg = readl_relaxed(ch->base + VCO_CTRL12); berlin2_avpll_channel_recalc_rate()
320 reg >>= 18 + (ch->index * 7); berlin2_avpll_channel_recalc_rate()
322 reg = readl_relaxed(ch->base + VCO_CTRL13); berlin2_avpll_channel_recalc_rate()
323 reg >>= (ch->index - 2) * 7; berlin2_avpll_channel_recalc_rate()
325 reg = readl_relaxed(ch->base + VCO_CTRL14); berlin2_avpll_channel_recalc_rate()
327 div_av2 = reg & 0x7f; berlin2_avpll_channel_recalc_rate()
337 reg = readl_relaxed(ch->base + VCO_CTRL14); berlin2_avpll_channel_recalc_rate()
338 reg >>= 7 + (ch->index * 4); berlin2_avpll_channel_recalc_rate()
340 reg = readl_relaxed(ch->base + VCO_CTRL15); berlin2_avpll_channel_recalc_rate()
342 div_av3 = reg & 0xf; berlin2_avpll_channel_recalc_rate()
H A Dberlin2-div.c79 u32 reg; berlin2_div_is_enabled() local
84 reg = readl_relaxed(div->base + map->gate_offs); berlin2_div_is_enabled()
85 reg >>= map->gate_shift; berlin2_div_is_enabled()
90 return (reg & 0x1); berlin2_div_is_enabled()
97 u32 reg; berlin2_div_enable() local
102 reg = readl_relaxed(div->base + map->gate_offs); berlin2_div_enable()
103 reg |= BIT(map->gate_shift); berlin2_div_enable()
104 writel_relaxed(reg, div->base + map->gate_offs); berlin2_div_enable()
116 u32 reg; berlin2_div_disable() local
121 reg = readl_relaxed(div->base + map->gate_offs); berlin2_div_disable()
122 reg &= ~BIT(map->gate_shift); berlin2_div_disable()
123 writel_relaxed(reg, div->base + map->gate_offs); berlin2_div_disable()
133 u32 reg; berlin2_div_set_parent() local
139 reg = readl_relaxed(div->base + map->pll_switch_offs); berlin2_div_set_parent()
141 reg &= ~BIT(map->pll_switch_shift); berlin2_div_set_parent()
143 reg |= BIT(map->pll_switch_shift); berlin2_div_set_parent()
144 writel_relaxed(reg, div->base + map->pll_switch_offs); berlin2_div_set_parent()
148 reg = readl_relaxed(div->base + map->pll_select_offs); berlin2_div_set_parent()
149 reg &= ~(PLL_SELECT_MASK << map->pll_select_shift); berlin2_div_set_parent()
150 reg |= (index - 1) << map->pll_select_shift; berlin2_div_set_parent()
151 writel_relaxed(reg, div->base + map->pll_select_offs); berlin2_div_set_parent()
164 u32 reg; berlin2_div_get_parent() local
171 reg = readl_relaxed(div->base + map->pll_switch_offs); berlin2_div_get_parent()
172 reg &= BIT(map->pll_switch_shift); berlin2_div_get_parent()
173 if (reg) { berlin2_div_get_parent()
174 reg = readl_relaxed(div->base + map->pll_select_offs); berlin2_div_get_parent()
175 reg >>= map->pll_select_shift; berlin2_div_get_parent()
176 reg &= PLL_SELECT_MASK; berlin2_div_get_parent()
177 index = 1 + reg; berlin2_div_get_parent()
209 u32 reg; berlin2_div_recalc_rate() local
210 reg = readl_relaxed(div->base + map->div_select_offs); berlin2_div_recalc_rate()
211 reg >>= map->div_select_shift; berlin2_div_recalc_rate()
212 reg &= DIV_SELECT_MASK; berlin2_div_recalc_rate()
213 divider = clk_div[reg]; berlin2_div_recalc_rate()
/linux-4.1.27/drivers/usb/gadget/udc/
H A Dfusb300_udc.c42 u32 reg = ioread32(fusb300->reg + offset); fusb300_enable_bit() local
44 reg |= value; fusb300_enable_bit()
45 iowrite32(reg, fusb300->reg + offset); fusb300_enable_bit()
51 u32 reg = ioread32(fusb300->reg + offset); fusb300_disable_bit() local
53 reg &= ~value; fusb300_disable_bit()
54 iowrite32(reg, fusb300->reg + offset); fusb300_disable_bit()
78 u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); fusb300_set_fifo_entry()
82 iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); fusb300_set_fifo_entry()
88 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); fusb300_set_start_entry() local
91 reg &= ~FUSB300_EPSET1_START_ENTRY_MSK ; fusb300_set_start_entry()
92 reg |= FUSB300_EPSET1_START_ENTRY(start_entry); fusb300_set_start_entry()
93 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); fusb300_set_start_entry()
106 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); fusb300_set_epaddrofs() local
108 reg &= ~FUSB300_EPSET2_ADDROFS_MSK; fusb300_set_epaddrofs()
109 reg |= FUSB300_EPSET2_ADDROFS(fusb300->addrofs); fusb300_set_epaddrofs()
110 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); fusb300_set_epaddrofs()
125 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); fusb300_set_eptype() local
127 reg &= ~FUSB300_EPSET1_TYPE_MSK; fusb300_set_eptype()
128 reg |= FUSB300_EPSET1_TYPE(info.type); fusb300_set_eptype()
129 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); fusb300_set_eptype()
135 u32 reg; fusb300_set_epdir() local
139 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); fusb300_set_epdir()
140 reg &= ~FUSB300_EPSET1_DIR_MSK; fusb300_set_epdir()
141 reg |= FUSB300_EPSET1_DIRIN; fusb300_set_epdir()
142 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); fusb300_set_epdir()
148 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); fusb300_set_ep_active() local
150 reg |= FUSB300_EPSET1_ACTEN; fusb300_set_ep_active()
151 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); fusb300_set_ep_active()
157 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); fusb300_set_epmps() local
159 reg &= ~FUSB300_EPSET2_MPS_MSK; fusb300_set_epmps()
160 reg |= FUSB300_EPSET2_MPS(info.maxpacket); fusb300_set_epmps()
161 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); fusb300_set_epmps()
167 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); fusb300_set_interval() local
169 reg &= ~FUSB300_EPSET1_INTERVAL(0x7); fusb300_set_interval()
170 reg |= FUSB300_EPSET1_INTERVAL(info.interval); fusb300_set_interval()
171 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); fusb300_set_interval()
177 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); fusb300_set_bwnum() local
179 reg &= ~FUSB300_EPSET1_BWNUM(0x3); fusb300_set_bwnum()
180 reg |= FUSB300_EPSET1_BWNUM(info.bw_num); fusb300_set_bwnum()
181 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); fusb300_set_bwnum()
324 u32 reg; fusb300_set_cxlen() local
326 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR); fusb300_set_cxlen()
327 reg &= ~FUSB300_CSR_LEN_MSK; fusb300_set_cxlen()
328 reg |= FUSB300_CSR_LEN(length); fusb300_set_cxlen()
329 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_CSR); fusb300_set_cxlen()
349 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); fusb300_wrcxf()
359 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); fusb300_wrcxf()
366 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); fusb300_wrcxf()
371 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); fusb300_wrcxf()
376 iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); fusb300_wrcxf()
393 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep)); fusb300_clear_epnstall() local
395 if (reg & FUSB300_EPSET0_STL) { fusb300_clear_epnstall()
397 reg |= FUSB300_EPSET0_STL_CLR; fusb300_clear_epnstall()
398 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep)); fusb300_clear_epnstall()
540 iowrite32(value, fusb300->reg + offset); fusb300_clear_int()
570 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); fusb300_rdcxf()
581 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); fusb300_rdcxf()
586 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); fusb300_rdcxf()
592 data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); fusb300_rdcxf()
609 u32 data, reg; fusb300_rdfifo() local
619 data = ioread32(fusb300->reg + fusb300_rdfifo()
630 data = ioread32(fusb300->reg + fusb300_rdfifo()
635 data = ioread32(fusb300->reg + fusb300_rdfifo()
641 data = ioread32(fusb300->reg + fusb300_rdfifo()
652 reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1); fusb300_rdfifo()
653 reg &= FUSB300_IGR1_SYNF0_EMPTY_INT; fusb300_rdfifo()
657 } while (!reg); fusb300_rdfifo()
663 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep)); fusb300_get_epnstall() local
665 value = reg & FUSB300_EPSET0_STL; fusb300_get_epnstall()
673 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR); fusb300_get_cxstall() local
675 value = (reg & FUSB300_CSR_STL) >> 1; fusb300_get_cxstall()
796 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_DAR); fusb300_set_dev_addr() local
798 reg &= ~FUSB300_DAR_DRVADDR_MSK; fusb300_set_dev_addr()
799 reg |= FUSB300_DAR_DRVADDR(addr); fusb300_set_dev_addr()
801 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_DAR); fusb300_set_dev_addr()
894 u32 reg; fusb300_fill_idma_prdtbl() local
898 reg = ioread32(ep->fusb300->reg + fusb300_fill_idma_prdtbl()
900 reg &= FUSB300_EPPRD0_H; fusb300_fill_idma_prdtbl()
901 } while (reg); fusb300_fill_idma_prdtbl()
903 iowrite32(d, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W1(ep->epnum)); fusb300_fill_idma_prdtbl()
907 iowrite32(value, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W0(ep->epnum)); fusb300_fill_idma_prdtbl()
909 iowrite32(0x0, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W2(ep->epnum)); fusb300_fill_idma_prdtbl()
917 u32 reg; fusb300_wait_idma_finished() local
920 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR1); fusb300_wait_idma_finished()
921 if ((reg & FUSB300_IGR1_VBUS_CHG_INT) || fusb300_wait_idma_finished()
922 (reg & FUSB300_IGR1_WARM_RST_INT) || fusb300_wait_idma_finished()
923 (reg & FUSB300_IGR1_HOT_RST_INT) || fusb300_wait_idma_finished()
924 (reg & FUSB300_IGR1_USBRST_INT) fusb300_wait_idma_finished()
927 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR0); fusb300_wait_idma_finished()
928 reg &= FUSB300_IGR0_EPn_PRD_INT(ep->epnum); fusb300_wait_idma_finished()
929 } while (!reg); fusb300_wait_idma_finished()
936 reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGER0); fusb300_wait_idma_finished()
937 reg &= ~FUSB300_IGER0_EEPn_PRD_INT(ep->epnum); fusb300_wait_idma_finished()
938 iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_IGER0); fusb300_wait_idma_finished()
977 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum)); out_ep_fifo_handler() local
978 u32 length = reg & FUSB300_FFR_BYCNT; out_ep_fifo_handler()
989 u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_GCR); check_device_mode() local
991 switch (reg & FUSB300_GCR_DEVEN_MSK) { check_device_mode()
1005 printk(KERN_INFO "dev_mode = %d\n", (reg & FUSB300_GCR_DEVEN_MSK)); check_device_mode()
1012 u32 reg; fusb300_ep0out() local
1023 reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1); fusb300_ep0out()
1024 reg &= ~FUSB300_IGER1_CX_OUT_INT; fusb300_ep0out()
1025 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_IGER1); fusb300_ep0out()
1065 u32 int_grp1 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1); fusb300_irq()
1066 u32 int_grp1_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1); fusb300_irq()
1067 u32 int_grp0 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR0); fusb300_irq()
1068 u32 int_grp0_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER0); fusb300_irq()
1071 u32 reg; fusb300_irq() local
1243 reg = ioread32(fusb300->reg + fusb300_irq()
1245 in = (reg & FUSB300_EPSET1_DIRIN) ? 1 : 0; fusb300_irq()
1262 u32 reg; fusb300_set_u2_timeout() local
1264 reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT); fusb300_set_u2_timeout()
1265 reg &= ~0xff; fusb300_set_u2_timeout()
1266 reg |= FUSB300_SSCR2_U2TIMEOUT(time); fusb300_set_u2_timeout()
1268 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT); fusb300_set_u2_timeout()
1274 u32 reg; fusb300_set_u1_timeout() local
1276 reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT); fusb300_set_u1_timeout()
1277 reg &= ~(0xff << 8); fusb300_set_u1_timeout()
1278 reg |= FUSB300_SSCR2_U1TIMEOUT(time); fusb300_set_u1_timeout()
1280 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT); fusb300_set_u1_timeout()
1285 u32 reg; init_controller() local
1291 reg = ioread32(fusb300->reg + FUSB300_OFFSET_AHBCR); init_controller()
1292 reg &= ~mask; init_controller()
1293 reg |= val; init_controller()
1294 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_AHBCR); init_controller()
1298 reg = ioread32(fusb300->reg + FUSB300_OFFSET_HSCR); init_controller()
1299 reg &= ~mask; init_controller()
1300 reg |= val; init_controller()
1301 iowrite32(reg, fusb300->reg + FUSB300_OFFSET_HSCR); init_controller()
1308 iowrite32(0xcfffff9f, fusb300->reg + FUSB300_OFFSET_IGER1); init_controller()
1350 iounmap(fusb300->reg); fusb300_remove()
1362 void __iomem *reg = NULL; fusb300_probe() local
1391 reg = ioremap(res->start, resource_size(res)); fusb300_probe()
1392 if (reg == NULL) { fusb300_probe()
1422 fusb300->reg = reg; fusb300_probe()
1488 if (reg) fusb300_probe()
1489 iounmap(reg); fusb300_probe()
H A Dfotg210-udc.c33 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1); fotg210_disable_fifo_int()
39 iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1); fotg210_disable_fifo_int()
44 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1); fotg210_enable_fifo_int()
50 iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1); fotg210_enable_fifo_int()
55 u32 value = ioread32(fotg210->reg + FOTG210_DCFESR); fotg210_set_cxdone()
58 iowrite32(value, fotg210->reg + FOTG210_DCFESR); fotg210_set_cxdone()
95 val = ioread32(fotg210->reg + FOTG210_EPMAP); fotg210_fifo_ep_mapping()
98 iowrite32(val, fotg210->reg + FOTG210_EPMAP); fotg210_fifo_ep_mapping()
101 val = ioread32(fotg210->reg + FOTG210_FIFOMAP); fotg210_fifo_ep_mapping()
104 iowrite32(val, fotg210->reg + FOTG210_FIFOMAP); fotg210_fifo_ep_mapping()
107 val = ioread32(fotg210->reg + FOTG210_FIFOCF); fotg210_fifo_ep_mapping()
109 iowrite32(val, fotg210->reg + FOTG210_FIFOCF); fotg210_fifo_ep_mapping()
117 val = ioread32(fotg210->reg + FOTG210_FIFOMAP); fotg210_set_fifo_dir()
119 iowrite32(val, fotg210->reg + FOTG210_FIFOMAP); fotg210_set_fifo_dir()
127 val = ioread32(fotg210->reg + FOTG210_FIFOCF); fotg210_set_tfrtype()
129 iowrite32(val, fotg210->reg + FOTG210_FIFOCF); fotg210_set_tfrtype()
140 val = ioread32(fotg210->reg + offset); fotg210_set_mps()
142 iowrite32(val, fotg210->reg + offset); fotg210_set_mps()
180 void __iomem *reg; fotg210_reset_tseq() local
182 reg = (ep->dir_in) ? fotg210_reset_tseq()
183 fotg210->reg + FOTG210_INEPMPSR(epnum) : fotg210_reset_tseq()
184 fotg210->reg + FOTG210_OUTEPMPSR(epnum); fotg210_reset_tseq()
190 value = ioread32(reg); fotg210_reset_tseq()
192 iowrite32(value, reg); fotg210_reset_tseq()
194 value = ioread32(reg); fotg210_reset_tseq()
196 iowrite32(value, reg); fotg210_reset_tseq()
263 value = ioread32(fotg210->reg + FOTG210_DMACPSR1); fotg210_enable_dma()
266 iowrite32(value, fotg210->reg + FOTG210_DMACPSR1); fotg210_enable_dma()
269 value = ioread32(fotg210->reg + FOTG210_DMATFNR); fotg210_enable_dma()
274 iowrite32(value, fotg210->reg + FOTG210_DMATFNR); fotg210_enable_dma()
277 iowrite32(d, fotg210->reg + FOTG210_DMACPSR2); fotg210_enable_dma()
280 value = ioread32(fotg210->reg + FOTG210_DMISGR2); fotg210_enable_dma()
282 iowrite32(value, fotg210->reg + FOTG210_DMISGR2); fotg210_enable_dma()
285 value = ioread32(fotg210->reg + FOTG210_DMACPSR1); fotg210_enable_dma()
287 iowrite32(value, fotg210->reg + FOTG210_DMACPSR1); fotg210_enable_dma()
292 iowrite32(DMATFNR_DISDMA, ep->fotg210->reg + FOTG210_DMATFNR); fotg210_disable_dma()
300 value = ioread32(ep->fotg210->reg + FOTG210_DISGR2); fotg210_wait_dma_done()
307 iowrite32(value, ep->fotg210->reg + FOTG210_DISGR2); fotg210_wait_dma_done()
311 value = ioread32(ep->fotg210->reg + FOTG210_DMACPSR1); fotg210_wait_dma_done()
313 iowrite32(value, ep->fotg210->reg + FOTG210_DMACPSR1); fotg210_wait_dma_done()
317 value = ioread32(ep->fotg210->reg + fotg210_wait_dma_done()
320 iowrite32(value, ep->fotg210->reg + fotg210_wait_dma_done()
323 value = ioread32(ep->fotg210->reg + FOTG210_DCFESR); fotg210_wait_dma_done()
325 iowrite32(value, ep->fotg210->reg + FOTG210_DCFESR); fotg210_wait_dma_done()
342 length = ioread32(ep->fotg210->reg + fotg210_start_dma()
400 u32 value = ioread32(ep->fotg210->reg + fotg210_ep0_queue()
404 iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR0); fotg210_ep0_queue()
464 void __iomem *reg; fotg210_set_epnstall() local
469 value = ioread32(fotg210->reg + FOTG210_DCFESR); fotg210_set_epnstall()
473 reg = (ep->dir_in) ? fotg210_set_epnstall()
474 fotg210->reg + FOTG210_INEPMPSR(ep->epnum) : fotg210_set_epnstall()
475 fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum); fotg210_set_epnstall()
476 value = ioread32(reg); fotg210_set_epnstall()
478 iowrite32(value, reg); fotg210_set_epnstall()
485 void __iomem *reg; fotg210_clear_epnstall() local
487 reg = (ep->dir_in) ? fotg210_clear_epnstall()
488 fotg210->reg + FOTG210_INEPMPSR(ep->epnum) : fotg210_clear_epnstall()
489 fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum); fotg210_clear_epnstall()
490 value = ioread32(reg); fotg210_clear_epnstall()
492 iowrite32(value, reg); fotg210_clear_epnstall()
557 u32 value = ioread32(fotg210->reg + FOTG210_TX0BYTE); fotg210_clear_tx0byte()
561 iowrite32(value, fotg210->reg + FOTG210_TX0BYTE); fotg210_clear_tx0byte()
566 u32 value = ioread32(fotg210->reg + FOTG210_RX0BYTE); fotg210_clear_rx0byte()
570 iowrite32(value, fotg210->reg + FOTG210_RX0BYTE); fotg210_clear_rx0byte()
582 iowrite32(DMATFNR_ACC_CXF, fotg210->reg + FOTG210_DMATFNR); fotg210_rdsetupp()
585 data = ioread32(fotg210->reg + FOTG210_CXPORT); fotg210_rdsetupp()
595 data = ioread32(fotg210->reg + FOTG210_CXPORT); fotg210_rdsetupp()
599 data = ioread32(fotg210->reg + FOTG210_CXPORT); fotg210_rdsetupp()
604 data = ioread32(fotg210->reg + FOTG210_CXPORT); fotg210_rdsetupp()
613 iowrite32(DMATFNR_DISDMA, fotg210->reg + FOTG210_DMATFNR); fotg210_rdsetupp()
618 u32 value = ioread32(fotg210->reg + FOTG210_DAR); fotg210_set_configuration()
621 iowrite32(value, fotg210->reg + FOTG210_DAR); fotg210_set_configuration()
626 u32 value = ioread32(fotg210->reg + FOTG210_DAR); fotg210_set_dev_addr()
629 iowrite32(value, fotg210->reg + FOTG210_DAR); fotg210_set_dev_addr()
634 u32 value = ioread32(fotg210->reg + FOTG210_DCFESR); fotg210_set_cxstall()
637 iowrite32(value, fotg210->reg + FOTG210_DCFESR); fotg210_set_cxstall()
717 void __iomem *reg; fotg210_is_epnstall() local
719 reg = (ep->dir_in) ? fotg210_is_epnstall()
720 fotg210->reg + FOTG210_INEPMPSR(ep->epnum) : fotg210_is_epnstall()
721 fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum); fotg210_is_epnstall()
722 value = ioread32(reg); fotg210_is_epnstall()
772 u32 value = ioread32(fotg210->reg + FOTG210_DMCR); fotg210_setup_packet()
849 u32 value = ioread32(fotg210->reg + FOTG210_DISGR0); fotg210_clear_comabt_int()
852 iowrite32(value, fotg210->reg + FOTG210_DISGR0); fotg210_clear_comabt_int()
881 u32 int_grp = ioread32(fotg210->reg + FOTG210_DIGR); fotg210_irq()
882 u32 int_msk = ioread32(fotg210->reg + FOTG210_DMIGR); fotg210_irq()
889 void __iomem *reg = fotg210->reg + FOTG210_DISGR2; fotg210_irq() local
890 u32 int_grp2 = ioread32(reg); fotg210_irq()
891 u32 int_msk2 = ioread32(fotg210->reg + FOTG210_DMISGR2); fotg210_irq()
897 value = ioread32(reg); fotg210_irq()
899 iowrite32(value, reg); fotg210_irq()
903 value = ioread32(reg); fotg210_irq()
905 iowrite32(value, reg); fotg210_irq()
909 value = ioread32(reg); fotg210_irq()
911 iowrite32(value, reg); fotg210_irq()
915 value = ioread32(reg); fotg210_irq()
917 iowrite32(value, reg); fotg210_irq()
921 value = ioread32(reg); fotg210_irq()
923 iowrite32(value, reg); fotg210_irq()
928 value = ioread32(reg); fotg210_irq()
930 iowrite32(value, reg); fotg210_irq()
935 value = ioread32(reg); fotg210_irq()
937 iowrite32(value, reg); fotg210_irq()
941 value = ioread32(reg); fotg210_irq()
943 iowrite32(value, reg); fotg210_irq()
948 void __iomem *reg = fotg210->reg + FOTG210_DISGR0; fotg210_irq() local
949 u32 int_grp0 = ioread32(reg); fotg210_irq()
950 u32 int_msk0 = ioread32(fotg210->reg + FOTG210_DMISGR0); fotg210_irq()
986 void __iomem *reg = fotg210->reg + FOTG210_DISGR1; fotg210_irq() local
987 u32 int_grp1 = ioread32(reg); fotg210_irq()
988 u32 int_msk1 = ioread32(fotg210->reg + FOTG210_DMISGR1); fotg210_irq()
1010 u32 reg = ioread32(fotg210->reg + FOTG210_PHYTMSR); fotg210_disable_unplug() local
1012 reg &= ~PHYTMSR_UNPLUG; fotg210_disable_unplug()
1013 iowrite32(reg, fotg210->reg + FOTG210_PHYTMSR); fotg210_disable_unplug()
1027 value = ioread32(fotg210->reg + FOTG210_DMCR); fotg210_udc_start()
1029 iowrite32(value, fotg210->reg + FOTG210_DMCR); fotg210_udc_start()
1040 fotg210->reg + FOTG210_GMIR); fotg210_init()
1043 value = ioread32(fotg210->reg + FOTG210_DMCR); fotg210_init()
1045 iowrite32(value, fotg210->reg + FOTG210_DMCR); fotg210_init()
1048 iowrite32(~(u32)0, fotg210->reg + FOTG210_DMISGR1); fotg210_init()
1051 value = ioread32(fotg210->reg + FOTG210_DMISGR0); fotg210_init()
1053 iowrite32(value, fotg210->reg + FOTG210_DMISGR0); fotg210_init()
1081 iounmap(fotg210->reg); fotg210_udc_remove()
1124 fotg210->reg = ioremap(res->start, resource_size(res)); fotg210_udc_probe()
1125 if (fotg210->reg == NULL) { fotg210_udc_probe()
1193 if (fotg210->reg) fotg210_udc_probe()
1194 iounmap(fotg210->reg); fotg210_udc_probe()
/linux-4.1.27/drivers/media/platform/blackfin/
H A Dppi.c56 struct bfin_ppi_regs *reg = info->base; ppi_irq_err() local
62 status = bfin_read16(&reg->status); ppi_irq_err()
65 bfin_write16(&reg->status, 0xff00); ppi_irq_err()
70 struct bfin_eppi_regs *reg = info->base; ppi_irq_err() local
73 status = bfin_read16(&reg->status); ppi_irq_err()
76 bfin_write16(&reg->status, 0xffff); ppi_irq_err()
81 struct bfin_eppi3_regs *reg = info->base; ppi_irq_err() local
84 stat = bfin_read32(&reg->stat); ppi_irq_err()
87 bfin_write32(&reg->stat, 0xc0ff); ppi_irq_err()
141 struct bfin_ppi_regs *reg = info->base; ppi_start() local
142 bfin_write16(&reg->control, ppi->ppi_control); ppi_start()
147 struct bfin_eppi_regs *reg = info->base; ppi_start() local
148 bfin_write32(&reg->control, ppi->ppi_control); ppi_start()
153 struct bfin_eppi3_regs *reg = info->base; ppi_start() local
154 bfin_write32(&reg->ctl, ppi->ppi_control); ppi_start()
174 struct bfin_ppi_regs *reg = info->base; ppi_stop() local
175 bfin_write16(&reg->control, ppi->ppi_control); ppi_stop()
180 struct bfin_eppi_regs *reg = info->base; ppi_stop() local
181 bfin_write32(&reg->control, ppi->ppi_control); ppi_stop()
186 struct bfin_eppi3_regs *reg = info->base; ppi_stop() local
187 bfin_write32(&reg->ctl, ppi->ppi_control); ppi_stop()
240 struct bfin_ppi_regs *reg = info->base; ppi_set_params() local
245 bfin_write16(&reg->control, ppi->ppi_control); ppi_set_params()
246 bfin_write16(&reg->count, samples_per_line - 1); ppi_set_params()
247 bfin_write16(&reg->frame, params->frame); ppi_set_params()
252 struct bfin_eppi_regs *reg = info->base; ppi_set_params() local
258 bfin_write32(&reg->control, ppi->ppi_control); ppi_set_params()
259 bfin_write16(&reg->line, samples_per_line); ppi_set_params()
260 bfin_write16(&reg->frame, params->frame); ppi_set_params()
261 bfin_write16(&reg->hdelay, hdelay); ppi_set_params()
262 bfin_write16(&reg->vdelay, params->vdelay); ppi_set_params()
263 bfin_write16(&reg->hcount, hcount); ppi_set_params()
264 bfin_write16(&reg->vcount, params->height); ppi_set_params()
269 struct bfin_eppi3_regs *reg = info->base; ppi_set_params() local
275 bfin_write32(&reg->ctl, ppi->ppi_control); ppi_set_params()
276 bfin_write32(&reg->line, samples_per_line); ppi_set_params()
277 bfin_write32(&reg->frame, params->frame); ppi_set_params()
278 bfin_write32(&reg->hdly, hdelay); ppi_set_params()
279 bfin_write32(&reg->vdly, params->vdelay); ppi_set_params()
280 bfin_write32(&reg->hcnt, hcount); ppi_set_params()
281 bfin_write32(&reg->vcnt, params->height); ppi_set_params()
283 bfin_write32(&reg->imsk, params->int_mask & 0xFF); ppi_set_params()
291 bfin_write32(&reg->fs1_wlhb, hsync_width); ppi_set_params()
292 bfin_write32(&reg->fs1_paspl, samples_per_line); ppi_set_params()
293 bfin_write32(&reg->fs2_wlvb, vsync_width); ppi_set_params()
294 bfin_write32(&reg->fs2_palpf, vsync_period); ppi_set_params()
/linux-4.1.27/arch/sparc/include/asm/
H A Dwinmacro.h13 * at %reg. It might be %sp, it might not, we don't care.
15 #define STORE_WINDOW(reg) \
16 std %l0, [%reg + RW_L0]; \
17 std %l2, [%reg + RW_L2]; \
18 std %l4, [%reg + RW_L4]; \
19 std %l6, [%reg + RW_L6]; \
20 std %i0, [%reg + RW_I0]; \
21 std %i2, [%reg + RW_I2]; \
22 std %i4, [%reg + RW_I4]; \
23 std %i6, [%reg + RW_I6];
25 /* Load a register window from the area beginning at %reg. */
26 #define LOAD_WINDOW(reg) \
27 ldd [%reg + RW_L0], %l0; \
28 ldd [%reg + RW_L2], %l2; \
29 ldd [%reg + RW_L4], %l4; \
30 ldd [%reg + RW_L6], %l6; \
31 ldd [%reg + RW_I0], %i0; \
32 ldd [%reg + RW_I2], %i2; \
33 ldd [%reg + RW_I4], %i4; \
34 ldd [%reg + RW_I6], %i6;
/linux-4.1.27/drivers/media/i2c/smiapp/
H A Dsmiapp-regs.h25 #define SMIAPP_REG_ADDR(reg) ((u16)reg)
26 #define SMIAPP_REG_WIDTH(reg) ((u8)(reg >> 16))
27 #define SMIAPP_REG_FLAGS(reg) ((u8)(reg >> 24))
38 int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val);
39 int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val);
40 int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val);
41 int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val);
42 int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val);
/linux-4.1.27/arch/x86/lib/
H A Dmsr-smp.c9 struct msr *reg; __rdmsr_on_cpu() local
13 reg = per_cpu_ptr(rv->msrs, this_cpu); __rdmsr_on_cpu()
15 reg = &rv->reg; __rdmsr_on_cpu()
17 rdmsr(rv->msr_no, reg->l, reg->h); __rdmsr_on_cpu()
23 struct msr *reg; __wrmsr_on_cpu() local
27 reg = per_cpu_ptr(rv->msrs, this_cpu); __wrmsr_on_cpu()
29 reg = &rv->reg; __wrmsr_on_cpu()
31 wrmsr(rv->msr_no, reg->l, reg->h); __wrmsr_on_cpu()
43 *l = rv.reg.l; rdmsr_on_cpu()
44 *h = rv.reg.h; rdmsr_on_cpu()
59 *q = rv.reg.q; rdmsrl_on_cpu()
73 rv.reg.l = l; wrmsr_on_cpu()
74 rv.reg.h = h; wrmsr_on_cpu()
89 rv.reg.q = q; wrmsrl_on_cpu()
151 rv->err = rdmsr_safe(rv->msr_no, &rv->reg.l, &rv->reg.h); __rdmsr_safe_on_cpu()
158 rv->err = wrmsr_safe(rv->msr_no, rv->reg.l, rv->reg.h); __wrmsr_safe_on_cpu()
170 *l = rv.reg.l; rdmsr_safe_on_cpu()
171 *h = rv.reg.h; rdmsr_safe_on_cpu()
185 rv.reg.l = l; wrmsr_safe_on_cpu()
186 rv.reg.h = h; wrmsr_safe_on_cpu()
201 rv.reg.q = q; wrmsrl_safe_on_cpu()
218 *q = rv.reg.q; rdmsrl_safe_on_cpu()
/linux-4.1.27/arch/arm/mach-omap2/
H A Dprcm_mpu44xx.c31 u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg) omap4_prcm_mpu_read_inst_reg() argument
33 return readl_relaxed(OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); omap4_prcm_mpu_read_inst_reg()
36 void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg) omap4_prcm_mpu_write_inst_reg() argument
38 writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); omap4_prcm_mpu_write_inst_reg()
41 u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) omap4_prcm_mpu_rmw_inst_reg_bits() argument
45 v = omap4_prcm_mpu_read_inst_reg(inst, reg); omap4_prcm_mpu_rmw_inst_reg_bits()
48 omap4_prcm_mpu_write_inst_reg(v, inst, reg); omap4_prcm_mpu_rmw_inst_reg_bits()
H A Dvp.h40 * @vpconfig_erroroffset_mask: ERROROFFSET bitmask in the PRM_VP*_CONFIG reg
41 * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
42 * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
43 * @vpconfig_timeouten: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
44 * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
45 * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
46 * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
47 * @vpconfig_erroroffset_shift: ERROROFFSET field shift in PRM_VP*_CONFIG reg
48 * @vpconfig_errorgain_shift: ERRORGAIN field shift in PRM_VP*_CONFIG reg
49 * @vpconfig_initvoltage_shift: INITVOLTAGE field shift in PRM_VP*_CONFIG reg
50 * @vstepmin_stepmin_shift: VSTEPMIN field shift in the PRM_VP*_VSTEPMIN reg
51 * @vstepmin_smpswaittimemin_shift: SMPSWAITTIMEMIN field shift in PRM_VP*_VSTEPMIN reg
52 * @vstepmax_stepmax_shift: VSTEPMAX field shift in the PRM_VP*_VSTEPMAX reg
53 * @vstepmax_smpswaittimemax_shift: SMPSWAITTIMEMAX field shift in PRM_VP*_VSTEPMAX reg
54 * @vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg
55 * @vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg
56 * @vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg
57 * @vpvoltage_mask: VPVOLTAGE field mask in PRM_VP*_VOLTAGE reg
82 * @vpconfig: PRM_VP*_CONFIG reg offset from PRM start
83 * @vstepmin: PRM_VP*_VSTEPMIN reg offset from PRM start
84 * @vlimitto: PRM_VP*_VLIMITTO reg offset from PRM start
85 * @vstatus: PRM_VP*_VSTATUS reg offset from PRM start
86 * @voltage: PRM_VP*_VOLTAGE reg offset from PRM start
/linux-4.1.27/drivers/thermal/
H A Darmada_thermal.c61 /* Formula coeficients: temp = (b + m * reg) / div */
76 unsigned long reg; armadaxp_init_sensor() local
78 reg = readl_relaxed(priv->control); armadaxp_init_sensor()
79 reg |= PMU_TDC0_OTF_CAL_MASK; armadaxp_init_sensor()
80 writel(reg, priv->control); armadaxp_init_sensor()
83 reg &= ~PMU_TDC0_REF_CAL_CNT_MASK; armadaxp_init_sensor()
84 reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS); armadaxp_init_sensor()
85 writel(reg, priv->control); armadaxp_init_sensor()
88 reg = readl_relaxed(priv->control); armadaxp_init_sensor()
89 writel((reg | PMU_TDC0_SW_RST_MASK), priv->control); armadaxp_init_sensor()
91 writel(reg, priv->control); armadaxp_init_sensor()
94 reg = readl_relaxed(priv->sensor); armadaxp_init_sensor()
95 reg &= ~PMU_TM_DISABLE_MASK; armadaxp_init_sensor()
96 writel(reg, priv->sensor); armadaxp_init_sensor()
102 unsigned long reg; armada370_init_sensor() local
104 reg = readl_relaxed(priv->control); armada370_init_sensor()
105 reg |= PMU_TDC0_OTF_CAL_MASK; armada370_init_sensor()
106 writel(reg, priv->control); armada370_init_sensor()
109 reg &= ~PMU_TDC0_REF_CAL_CNT_MASK; armada370_init_sensor()
110 reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS); armada370_init_sensor()
111 writel(reg, priv->control); armada370_init_sensor()
113 reg &= ~PMU_TDC0_START_CAL_MASK; armada370_init_sensor()
114 writel(reg, priv->control); armada370_init_sensor()
122 unsigned long reg; armada375_init_sensor() local
124 reg = readl(priv->control + 4); armada375_init_sensor()
125 reg &= ~(A375_UNIT_CONTROL_MASK << A375_UNIT_CONTROL_SHIFT); armada375_init_sensor()
126 reg &= ~A375_READOUT_INVERT; armada375_init_sensor()
127 reg &= ~A375_HW_RESETn; armada375_init_sensor()
129 writel(reg, priv->control + 4); armada375_init_sensor()
132 reg |= A375_HW_RESETn; armada375_init_sensor()
133 writel(reg, priv->control + 4); armada375_init_sensor()
140 unsigned long reg = readl_relaxed(priv->control); armada380_init_sensor() local
143 if (!(reg & A380_HW_RESET)) { armada380_init_sensor()
144 reg |= A380_HW_RESET; armada380_init_sensor()
145 writel(reg, priv->control); armada380_init_sensor()
152 unsigned long reg = readl_relaxed(priv->sensor); armada_is_valid() local
154 return (reg >> priv->data->is_valid_shift) & THERMAL_VALID_MASK; armada_is_valid()
161 unsigned long reg; armada_get_temp() local
171 reg = readl_relaxed(priv->sensor); armada_get_temp()
172 reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask; armada_get_temp()
180 *temp = ((m * reg) - b) / div; armada_get_temp()
182 *temp = (b - (m * reg)) / div; armada_get_temp()
H A Ddove_thermal.c53 u32 reg; dove_init_sensor() local
57 reg = readl_relaxed(priv->control); dove_init_sensor()
60 reg &= ~PMU_TDC0_AVG_NUM_MASK; dove_init_sensor()
61 reg |= (0x1 << PMU_TDC0_AVG_NUM_OFFS); dove_init_sensor()
64 reg &= ~PMU_TDC0_REF_CAL_CNT_MASK; dove_init_sensor()
65 reg |= (0x0F1 << PMU_TDC0_REF_CAL_CNT_OFFS); dove_init_sensor()
68 reg &= ~PMU_TDC0_SEL_VCAL_MASK; dove_init_sensor()
69 reg |= (0x2 << PMU_TDC0_SEL_VCAL_OFFS); dove_init_sensor()
70 writel(reg, priv->control); dove_init_sensor()
73 reg = readl_relaxed(priv->control); dove_init_sensor()
74 writel((reg | PMU_TDC0_SW_RST_MASK), priv->control); dove_init_sensor()
75 writel(reg, priv->control); dove_init_sensor()
78 reg = readl_relaxed(priv->sensor); dove_init_sensor()
79 reg &= ~PMU_TM_DISABLE_MASK; dove_init_sensor()
80 writel(reg, priv->sensor); dove_init_sensor()
84 reg = readl_relaxed(priv->sensor); dove_init_sensor()
85 if (reg & DOVE_THERMAL_TEMP_MASK) dove_init_sensor()
98 unsigned long reg; dove_get_temp() local
102 reg = readl_relaxed(priv->control + PMU_TEMP_DIOD_CTRL1_REG); dove_get_temp()
103 if ((reg & PMU_TDC1_TEMP_VALID_MASK) == 0x0) { dove_get_temp()
112 * Celsius = (322-reg)/1.3625 dove_get_temp()
114 reg = readl_relaxed(priv->sensor); dove_get_temp()
115 reg = (reg >> DOVE_THERMAL_TEMP_OFFSET) & DOVE_THERMAL_TEMP_MASK; dove_get_temp()
116 *temp = ((3220000000UL - (10000000UL * reg)) / 13625); dove_get_temp()
/linux-4.1.27/drivers/input/misc/
H A Dadxl34x-spi.c21 #define ADXL34X_WRITECMD(reg) (reg & 0x3F)
22 #define ADXL34X_READCMD(reg) (ADXL34X_CMD_READ | (reg & 0x3F))
23 #define ADXL34X_READMB_CMD(reg) (ADXL34X_CMD_READ | ADXL34X_CMD_MULTB \
24 | (reg & 0x3F))
26 static int adxl34x_spi_read(struct device *dev, unsigned char reg) adxl34x_spi_read() argument
31 cmd = ADXL34X_READCMD(reg); adxl34x_spi_read()
37 unsigned char reg, unsigned char val) adxl34x_spi_write()
42 buf[0] = ADXL34X_WRITECMD(reg); adxl34x_spi_write()
49 unsigned char reg, int count, adxl34x_spi_read_block()
55 reg = ADXL34X_READMB_CMD(reg); adxl34x_spi_read_block()
56 status = spi_write_then_read(spi, &reg, 1, buf, count); adxl34x_spi_read_block()
36 adxl34x_spi_write(struct device *dev, unsigned char reg, unsigned char val) adxl34x_spi_write() argument
48 adxl34x_spi_read_block(struct device *dev, unsigned char reg, int count, void *buf) adxl34x_spi_read_block() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramfuc.h83 ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg) ramfuc_rd32() argument
85 if (reg->sequence != ram->sequence) ramfuc_rd32()
86 reg->data = nv_rd32(ram->pfb, reg->addr); ramfuc_rd32()
87 return reg->data; ramfuc_rd32()
91 ramfuc_wr32(struct ramfuc *ram, struct ramfuc_reg *reg, u32 data) ramfuc_wr32() argument
95 reg->sequence = ram->sequence; ramfuc_wr32()
96 reg->data = data; ramfuc_wr32()
98 for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) { ramfuc_wr32()
100 nvkm_memx_wr32(ram->memx, reg->addr+off, reg->data); ramfuc_wr32()
101 off += reg->stride; ramfuc_wr32()
106 ramfuc_nuke(struct ramfuc *ram, struct ramfuc_reg *reg) ramfuc_nuke() argument
108 reg->force = true; ramfuc_nuke()
112 ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data) ramfuc_mask() argument
114 u32 temp = ramfuc_rd32(ram, reg); ramfuc_mask()
115 if (temp != ((temp & ~mask) | data) || reg->force) { ramfuc_mask()
116 ramfuc_wr32(ram, reg, (temp & ~mask) | data); ramfuc_mask()
117 reg->force = false; ramfuc_mask()
/linux-4.1.27/drivers/net/ethernet/intel/ixgb/
H A Dixgb_ethtool.c225 u32 *reg = p; ixgb_get_regs() local
226 u32 *reg_start = reg; ixgb_get_regs()
235 *reg++ = IXGB_READ_REG(hw, CTRL0); /* 0 */ ixgb_get_regs()
236 *reg++ = IXGB_READ_REG(hw, CTRL1); /* 1 */ ixgb_get_regs()
237 *reg++ = IXGB_READ_REG(hw, STATUS); /* 2 */ ixgb_get_regs()
238 *reg++ = IXGB_READ_REG(hw, EECD); /* 3 */ ixgb_get_regs()
239 *reg++ = IXGB_READ_REG(hw, MFS); /* 4 */ ixgb_get_regs()
242 *reg++ = IXGB_READ_REG(hw, ICR); /* 5 */ ixgb_get_regs()
243 *reg++ = IXGB_READ_REG(hw, ICS); /* 6 */ ixgb_get_regs()
244 *reg++ = IXGB_READ_REG(hw, IMS); /* 7 */ ixgb_get_regs()
245 *reg++ = IXGB_READ_REG(hw, IMC); /* 8 */ ixgb_get_regs()
248 *reg++ = IXGB_READ_REG(hw, RCTL); /* 9 */ ixgb_get_regs()
249 *reg++ = IXGB_READ_REG(hw, FCRTL); /* 10 */ ixgb_get_regs()
250 *reg++ = IXGB_READ_REG(hw, FCRTH); /* 11 */ ixgb_get_regs()
251 *reg++ = IXGB_READ_REG(hw, RDBAL); /* 12 */ ixgb_get_regs()
252 *reg++ = IXGB_READ_REG(hw, RDBAH); /* 13 */ ixgb_get_regs()
253 *reg++ = IXGB_READ_REG(hw, RDLEN); /* 14 */ ixgb_get_regs()
254 *reg++ = IXGB_READ_REG(hw, RDH); /* 15 */ ixgb_get_regs()
255 *reg++ = IXGB_READ_REG(hw, RDT); /* 16 */ ixgb_get_regs()
256 *reg++ = IXGB_READ_REG(hw, RDTR); /* 17 */ ixgb_get_regs()
257 *reg++ = IXGB_READ_REG(hw, RXDCTL); /* 18 */ ixgb_get_regs()
258 *reg++ = IXGB_READ_REG(hw, RAIDC); /* 19 */ ixgb_get_regs()
259 *reg++ = IXGB_READ_REG(hw, RXCSUM); /* 20 */ ixgb_get_regs()
263 *reg++ = IXGB_READ_REG_ARRAY(hw, RAL, (i << 1)); /*21,...,51 */ ixgb_get_regs()
264 *reg++ = IXGB_READ_REG_ARRAY(hw, RAH, (i << 1)); /*22,...,52 */ ixgb_get_regs()
268 *reg++ = IXGB_READ_REG(hw, TCTL); /* 53 */ ixgb_get_regs()
269 *reg++ = IXGB_READ_REG(hw, TDBAL); /* 54 */ ixgb_get_regs()
270 *reg++ = IXGB_READ_REG(hw, TDBAH); /* 55 */ ixgb_get_regs()
271 *reg++ = IXGB_READ_REG(hw, TDLEN); /* 56 */ ixgb_get_regs()
272 *reg++ = IXGB_READ_REG(hw, TDH); /* 57 */ ixgb_get_regs()
273 *reg++ = IXGB_READ_REG(hw, TDT); /* 58 */ ixgb_get_regs()
274 *reg++ = IXGB_READ_REG(hw, TIDV); /* 59 */ ixgb_get_regs()
275 *reg++ = IXGB_READ_REG(hw, TXDCTL); /* 60 */ ixgb_get_regs()
276 *reg++ = IXGB_READ_REG(hw, TSPMT); /* 61 */ ixgb_get_regs()
277 *reg++ = IXGB_READ_REG(hw, PAP); /* 62 */ ixgb_get_regs()
280 *reg++ = IXGB_READ_REG(hw, PCSC1); /* 63 */ ixgb_get_regs()
281 *reg++ = IXGB_READ_REG(hw, PCSC2); /* 64 */ ixgb_get_regs()
282 *reg++ = IXGB_READ_REG(hw, PCSS1); /* 65 */ ixgb_get_regs()
283 *reg++ = IXGB_READ_REG(hw, PCSS2); /* 66 */ ixgb_get_regs()
284 *reg++ = IXGB_READ_REG(hw, XPCSS); /* 67 */ ixgb_get_regs()
285 *reg++ = IXGB_READ_REG(hw, UCCR); /* 68 */ ixgb_get_regs()
286 *reg++ = IXGB_READ_REG(hw, XPCSTC); /* 69 */ ixgb_get_regs()
287 *reg++ = IXGB_READ_REG(hw, MACA); /* 70 */ ixgb_get_regs()
288 *reg++ = IXGB_READ_REG(hw, APAE); /* 71 */ ixgb_get_regs()
289 *reg++ = IXGB_READ_REG(hw, ARD); /* 72 */ ixgb_get_regs()
290 *reg++ = IXGB_READ_REG(hw, AIS); /* 73 */ ixgb_get_regs()
291 *reg++ = IXGB_READ_REG(hw, MSCA); /* 74 */ ixgb_get_regs()
292 *reg++ = IXGB_READ_REG(hw, MSRWD); /* 75 */ ixgb_get_regs()
295 *reg++ = IXGB_GET_STAT(adapter, tprl); /* 76 */ ixgb_get_regs()
296 *reg++ = IXGB_GET_STAT(adapter, tprh); /* 77 */ ixgb_get_regs()
297 *reg++ = IXGB_GET_STAT(adapter, gprcl); /* 78 */ ixgb_get_regs()
298 *reg++ = IXGB_GET_STAT(adapter, gprch); /* 79 */ ixgb_get_regs()
299 *reg++ = IXGB_GET_STAT(adapter, bprcl); /* 80 */ ixgb_get_regs()
300 *reg++ = IXGB_GET_STAT(adapter, bprch); /* 81 */ ixgb_get_regs()
301 *reg++ = IXGB_GET_STAT(adapter, mprcl); /* 82 */ ixgb_get_regs()
302 *reg++ = IXGB_GET_STAT(adapter, mprch); /* 83 */ ixgb_get_regs()
303 *reg++ = IXGB_GET_STAT(adapter, uprcl); /* 84 */ ixgb_get_regs()
304 *reg++ = IXGB_GET_STAT(adapter, uprch); /* 85 */ ixgb_get_regs()
305 *reg++ = IXGB_GET_STAT(adapter, vprcl); /* 86 */ ixgb_get_regs()
306 *reg++ = IXGB_GET_STAT(adapter, vprch); /* 87 */ ixgb_get_regs()
307 *reg++ = IXGB_GET_STAT(adapter, jprcl); /* 88 */ ixgb_get_regs()
308 *reg++ = IXGB_GET_STAT(adapter, jprch); /* 89 */ ixgb_get_regs()
309 *reg++ = IXGB_GET_STAT(adapter, gorcl); /* 90 */ ixgb_get_regs()
310 *reg++ = IXGB_GET_STAT(adapter, gorch); /* 91 */ ixgb_get_regs()
311 *reg++ = IXGB_GET_STAT(adapter, torl); /* 92 */ ixgb_get_regs()
312 *reg++ = IXGB_GET_STAT(adapter, torh); /* 93 */ ixgb_get_regs()
313 *reg++ = IXGB_GET_STAT(adapter, rnbc); /* 94 */ ixgb_get_regs()
314 *reg++ = IXGB_GET_STAT(adapter, ruc); /* 95 */ ixgb_get_regs()
315 *reg++ = IXGB_GET_STAT(adapter, roc); /* 96 */ ixgb_get_regs()
316 *reg++ = IXGB_GET_STAT(adapter, rlec); /* 97 */ ixgb_get_regs()
317 *reg++ = IXGB_GET_STAT(adapter, crcerrs); /* 98 */ ixgb_get_regs()
318 *reg++ = IXGB_GET_STAT(adapter, icbc); /* 99 */ ixgb_get_regs()
319 *reg++ = IXGB_GET_STAT(adapter, ecbc); /* 100 */ ixgb_get_regs()
320 *reg++ = IXGB_GET_STAT(adapter, mpc); /* 101 */ ixgb_get_regs()
321 *reg++ = IXGB_GET_STAT(adapter, tptl); /* 102 */ ixgb_get_regs()
322 *reg++ = IXGB_GET_STAT(adapter, tpth); /* 103 */ ixgb_get_regs()
323 *reg++ = IXGB_GET_STAT(adapter, gptcl); /* 104 */ ixgb_get_regs()
324 *reg++ = IXGB_GET_STAT(adapter, gptch); /* 105 */ ixgb_get_regs()
325 *reg++ = IXGB_GET_STAT(adapter, bptcl); /* 106 */ ixgb_get_regs()
326 *reg++ = IXGB_GET_STAT(adapter, bptch); /* 107 */ ixgb_get_regs()
327 *reg++ = IXGB_GET_STAT(adapter, mptcl); /* 108 */ ixgb_get_regs()
328 *reg++ = IXGB_GET_STAT(adapter, mptch); /* 109 */ ixgb_get_regs()
329 *reg++ = IXGB_GET_STAT(adapter, uptcl); /* 110 */ ixgb_get_regs()
330 *reg++ = IXGB_GET_STAT(adapter, uptch); /* 111 */ ixgb_get_regs()
331 *reg++ = IXGB_GET_STAT(adapter, vptcl); /* 112 */ ixgb_get_regs()
332 *reg++ = IXGB_GET_STAT(adapter, vptch); /* 113 */ ixgb_get_regs()
333 *reg++ = IXGB_GET_STAT(adapter, jptcl); /* 114 */ ixgb_get_regs()
334 *reg++ = IXGB_GET_STAT(adapter, jptch); /* 115 */ ixgb_get_regs()
335 *reg++ = IXGB_GET_STAT(adapter, gotcl); /* 116 */ ixgb_get_regs()
336 *reg++ = IXGB_GET_STAT(adapter, gotch); /* 117 */ ixgb_get_regs()
337 *reg++ = IXGB_GET_STAT(adapter, totl); /* 118 */ ixgb_get_regs()
338 *reg++ = IXGB_GET_STAT(adapter, toth); /* 119 */ ixgb_get_regs()
339 *reg++ = IXGB_GET_STAT(adapter, dc); /* 120 */ ixgb_get_regs()
340 *reg++ = IXGB_GET_STAT(adapter, plt64c); /* 121 */ ixgb_get_regs()
341 *reg++ = IXGB_GET_STAT(adapter, tsctc); /* 122 */ ixgb_get_regs()
342 *reg++ = IXGB_GET_STAT(adapter, tsctfc); /* 123 */ ixgb_get_regs()
343 *reg++ = IXGB_GET_STAT(adapter, ibic); /* 124 */ ixgb_get_regs()
344 *reg++ = IXGB_GET_STAT(adapter, rfc); /* 125 */ ixgb_get_regs()
345 *reg++ = IXGB_GET_STAT(adapter, lfc); /* 126 */ ixgb_get_regs()
346 *reg++ = IXGB_GET_STAT(adapter, pfrc); /* 127 */ ixgb_get_regs()
347 *reg++ = IXGB_GET_STAT(adapter, pftc); /* 128 */ ixgb_get_regs()
348 *reg++ = IXGB_GET_STAT(adapter, mcfrc); /* 129 */ ixgb_get_regs()
349 *reg++ = IXGB_GET_STAT(adapter, mcftc); /* 130 */ ixgb_get_regs()
350 *reg++ = IXGB_GET_STAT(adapter, xonrxc); /* 131 */ ixgb_get_regs()
351 *reg++ = IXGB_GET_STAT(adapter, xontxc); /* 132 */ ixgb_get_regs()
352 *reg++ = IXGB_GET_STAT(adapter, xoffrxc); /* 133 */ ixgb_get_regs()
353 *reg++ = IXGB_GET_STAT(adapter, xofftxc); /* 134 */ ixgb_get_regs()
354 *reg++ = IXGB_GET_STAT(adapter, rjc); /* 135 */ ixgb_get_regs()
356 regs->len = (reg - reg_start) * sizeof(u32); ixgb_get_regs()
/linux-4.1.27/drivers/video/fbdev/savage/
H A Dsavagefb_driver.c121 static void vgaHWRestore(struct savagefb_par *par, struct savage_reg *reg) vgaHWRestore() argument
125 VGAwMISC(reg->MiscOutReg, par); vgaHWRestore()
128 VGAwSEQ(i, reg->Sequencer[i], par); vgaHWRestore()
132 VGAwCR(17, reg->CRTC[17] & ~0x80, par); vgaHWRestore()
135 VGAwCR(i, reg->CRTC[i], par); vgaHWRestore()
138 VGAwGR(i, reg->Graphics[i], par); vgaHWRestore()
143 VGAwATTR(i, reg->Attribute[i], par); vgaHWRestore()
151 struct savage_reg *reg) vgaHWInit()
153 reg->MiscOutReg = 0x23; vgaHWInit()
156 reg->MiscOutReg |= 0x40; vgaHWInit()
159 reg->MiscOutReg |= 0x80; vgaHWInit()
164 reg->Sequencer[0x00] = 0x00; vgaHWInit()
165 reg->Sequencer[0x01] = 0x01; vgaHWInit()
166 reg->Sequencer[0x02] = 0x0F; vgaHWInit()
167 reg->Sequencer[0x03] = 0x00; /* Font select */ vgaHWInit()
168 reg->Sequencer[0x04] = 0x0E; /* Misc */ vgaHWInit()
173 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5; vgaHWInit()
174 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1; vgaHWInit()
175 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1; vgaHWInit()
176 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80; vgaHWInit()
177 reg->CRTC[0x04] = (timings->HSyncStart >> 3); vgaHWInit()
178 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) | vgaHWInit()
180 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF; vgaHWInit()
181 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) | vgaHWInit()
189 reg->CRTC[0x08] = 0x00; vgaHWInit()
190 reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40; vgaHWInit()
193 reg->CRTC[0x09] |= 0x80; vgaHWInit()
195 reg->CRTC[0x0a] = 0x00; vgaHWInit()
196 reg->CRTC[0x0b] = 0x00; vgaHWInit()
197 reg->CRTC[0x0c] = 0x00; vgaHWInit()
198 reg->CRTC[0x0d] = 0x00; vgaHWInit()
199 reg->CRTC[0x0e] = 0x00; vgaHWInit()
200 reg->CRTC[0x0f] = 0x00; vgaHWInit()
201 reg->CRTC[0x10] = timings->VSyncStart & 0xff; vgaHWInit()
202 reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20; vgaHWInit()
203 reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff; vgaHWInit()
204 reg->CRTC[0x13] = var->xres_virtual >> 4; vgaHWInit()
205 reg->CRTC[0x14] = 0x00; vgaHWInit()
206 reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff; vgaHWInit()
207 reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff; vgaHWInit()
208 reg->CRTC[0x17] = 0xc3; vgaHWInit()
209 reg->CRTC[0x18] = 0xff; vgaHWInit()
220 reg->Graphics[0x00] = 0x00; vgaHWInit()
221 reg->Graphics[0x01] = 0x00; vgaHWInit()
222 reg->Graphics[0x02] = 0x00; vgaHWInit()
223 reg->Graphics[0x03] = 0x00; vgaHWInit()
224 reg->Graphics[0x04] = 0x00; vgaHWInit()
225 reg->Graphics[0x05] = 0x40; vgaHWInit()
226 reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */ vgaHWInit()
227 reg->Graphics[0x07] = 0x0F; vgaHWInit()
228 reg->Graphics[0x08] = 0xFF; vgaHWInit()
231 reg->Attribute[0x00] = 0x00; /* standard colormap translation */ vgaHWInit()
232 reg->Attribute[0x01] = 0x01; vgaHWInit()
233 reg->Attribute[0x02] = 0x02; vgaHWInit()
234 reg->Attribute[0x03] = 0x03; vgaHWInit()
235 reg->Attribute[0x04] = 0x04; vgaHWInit()
236 reg->Attribute[0x05] = 0x05; vgaHWInit()
237 reg->Attribute[0x06] = 0x06; vgaHWInit()
238 reg->Attribute[0x07] = 0x07; vgaHWInit()
239 reg->Attribute[0x08] = 0x08; vgaHWInit()
240 reg->Attribute[0x09] = 0x09; vgaHWInit()
241 reg->Attribute[0x0a] = 0x0A; vgaHWInit()
242 reg->Attribute[0x0b] = 0x0B; vgaHWInit()
243 reg->Attribute[0x0c] = 0x0C; vgaHWInit()
244 reg->Attribute[0x0d] = 0x0D; vgaHWInit()
245 reg->Attribute[0x0e] = 0x0E; vgaHWInit()
246 reg->Attribute[0x0f] = 0x0F; vgaHWInit()
247 reg->Attribute[0x10] = 0x41; vgaHWInit()
248 reg->Attribute[0x11] = 0xFF; vgaHWInit()
249 reg->Attribute[0x12] = 0x0F; vgaHWInit()
250 reg->Attribute[0x13] = 0x00; vgaHWInit()
251 reg->Attribute[0x14] = 0x00; vgaHWInit()
544 static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg) savage_get_default_par() argument
574 reg->SR08 = vga_in8(0x3c5, par); savage_get_default_par()
579 reg->CR31 = vga_in8(0x3d5, par); savage_get_default_par()
581 reg->CR32 = vga_in8(0x3d5, par); savage_get_default_par()
583 reg->CR34 = vga_in8(0x3d5, par); savage_get_default_par()
585 reg->CR36 = vga_in8(0x3d5, par); savage_get_default_par()
587 reg->CR3A = vga_in8(0x3d5, par); savage_get_default_par()
589 reg->CR40 = vga_in8(0x3d5, par); savage_get_default_par()
591 reg->CR42 = vga_in8(0x3d5, par); savage_get_default_par()
593 reg->CR45 = vga_in8(0x3d5, par); savage_get_default_par()
595 reg->CR50 = vga_in8(0x3d5, par); savage_get_default_par()
597 reg->CR51 = vga_in8(0x3d5, par); savage_get_default_par()
599 reg->CR53 = vga_in8(0x3d5, par); savage_get_default_par()
601 reg->CR58 = vga_in8(0x3d5, par); savage_get_default_par()
603 reg->CR60 = vga_in8(0x3d5, par); savage_get_default_par()
605 reg->CR66 = vga_in8(0x3d5, par); savage_get_default_par()
607 reg->CR67 = vga_in8(0x3d5, par); savage_get_default_par()
609 reg->CR68 = vga_in8(0x3d5, par); savage_get_default_par()
611 reg->CR69 = vga_in8(0x3d5, par); savage_get_default_par()
613 reg->CR6F = vga_in8(0x3d5, par); savage_get_default_par()
616 reg->CR33 = vga_in8(0x3d5, par); savage_get_default_par()
618 reg->CR86 = vga_in8(0x3d5, par); savage_get_default_par()
620 reg->CR88 = vga_in8(0x3d5, par); savage_get_default_par()
622 reg->CR90 = vga_in8(0x3d5, par); savage_get_default_par()
624 reg->CR91 = vga_in8(0x3d5, par); savage_get_default_par()
626 reg->CRB0 = vga_in8(0x3d5, par) | 0x80; savage_get_default_par()
630 reg->CR3B = vga_in8(0x3d5, par); savage_get_default_par()
632 reg->CR3C = vga_in8(0x3d5, par); savage_get_default_par()
634 reg->CR43 = vga_in8(0x3d5, par); savage_get_default_par()
636 reg->CR5D = vga_in8(0x3d5, par); savage_get_default_par()
638 reg->CR5E = vga_in8(0x3d5, par); savage_get_default_par()
640 reg->CR65 = vga_in8(0x3d5, par); savage_get_default_par()
644 reg->SR0E = vga_in8(0x3c5, par); savage_get_default_par()
646 reg->SR0F = vga_in8(0x3c5, par); savage_get_default_par()
648 reg->SR10 = vga_in8(0x3c5, par); savage_get_default_par()
650 reg->SR11 = vga_in8(0x3c5, par); savage_get_default_par()
652 reg->SR12 = vga_in8(0x3c5, par); savage_get_default_par()
654 reg->SR13 = vga_in8(0x3c5, par); savage_get_default_par()
656 reg->SR29 = vga_in8(0x3c5, par); savage_get_default_par()
659 reg->SR15 = vga_in8(0x3c5, par); savage_get_default_par()
661 reg->SR30 = vga_in8(0x3c5, par); savage_get_default_par()
663 reg->SR18 = vga_in8(0x3c5, par); savage_get_default_par()
671 reg->SR54[i] = vga_in8(0x3c5, par); savage_get_default_par()
684 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par); savage_get_default_par()
685 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par); savage_get_default_par()
686 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par); savage_get_default_par()
687 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par); savage_get_default_par()
697 struct savage_reg *reg) savage_set_default_par()
727 vga_out8(0x3c5, reg->SR08, par); savage_set_default_par()
732 vga_out8(0x3d5, reg->CR31, par); savage_set_default_par()
734 vga_out8(0x3d5, reg->CR32, par); savage_set_default_par()
736 vga_out8(0x3d5, reg->CR34, par); savage_set_default_par()
738 vga_out8(0x3d5,reg->CR36, par); savage_set_default_par()
740 vga_out8(0x3d5, reg->CR3A, par); savage_set_default_par()
742 vga_out8(0x3d5, reg->CR40, par); savage_set_default_par()
744 vga_out8(0x3d5, reg->CR42, par); savage_set_default_par()
746 vga_out8(0x3d5, reg->CR45, par); savage_set_default_par()
748 vga_out8(0x3d5, reg->CR50, par); savage_set_default_par()
750 vga_out8(0x3d5, reg->CR51, par); savage_set_default_par()
752 vga_out8(0x3d5, reg->CR53, par); savage_set_default_par()
754 vga_out8(0x3d5, reg->CR58, par); savage_set_default_par()
756 vga_out8(0x3d5, reg->CR60, par); savage_set_default_par()
758 vga_out8(0x3d5, reg->CR66, par); savage_set_default_par()
760 vga_out8(0x3d5, reg->CR67, par); savage_set_default_par()
762 vga_out8(0x3d5, reg->CR68, par); savage_set_default_par()
764 vga_out8(0x3d5, reg->CR69, par); savage_set_default_par()
766 vga_out8(0x3d5, reg->CR6F, par); savage_set_default_par()
769 vga_out8(0x3d5, reg->CR33, par); savage_set_default_par()
771 vga_out8(0x3d5, reg->CR86, par); savage_set_default_par()
773 vga_out8(0x3d5, reg->CR88, par); savage_set_default_par()
775 vga_out8(0x3d5, reg->CR90, par); savage_set_default_par()
777 vga_out8(0x3d5, reg->CR91, par); savage_set_default_par()
779 vga_out8(0x3d5, reg->CRB0, par); savage_set_default_par()
783 vga_out8(0x3d5, reg->CR3B, par); savage_set_default_par()
785 vga_out8(0x3d5, reg->CR3C, par); savage_set_default_par()
787 vga_out8(0x3d5, reg->CR43, par); savage_set_default_par()
789 vga_out8(0x3d5, reg->CR5D, par); savage_set_default_par()
791 vga_out8(0x3d5, reg->CR5E, par); savage_set_default_par()
793 vga_out8(0x3d5, reg->CR65, par); savage_set_default_par()
797 vga_out8(0x3c5, reg->SR0E, par); savage_set_default_par()
799 vga_out8(0x3c5, reg->SR0F, par); savage_set_default_par()
801 vga_out8(0x3c5, reg->SR10, par); savage_set_default_par()
803 vga_out8(0x3c5, reg->SR11, par); savage_set_default_par()
805 vga_out8(0x3c5, reg->SR12, par); savage_set_default_par()
807 vga_out8(0x3c5, reg->SR13, par); savage_set_default_par()
809 vga_out8(0x3c5, reg->SR29, par); savage_set_default_par()
812 vga_out8(0x3c5, reg->SR15, par); savage_set_default_par()
814 vga_out8(0x3c5, reg->SR30, par); savage_set_default_par()
816 vga_out8(0x3c5, reg->SR18, par); savage_set_default_par()
824 vga_out8(0x3c5, reg->SR54[i], par); savage_set_default_par()
837 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par); savage_set_default_par()
838 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par); savage_set_default_par()
839 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par); savage_set_default_par()
840 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par); savage_set_default_par()
975 struct savage_reg *reg) savagefb_decode_var()
1017 vgaHWInit(var, par, &timings, reg); savagefb_decode_var()
1022 reg->CR67 = 0x00; savagefb_decode_var()
1027 reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */ savagefb_decode_var()
1029 reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */ savagefb_decode_var()
1034 reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */ savagefb_decode_var()
1036 reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */ savagefb_decode_var()
1041 reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */ savagefb_decode_var()
1043 reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */ savagefb_decode_var()
1046 reg->CR67 = 0x70; savagefb_decode_var()
1049 reg->CR67 = 0xd0; savagefb_decode_var()
1061 reg->CR3A = (tmp & 0x7f) | 0x15; savagefb_decode_var()
1063 reg->CR3A = tmp | 0x95; savagefb_decode_var()
1065 reg->CR53 = 0x00; savagefb_decode_var()
1066 reg->CR31 = 0x8c; savagefb_decode_var()
1067 reg->CR66 = 0x89; savagefb_decode_var()
1070 reg->CR58 = vga_in8(0x3d5, par) & 0x80; savagefb_decode_var()
1071 reg->CR58 |= 0x13; savagefb_decode_var()
1073 reg->SR15 = 0x03 | 0x80; savagefb_decode_var()
1074 reg->SR18 = 0x00; savagefb_decode_var()
1075 reg->CR43 = reg->CR45 = reg->CR65 = 0x00; savagefb_decode_var()
1078 reg->CR40 = vga_in8(0x3d5, par) & ~0x01; savagefb_decode_var()
1080 reg->MMPR0 = 0x010400; savagefb_decode_var()
1081 reg->MMPR1 = 0x00; savagefb_decode_var()
1082 reg->MMPR2 = 0x0808; savagefb_decode_var()
1083 reg->MMPR3 = 0x08080810; savagefb_decode_var()
1089 reg->SR10 = 255; savagefb_decode_var()
1090 reg->SR11 = 255; savagefb_decode_var()
1093 &reg->SR11, &reg->SR10); savagefb_decode_var()
1094 /* reg->SR10 = 80; // MCLK == 286000 */ savagefb_decode_var()
1095 /* reg->SR11 = 125; */ savagefb_decode_var()
1098 reg->SR12 = (r << 6) | (n & 0x3f); savagefb_decode_var()
1099 reg->SR13 = m & 0xff; savagefb_decode_var()
1100 reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2; savagefb_decode_var()
1103 reg->MMPR0 -= 0x8000; savagefb_decode_var()
1105 reg->MMPR0 -= 0x4000; savagefb_decode_var()
1108 reg->CR42 = 0x20; savagefb_decode_var()
1110 reg->CR42 = 0x00; savagefb_decode_var()
1112 reg->CR34 = 0x10; /* display fifo */ savagefb_decode_var()
1124 j = (reg->CRTC[0] + ((i & 0x01) << 8) + savagefb_decode_var()
1125 reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2; savagefb_decode_var()
1127 if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) { savagefb_decode_var()
1128 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <= savagefb_decode_var()
1129 reg->CRTC[0] + ((i & 0x01) << 8)) savagefb_decode_var()
1130 j = reg->CRTC[4] + ((i & 0x10) << 4) + 4; savagefb_decode_var()
1132 j = reg->CRTC[0] + ((i & 0x01) << 8) + 1; savagefb_decode_var()
1135 reg->CR3B = j & 0xff; savagefb_decode_var()
1137 reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2; savagefb_decode_var()
1138 reg->CR5D = i; savagefb_decode_var()
1139 reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) | savagefb_decode_var()
1144 reg->CR91 = reg->CRTC[19] = 0xff & width; savagefb_decode_var()
1145 reg->CR51 = (0x300 & width) >> 4; savagefb_decode_var()
1146 reg->CR90 = 0x80 | (width >> 8); savagefb_decode_var()
1147 reg->MiscOutReg |= 0x0c; savagefb_decode_var()
1152 reg->CR50 = 0; savagefb_decode_var()
1154 reg->CR50 = 0x10; savagefb_decode_var()
1156 reg->CR50 = 0x30; savagefb_decode_var()
1159 reg->CR50 |= 0x40; savagefb_decode_var()
1161 reg->CR50 |= 0x80; savagefb_decode_var()
1163 reg->CR50 |= 0x00; savagefb_decode_var()
1165 reg->CR50 |= 0x01; savagefb_decode_var()
1167 reg->CR50 |= 0xc0; savagefb_decode_var()
1169 reg->CR50 |= 0x81; savagefb_decode_var()
1171 reg->CR50 |= 0xc1; /* Use GBD */ savagefb_decode_var()
1174 reg->CR33 = 0x08; savagefb_decode_var()
1176 reg->CR33 = 0x20; savagefb_decode_var()
1178 reg->CRTC[0x17] = 0xeb; savagefb_decode_var()
1180 reg->CR67 |= 1; savagefb_decode_var()
1183 reg->CR36 = vga_in8(0x3d5, par); savagefb_decode_var()
1185 reg->CR68 = vga_in8(0x3d5, par); savagefb_decode_var()
1186 reg->CR69 = 0; savagefb_decode_var()
1188 reg->CR6F = vga_in8(0x3d5, par); savagefb_decode_var()
1190 reg->CR86 = vga_in8(0x3d5, par); savagefb_decode_var()
1192 reg->CR88 = vga_in8(0x3d5, par) | 0x08; savagefb_decode_var()
1194 reg->CRB0 = vga_in8(0x3d5, par) | 0x80; savagefb_decode_var()
1261 static void savagefb_set_par_int(struct savagefb_par *par, struct savage_reg *reg) savagefb_set_par_int() argument
1296 vga_out8(0x3d5, reg->CR66, par); savagefb_set_par_int()
1298 vga_out8(0x3d5, reg->CR3A, par); savagefb_set_par_int()
1300 vga_out8(0x3d5, reg->CR31, par); savagefb_set_par_int()
1302 vga_out8(0x3d5, reg->CR32, par); savagefb_set_par_int()
1304 vga_out8(0x3d5, reg->CR58, par); savagefb_set_par_int()
1306 vga_out8(0x3d5, reg->CR53 & 0x7f, par); savagefb_set_par_int()
1313 vga_out8(0x3c5, reg->SR0E, par); savagefb_set_par_int()
1315 vga_out8(0x3c5, reg->SR0F, par); savagefb_set_par_int()
1317 vga_out8(0x3c5, reg->SR29, par); savagefb_set_par_int()
1319 vga_out8(0x3c5, reg->SR15, par); savagefb_set_par_int()
1327 vga_out8(0x3c5, reg->SR54[i], par); savagefb_set_par_int()
1331 vgaHWRestore (par, reg); savagefb_set_par_int()
1335 vga_out8(0x3d5, reg->CR53, par); savagefb_set_par_int()
1337 vga_out8(0x3d5, reg->CR5D, par); savagefb_set_par_int()
1339 vga_out8(0x3d5, reg->CR5E, par); savagefb_set_par_int()
1341 vga_out8(0x3d5, reg->CR3B, par); savagefb_set_par_int()
1343 vga_out8(0x3d5, reg->CR3C, par); savagefb_set_par_int()
1345 vga_out8(0x3d5, reg->CR43, par); savagefb_set_par_int()
1347 vga_out8(0x3d5, reg->CR65, par); savagefb_set_par_int()
1357 vga_out8(0x3d5, reg->CR67 & ~0x0c, par); savagefb_set_par_int()
1361 vga_out8(0x3d5, reg->CR34, par); savagefb_set_par_int()
1363 vga_out8(0x3d5, reg->CR40, par); savagefb_set_par_int()
1365 vga_out8(0x3d5, reg->CR42, par); savagefb_set_par_int()
1367 vga_out8(0x3d5, reg->CR45, par); savagefb_set_par_int()
1369 vga_out8(0x3d5, reg->CR50, par); savagefb_set_par_int()
1371 vga_out8(0x3d5, reg->CR51, par); savagefb_set_par_int()
1375 vga_out8(0x3d5, reg->CR36, par); savagefb_set_par_int()
1377 vga_out8(0x3d5, reg->CR60, par); savagefb_set_par_int()
1379 vga_out8(0x3d5, reg->CR68, par); savagefb_set_par_int()
1381 vga_out8(0x3d5, reg->CR69, par); savagefb_set_par_int()
1383 vga_out8(0x3d5, reg->CR6F, par); savagefb_set_par_int()
1386 vga_out8(0x3d5, reg->CR33, par); savagefb_set_par_int()
1388 vga_out8(0x3d5, reg->CR86, par); savagefb_set_par_int()
1390 vga_out8(0x3d5, reg->CR88, par); savagefb_set_par_int()
1392 vga_out8(0x3d5, reg->CR90, par); savagefb_set_par_int()
1394 vga_out8(0x3d5, reg->CR91, par); savagefb_set_par_int()
1398 vga_out8(0x3d5, reg->CRB0, par); savagefb_set_par_int()
1402 vga_out8(0x3d5, reg->CR32, par); savagefb_set_par_int()
1411 if (reg->SR10 != 255) { savagefb_set_par_int()
1413 vga_out8(0x3c5, reg->SR10, par); savagefb_set_par_int()
1415 vga_out8(0x3c5, reg->SR11, par); savagefb_set_par_int()
1420 vga_out8(0x3c5, reg->SR0E, par); savagefb_set_par_int()
1422 vga_out8(0x3c5, reg->SR0F, par); savagefb_set_par_int()
1424 vga_out8(0x3c5, reg->SR12, par); savagefb_set_par_int()
1426 vga_out8(0x3c5, reg->SR13, par); savagefb_set_par_int()
1428 vga_out8(0x3c5, reg->SR29, par); savagefb_set_par_int()
1430 vga_out8(0x3c5, reg->SR18, par); savagefb_set_par_int()
1439 vga_out8(0x3c5, reg->SR15, par); savagefb_set_par_int()
1443 vga_out8(0x3c5, reg->SR30, par); savagefb_set_par_int()
1445 vga_out8(0x3c5, reg->SR08, par); savagefb_set_par_int()
1450 vga_out8(0x3d5, reg->CR67, par); savagefb_set_par_int()
1461 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par); savagefb_set_par_int()
1463 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par); savagefb_set_par_int()
1465 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par); savagefb_set_par_int()
1467 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par); savagefb_set_par_int()
148 vgaHWInit(struct fb_var_screeninfo *var, struct savagefb_par *par, struct xtimings *timings, struct savage_reg *reg) vgaHWInit() argument
696 savage_set_default_par(struct savagefb_par *par, struct savage_reg *reg) savage_set_default_par() argument
973 savagefb_decode_var(struct fb_var_screeninfo *var, struct savagefb_par *par, struct savage_reg *reg) savagefb_decode_var() argument
/linux-4.1.27/fs/ocfs2/cluster/
H A Dheartbeat.c290 struct o2hb_region *reg = o2hb_write_timeout() local
295 "milliseconds\n", reg->hr_dev_name, o2hb_write_timeout()
296 jiffies_to_msecs(jiffies - reg->hr_last_timeout_start)); o2hb_write_timeout()
300 if (test_bit(reg->hr_region_num, o2hb_quorum_region_bitmap)) o2hb_write_timeout()
301 set_bit(reg->hr_region_num, o2hb_failed_region_bitmap); o2hb_write_timeout()
322 static void o2hb_arm_write_timeout(struct o2hb_region *reg) o2hb_arm_write_timeout() argument
325 if (atomic_read(&reg->hr_steady_iterations) != 0) o2hb_arm_write_timeout()
333 clear_bit(reg->hr_region_num, o2hb_failed_region_bitmap); o2hb_arm_write_timeout()
336 cancel_delayed_work(&reg->hr_write_timeout_work); o2hb_arm_write_timeout()
337 reg->hr_last_timeout_start = jiffies; o2hb_arm_write_timeout()
338 schedule_delayed_work(&reg->hr_write_timeout_work, o2hb_arm_write_timeout()
342 static void o2hb_disarm_write_timeout(struct o2hb_region *reg) o2hb_disarm_write_timeout() argument
344 cancel_delayed_work_sync(&reg->hr_write_timeout_work); o2hb_disarm_write_timeout()
368 static void o2hb_wait_on_io(struct o2hb_region *reg, o2hb_wait_on_io() argument
391 static struct bio *o2hb_setup_one_bio(struct o2hb_region *reg, o2hb_setup_one_bio() argument
398 unsigned int bits = reg->hr_block_bits; o2hb_setup_one_bio()
399 unsigned int spp = reg->hr_slots_per_page; o2hb_setup_one_bio()
416 bio->bi_iter.bi_sector = (reg->hr_start_block + cs) << (bits - 9); o2hb_setup_one_bio()
417 bio->bi_bdev = reg->hr_bdev; o2hb_setup_one_bio()
424 page = reg->hr_slot_data[current_page]; o2hb_setup_one_bio()
444 static int o2hb_read_slots(struct o2hb_region *reg, o2hb_read_slots() argument
455 bio = o2hb_setup_one_bio(reg, &wc, &current_slot, max_slots); o2hb_read_slots()
469 o2hb_wait_on_io(reg, &wc); o2hb_read_slots()
476 static int o2hb_issue_node_write(struct o2hb_region *reg, o2hb_issue_node_write() argument
487 bio = o2hb_setup_one_bio(reg, write_wc, &slot, slot+1); o2hb_issue_node_write()
502 static u32 o2hb_compute_block_crc_le(struct o2hb_region *reg, o2hb_compute_block_crc_le() argument
514 ret = crc32_le(0, (unsigned char *) hb_block, reg->hr_block_bytes); o2hb_compute_block_crc_le()
530 static int o2hb_verify_crc(struct o2hb_region *reg, o2hb_verify_crc() argument
536 computed = o2hb_compute_block_crc_le(reg, hb_block); o2hb_verify_crc()
548 static int o2hb_check_own_slot(struct o2hb_region *reg) o2hb_check_own_slot() argument
554 slot = &reg->hr_slots[o2nm_this_node()]; o2hb_check_own_slot()
578 "ondisk(%u:0x%llx, 0x%llx)\n", errstr, reg->hr_dev_name, o2hb_check_own_slot()
587 static inline void o2hb_prepare_block(struct o2hb_region *reg, o2hb_prepare_block() argument
596 slot = &reg->hr_slots[node_num]; o2hb_prepare_block()
599 memset(hb_block, 0, reg->hr_block_bytes); o2hb_prepare_block()
611 hb_block->hb_cksum = cpu_to_le32(o2hb_compute_block_crc_le(reg, o2hb_prepare_block()
724 static void o2hb_set_quorum_device(struct o2hb_region *reg) o2hb_set_quorum_device() argument
734 if (atomic_read(&reg->hr_steady_iterations) != 0) o2hb_set_quorum_device()
739 if (test_bit(reg->hr_region_num, o2hb_quorum_region_bitmap)) o2hb_set_quorum_device()
747 if (memcmp(reg->hr_live_node_bitmap, o2hb_live_node_bitmap, o2hb_set_quorum_device()
752 config_item_name(&reg->hr_item), reg->hr_dev_name); o2hb_set_quorum_device()
754 set_bit(reg->hr_region_num, o2hb_quorum_region_bitmap); o2hb_set_quorum_device()
767 static int o2hb_check_slot(struct o2hb_region *reg, o2hb_check_slot() argument
774 struct o2hb_disk_heartbeat_block *hb_block = reg->hr_tmp_block; o2hb_check_slot()
781 memcpy(hb_block, slot->ds_raw_block, reg->hr_block_bytes); o2hb_check_slot()
796 if (!o2hb_verify_crc(reg, hb_block)) { o2hb_check_slot()
811 slot->ds_node_num, reg->hr_dev_name); o2hb_check_slot()
861 set_bit(slot->ds_node_num, reg->hr_live_node_bitmap); o2hb_check_slot()
894 slot->ds_node_num, reg->hr_dev_name, slot_dead_ms, o2hb_check_slot()
911 clear_bit(slot->ds_node_num, reg->hr_live_node_bitmap); o2hb_check_slot()
954 static int o2hb_do_disk_heartbeat(struct o2hb_region *reg) o2hb_do_disk_heartbeat() argument
991 ret = o2hb_read_slots(reg, highest_node + 1); o2hb_do_disk_heartbeat()
1000 own_slot_ok = o2hb_check_own_slot(reg); o2hb_do_disk_heartbeat()
1003 o2hb_prepare_block(reg, reg->hr_generation); o2hb_do_disk_heartbeat()
1005 ret = o2hb_issue_node_write(reg, &write_wc); o2hb_do_disk_heartbeat()
1014 membership_change |= o2hb_check_slot(reg, &reg->hr_slots[i]); o2hb_do_disk_heartbeat()
1022 o2hb_wait_on_io(reg, &write_wc); o2hb_do_disk_heartbeat()
1028 write_wc.wc_error, reg->hr_dev_name); o2hb_do_disk_heartbeat()
1035 o2hb_set_quorum_device(reg); o2hb_do_disk_heartbeat()
1036 o2hb_arm_write_timeout(reg); o2hb_do_disk_heartbeat()
1041 if (atomic_read(&reg->hr_steady_iterations) != 0) { o2hb_do_disk_heartbeat()
1043 if (atomic_dec_and_test(&reg->hr_steady_iterations)) o2hb_do_disk_heartbeat()
1048 if (atomic_read(&reg->hr_steady_iterations) != 0) { o2hb_do_disk_heartbeat()
1049 if (atomic_dec_and_test(&reg->hr_unsteady_iterations)) { o2hb_do_disk_heartbeat()
1052 config_item_name(&reg->hr_item), o2hb_do_disk_heartbeat()
1053 reg->hr_dev_name); o2hb_do_disk_heartbeat()
1054 atomic_set(&reg->hr_steady_iterations, 0); o2hb_do_disk_heartbeat()
1055 reg->hr_aborted_start = 1; o2hb_do_disk_heartbeat()
1103 struct o2hb_region *reg = data; o2hb_thread() local
1116 !reg->hr_unclean_stop && !reg->hr_aborted_start) { o2hb_thread()
1124 ret = o2hb_do_disk_heartbeat(reg); o2hb_thread()
1136 elapsed_msec < reg->hr_timeout_ms) { o2hb_thread()
1139 msleep_interruptible(reg->hr_timeout_ms - elapsed_msec); o2hb_thread()
1143 o2hb_disarm_write_timeout(reg); o2hb_thread()
1146 for(i = 0; !reg->hr_unclean_stop && i < reg->hr_blocks; i++) o2hb_thread()
1147 o2hb_shutdown_slot(&reg->hr_slots[i]); o2hb_thread()
1154 if (!reg->hr_unclean_stop && !reg->hr_aborted_start) { o2hb_thread()
1155 o2hb_prepare_block(reg, 0); o2hb_thread()
1156 ret = o2hb_issue_node_write(reg, &write_wc); o2hb_thread()
1158 o2hb_wait_on_io(reg, &write_wc); o2hb_thread()
1175 struct o2hb_region *reg; o2hb_debug_open() local
1201 reg = (struct o2hb_region *)db->db_data; o2hb_debug_open()
1202 memcpy(map, reg->hr_live_node_bitmap, db->db_size); o2hb_debug_open()
1207 reg = (struct o2hb_region *)db->db_data; o2hb_debug_open()
1209 reg->hr_region_num); o2hb_debug_open()
1213 reg = (struct o2hb_region *)db->db_data; o2hb_debug_open()
1214 lts = reg->hr_last_timeout_start; o2hb_debug_open()
1222 reg = (struct o2hb_region *)db->db_data; o2hb_debug_open()
1224 !!reg->hr_item_pinned); o2hb_debug_open()
1446 struct o2hb_region *reg = to_o2hb_region(item); o2hb_region_release() local
1448 mlog(ML_HEARTBEAT, "hb region release (%s)\n", reg->hr_dev_name); o2hb_region_release()
1450 kfree(reg->hr_tmp_block); o2hb_region_release()
1452 if (reg->hr_slot_data) { o2hb_region_release()
1453 for (i = 0; i < reg->hr_num_pages; i++) { o2hb_region_release()
1454 page = reg->hr_slot_data[i]; o2hb_region_release()
1458 kfree(reg->hr_slot_data); o2hb_region_release()
1461 if (reg->hr_bdev) o2hb_region_release()
1462 blkdev_put(reg->hr_bdev, FMODE_READ|FMODE_WRITE); o2hb_region_release()
1464 kfree(reg->hr_slots); o2hb_region_release()
1466 kfree(reg->hr_db_regnum); o2hb_region_release()
1467 kfree(reg->hr_db_livenodes); o2hb_region_release()
1468 debugfs_remove(reg->hr_debug_livenodes); o2hb_region_release()
1469 debugfs_remove(reg->hr_debug_regnum); o2hb_region_release()
1470 debugfs_remove(reg->hr_debug_elapsed_time); o2hb_region_release()
1471 debugfs_remove(reg->hr_debug_pinned); o2hb_region_release()
1472 debugfs_remove(reg->hr_debug_dir); o2hb_region_release()
1475 list_del(&reg->hr_all_item); o2hb_region_release()
1478 kfree(reg); o2hb_region_release()
1481 static int o2hb_read_block_input(struct o2hb_region *reg, o2hb_read_block_input() argument
1508 static ssize_t o2hb_region_block_bytes_read(struct o2hb_region *reg, o2hb_region_block_bytes_read() argument
1511 return sprintf(page, "%u\n", reg->hr_block_bytes); o2hb_region_block_bytes_read()
1514 static ssize_t o2hb_region_block_bytes_write(struct o2hb_region *reg, o2hb_region_block_bytes_write() argument
1522 if (reg->hr_bdev) o2hb_region_block_bytes_write()
1525 status = o2hb_read_block_input(reg, page, count, o2hb_region_block_bytes_write()
1530 reg->hr_block_bytes = (unsigned int)block_bytes; o2hb_region_block_bytes_write()
1531 reg->hr_block_bits = block_bits; o2hb_region_block_bytes_write()
1536 static ssize_t o2hb_region_start_block_read(struct o2hb_region *reg, o2hb_region_start_block_read() argument
1539 return sprintf(page, "%llu\n", reg->hr_start_block); o2hb_region_start_block_read()
1542 static ssize_t o2hb_region_start_block_write(struct o2hb_region *reg, o2hb_region_start_block_write() argument
1549 if (reg->hr_bdev) o2hb_region_start_block_write()
1556 reg->hr_start_block = tmp; o2hb_region_start_block_write()
1561 static ssize_t o2hb_region_blocks_read(struct o2hb_region *reg, o2hb_region_blocks_read() argument
1564 return sprintf(page, "%d\n", reg->hr_blocks); o2hb_region_blocks_read()
1567 static ssize_t o2hb_region_blocks_write(struct o2hb_region *reg, o2hb_region_blocks_write() argument
1574 if (reg->hr_bdev) o2hb_region_blocks_write()
1584 reg->hr_blocks = (unsigned int)tmp; o2hb_region_blocks_write()
1589 static ssize_t o2hb_region_dev_read(struct o2hb_region *reg, o2hb_region_dev_read() argument
1594 if (reg->hr_bdev) o2hb_region_dev_read()
1595 ret = sprintf(page, "%s\n", reg->hr_dev_name); o2hb_region_dev_read()
1600 static void o2hb_init_region_params(struct o2hb_region *reg) o2hb_init_region_params() argument
1602 reg->hr_slots_per_page = PAGE_CACHE_SIZE >> reg->hr_block_bits; o2hb_init_region_params()
1603 reg->hr_timeout_ms = O2HB_REGION_TIMEOUT_MS; o2hb_init_region_params()
1606 reg->hr_start_block, reg->hr_blocks); o2hb_init_region_params()
1608 reg->hr_block_bytes, reg->hr_block_bits); o2hb_init_region_params()
1609 mlog(ML_HEARTBEAT, "hr_timeout_ms = %u\n", reg->hr_timeout_ms); o2hb_init_region_params()
1613 static int o2hb_map_slot_data(struct o2hb_region *reg) o2hb_map_slot_data() argument
1617 unsigned int spp = reg->hr_slots_per_page; o2hb_map_slot_data()
1622 reg->hr_tmp_block = kmalloc(reg->hr_block_bytes, GFP_KERNEL); o2hb_map_slot_data()
1623 if (reg->hr_tmp_block == NULL) { o2hb_map_slot_data()
1628 reg->hr_slots = kcalloc(reg->hr_blocks, o2hb_map_slot_data()
1630 if (reg->hr_slots == NULL) { o2hb_map_slot_data()
1635 for(i = 0; i < reg->hr_blocks; i++) { o2hb_map_slot_data()
1636 slot = &reg->hr_slots[i]; o2hb_map_slot_data()
1642 reg->hr_num_pages = (reg->hr_blocks + spp - 1) / spp; o2hb_map_slot_data()
1645 reg->hr_num_pages, reg->hr_blocks, spp); o2hb_map_slot_data()
1647 reg->hr_slot_data = kcalloc(reg->hr_num_pages, sizeof(struct page *), o2hb_map_slot_data()
1649 if (!reg->hr_slot_data) { o2hb_map_slot_data()
1654 for(i = 0; i < reg->hr_num_pages; i++) { o2hb_map_slot_data()
1661 reg->hr_slot_data[i] = page; o2hb_map_slot_data()
1666 (j < spp) && ((j + last_slot) < reg->hr_blocks); o2hb_map_slot_data()
1668 BUG_ON((j + last_slot) >= reg->hr_blocks); o2hb_map_slot_data()
1670 slot = &reg->hr_slots[j + last_slot]; o2hb_map_slot_data()
1674 raw += reg->hr_block_bytes; o2hb_map_slot_data()
1684 static int o2hb_populate_slot_data(struct o2hb_region *reg) o2hb_populate_slot_data() argument
1690 ret = o2hb_read_slots(reg, reg->hr_blocks); o2hb_populate_slot_data()
1700 for(i = 0; i < reg->hr_blocks; i++) { o2hb_populate_slot_data()
1701 slot = &reg->hr_slots[i]; o2hb_populate_slot_data()
1715 static ssize_t o2hb_region_dev_write(struct o2hb_region *reg, o2hb_region_dev_write() argument
1728 if (reg->hr_bdev) o2hb_region_dev_write()
1747 if (reg->hr_blocks == 0 || reg->hr_start_block == 0 || o2hb_region_dev_write()
1748 reg->hr_block_bytes == 0) o2hb_region_dev_write()
1758 reg->hr_bdev = I_BDEV(f.file->f_mapping->host); o2hb_region_dev_write()
1759 ret = blkdev_get(reg->hr_bdev, FMODE_WRITE | FMODE_READ, NULL); o2hb_region_dev_write()
1761 reg->hr_bdev = NULL; o2hb_region_dev_write()
1766 bdevname(reg->hr_bdev, reg->hr_dev_name); o2hb_region_dev_write()
1768 sectsize = bdev_logical_block_size(reg->hr_bdev); o2hb_region_dev_write()
1769 if (sectsize != reg->hr_block_bytes) { o2hb_region_dev_write()
1772 reg->hr_block_bytes, sectsize); o2hb_region_dev_write()
1777 o2hb_init_region_params(reg); o2hb_region_dev_write()
1781 get_random_bytes(&reg->hr_generation, o2hb_region_dev_write()
1782 sizeof(reg->hr_generation)); o2hb_region_dev_write()
1783 } while (reg->hr_generation == 0); o2hb_region_dev_write()
1785 ret = o2hb_map_slot_data(reg); o2hb_region_dev_write()
1791 ret = o2hb_populate_slot_data(reg); o2hb_region_dev_write()
1797 INIT_DELAYED_WORK(&reg->hr_write_timeout_work, o2hb_write_timeout); o2hb_region_dev_write()
1815 atomic_set(&reg->hr_steady_iterations, live_threshold); o2hb_region_dev_write()
1817 atomic_set(&reg->hr_unsteady_iterations, (live_threshold << 1)); o2hb_region_dev_write()
1819 hb_task = kthread_run(o2hb_thread, reg, "o2hb-%s", o2hb_region_dev_write()
1820 reg->hr_item.ci_name); o2hb_region_dev_write()
1828 reg->hr_task = hb_task; o2hb_region_dev_write()
1832 atomic_read(&reg->hr_steady_iterations) == 0); o2hb_region_dev_write()
1834 atomic_set(&reg->hr_steady_iterations, 0); o2hb_region_dev_write()
1835 reg->hr_aborted_start = 1; o2hb_region_dev_write()
1838 if (reg->hr_aborted_start) { o2hb_region_dev_write()
1845 hb_task = reg->hr_task; o2hb_region_dev_write()
1847 set_bit(reg->hr_region_num, o2hb_live_region_bitmap); o2hb_region_dev_write()
1857 config_item_name(&reg->hr_item), reg->hr_dev_name); o2hb_region_dev_write()
1865 if (reg->hr_bdev) { o2hb_region_dev_write()
1866 blkdev_put(reg->hr_bdev, FMODE_READ|FMODE_WRITE); o2hb_region_dev_write()
1867 reg->hr_bdev = NULL; o2hb_region_dev_write()
1873 static ssize_t o2hb_region_pid_read(struct o2hb_region *reg, o2hb_region_pid_read() argument
1879 if (reg->hr_task) o2hb_region_pid_read()
1880 pid = task_pid_nr(reg->hr_task); o2hb_region_pid_read()
1947 struct o2hb_region *reg = to_o2hb_region(item); o2hb_region_show() local
1953 ret = o2hb_region_attr->show(reg, page); o2hb_region_show()
1961 struct o2hb_region *reg = to_o2hb_region(item); o2hb_region_store() local
1967 ret = o2hb_region_attr->store(reg, page, count); o2hb_region_store()
1997 static int o2hb_debug_region_init(struct o2hb_region *reg, struct dentry *dir) o2hb_debug_region_init() argument
2001 reg->hr_debug_dir = o2hb_debug_region_init()
2002 debugfs_create_dir(config_item_name(&reg->hr_item), dir); o2hb_debug_region_init()
2003 if (!reg->hr_debug_dir) { o2hb_debug_region_init()
2008 reg->hr_debug_livenodes = o2hb_debug_region_init()
2010 reg->hr_debug_dir, o2hb_debug_region_init()
2011 &(reg->hr_db_livenodes), o2hb_debug_region_init()
2012 sizeof(*(reg->hr_db_livenodes)), o2hb_debug_region_init()
2014 sizeof(reg->hr_live_node_bitmap), o2hb_debug_region_init()
2015 O2NM_MAX_NODES, reg); o2hb_debug_region_init()
2016 if (!reg->hr_debug_livenodes) { o2hb_debug_region_init()
2021 reg->hr_debug_regnum = o2hb_debug_region_init()
2023 reg->hr_debug_dir, o2hb_debug_region_init()
2024 &(reg->hr_db_regnum), o2hb_debug_region_init()
2025 sizeof(*(reg->hr_db_regnum)), o2hb_debug_region_init()
2027 0, O2NM_MAX_NODES, reg); o2hb_debug_region_init()
2028 if (!reg->hr_debug_regnum) { o2hb_debug_region_init()
2033 reg->hr_debug_elapsed_time = o2hb_debug_region_init()
2035 reg->hr_debug_dir, o2hb_debug_region_init()
2036 &(reg->hr_db_elapsed_time), o2hb_debug_region_init()
2037 sizeof(*(reg->hr_db_elapsed_time)), o2hb_debug_region_init()
2039 0, 0, reg); o2hb_debug_region_init()
2040 if (!reg->hr_debug_elapsed_time) { o2hb_debug_region_init()
2045 reg->hr_debug_pinned = o2hb_debug_region_init()
2047 reg->hr_debug_dir, o2hb_debug_region_init()
2048 &(reg->hr_db_pinned), o2hb_debug_region_init()
2049 sizeof(*(reg->hr_db_pinned)), o2hb_debug_region_init()
2051 0, 0, reg); o2hb_debug_region_init()
2052 if (!reg->hr_debug_pinned) { o2hb_debug_region_init()
2065 struct o2hb_region *reg = NULL; o2hb_heartbeat_group_make_item() local
2068 reg = kzalloc(sizeof(struct o2hb_region), GFP_KERNEL); o2hb_heartbeat_group_make_item()
2069 if (reg == NULL) o2hb_heartbeat_group_make_item()
2078 reg->hr_region_num = 0; o2hb_heartbeat_group_make_item()
2080 reg->hr_region_num = find_first_zero_bit(o2hb_region_bitmap, o2hb_heartbeat_group_make_item()
2082 if (reg->hr_region_num >= O2NM_MAX_REGIONS) { o2hb_heartbeat_group_make_item()
2087 set_bit(reg->hr_region_num, o2hb_region_bitmap); o2hb_heartbeat_group_make_item()
2089 list_add_tail(&reg->hr_all_item, &o2hb_all_regions); o2hb_heartbeat_group_make_item()
2092 config_item_init_type_name(&reg->hr_item, name, &o2hb_region_type); o2hb_heartbeat_group_make_item()
2094 ret = o2hb_debug_region_init(reg, o2hb_debug_dir); o2hb_heartbeat_group_make_item()
2096 config_item_put(&reg->hr_item); o2hb_heartbeat_group_make_item()
2100 return &reg->hr_item; o2hb_heartbeat_group_make_item()
2102 kfree(reg); o2hb_heartbeat_group_make_item()
2110 struct o2hb_region *reg = to_o2hb_region(item); o2hb_heartbeat_group_drop_item() local
2115 hb_task = reg->hr_task; o2hb_heartbeat_group_drop_item()
2116 reg->hr_task = NULL; o2hb_heartbeat_group_drop_item()
2117 reg->hr_item_dropped = 1; o2hb_heartbeat_group_drop_item()
2125 clear_bit(reg->hr_region_num, o2hb_region_bitmap); o2hb_heartbeat_group_drop_item()
2126 clear_bit(reg->hr_region_num, o2hb_live_region_bitmap); o2hb_heartbeat_group_drop_item()
2127 if (test_bit(reg->hr_region_num, o2hb_quorum_region_bitmap)) o2hb_heartbeat_group_drop_item()
2129 clear_bit(reg->hr_region_num, o2hb_quorum_region_bitmap); o2hb_heartbeat_group_drop_item()
2132 ((atomic_read(&reg->hr_steady_iterations) == 0) ? o2hb_heartbeat_group_drop_item()
2134 reg->hr_dev_name); o2hb_heartbeat_group_drop_item()
2139 * check reg->hr_task o2hb_heartbeat_group_drop_item()
2141 if (atomic_read(&reg->hr_steady_iterations) != 0) { o2hb_heartbeat_group_drop_item()
2142 reg->hr_aborted_start = 1; o2hb_heartbeat_group_drop_item()
2143 atomic_set(&reg->hr_steady_iterations, 0); o2hb_heartbeat_group_drop_item()
2179 struct o2hb_heartbeat_group *reg = to_o2hb_heartbeat_group(to_config_group(item)); o2hb_heartbeat_group_show() local
2185 ret = o2hb_heartbeat_group_attr->show(reg, page); o2hb_heartbeat_group_show()
2193 struct o2hb_heartbeat_group *reg = to_o2hb_heartbeat_group(to_config_group(item)); o2hb_heartbeat_group_store() local
2199 ret = o2hb_heartbeat_group_attr->store(reg, page, count); o2hb_heartbeat_group_store()
2362 struct o2hb_region *reg; o2hb_region_pin() local
2367 list_for_each_entry(reg, &o2hb_all_regions, hr_all_item) { o2hb_region_pin()
2368 if (reg->hr_item_dropped) o2hb_region_pin()
2371 uuid = config_item_name(&reg->hr_item); o2hb_region_pin()
2380 if (reg->hr_item_pinned || reg->hr_item_dropped) o2hb_region_pin()
2384 ret = o2nm_depend_item(&reg->hr_item); o2hb_region_pin()
2387 reg->hr_item_pinned = 1; o2hb_region_pin()
2414 struct o2hb_region *reg; o2hb_region_unpin() local
2420 list_for_each_entry(reg, &o2hb_all_regions, hr_all_item) { o2hb_region_unpin()
2421 if (reg->hr_item_dropped) o2hb_region_unpin()
2424 uuid = config_item_name(&reg->hr_item); o2hb_region_unpin()
2431 if (reg->hr_item_pinned) { o2hb_region_unpin()
2433 o2nm_undepend_item(&reg->hr_item); o2hb_region_unpin()
2434 reg->hr_item_pinned = 0; o2hb_region_unpin()
2633 struct o2hb_region *reg; o2hb_stop_all_regions() local
2639 list_for_each_entry(reg, &o2hb_all_regions, hr_all_item) o2hb_stop_all_regions()
2640 reg->hr_unclean_stop = 1; o2hb_stop_all_regions()
2648 struct o2hb_region *reg; o2hb_get_all_regions() local
2655 list_for_each_entry(reg, &o2hb_all_regions, hr_all_item) { o2hb_get_all_regions()
2656 if (reg->hr_item_dropped) o2hb_get_all_regions()
2659 mlog(0, "Region: %s\n", config_item_name(&reg->hr_item)); o2hb_get_all_regions()
2661 memcpy(p, config_item_name(&reg->hr_item), o2hb_get_all_regions()
/linux-4.1.27/drivers/scsi/qla4xxx/
H A Dql4_dbg.c47 readw(&ha->reg->mailbox[i])); qla4xxx_dump_registers()
52 readw(&ha->reg->flash_address)); qla4xxx_dump_registers()
55 readw(&ha->reg->flash_data)); qla4xxx_dump_registers()
58 readw(&ha->reg->ctrl_status)); qla4xxx_dump_registers()
63 readw(&ha->reg->u1.isp4010.nvram)); qla4xxx_dump_registers()
67 readw(&ha->reg->u1.isp4022.intr_mask)); qla4xxx_dump_registers()
70 readw(&ha->reg->u1.isp4022.nvram)); qla4xxx_dump_registers()
73 readw(&ha->reg->u1.isp4022.semaphore)); qla4xxx_dump_registers()
77 readw(&ha->reg->req_q_in)); qla4xxx_dump_registers()
80 readw(&ha->reg->rsp_q_out)); qla4xxx_dump_registers()
85 readw(&ha->reg->u2.isp4010.ext_hw_conf)); qla4xxx_dump_registers()
88 readw(&ha->reg->u2.isp4010.port_ctrl)); qla4xxx_dump_registers()
91 readw(&ha->reg->u2.isp4010.port_status)); qla4xxx_dump_registers()
94 readw(&ha->reg->u2.isp4010.req_q_out)); qla4xxx_dump_registers()
97 readw(&ha->reg->u2.isp4010.gp_out)); qla4xxx_dump_registers()
100 readw(&ha->reg->u2.isp4010.gp_in)); qla4xxx_dump_registers()
103 readw(&ha->reg->u2.isp4010.port_err_status)); qla4xxx_dump_registers()
108 readw(&ha->reg->u2.isp4022.p0.ext_hw_conf)); qla4xxx_dump_registers()
111 readw(&ha->reg->u2.isp4022.p0.port_ctrl)); qla4xxx_dump_registers()
114 readw(&ha->reg->u2.isp4022.p0.port_status)); qla4xxx_dump_registers()
117 readw(&ha->reg->u2.isp4022.p0.gp_out)); qla4xxx_dump_registers()
120 readw(&ha->reg->u2.isp4022.p0.gp_in)); qla4xxx_dump_registers()
123 readw(&ha->reg->u2.isp4022.p0.port_err_status)); qla4xxx_dump_registers()
126 &ha->reg->ctrl_status); qla4xxx_dump_registers()
129 readw(&ha->reg->u2.isp4022.p1.req_q_out)); qla4xxx_dump_registers()
131 &ha->reg->ctrl_status); qla4xxx_dump_registers()
/linux-4.1.27/arch/powerpc/kernel/
H A Dudbg_16550.c46 static u8 (*udbg_uart_in)(unsigned int reg);
47 static void (*udbg_uart_out)(unsigned int reg, u8 data);
169 static u8 udbg_uart_in_pio(unsigned int reg) udbg_uart_in_pio() argument
171 return inb(udbg_uart.pio_base + (reg * udbg_uart_stride)); udbg_uart_in_pio()
174 static void udbg_uart_out_pio(unsigned int reg, u8 data) udbg_uart_out_pio() argument
176 outb(data, udbg_uart.pio_base + (reg * udbg_uart_stride)); udbg_uart_out_pio()
190 static u8 udbg_uart_in_mmio(unsigned int reg) udbg_uart_in_mmio() argument
192 return in_8(udbg_uart.mmio_base + (reg * udbg_uart_stride)); udbg_uart_in_mmio()
195 static void udbg_uart_out_mmio(unsigned int reg, u8 data) udbg_uart_out_mmio() argument
197 out_8(udbg_uart.mmio_base + (reg * udbg_uart_stride), data); udbg_uart_out_mmio()
216 static u8 udbg_uart_in_maple(unsigned int reg) udbg_uart_in_maple() argument
218 return real_readb(UDBG_UART_MAPLE_ADDR + reg); udbg_uart_in_maple()
221 static void udbg_uart_out_maple(unsigned int reg, u8 val) udbg_uart_out_maple() argument
223 real_writeb(val, UDBG_UART_MAPLE_ADDR + reg); udbg_uart_out_maple()
239 static u8 udbg_uart_in_pas(unsigned int reg) udbg_uart_in_pas() argument
241 return real_205_readb(UDBG_UART_PAS_ADDR + reg); udbg_uart_in_pas()
244 static void udbg_uart_out_pas(unsigned int reg, u8 val) udbg_uart_out_pas() argument
246 real_205_writeb(val, UDBG_UART_PAS_ADDR + reg); udbg_uart_out_pas()
262 static u8 udbg_uart_in_44x_as1(unsigned int reg) udbg_uart_in_44x_as1() argument
264 return as1_readb((void __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR + reg); udbg_uart_in_44x_as1()
267 static void udbg_uart_out_44x_as1(unsigned int reg, u8 val) udbg_uart_out_44x_as1() argument
269 as1_writeb(val, (void __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR + reg); udbg_uart_out_44x_as1() local
283 static u8 udbg_uart_in_40x(unsigned int reg) udbg_uart_in_40x() argument
286 + reg); udbg_uart_in_40x()
289 static void udbg_uart_out_40x(unsigned int reg, u8 val) udbg_uart_out_40x() argument
292 + reg); udbg_uart_out_40x() local
/linux-4.1.27/drivers/net/ethernet/intel/i40e/
H A Di40e_diag.c33 * @reg: reg to be tested
37 u32 reg, u32 mask) i40e_diag_reg_pattern_test()
43 orig_val = rd32(hw, reg); i40e_diag_reg_pattern_test()
46 wr32(hw, reg, (pat & mask)); i40e_diag_reg_pattern_test()
47 val = rd32(hw, reg); i40e_diag_reg_pattern_test()
50 "%s: reg pattern test failed - reg 0x%08x pat 0x%08x val 0x%08x\n", i40e_diag_reg_pattern_test()
51 __func__, reg, pat, val); i40e_diag_reg_pattern_test()
56 wr32(hw, reg, orig_val); i40e_diag_reg_pattern_test()
57 val = rd32(hw, reg); i40e_diag_reg_pattern_test()
60 "%s: reg restore test failed - reg 0x%08x orig_val 0x%08x val 0x%08x\n", i40e_diag_reg_pattern_test()
61 __func__, reg, orig_val, val); i40e_diag_reg_pattern_test()
101 u32 reg, mask; i40e_diag_reg_test() local
107 /* set actual reg range for dynamically allocated resources */ i40e_diag_reg_test()
123 reg = i40e_reg_list[i].offset + i40e_diag_reg_test()
125 ret_code = i40e_diag_reg_pattern_test(hw, reg, mask); i40e_diag_reg_test()
36 i40e_diag_reg_pattern_test(struct i40e_hw *hw, u32 reg, u32 mask) i40e_diag_reg_pattern_test() argument
/linux-4.1.27/arch/mips/loongson/common/cs5536/
H A Dcs5536_pci.c59 void cs5536_pci_conf_write4(int function, int reg, u32 value) cs5536_pci_conf_write4() argument
63 if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0)) cs5536_pci_conf_write4()
67 vsm_conf_write[function](reg, value); cs5536_pci_conf_write4()
73 u32 cs5536_pci_conf_read4(int function, int reg) cs5536_pci_conf_read4() argument
79 if ((reg < 0) || ((reg & 0x03) != 0)) cs5536_pci_conf_read4()
81 if (reg > 0x100) cs5536_pci_conf_read4()
85 data = vsm_conf_read[function](reg); cs5536_pci_conf_read4()
/linux-4.1.27/arch/c6x/include/asm/
H A Dspecial_insns.h15 #define get_creg(reg) \
17 asm volatile ("mvc .s2 " #reg ",%0\n" : "=b"(__x)); __x; })
19 #define set_creg(reg, v) \
21 asm volatile ("mvc .s2 %0," #reg "\n" : : "b"(__x)); \
24 #define or_creg(reg, n) \
26 asm volatile ("mvc .s2 " #reg ",%0\n" \
28 "mvc .s2 %0," #reg "\n" \
33 #define and_creg(reg, n) \
35 asm volatile ("mvc .s2 " #reg ",%0\n" \
37 "mvc .s2 %0," #reg "\n" \
/linux-4.1.27/arch/powerpc/boot/
H A Debony.c26 #include "reg.h"
41 u32 reg[3] = {0x0, 0x0, 0x80000}; ebony_flashsel_fixup() local
49 if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga)) ebony_flashsel_fixup()
50 fatal("%s has missing or invalid virtual-reg property\n\r", ebony_flashsel_fixup()
60 if (getprop(devp, "reg", reg, sizeof(reg)) != sizeof(reg)) ebony_flashsel_fixup()
61 fatal("%s has reg property of unexpected size\n\r", ebony_flashsel_fixup()
66 reg[1] ^= 0x80000; ebony_flashsel_fixup()
68 setprop(devp, "reg", reg, sizeof(reg)); ebony_flashsel_fixup()
H A Duartlite.c40 u32 reg = ULITE_STATUS_TXFULL; uartlite_putc() local
41 while (reg & ULITE_STATUS_TXFULL) /* spin on TXFULL bit */ uartlite_putc()
42 reg = in_be32(reg_base + ULITE_STATUS); uartlite_putc()
48 u32 reg = 0; uartlite_getc() local
49 while (!(reg & ULITE_STATUS_RXVALID)) /* spin waiting for RXVALID bit */ uartlite_getc()
50 reg = in_be32(reg_base + ULITE_STATUS); uartlite_getc()
56 u32 reg = in_be32(reg_base + ULITE_STATUS); uartlite_tstc() local
57 return reg & ULITE_STATUS_RXVALID; uartlite_tstc()
65 n = getprop(devp, "virtual-reg", &reg_base, sizeof(reg_base)); uartlite_console_init()
H A Dwii.c107 u32 reg[4]; platform_fixups() local
117 len = getprop(mem, "reg", reg, sizeof(reg)); platform_fixups()
118 if (len != sizeof(reg)) { platform_fixups()
130 if (mem2_boundary > reg[2] && mem2_boundary < reg[2] + reg[3]) { platform_fixups()
131 reg[3] = mem2_boundary - reg[2]; platform_fixups()
132 printf("top of MEM2 @ %08X\n", reg[2] + reg[3]); platform_fixups()
133 setprop(mem, "reg", reg, sizeof(reg)); platform_fixups()
/linux-4.1.27/arch/ia64/kernel/
H A Dcyclone.c39 u64 __iomem *reg; init_cyclone_clock() local
52 reg = ioremap_nocache(offset, sizeof(u64)); init_cyclone_clock()
53 if(!reg){ init_cyclone_clock()
59 base = readq(reg); init_cyclone_clock()
60 iounmap(reg); init_cyclone_clock()
70 reg = ioremap_nocache(offset, sizeof(u64)); init_cyclone_clock()
71 if(!reg){ init_cyclone_clock()
77 writel(0x00000001,reg); init_cyclone_clock()
78 iounmap(reg); init_cyclone_clock()
82 reg = ioremap_nocache(offset, sizeof(u64)); init_cyclone_clock()
83 if(!reg){ init_cyclone_clock()
89 writel(0x00000001,reg); init_cyclone_clock()
90 iounmap(reg); init_cyclone_clock()
/linux-4.1.27/sound/soc/tegra/
H A Dtegra30_ahub.c36 static inline void tegra30_apbif_write(u32 reg, u32 val) tegra30_apbif_write() argument
38 regmap_write(ahub->regmap_apbif, reg, val); tegra30_apbif_write()
41 static inline u32 tegra30_apbif_read(u32 reg) tegra30_apbif_read() argument
44 regmap_read(ahub->regmap_apbif, reg, &val); tegra30_apbif_read()
48 static inline void tegra30_audio_write(u32 reg, u32 val) tegra30_audio_write() argument
50 regmap_write(ahub->regmap_ahub, reg, val); tegra30_audio_write()
102 u32 reg, val; tegra30_ahub_allocate_rx_fifo() local
119 reg = TEGRA30_AHUB_CHANNEL_CTRL + tegra30_ahub_allocate_rx_fifo()
121 val = tegra30_apbif_read(reg); tegra30_ahub_allocate_rx_fifo()
127 tegra30_apbif_write(reg, val); tegra30_ahub_allocate_rx_fifo()
141 reg = TEGRA30_AHUB_CIF_RX_CTRL + tegra30_ahub_allocate_rx_fifo()
143 ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); tegra30_ahub_allocate_rx_fifo()
154 int reg, val; tegra30_ahub_enable_rx_fifo() local
158 reg = TEGRA30_AHUB_CHANNEL_CTRL + tegra30_ahub_enable_rx_fifo()
160 val = tegra30_apbif_read(reg); tegra30_ahub_enable_rx_fifo()
162 tegra30_apbif_write(reg, val); tegra30_ahub_enable_rx_fifo()
173 int reg, val; tegra30_ahub_disable_rx_fifo() local
177 reg = TEGRA30_AHUB_CHANNEL_CTRL + tegra30_ahub_disable_rx_fifo()
179 val = tegra30_apbif_read(reg); tegra30_ahub_disable_rx_fifo()
181 tegra30_apbif_write(reg, val); tegra30_ahub_disable_rx_fifo()
204 u32 reg, val; tegra30_ahub_allocate_tx_fifo() local
221 reg = TEGRA30_AHUB_CHANNEL_CTRL + tegra30_ahub_allocate_tx_fifo()
223 val = tegra30_apbif_read(reg); tegra30_ahub_allocate_tx_fifo()
229 tegra30_apbif_write(reg, val); tegra30_ahub_allocate_tx_fifo()
243 reg = TEGRA30_AHUB_CIF_TX_CTRL + tegra30_ahub_allocate_tx_fifo()
245 ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); tegra30_ahub_allocate_tx_fifo()
256 int reg, val; tegra30_ahub_enable_tx_fifo() local
260 reg = TEGRA30_AHUB_CHANNEL_CTRL + tegra30_ahub_enable_tx_fifo()
262 val = tegra30_apbif_read(reg); tegra30_ahub_enable_tx_fifo()
264 tegra30_apbif_write(reg, val); tegra30_ahub_enable_tx_fifo()
275 int reg, val; tegra30_ahub_disable_tx_fifo() local
279 reg = TEGRA30_AHUB_CHANNEL_CTRL + tegra30_ahub_disable_tx_fifo()
281 val = tegra30_apbif_read(reg); tegra30_ahub_disable_tx_fifo()
283 tegra30_apbif_write(reg, val); tegra30_ahub_disable_tx_fifo()
305 int reg; tegra30_ahub_set_rx_cif_source() local
309 reg = TEGRA30_AHUB_AUDIO_RX + tegra30_ahub_set_rx_cif_source()
311 tegra30_audio_write(reg, 1 << txcif); tegra30_ahub_set_rx_cif_source()
322 int reg; tegra30_ahub_unset_rx_cif_source() local
326 reg = TEGRA30_AHUB_AUDIO_RX + tegra30_ahub_unset_rx_cif_source()
328 tegra30_audio_write(reg, 0); tegra30_ahub_unset_rx_cif_source()
375 #define REG_IN_ARRAY(reg, name) \
376 ((reg >= TEGRA30_AHUB_##name) && \
377 (reg <= LAST_REG(name) && \
378 (!((reg - TEGRA30_AHUB_##name) % TEGRA30_AHUB_##name##_STRIDE))))
380 static bool tegra30_ahub_apbif_wr_rd_reg(struct device *dev, unsigned int reg) tegra30_ahub_apbif_wr_rd_reg() argument
382 switch (reg) { tegra30_ahub_apbif_wr_rd_reg()
409 if (REG_IN_ARRAY(reg, CHANNEL_CTRL) || tegra30_ahub_apbif_wr_rd_reg()
410 REG_IN_ARRAY(reg, CHANNEL_CLEAR) || tegra30_ahub_apbif_wr_rd_reg()
411 REG_IN_ARRAY(reg, CHANNEL_STATUS) || tegra30_ahub_apbif_wr_rd_reg()
412 REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || tegra30_ahub_apbif_wr_rd_reg()
413 REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || tegra30_ahub_apbif_wr_rd_reg()
414 REG_IN_ARRAY(reg, CIF_TX_CTRL) || tegra30_ahub_apbif_wr_rd_reg()
415 REG_IN_ARRAY(reg, CIF_RX_CTRL) || tegra30_ahub_apbif_wr_rd_reg()
416 REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) tegra30_ahub_apbif_wr_rd_reg()
423 unsigned int reg) tegra30_ahub_apbif_volatile_reg()
425 switch (reg) { tegra30_ahub_apbif_volatile_reg()
444 if (REG_IN_ARRAY(reg, CHANNEL_CLEAR) || tegra30_ahub_apbif_volatile_reg()
445 REG_IN_ARRAY(reg, CHANNEL_STATUS) || tegra30_ahub_apbif_volatile_reg()
446 REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || tegra30_ahub_apbif_volatile_reg()
447 REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || tegra30_ahub_apbif_volatile_reg()
448 REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) tegra30_ahub_apbif_volatile_reg()
455 unsigned int reg) tegra30_ahub_apbif_precious_reg()
457 if (REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || tegra30_ahub_apbif_precious_reg()
458 REG_IN_ARRAY(reg, CHANNEL_RXFIFO)) tegra30_ahub_apbif_precious_reg()
477 static bool tegra30_ahub_ahub_wr_rd_reg(struct device *dev, unsigned int reg) tegra30_ahub_ahub_wr_rd_reg() argument
479 if (REG_IN_ARRAY(reg, AUDIO_RX)) tegra30_ahub_ahub_wr_rd_reg()
732 void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg, tegra30_ahub_set_cif() argument
760 regmap_write(regmap, reg, value); tegra30_ahub_set_cif()
764 void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg, tegra124_ahub_set_cif() argument
792 regmap_write(regmap, reg, value); tegra124_ahub_set_cif()
422 tegra30_ahub_apbif_volatile_reg(struct device *dev, unsigned int reg) tegra30_ahub_apbif_volatile_reg() argument
454 tegra30_ahub_apbif_precious_reg(struct device *dev, unsigned int reg) tegra30_ahub_apbif_precious_reg() argument
/linux-4.1.27/arch/powerpc/lib/
H A Dldstfp.S16 #include <asm/reg.h>
31 reg = 0 define
33 20: \op reg,0,r4
36 reg = reg + 1 define
47 reg = 1 define
49 fmr fr0,reg
51 reg = reg + 1 define
66 reg = 1 define
68 fmr reg,fr0
70 reg = reg + 1 define
78 /* Load FP reg N from float at *p. N is in r3, p in r4. */
105 /* Load FP reg N from double at *p. N is in r3, p in r4. */
132 /* Store FP reg N to float at *p. N is in r3, p in r4. */
159 /* Store FP reg N to double at *p. N is in r3, p in r4. */
194 reg = 1 define
196 vor v0,reg,reg /* assembler doesn't know vmr? */
198 reg = reg + 1 define
213 reg = 1 define
215 vor reg,v0,v0
217 reg = reg + 1 define
225 /* Load vector reg N from *p. N is in r3, p in r4. */
253 /* Store vector reg N to *p. N is in r3, p in r4. */
290 reg = 1 define
292 XXLOR(0,reg,reg)
294 reg = reg + 1 define
309 reg = 1 define
311 XXLOR(reg,0,0)
313 reg = reg + 1 define
321 /* Load VSX reg N from vector doubleword *p. N is in r3, p in r4. */
349 /* Store VSX reg N to vector doubleword *p. N is in r3, p in r4. */
/linux-4.1.27/sound/pci/oxygen/
H A Doxygen_io.c28 u8 oxygen_read8(struct oxygen *chip, unsigned int reg) oxygen_read8() argument
30 return inb(chip->addr + reg); oxygen_read8()
34 u16 oxygen_read16(struct oxygen *chip, unsigned int reg) oxygen_read16() argument
36 return inw(chip->addr + reg); oxygen_read16()
40 u32 oxygen_read32(struct oxygen *chip, unsigned int reg) oxygen_read32() argument
42 return inl(chip->addr + reg); oxygen_read32()
46 void oxygen_write8(struct oxygen *chip, unsigned int reg, u8 value) oxygen_write8() argument
48 outb(value, chip->addr + reg); oxygen_write8()
49 chip->saved_registers._8[reg] = value; oxygen_write8()
53 void oxygen_write16(struct oxygen *chip, unsigned int reg, u16 value) oxygen_write16() argument
55 outw(value, chip->addr + reg); oxygen_write16()
56 chip->saved_registers._16[reg / 2] = cpu_to_le16(value); oxygen_write16()
60 void oxygen_write32(struct oxygen *chip, unsigned int reg, u32 value) oxygen_write32() argument
62 outl(value, chip->addr + reg); oxygen_write32()
63 chip->saved_registers._32[reg / 4] = cpu_to_le32(value); oxygen_write32()
67 void oxygen_write8_masked(struct oxygen *chip, unsigned int reg, oxygen_write8_masked() argument
70 u8 tmp = inb(chip->addr + reg); oxygen_write8_masked()
73 outb(tmp, chip->addr + reg); oxygen_write8_masked()
74 chip->saved_registers._8[reg] = tmp; oxygen_write8_masked()
78 void oxygen_write16_masked(struct oxygen *chip, unsigned int reg, oxygen_write16_masked() argument
81 u16 tmp = inw(chip->addr + reg); oxygen_write16_masked()
84 outw(tmp, chip->addr + reg); oxygen_write16_masked()
85 chip->saved_registers._16[reg / 2] = cpu_to_le16(tmp); oxygen_write16_masked()
89 void oxygen_write32_masked(struct oxygen *chip, unsigned int reg, oxygen_write32_masked() argument
92 u32 tmp = inl(chip->addr + reg); oxygen_write32_masked()
95 outl(tmp, chip->addr + reg); oxygen_write32_masked()
96 chip->saved_registers._32[reg / 4] = cpu_to_le32(tmp); oxygen_write32_masked()
133 u32 reg; oxygen_write_ac97() local
135 reg = data; oxygen_write_ac97()
136 reg |= index << OXYGEN_AC97_REG_ADDR_SHIFT; oxygen_write_ac97()
137 reg |= OXYGEN_AC97_REG_DIR_WRITE; oxygen_write_ac97()
138 reg |= codec << OXYGEN_AC97_REG_CODEC_SHIFT; oxygen_write_ac97()
142 oxygen_write32(chip, OXYGEN_AC97_REGS, reg); oxygen_write_ac97()
159 u32 reg; oxygen_read_ac97() local
161 reg = index << OXYGEN_AC97_REG_ADDR_SHIFT; oxygen_read_ac97()
162 reg |= OXYGEN_AC97_REG_DIR_READ; oxygen_read_ac97()
163 reg |= codec << OXYGEN_AC97_REG_CODEC_SHIFT; oxygen_read_ac97()
166 oxygen_write32(chip, OXYGEN_AC97_REGS, reg); oxygen_read_ac97()
179 reg ^= 0xffff; oxygen_read_ac97()
/linux-4.1.27/drivers/watchdog/
H A Dwm8350_wdt.c44 u16 reg; wm8350_wdt_set_timeout() local
55 reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2); wm8350_wdt_set_timeout()
56 reg &= ~WM8350_WDOG_TO_MASK; wm8350_wdt_set_timeout()
57 reg |= wm8350_wdt_cfgs[i].val; wm8350_wdt_set_timeout()
58 ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg); wm8350_wdt_set_timeout()
71 u16 reg; wm8350_wdt_start() local
76 reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2); wm8350_wdt_start()
77 reg &= ~WM8350_WDOG_MODE_MASK; wm8350_wdt_start()
78 reg |= 0x20; wm8350_wdt_start()
79 ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg); wm8350_wdt_start()
91 u16 reg; wm8350_wdt_stop() local
96 reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2); wm8350_wdt_stop()
97 reg &= ~WM8350_WDOG_MODE_MASK; wm8350_wdt_stop()
98 ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg); wm8350_wdt_stop()
110 u16 reg; wm8350_wdt_ping() local
114 reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2); wm8350_wdt_ping()
115 ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg); wm8350_wdt_ping()
/linux-4.1.27/arch/unicore32/include/mach/
H A Dregs-unigfx.h9 * command reg for UNIGFX DE
12 * control reg UDE_CFG
16 * framebuffer start address reg UDE_FSA
20 * line size reg UDE_LS
24 * pitch size reg UDE_PS
28 * horizontal active time reg UDE_HAT
32 * horizontal blank time reg UDE_HBT
36 * horizontal sync time reg UDE_HST
40 * vertival active time reg UDE_VAT
44 * vertival blank time reg UDE_VBT
48 * vertival sync time reg UDE_VST
68 * video start address reg UDE_VSA
72 * video size reg UDE_VS
77 * command reg for UNIGFX GE
80 * src xy reg UGE_SRCXY
84 * dst xy reg UGE_DSTXY
88 * pitch reg UGE_PITCH
92 * src start reg UGE_SRCSTART
96 * dst start reg UGE_DSTSTART
100 * width height reg UGE_WIDHEIGHT
104 * rop alpah reg UGE_ROPALPHA
132 * clip 0 reg UGE_CLIP0
136 * clip 1 reg UGE_CLIP1
140 * command reg UGE_COMMAND
/linux-4.1.27/arch/arm/mach-ebsa110/
H A Dleds.c22 u8 reg = __raw_readb(SOFT_BASE); ebsa110_led_set() local
25 reg |= 0x80; ebsa110_led_set()
27 reg &= ~0x80; ebsa110_led_set()
29 __raw_writeb(reg, SOFT_BASE); ebsa110_led_set()
34 u8 reg = __raw_readb(SOFT_BASE); ebsa110_led_get() local
36 return (reg & 0x80) ? LED_FULL : LED_OFF; ebsa110_led_get()
/linux-4.1.27/sound/synth/emux/
H A Demux_proc.c69 vp->reg.parm.moddelay, snd_emux_proc_info_read()
70 vp->reg.parm.modatkhld, snd_emux_proc_info_read()
71 vp->reg.parm.moddcysus, snd_emux_proc_info_read()
72 vp->reg.parm.modrelease); snd_emux_proc_info_read()
74 vp->reg.parm.voldelay, snd_emux_proc_info_read()
75 vp->reg.parm.volatkhld, snd_emux_proc_info_read()
76 vp->reg.parm.voldcysus, snd_emux_proc_info_read()
77 vp->reg.parm.volrelease); snd_emux_proc_info_read()
79 vp->reg.parm.lfo1delay, snd_emux_proc_info_read()
80 vp->reg.parm.lfo2delay, snd_emux_proc_info_read()
81 vp->reg.parm.pefe); snd_emux_proc_info_read()
83 vp->reg.parm.fmmod, snd_emux_proc_info_read()
84 vp->reg.parm.tremfrq, snd_emux_proc_info_read()
85 vp->reg.parm.fm2frq2); snd_emux_proc_info_read()
87 vp->reg.parm.cutoff, snd_emux_proc_info_read()
88 vp->reg.parm.filterQ, snd_emux_proc_info_read()
89 vp->reg.parm.chorus, snd_emux_proc_info_read()
90 vp->reg.parm.reverb); snd_emux_proc_info_read()
99 vp->reg.start, vp->reg.end, vp->reg.loopstart, vp->reg.loopend); snd_emux_proc_info_read()
100 snd_iprintf(buf, "sample_mode=%x, rate=%x\n", vp->reg.sample_mode, vp->reg.rate_offset); snd_emux_proc_info_read()
/linux-4.1.27/drivers/clk/mvebu/
H A Dclk-corediv.c57 void __iomem *reg; member in struct:clk_corediv
83 return !!(readl(corediv->reg) & enable_mask); clk_corediv_is_enabled()
92 u32 reg; clk_corediv_enable() local
96 reg = readl(corediv->reg); clk_corediv_enable()
97 reg |= (BIT(desc->fieldbit) << soc_desc->enable_bit_offset); clk_corediv_enable()
98 writel(reg, corediv->reg); clk_corediv_enable()
111 u32 reg; clk_corediv_disable() local
115 reg = readl(corediv->reg); clk_corediv_disable()
116 reg &= ~(BIT(desc->fieldbit) << soc_desc->enable_bit_offset); clk_corediv_disable()
117 writel(reg, corediv->reg); clk_corediv_disable()
128 u32 reg, div; clk_corediv_recalc_rate() local
130 reg = readl(corediv->reg + soc_desc->ratio_offset); clk_corediv_recalc_rate()
131 div = (reg >> desc->offset) & desc->mask; clk_corediv_recalc_rate()
157 u32 reg, div; clk_corediv_set_rate() local
164 reg = readl(corediv->reg + soc_desc->ratio_offset); clk_corediv_set_rate()
165 reg &= ~(desc->mask << desc->offset); clk_corediv_set_rate()
166 reg |= (div & desc->mask) << desc->offset; clk_corediv_set_rate()
167 writel(reg, corediv->reg + soc_desc->ratio_offset); clk_corediv_set_rate()
170 reg = readl(corediv->reg) | BIT(desc->fieldbit); clk_corediv_set_rate()
171 writel(reg, corediv->reg); clk_corediv_set_rate()
174 reg = readl(corediv->reg) | soc_desc->ratio_reload; clk_corediv_set_rate()
175 writel(reg, corediv->reg); clk_corediv_set_rate()
182 reg &= ~(CORE_CLK_DIV_RATIO_MASK | soc_desc->ratio_reload); clk_corediv_set_rate()
183 writel(reg, corediv->reg); clk_corediv_set_rate()
279 corediv[i].reg = base; mvebu_corediv_clk_init()
H A Dclk-cpu.c53 u32 reg, div; clk_cpu_recalc_rate() local
55 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); clk_cpu_recalc_rate()
56 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; clk_cpu_recalc_rate()
80 u32 reg, div; clk_cpu_off_set_rate() local
84 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) clk_cpu_off_set_rate()
87 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); clk_cpu_off_set_rate()
91 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) clk_cpu_off_set_rate()
93 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); clk_cpu_off_set_rate()
96 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) clk_cpu_off_set_rate()
98 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); clk_cpu_off_set_rate()
102 reg &= ~(reload_mask | 1 << 24); clk_cpu_off_set_rate()
103 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); clk_cpu_off_set_rate()
112 u32 reg; clk_cpu_on_set_rate() local
125 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET); clk_cpu_on_set_rate()
126 fabric_div = (reg >> SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT) & clk_cpu_on_set_rate()
139 reg = readl(cpuclk->pmu_dfs); clk_cpu_on_set_rate()
140 reg &= ~(PMU_DFS_RATIO_MASK << PMU_DFS_RATIO_SHIFT); clk_cpu_on_set_rate()
141 reg |= (target_div << PMU_DFS_RATIO_SHIFT); clk_cpu_on_set_rate()
142 writel(reg, cpuclk->pmu_dfs); clk_cpu_on_set_rate()
144 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); clk_cpu_on_set_rate()
145 reg |= (SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL << clk_cpu_on_set_rate()
147 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); clk_cpu_on_set_rate()
206 err = of_property_read_u32(dn, "reg", &cpu); of_cpu_clk_setup()
/linux-4.1.27/arch/x86/pci/
H A Dce4100.c47 int reg; member in struct:sim_dev_reg
48 void (*init)(struct sim_dev_reg *reg);
49 void (*read)(struct sim_dev_reg *reg, u32 *value);
50 void (*write)(struct sim_dev_reg *reg, u32 value);
55 void (*init)(struct sim_dev_reg *reg);
56 void (*read)(struct sim_dev_reg *reg, u32 value);
57 void (*write)(struct sim_dev_reg *reg, u32 value);
68 static void reg_init(struct sim_dev_reg *reg) reg_init() argument
70 pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4, reg_init()
71 &reg->sim_reg.value); reg_init()
74 static void reg_read(struct sim_dev_reg *reg, u32 *value) reg_read() argument
79 *value = reg->sim_reg.value; reg_read()
83 static void reg_write(struct sim_dev_reg *reg, u32 value) reg_write() argument
88 reg->sim_reg.value = (value & reg->sim_reg.mask) | reg_write()
89 (reg->sim_reg.value & ~reg->sim_reg.mask); reg_write()
93 static void sata_reg_init(struct sim_dev_reg *reg) sata_reg_init() argument
96 &reg->sim_reg.value); sata_reg_init()
97 reg->sim_reg.value += 0x400; sata_reg_init()
100 static void ehci_reg_read(struct sim_dev_reg *reg, u32 *value) ehci_reg_read() argument
102 reg_read(reg, value); ehci_reg_read()
103 if (*value != reg->sim_reg.mask) ehci_reg_read()
107 void sata_revid_init(struct sim_dev_reg *reg) sata_revid_init() argument
109 reg->sim_reg.value = 0x01060100; sata_revid_init()
110 reg->sim_reg.mask = 0; sata_revid_init()
113 static void sata_revid_read(struct sim_dev_reg *reg, u32 *value) sata_revid_read() argument
115 reg_read(reg, value); sata_revid_read()
118 static void reg_noirq_read(struct sim_dev_reg *reg, u32 *value) reg_noirq_read() argument
124 *value = reg->sim_reg.value & 0xfff00ff; reg_noirq_read()
191 static inline void extract_bytes(u32 *value, int reg, int len) extract_bytes() argument
195 *value >>= ((reg & 3) * 8); extract_bytes()
200 int bridge_read(unsigned int devfn, int reg, int len, u32 *value) bridge_read() argument
205 switch (reg) { bridge_read()
239 if (reg == PCI_MEMORY_LIMIT) bridge_read()
269 unsigned int devfn, int reg, int len, u32 *value) ce4100_conf_read()
277 bus1_fixups[i].reg == (reg & ~3) && ce4100_conf_read()
281 extract_bytes(value, reg, len); ce4100_conf_read()
288 !bridge_read(devfn, reg, len, value)) ce4100_conf_read()
291 return pci_direct_conf1.read(seg, bus, devfn, reg, len, value); ce4100_conf_read()
295 unsigned int devfn, int reg, int len, u32 value) ce4100_conf_write()
303 bus1_fixups[i].reg == (reg & ~3) && ce4100_conf_write()
314 ((reg & ~3) == PCI_BASE_ADDRESS_0)) ce4100_conf_write()
317 return pci_direct_conf1.write(seg, bus, devfn, reg, len, value); ce4100_conf_write()
268 ce4100_conf_read(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 *value) ce4100_conf_read() argument
294 ce4100_conf_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value) ce4100_conf_write() argument
/linux-4.1.27/drivers/tty/serial/
H A Dsamsung.h116 #define portaddr(port, reg) ((port)->membase + (reg))
117 #define portaddrl(port, reg) \
118 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
120 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
121 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
123 #define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
124 #define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
/linux-4.1.27/drivers/staging/rtl8188eu/hal/
H A Dbb_cfg.c603 struct bb_reg_def *reg[4]; rtl88e_phy_init_bb_rf_register_definition() local
605 reg[RF_PATH_A] = &(hal_data->PHYRegDef[RF_PATH_A]); rtl88e_phy_init_bb_rf_register_definition()
606 reg[RF_PATH_B] = &(hal_data->PHYRegDef[RF_PATH_B]); rtl88e_phy_init_bb_rf_register_definition()
607 reg[RF_PATH_C] = &(hal_data->PHYRegDef[RF_PATH_C]); rtl88e_phy_init_bb_rf_register_definition()
608 reg[RF_PATH_D] = &(hal_data->PHYRegDef[RF_PATH_D]); rtl88e_phy_init_bb_rf_register_definition()
610 reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW; rtl88e_phy_init_bb_rf_register_definition()
611 reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW; rtl88e_phy_init_bb_rf_register_definition()
612 reg[RF_PATH_C]->rfintfs = rFPGA0_XCD_RFInterfaceSW; rtl88e_phy_init_bb_rf_register_definition()
613 reg[RF_PATH_D]->rfintfs = rFPGA0_XCD_RFInterfaceSW; rtl88e_phy_init_bb_rf_register_definition()
615 reg[RF_PATH_A]->rfintfi = rFPGA0_XAB_RFInterfaceRB; rtl88e_phy_init_bb_rf_register_definition()
616 reg[RF_PATH_B]->rfintfi = rFPGA0_XAB_RFInterfaceRB; rtl88e_phy_init_bb_rf_register_definition()
617 reg[RF_PATH_C]->rfintfi = rFPGA0_XCD_RFInterfaceRB; rtl88e_phy_init_bb_rf_register_definition()
618 reg[RF_PATH_D]->rfintfi = rFPGA0_XCD_RFInterfaceRB; rtl88e_phy_init_bb_rf_register_definition()
620 reg[RF_PATH_A]->rfintfo = rFPGA0_XA_RFInterfaceOE; rtl88e_phy_init_bb_rf_register_definition()
621 reg[RF_PATH_B]->rfintfo = rFPGA0_XB_RFInterfaceOE; rtl88e_phy_init_bb_rf_register_definition()
623 reg[RF_PATH_A]->rfintfe = rFPGA0_XA_RFInterfaceOE; rtl88e_phy_init_bb_rf_register_definition()
624 reg[RF_PATH_B]->rfintfe = rFPGA0_XB_RFInterfaceOE; rtl88e_phy_init_bb_rf_register_definition()
626 reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter; rtl88e_phy_init_bb_rf_register_definition()
627 reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter; rtl88e_phy_init_bb_rf_register_definition()
629 reg[RF_PATH_A]->rfLSSI_Select = rFPGA0_XAB_RFParameter; rtl88e_phy_init_bb_rf_register_definition()
630 reg[RF_PATH_B]->rfLSSI_Select = rFPGA0_XAB_RFParameter; rtl88e_phy_init_bb_rf_register_definition()
631 reg[RF_PATH_C]->rfLSSI_Select = rFPGA0_XCD_RFParameter; rtl88e_phy_init_bb_rf_register_definition()
632 reg[RF_PATH_D]->rfLSSI_Select = rFPGA0_XCD_RFParameter; rtl88e_phy_init_bb_rf_register_definition()
634 reg[RF_PATH_A]->rfTxGainStage = rFPGA0_TxGainStage; rtl88e_phy_init_bb_rf_register_definition()
635 reg[RF_PATH_B]->rfTxGainStage = rFPGA0_TxGainStage; rtl88e_phy_init_bb_rf_register_definition()
636 reg[RF_PATH_C]->rfTxGainStage = rFPGA0_TxGainStage; rtl88e_phy_init_bb_rf_register_definition()
637 reg[RF_PATH_D]->rfTxGainStage = rFPGA0_TxGainStage; rtl88e_phy_init_bb_rf_register_definition()
639 reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; rtl88e_phy_init_bb_rf_register_definition()
640 reg[RF_PATH_B]->rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; rtl88e_phy_init_bb_rf_register_definition()
642 reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; rtl88e_phy_init_bb_rf_register_definition()
643 reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; rtl88e_phy_init_bb_rf_register_definition()
645 reg[RF_PATH_A]->rfSwitchControl = rFPGA0_XAB_SwitchControl; rtl88e_phy_init_bb_rf_register_definition()
646 reg[RF_PATH_B]->rfSwitchControl = rFPGA0_XAB_SwitchControl; rtl88e_phy_init_bb_rf_register_definition()
647 reg[RF_PATH_C]->rfSwitchControl = rFPGA0_XCD_SwitchControl; rtl88e_phy_init_bb_rf_register_definition()
648 reg[RF_PATH_D]->rfSwitchControl = rFPGA0_XCD_SwitchControl; rtl88e_phy_init_bb_rf_register_definition()
650 reg[RF_PATH_A]->rfAGCControl1 = rOFDM0_XAAGCCore1; rtl88e_phy_init_bb_rf_register_definition()
651 reg[RF_PATH_B]->rfAGCControl1 = rOFDM0_XBAGCCore1; rtl88e_phy_init_bb_rf_register_definition()
652 reg[RF_PATH_C]->rfAGCControl1 = rOFDM0_XCAGCCore1; rtl88e_phy_init_bb_rf_register_definition()
653 reg[RF_PATH_D]->rfAGCControl1 = rOFDM0_XDAGCCore1; rtl88e_phy_init_bb_rf_register_definition()
655 reg[RF_PATH_A]->rfAGCControl2 = rOFDM0_XAAGCCore2; rtl88e_phy_init_bb_rf_register_definition()
656 reg[RF_PATH_B]->rfAGCControl2 = rOFDM0_XBAGCCore2; rtl88e_phy_init_bb_rf_register_definition()
657 reg[RF_PATH_C]->rfAGCControl2 = rOFDM0_XCAGCCore2; rtl88e_phy_init_bb_rf_register_definition()
658 reg[RF_PATH_D]->rfAGCControl2 = rOFDM0_XDAGCCore2; rtl88e_phy_init_bb_rf_register_definition()
660 reg[RF_PATH_A]->rfRxIQImbalance = rOFDM0_XARxIQImbalance; rtl88e_phy_init_bb_rf_register_definition()
661 reg[RF_PATH_B]->rfRxIQImbalance = rOFDM0_XBRxIQImbalance; rtl88e_phy_init_bb_rf_register_definition()
662 reg[RF_PATH_C]->rfRxIQImbalance = rOFDM0_XCRxIQImbalance; rtl88e_phy_init_bb_rf_register_definition()
663 reg[RF_PATH_D]->rfRxIQImbalance = rOFDM0_XDRxIQImbalance; rtl88e_phy_init_bb_rf_register_definition()
665 reg[RF_PATH_A]->rfRxAFE = rOFDM0_XARxAFE; rtl88e_phy_init_bb_rf_register_definition()
666 reg[RF_PATH_B]->rfRxAFE = rOFDM0_XBRxAFE; rtl88e_phy_init_bb_rf_register_definition()
667 reg[RF_PATH_C]->rfRxAFE = rOFDM0_XCRxAFE; rtl88e_phy_init_bb_rf_register_definition()
668 reg[RF_PATH_D]->rfRxAFE = rOFDM0_XDRxAFE; rtl88e_phy_init_bb_rf_register_definition()
670 reg[RF_PATH_A]->rfTxIQImbalance = rOFDM0_XATxIQImbalance; rtl88e_phy_init_bb_rf_register_definition()
671 reg[RF_PATH_B]->rfTxIQImbalance = rOFDM0_XBTxIQImbalance; rtl88e_phy_init_bb_rf_register_definition()
672 reg[RF_PATH_C]->rfTxIQImbalance = rOFDM0_XCTxIQImbalance; rtl88e_phy_init_bb_rf_register_definition()
673 reg[RF_PATH_D]->rfTxIQImbalance = rOFDM0_XDTxIQImbalance; rtl88e_phy_init_bb_rf_register_definition()
675 reg[RF_PATH_A]->rfTxAFE = rOFDM0_XATxAFE; rtl88e_phy_init_bb_rf_register_definition()
676 reg[RF_PATH_B]->rfTxAFE = rOFDM0_XBTxAFE; rtl88e_phy_init_bb_rf_register_definition()
677 reg[RF_PATH_C]->rfTxAFE = rOFDM0_XCTxAFE; rtl88e_phy_init_bb_rf_register_definition()
678 reg[RF_PATH_D]->rfTxAFE = rOFDM0_XDTxAFE; rtl88e_phy_init_bb_rf_register_definition()
680 reg[RF_PATH_A]->rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; rtl88e_phy_init_bb_rf_register_definition()
681 reg[RF_PATH_B]->rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; rtl88e_phy_init_bb_rf_register_definition()
682 reg[RF_PATH_C]->rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; rtl88e_phy_init_bb_rf_register_definition()
683 reg[RF_PATH_D]->rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; rtl88e_phy_init_bb_rf_register_definition()
685 reg[RF_PATH_A]->rfLSSIReadBackPi = TransceiverA_HSPI_Readback; rtl88e_phy_init_bb_rf_register_definition()
686 reg[RF_PATH_B]->rfLSSIReadBackPi = TransceiverB_HSPI_Readback; rtl88e_phy_init_bb_rf_register_definition()
/linux-4.1.27/drivers/md/
H A Ddm-region-hash.c134 void *dm_rh_region_context(struct dm_region *reg) dm_rh_region_context() argument
136 return reg->rh->context; dm_rh_region_context()
140 region_t dm_rh_get_region_key(struct dm_region *reg) dm_rh_get_region_key() argument
142 return reg->key; dm_rh_get_region_key()
238 struct dm_region *reg, *nreg; dm_region_hash_destroy() local
242 list_for_each_entry_safe(reg, nreg, rh->buckets + h, dm_region_hash_destroy()
244 BUG_ON(atomic_read(&reg->pending)); dm_region_hash_destroy()
245 mempool_free(reg, rh->region_pool); dm_region_hash_destroy()
273 struct dm_region *reg; __rh_lookup() local
276 list_for_each_entry(reg, bucket, hash_list) __rh_lookup()
277 if (reg->key == region) __rh_lookup()
278 return reg; __rh_lookup()
283 static void __rh_insert(struct dm_region_hash *rh, struct dm_region *reg) __rh_insert() argument
285 list_add(&reg->hash_list, rh->buckets + rh_hash(rh, reg->key)); __rh_insert()
290 struct dm_region *reg, *nreg; __rh_alloc() local
305 reg = __rh_lookup(rh, region); __rh_alloc()
306 if (reg) __rh_alloc()
317 reg = nreg; __rh_alloc()
321 return reg; __rh_alloc()
326 struct dm_region *reg; __rh_find() local
328 reg = __rh_lookup(rh, region); __rh_find()
329 if (!reg) { __rh_find()
331 reg = __rh_alloc(rh, region); __rh_find()
335 return reg; __rh_find()
341 struct dm_region *reg; dm_rh_get_state() local
344 reg = __rh_lookup(rh, region); dm_rh_get_state()
347 if (reg) dm_rh_get_state()
348 return reg->state; dm_rh_get_state()
364 static void complete_resync_work(struct dm_region *reg, int success) complete_resync_work() argument
366 struct dm_region_hash *rh = reg->rh; complete_resync_work()
368 rh->log->type->set_region_sync(rh->log, reg->key, success); complete_resync_work()
379 rh->dispatch_bios(rh->context, &reg->delayed_bios); complete_resync_work()
399 struct dm_region *reg; dm_rh_mark_nosync() local
415 reg = __rh_find(rh, region); dm_rh_mark_nosync()
419 BUG_ON(!reg); dm_rh_mark_nosync()
420 BUG_ON(!list_empty(&reg->list)); dm_rh_mark_nosync()
430 recovering = (reg->state == DM_RH_RECOVERING); dm_rh_mark_nosync()
431 reg->state = DM_RH_NOSYNC; dm_rh_mark_nosync()
432 BUG_ON(!list_empty(&reg->list)); dm_rh_mark_nosync()
436 complete_resync_work(reg, 0); dm_rh_mark_nosync()
442 struct dm_region *reg, *next; dm_rh_update_states() local
456 list_for_each_entry(reg, &clean, list) dm_rh_update_states()
457 list_del(&reg->hash_list); dm_rh_update_states()
463 list_for_each_entry(reg, &recovered, list) dm_rh_update_states()
464 list_del(&reg->hash_list); dm_rh_update_states()
471 list_for_each_entry(reg, &failed_recovered, list) dm_rh_update_states()
472 list_del(&reg->hash_list); dm_rh_update_states()
483 list_for_each_entry_safe(reg, next, &recovered, list) { dm_rh_update_states()
484 rh->log->type->clear_region(rh->log, reg->key); dm_rh_update_states()
485 complete_resync_work(reg, 1); dm_rh_update_states()
486 mempool_free(reg, rh->region_pool); dm_rh_update_states()
489 list_for_each_entry_safe(reg, next, &failed_recovered, list) { dm_rh_update_states()
490 complete_resync_work(reg, errors_handled ? 0 : 1); dm_rh_update_states()
491 mempool_free(reg, rh->region_pool); dm_rh_update_states()
494 list_for_each_entry_safe(reg, next, &clean, list) { dm_rh_update_states()
495 rh->log->type->clear_region(rh->log, reg->key); dm_rh_update_states()
496 mempool_free(reg, rh->region_pool); dm_rh_update_states()
505 struct dm_region *reg; rh_inc() local
508 reg = __rh_find(rh, region); rh_inc()
511 atomic_inc(&reg->pending); rh_inc()
513 if (reg->state == DM_RH_CLEAN) { rh_inc()
514 reg->state = DM_RH_DIRTY; rh_inc()
515 list_del_init(&reg->list); /* take off the clean list */ rh_inc()
518 rh->log->type->mark_region(rh->log, reg->key); rh_inc()
541 struct dm_region *reg; dm_rh_dec() local
545 reg = __rh_lookup(rh, region); dm_rh_dec()
549 if (atomic_dec_and_test(&reg->pending)) { dm_rh_dec()
568 reg->state = DM_RH_NOSYNC; dm_rh_dec()
569 } else if (reg->state == DM_RH_RECOVERING) { dm_rh_dec()
570 list_add_tail(&reg->list, &rh->quiesced_regions); dm_rh_dec()
571 } else if (reg->state == DM_RH_DIRTY) { dm_rh_dec()
572 reg->state = DM_RH_CLEAN; dm_rh_dec()
573 list_add(&reg->list, &rh->clean_regions); dm_rh_dec()
591 struct dm_region *reg; __rh_recovery_prepare() local
605 reg = __rh_find(rh, region); __rh_recovery_prepare()
609 reg->state = DM_RH_RECOVERING; __rh_recovery_prepare()
612 if (atomic_read(&reg->pending)) __rh_recovery_prepare()
613 list_del_init(&reg->list); __rh_recovery_prepare()
615 list_move(&reg->list, &rh->quiesced_regions); __rh_recovery_prepare()
647 struct dm_region *reg = NULL; dm_rh_recovery_start() local
651 reg = list_entry(rh->quiesced_regions.next, dm_rh_recovery_start()
653 list_del_init(&reg->list); /* remove from the quiesced list */ dm_rh_recovery_start()
657 return reg; dm_rh_recovery_start()
661 void dm_rh_recovery_end(struct dm_region *reg, int success) dm_rh_recovery_end() argument
663 struct dm_region_hash *rh = reg->rh; dm_rh_recovery_end()
667 list_add(&reg->list, &reg->rh->recovered_regions); dm_rh_recovery_end()
669 list_add(&reg->list, &reg->rh->failed_recovered_regions); dm_rh_recovery_end()
692 struct dm_region *reg; dm_rh_delay() local
695 reg = __rh_find(rh, dm_rh_bio_to_region(rh, bio)); dm_rh_delay()
696 bio_list_add(&reg->delayed_bios, bio); dm_rh_delay()
/linux-4.1.27/drivers/hwmon/
H A Dadt7x10.h20 int (*read_byte)(struct device *, u8 reg);
21 int (*write_byte)(struct device *, u8 reg, u8 data);
22 int (*read_word)(struct device *, u8 reg);
23 int (*write_word)(struct device *, u8 reg, u16 data);
/linux-4.1.27/drivers/net/irda/
H A Dw83977af.h31 static inline void w977_write_reg(__u8 reg, __u8 value, unsigned int efio) w977_write_reg() argument
33 outb(reg, efio); w977_write_reg()
40 static inline __u8 w977_read_reg(__u8 reg, unsigned int efio) w977_read_reg() argument
42 outb(reg, efio); w977_read_reg()
/linux-4.1.27/arch/mips/include/asm/dec/
H A Dioasic.h24 static inline void ioasic_write(unsigned int reg, u32 v) ioasic_write() argument
26 ioasic_base[reg / 4] = v; ioasic_write()
29 static inline u32 ioasic_read(unsigned int reg) ioasic_read() argument
31 return ioasic_base[reg / 4]; ioasic_read()
/linux-4.1.27/include/video/
H A Dvga.h212 static inline void vga_io_w_fast (unsigned short port, unsigned char reg, vga_io_w_fast() argument
215 outw(VGA_OUT16VAL (val, reg), port); vga_io_w_fast()
229 unsigned char reg, unsigned char val) vga_mm_w_fast()
231 writew (VGA_OUT16VAL (val, reg), regbase + port); vga_mm_w_fast()
252 unsigned char reg, unsigned char val) vga_w_fast()
255 vga_mm_w_fast (regbase, port, reg, val); vga_w_fast()
257 vga_io_w_fast (port, reg, val); vga_w_fast()
265 static inline unsigned char vga_rcrt (void __iomem *regbase, unsigned char reg) vga_rcrt() argument
267 vga_w (regbase, VGA_CRT_IC, reg); vga_rcrt()
271 static inline void vga_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) vga_wcrt() argument
274 vga_w_fast (regbase, VGA_CRT_IC, reg, val); vga_wcrt()
276 vga_w (regbase, VGA_CRT_IC, reg); vga_wcrt()
281 static inline unsigned char vga_io_rcrt (unsigned char reg) vga_io_rcrt() argument
283 vga_io_w (VGA_CRT_IC, reg); vga_io_rcrt()
287 static inline void vga_io_wcrt (unsigned char reg, unsigned char val) vga_io_wcrt() argument
290 vga_io_w_fast (VGA_CRT_IC, reg, val); vga_io_wcrt()
292 vga_io_w (VGA_CRT_IC, reg); vga_io_wcrt()
297 static inline unsigned char vga_mm_rcrt (void __iomem *regbase, unsigned char reg) vga_mm_rcrt() argument
299 vga_mm_w (regbase, VGA_CRT_IC, reg); vga_mm_rcrt()
303 static inline void vga_mm_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) vga_mm_wcrt() argument
306 vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val); vga_mm_wcrt()
308 vga_mm_w (regbase, VGA_CRT_IC, reg); vga_mm_wcrt()
318 static inline unsigned char vga_rseq (void __iomem *regbase, unsigned char reg) vga_rseq() argument
320 vga_w (regbase, VGA_SEQ_I, reg); vga_rseq()
324 static inline void vga_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) vga_wseq() argument
327 vga_w_fast (regbase, VGA_SEQ_I, reg, val); vga_wseq()
329 vga_w (regbase, VGA_SEQ_I, reg); vga_wseq()
334 static inline unsigned char vga_io_rseq (unsigned char reg) vga_io_rseq() argument
336 vga_io_w (VGA_SEQ_I, reg); vga_io_rseq()
340 static inline void vga_io_wseq (unsigned char reg, unsigned char val) vga_io_wseq() argument
343 vga_io_w_fast (VGA_SEQ_I, reg, val); vga_io_wseq()
345 vga_io_w (VGA_SEQ_I, reg); vga_io_wseq()
350 static inline unsigned char vga_mm_rseq (void __iomem *regbase, unsigned char reg) vga_mm_rseq() argument
352 vga_mm_w (regbase, VGA_SEQ_I, reg); vga_mm_rseq()
356 static inline void vga_mm_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) vga_mm_wseq() argument
359 vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val); vga_mm_wseq()
361 vga_mm_w (regbase, VGA_SEQ_I, reg); vga_mm_wseq()
370 static inline unsigned char vga_rgfx (void __iomem *regbase, unsigned char reg) vga_rgfx() argument
372 vga_w (regbase, VGA_GFX_I, reg); vga_rgfx()
376 static inline void vga_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) vga_wgfx() argument
379 vga_w_fast (regbase, VGA_GFX_I, reg, val); vga_wgfx()
381 vga_w (regbase, VGA_GFX_I, reg); vga_wgfx()
386 static inline unsigned char vga_io_rgfx (unsigned char reg) vga_io_rgfx() argument
388 vga_io_w (VGA_GFX_I, reg); vga_io_rgfx()
392 static inline void vga_io_wgfx (unsigned char reg, unsigned char val) vga_io_wgfx() argument
395 vga_io_w_fast (VGA_GFX_I, reg, val); vga_io_wgfx()
397 vga_io_w (VGA_GFX_I, reg); vga_io_wgfx()
402 static inline unsigned char vga_mm_rgfx (void __iomem *regbase, unsigned char reg) vga_mm_rgfx() argument
404 vga_mm_w (regbase, VGA_GFX_I, reg); vga_mm_rgfx()
408 static inline void vga_mm_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) vga_mm_wgfx() argument
411 vga_mm_w_fast (regbase, VGA_GFX_I, reg, val); vga_mm_wgfx()
413 vga_mm_w (regbase, VGA_GFX_I, reg); vga_mm_wgfx()
423 static inline unsigned char vga_rattr (void __iomem *regbase, unsigned char reg) vga_rattr() argument
425 vga_w (regbase, VGA_ATT_IW, reg); vga_rattr()
429 static inline void vga_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) vga_wattr() argument
431 vga_w (regbase, VGA_ATT_IW, reg); vga_wattr()
435 static inline unsigned char vga_io_rattr (unsigned char reg) vga_io_rattr() argument
437 vga_io_w (VGA_ATT_IW, reg); vga_io_rattr()
441 static inline void vga_io_wattr (unsigned char reg, unsigned char val) vga_io_wattr() argument
443 vga_io_w (VGA_ATT_IW, reg); vga_io_wattr()
447 static inline unsigned char vga_mm_rattr (void __iomem *regbase, unsigned char reg) vga_mm_rattr() argument
449 vga_mm_w (regbase, VGA_ATT_IW, reg); vga_mm_rattr()
453 static inline void vga_mm_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) vga_mm_wattr() argument
455 vga_mm_w (regbase, VGA_ATT_IW, reg); vga_mm_wattr()
228 vga_mm_w_fast(void __iomem *regbase, unsigned short port, unsigned char reg, unsigned char val) vga_mm_w_fast() argument
251 vga_w_fast(void __iomem *regbase, unsigned short port, unsigned char reg, unsigned char val) vga_w_fast() argument
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/
H A Dclkgen_defs_asm.h15 #define REG_FIELD( scope, reg, field, value ) \
16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
21 #define REG_STATE( scope, reg, field, symbolic_value ) \
22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
27 #define REG_MASK( scope, reg, field ) \
28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
33 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
46 #define REG_ADDR_VECT( scope, inst, reg, index ) \
47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
48 STRIDE_##scope##_##reg )
/linux-4.1.27/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/
H A Dconfig_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
24 #define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
30 #define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
/linux-4.1.27/sound/soc/
H A Dsoc-io.c23 * @reg: Register to read
29 unsigned int reg, unsigned int *val) snd_soc_component_read()
34 ret = regmap_read(component->regmap, reg, val); snd_soc_component_read()
36 ret = component->read(component, reg, val); snd_soc_component_read()
47 * @reg: Register to write
53 unsigned int reg, unsigned int val) snd_soc_component_write()
56 return regmap_write(component->regmap, reg, val); snd_soc_component_write()
58 return component->write(component, reg, val); snd_soc_component_write()
65 struct snd_soc_component *component, unsigned int reg, snd_soc_component_update_bits_legacy()
76 ret = component->read(component, reg, &old); snd_soc_component_update_bits_legacy()
83 ret = component->write(component, reg, new); snd_soc_component_update_bits_legacy()
93 * @reg: Register to update
102 unsigned int reg, unsigned int mask, unsigned int val) snd_soc_component_update_bits()
108 ret = regmap_update_bits_check(component->regmap, reg, mask, snd_soc_component_update_bits()
111 ret = snd_soc_component_update_bits_legacy(component, reg, snd_soc_component_update_bits()
124 * @reg: Register to update
138 unsigned int reg, unsigned int mask, unsigned int val) snd_soc_component_update_bits_async()
144 ret = regmap_update_bits_check_async(component->regmap, reg, snd_soc_component_update_bits_async()
147 ret = snd_soc_component_update_bits_legacy(component, reg, snd_soc_component_update_bits_async()
173 * @reg: Register to test
183 unsigned int reg, unsigned int mask, unsigned int value) snd_soc_component_test_bits()
188 ret = snd_soc_component_read(component, reg, &old); snd_soc_component_test_bits()
196 unsigned int snd_soc_read(struct snd_soc_codec *codec, unsigned int reg) snd_soc_read() argument
201 ret = snd_soc_component_read(&codec->component, reg, &val); snd_soc_read()
209 int snd_soc_write(struct snd_soc_codec *codec, unsigned int reg, snd_soc_write() argument
212 return snd_soc_component_write(&codec->component, reg, val); snd_soc_write()
219 * @reg: codec register
227 int snd_soc_update_bits(struct snd_soc_codec *codec, unsigned int reg, snd_soc_update_bits() argument
230 return snd_soc_component_update_bits(&codec->component, reg, mask, snd_soc_update_bits()
238 * @reg: codec register
247 int snd_soc_test_bits(struct snd_soc_codec *codec, unsigned int reg, snd_soc_test_bits() argument
250 return snd_soc_component_test_bits(&codec->component, reg, mask, value); snd_soc_test_bits()
255 unsigned int reg) snd_soc_platform_read()
260 ret = snd_soc_component_read(&platform->component, reg, &val); snd_soc_platform_read()
269 unsigned int reg, unsigned int val) snd_soc_platform_write()
271 return snd_soc_component_write(&platform->component, reg, val); snd_soc_platform_write()
28 snd_soc_component_read(struct snd_soc_component *component, unsigned int reg, unsigned int *val) snd_soc_component_read() argument
52 snd_soc_component_write(struct snd_soc_component *component, unsigned int reg, unsigned int val) snd_soc_component_write() argument
64 snd_soc_component_update_bits_legacy( struct snd_soc_component *component, unsigned int reg, unsigned int mask, unsigned int val, bool *change) snd_soc_component_update_bits_legacy() argument
101 snd_soc_component_update_bits(struct snd_soc_component *component, unsigned int reg, unsigned int mask, unsigned int val) snd_soc_component_update_bits() argument
137 snd_soc_component_update_bits_async(struct snd_soc_component *component, unsigned int reg, unsigned int mask, unsigned int val) snd_soc_component_update_bits_async() argument
182 snd_soc_component_test_bits(struct snd_soc_component *component, unsigned int reg, unsigned int mask, unsigned int value) snd_soc_component_test_bits() argument
254 snd_soc_platform_read(struct snd_soc_platform *platform, unsigned int reg) snd_soc_platform_read() argument
268 snd_soc_platform_write(struct snd_soc_platform *platform, unsigned int reg, unsigned int val) snd_soc_platform_write() argument
/linux-4.1.27/drivers/gpu/drm/i915/
H A Dintel_uncore.c475 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
476 ((reg) < 0x40000 && (reg) != FORCEWAKE)
478 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
480 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
481 (REG_RANGE((reg), 0x2000, 0x4000) || \
482 REG_RANGE((reg), 0x5000, 0x8000) || \
483 REG_RANGE((reg), 0xB000, 0x12000) || \
484 REG_RANGE((reg), 0x2E000, 0x30000))
486 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
487 (REG_RANGE((reg), 0x12000, 0x14000) || \
488 REG_RANGE((reg), 0x22000, 0x24000) || \
489 REG_RANGE((reg), 0x30000, 0x40000))
491 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
492 (REG_RANGE((reg), 0x2000, 0x4000) || \
493 REG_RANGE((reg), 0x5200, 0x8000) || \
494 REG_RANGE((reg), 0x8300, 0x8500) || \
495 REG_RANGE((reg), 0xB000, 0xB480) || \
496 REG_RANGE((reg), 0xE000, 0xE800))
498 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
499 (REG_RANGE((reg), 0x8800, 0x8900) || \
500 REG_RANGE((reg), 0xD000, 0xD800) || \
501 REG_RANGE((reg), 0x12000, 0x14000) || \
502 REG_RANGE((reg), 0x1A000, 0x1C000) || \
503 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
504 REG_RANGE((reg), 0x30000, 0x38000))
506 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
507 (REG_RANGE((reg), 0x4000, 0x5000) || \
508 REG_RANGE((reg), 0x8000, 0x8300) || \
509 REG_RANGE((reg), 0x8500, 0x8600) || \
510 REG_RANGE((reg), 0x9000, 0xB000) || \
511 REG_RANGE((reg), 0xF000, 0x10000))
513 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
514 REG_RANGE((reg), 0xB00, 0x2000)
516 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
517 (REG_RANGE((reg), 0x2000, 0x2700) || \
518 REG_RANGE((reg), 0x3000, 0x4000) || \
519 REG_RANGE((reg), 0x5200, 0x8000) || \
520 REG_RANGE((reg), 0x8140, 0x8160) || \
521 REG_RANGE((reg), 0x8300, 0x8500) || \
522 REG_RANGE((reg), 0x8C00, 0x8D00) || \
523 REG_RANGE((reg), 0xB000, 0xB480) || \
524 REG_RANGE((reg), 0xE000, 0xE900) || \
525 REG_RANGE((reg), 0x24400, 0x24800))
527 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
528 (REG_RANGE((reg), 0x8130, 0x8140) || \
529 REG_RANGE((reg), 0x8800, 0x8A00) || \
530 REG_RANGE((reg), 0xD000, 0xD800) || \
531 REG_RANGE((reg), 0x12000, 0x14000) || \
532 REG_RANGE((reg), 0x1A000, 0x1EA00) || \
533 REG_RANGE((reg), 0x30000, 0x40000))
535 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
536 REG_RANGE((reg), 0x9400, 0x9800)
538 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
539 ((reg) < 0x40000 &&\
540 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
541 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
542 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
543 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
555 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read, hsw_unclaimed_reg_debug() argument
566 when, op, reg); hsw_unclaimed_reg_debug()
594 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
599 gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
601 val = __raw_i915_read##x(dev_priv, reg); \
607 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
610 val = __raw_i915_read##x(dev_priv, reg); \
637 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
666 vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
668 val = __raw_i915_read##x(dev_priv, reg); \
674 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
676 hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
677 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \
679 val = __raw_i915_read##x(dev_priv, reg); \
680 hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
686 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
688 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
690 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \
692 val = __raw_i915_read##x(dev_priv, reg); \
698 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
700 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
702 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
704 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
707 val = __raw_i915_read##x(dev_priv, reg); \
711 #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg) \
712 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
716 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
719 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) \
721 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
723 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
725 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
731 val = __raw_i915_read##x(dev_priv, reg); \
765 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
772 gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
774 __raw_i915_write##x(dev_priv, reg, val); \
780 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
783 __raw_i915_write##x(dev_priv, reg, val); \
804 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
813 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
816 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
819 __raw_i915_write##x(dev_priv, reg, val); \
828 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
831 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
834 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
835 __raw_i915_write##x(dev_priv, reg, val); \
839 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
846 off_t reg, u##x val, bool trace) { \
848 __raw_i915_write##x(dev_priv, reg, val); \
863 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) is_gen8_shadowed() argument
867 if (reg == gen8_shadowed_regs[i]) is_gen8_shadowed()
875 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
877 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
878 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
880 __raw_i915_write##x(dev_priv, reg, val); \
881 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
888 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
889 bool shadowed = is_gen8_shadowed(dev_priv, reg); \
892 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
894 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
896 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
899 __raw_i915_write##x(dev_priv, reg, val); \
916 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg) is_gen9_shadowed() argument
920 if (reg == gen9_shadowed_regs[i]) is_gen9_shadowed()
928 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
932 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
933 is_gen9_shadowed(dev_priv, reg)) \
935 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
937 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
939 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
945 __raw_i915_write##x(dev_priv, reg, val); \
1225 struct drm_i915_reg_read *reg = data; i915_reg_read_ioctl() local
1232 if (entry->offset == (reg->offset & -entry->size) && i915_reg_read_ioctl()
1246 size |= reg->offset ^ offset; i915_reg_read_ioctl()
1252 reg->val = I915_READ64_2x32(offset, offset+4); i915_reg_read_ioctl()
1255 reg->val = I915_READ64(offset); i915_reg_read_ioctl()
1258 reg->val = I915_READ(offset); i915_reg_read_ioctl()
1261 reg->val = I915_READ16(offset); i915_reg_read_ioctl()
1264 reg->val = I915_READ8(offset); i915_reg_read_ioctl()
H A Dintel_sideband.c102 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg) vlv_bunit_read() argument
107 SB_CRRDDA_NP, reg, &val); vlv_bunit_read()
112 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) vlv_bunit_write() argument
115 SB_CRWRDA_NP, reg, &val); vlv_bunit_write()
132 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg) vlv_gpio_nc_read() argument
136 SB_CRRDDA_NP, reg, &val); vlv_gpio_nc_read()
140 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) vlv_gpio_nc_write() argument
143 SB_CRWRDA_NP, reg, &val); vlv_gpio_nc_write()
146 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) vlv_cck_read() argument
150 SB_CRRDDA_NP, reg, &val); vlv_cck_read()
154 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) vlv_cck_write() argument
157 SB_CRWRDA_NP, reg, &val); vlv_cck_write()
160 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg) vlv_ccu_read() argument
164 SB_CRRDDA_NP, reg, &val); vlv_ccu_read()
168 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) vlv_ccu_write() argument
171 SB_CRWRDA_NP, reg, &val); vlv_ccu_write()
174 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg) vlv_gps_core_read() argument
178 SB_CRRDDA_NP, reg, &val); vlv_gps_core_read()
182 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) vlv_gps_core_write() argument
185 SB_CRWRDA_NP, reg, &val); vlv_gps_core_write()
188 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) vlv_dpio_read() argument
193 SB_MRD_NP, reg, &val); vlv_dpio_read()
199 WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n", vlv_dpio_read()
200 pipe_name(pipe), reg, val); vlv_dpio_read()
205 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) vlv_dpio_write() argument
208 SB_MWR_NP, reg, &val); vlv_dpio_write()
212 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, intel_sbi_read() argument
224 I915_WRITE(SBI_ADDR, (reg << 16)); intel_sbi_read()
241 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, intel_sbi_write() argument
254 I915_WRITE(SBI_ADDR, (reg << 16)); intel_sbi_write()
270 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg) vlv_flisdsi_read() argument
274 reg, &val); vlv_flisdsi_read()
278 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) vlv_flisdsi_write() argument
281 reg, &val); vlv_flisdsi_write()
/linux-4.1.27/drivers/net/dsa/
H A Dbcm_sf2.c117 offset = s->reg + CORE_P_MIB_OFFSET(port); bcm_sf2_sw_get_ethtool_stats()
143 u32 reg; bcm_sf2_imp_vlan_setup() local
153 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i)); bcm_sf2_imp_vlan_setup()
154 reg |= (1 << cpu_port); bcm_sf2_imp_vlan_setup()
155 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i)); bcm_sf2_imp_vlan_setup()
162 u32 reg, val; bcm_sf2_imp_setup() local
165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); bcm_sf2_imp_setup()
166 reg &= ~P_TXQ_PSM_VDD(port); bcm_sf2_imp_setup()
167 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); bcm_sf2_imp_setup()
170 reg = core_readl(priv, CORE_IMP_CTL); bcm_sf2_imp_setup()
171 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); bcm_sf2_imp_setup()
172 reg &= ~(RX_DIS | TX_DIS); bcm_sf2_imp_setup()
173 core_writel(priv, reg, CORE_IMP_CTL); bcm_sf2_imp_setup()
179 reg = core_readl(priv, CORE_SWITCH_CTRL); bcm_sf2_imp_setup()
180 reg |= MII_DUMB_FWDG_EN; bcm_sf2_imp_setup()
181 core_writel(priv, reg, CORE_SWITCH_CTRL); bcm_sf2_imp_setup()
200 reg = core_readl(priv, CORE_BRCM_HDR_CTRL); bcm_sf2_imp_setup()
201 reg |= val; bcm_sf2_imp_setup()
202 core_writel(priv, reg, CORE_BRCM_HDR_CTRL); bcm_sf2_imp_setup()
207 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS); bcm_sf2_imp_setup()
208 reg &= ~(1 << port); bcm_sf2_imp_setup()
209 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS); bcm_sf2_imp_setup()
214 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS); bcm_sf2_imp_setup()
215 reg &= ~(1 << port); bcm_sf2_imp_setup()
216 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS); bcm_sf2_imp_setup()
219 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP); bcm_sf2_imp_setup()
220 reg |= (MII_SW_OR | LINK_STS); bcm_sf2_imp_setup()
221 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP); bcm_sf2_imp_setup()
227 u32 reg; bcm_sf2_eee_enable_set() local
229 reg = core_readl(priv, CORE_EEE_EN_CTRL); bcm_sf2_eee_enable_set()
231 reg |= 1 << port; bcm_sf2_eee_enable_set()
233 reg &= ~(1 << port); bcm_sf2_eee_enable_set()
234 core_writel(priv, reg, CORE_EEE_EN_CTRL); bcm_sf2_eee_enable_set()
240 u32 reg; bcm_sf2_gphy_enable_set() local
242 reg = reg_readl(priv, REG_SPHY_CNTRL); bcm_sf2_gphy_enable_set()
244 reg |= PHY_RESET; bcm_sf2_gphy_enable_set()
245 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS); bcm_sf2_gphy_enable_set()
246 reg_writel(priv, reg, REG_SPHY_CNTRL); bcm_sf2_gphy_enable_set()
248 reg = reg_readl(priv, REG_SPHY_CNTRL); bcm_sf2_gphy_enable_set()
249 reg &= ~PHY_RESET; bcm_sf2_gphy_enable_set()
251 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; bcm_sf2_gphy_enable_set()
252 reg_writel(priv, reg, REG_SPHY_CNTRL); bcm_sf2_gphy_enable_set()
254 reg |= CK25_DIS; bcm_sf2_gphy_enable_set()
256 reg_writel(priv, reg, REG_SPHY_CNTRL); bcm_sf2_gphy_enable_set()
260 reg = reg_readl(priv, REG_LED_CNTRL(0)); bcm_sf2_gphy_enable_set()
261 reg |= SPDLNK_SRC_SEL; bcm_sf2_gphy_enable_set()
262 reg_writel(priv, reg, REG_LED_CNTRL(0)); bcm_sf2_gphy_enable_set()
271 u32 reg; bcm_sf2_port_setup() local
274 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); bcm_sf2_port_setup()
275 reg &= ~P_TXQ_PSM_VDD(port); bcm_sf2_port_setup()
276 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); bcm_sf2_port_setup()
307 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port)); bcm_sf2_port_setup()
308 reg &= ~PORT_VLAN_CTRL_MASK; bcm_sf2_port_setup()
309 reg |= (1 << port); bcm_sf2_port_setup()
310 reg |= priv->port_sts[port].vlan_ctl_mask; bcm_sf2_port_setup()
311 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port)); bcm_sf2_port_setup()
326 u32 off, reg; bcm_sf2_port_disable() local
344 reg = core_readl(priv, off); bcm_sf2_port_disable()
345 reg |= RX_DIS | TX_DIS; bcm_sf2_port_disable()
346 core_writel(priv, reg, off); bcm_sf2_port_disable()
349 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); bcm_sf2_port_disable()
350 reg |= P_TXQ_PSM_VDD(port); bcm_sf2_port_disable()
351 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); bcm_sf2_port_disable()
379 u32 reg; bcm_sf2_sw_get_eee() local
381 reg = core_readl(priv, CORE_EEE_LPI_INDICATE); bcm_sf2_sw_get_eee()
383 e->eee_active = !!(reg & (1 << port)); bcm_sf2_sw_get_eee()
415 u32 reg; bcm_sf2_sw_fast_age_port() local
419 reg = core_readl(priv, CORE_FAST_AGE_CTRL); bcm_sf2_sw_fast_age_port()
420 reg |= EN_AGE_PORT | EN_AGE_DYNAMIC | FAST_AGE_STR_DONE; bcm_sf2_sw_fast_age_port()
421 core_writel(priv, reg, CORE_FAST_AGE_CTRL); bcm_sf2_sw_fast_age_port()
424 reg = core_readl(priv, CORE_FAST_AGE_CTRL); bcm_sf2_sw_fast_age_port()
425 if (!(reg & FAST_AGE_STR_DONE)) bcm_sf2_sw_fast_age_port()
444 u32 reg, p_ctl; bcm_sf2_sw_br_join() local
455 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i)); bcm_sf2_sw_br_join()
456 reg |= 1 << port; bcm_sf2_sw_br_join()
457 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i)); bcm_sf2_sw_br_join()
458 priv->port_sts[i].vlan_ctl_mask = reg; bcm_sf2_sw_br_join()
477 u32 reg, p_ctl; bcm_sf2_sw_br_leave() local
486 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i)); bcm_sf2_sw_br_leave()
487 reg &= ~(1 << port); bcm_sf2_sw_br_leave()
488 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i)); bcm_sf2_sw_br_leave()
489 priv->port_sts[port].vlan_ctl_mask = reg; bcm_sf2_sw_br_leave()
508 u32 reg; bcm_sf2_sw_br_set_stp_state() local
510 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); bcm_sf2_sw_br_set_stp_state()
511 cur_hw_state = reg & (G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT); bcm_sf2_sw_br_set_stp_state()
549 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); bcm_sf2_sw_br_set_stp_state()
550 reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT); bcm_sf2_sw_br_set_stp_state()
551 reg |= hw_state; bcm_sf2_sw_br_set_stp_state()
552 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); bcm_sf2_sw_br_set_stp_state()
587 u32 reg; bcm_sf2_sw_rst() local
589 reg = core_readl(priv, CORE_WATCHDOG_CTRL); bcm_sf2_sw_rst()
590 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; bcm_sf2_sw_rst()
591 core_writel(priv, reg, CORE_WATCHDOG_CTRL); bcm_sf2_sw_rst()
594 reg = core_readl(priv, CORE_WATCHDOG_CTRL); bcm_sf2_sw_rst()
595 if (!(reg & SOFTWARE_RESET)) bcm_sf2_sw_rst()
625 u32 reg, rev; bcm_sf2_sw_setup() local
674 reg = core_readl(priv, CORE_GMNCFGCFG); bcm_sf2_sw_setup()
675 reg |= RST_MIB_CNT; bcm_sf2_sw_setup()
676 core_writel(priv, reg, CORE_GMNCFGCFG); bcm_sf2_sw_setup()
677 reg &= ~RST_MIB_CNT; bcm_sf2_sw_setup()
678 core_writel(priv, reg, CORE_GMNCFGCFG); bcm_sf2_sw_setup()
755 u32 reg; bcm_sf2_sw_indir_rw() local
757 reg = reg_readl(priv, REG_SWITCH_CNTRL); bcm_sf2_sw_indir_rw()
758 reg |= MDIO_MASTER_SEL; bcm_sf2_sw_indir_rw()
759 reg_writel(priv, reg, REG_SWITCH_CNTRL); bcm_sf2_sw_indir_rw()
762 reg = 0x70; bcm_sf2_sw_indir_rw()
763 reg <<= 2; bcm_sf2_sw_indir_rw()
764 core_writel(priv, addr, reg); bcm_sf2_sw_indir_rw()
767 reg = 0x80 << 8 | regnum << 1; bcm_sf2_sw_indir_rw()
768 reg <<= 2; bcm_sf2_sw_indir_rw()
771 ret = core_readl(priv, reg); bcm_sf2_sw_indir_rw()
773 core_writel(priv, val, reg); bcm_sf2_sw_indir_rw()
775 reg = reg_readl(priv, REG_SWITCH_CNTRL); bcm_sf2_sw_indir_rw()
776 reg &= ~MDIO_MASTER_SEL; bcm_sf2_sw_indir_rw()
777 reg_writel(priv, reg, REG_SWITCH_CNTRL); bcm_sf2_sw_indir_rw()
818 u32 reg; bcm_sf2_sw_adjust_link() local
844 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); bcm_sf2_sw_adjust_link()
845 reg &= ~RGMII_MODE_EN; bcm_sf2_sw_adjust_link()
846 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); bcm_sf2_sw_adjust_link()
853 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); bcm_sf2_sw_adjust_link()
854 reg &= ~ID_MODE_DIS; bcm_sf2_sw_adjust_link()
855 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); bcm_sf2_sw_adjust_link()
856 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); bcm_sf2_sw_adjust_link()
858 reg |= port_mode | RGMII_MODE_EN; bcm_sf2_sw_adjust_link()
860 reg |= ID_MODE_DIS; bcm_sf2_sw_adjust_link()
864 reg |= TX_PAUSE_EN; bcm_sf2_sw_adjust_link()
865 reg |= RX_PAUSE_EN; bcm_sf2_sw_adjust_link()
868 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); bcm_sf2_sw_adjust_link()
874 reg = SW_OVERRIDE; bcm_sf2_sw_adjust_link()
877 reg |= SPDSTS_1000 << SPEED_SHIFT; bcm_sf2_sw_adjust_link()
880 reg |= SPDSTS_100 << SPEED_SHIFT; bcm_sf2_sw_adjust_link()
885 reg |= LINK_STS; bcm_sf2_sw_adjust_link()
887 reg |= DUPLX_MODE; bcm_sf2_sw_adjust_link()
889 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port)); bcm_sf2_sw_adjust_link()
897 u32 reg; bcm_sf2_sw_fixed_link_update() local
920 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port)); bcm_sf2_sw_fixed_link_update()
921 reg |= SW_OVERRIDE; bcm_sf2_sw_fixed_link_update()
923 reg |= LINK_STS; bcm_sf2_sw_fixed_link_update()
925 reg &= ~LINK_STS; bcm_sf2_sw_fixed_link_update()
926 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port)); bcm_sf2_sw_fixed_link_update()
/linux-4.1.27/drivers/media/platform/s5p-mfc/
H A Ds5p_mfc_opr_v6.c638 unsigned int reg = 0; s5p_mfc_set_enc_params() local
655 reg = 0; s5p_mfc_set_enc_params()
656 reg |= p->gop_size & 0xFFFF; s5p_mfc_set_enc_params()
657 writel(reg, mfc_regs->e_gop_config); s5p_mfc_set_enc_params()
662 reg = 0; s5p_mfc_set_enc_params()
664 reg |= (0x1 << 3); s5p_mfc_set_enc_params()
665 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
668 reg |= (0x1 << 3); s5p_mfc_set_enc_params()
669 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
672 reg &= ~(0x1 << 3); s5p_mfc_set_enc_params()
673 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
680 reg = readl(mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
682 reg &= ~(0x1 << 4); s5p_mfc_set_enc_params()
684 reg |= (0x1 << 4); s5p_mfc_set_enc_params()
685 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
688 reg = readl(mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
689 reg &= ~(0x1 << 9); s5p_mfc_set_enc_params()
690 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
695 reg = readl(mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
696 reg &= ~(0x1 << 7); s5p_mfc_set_enc_params()
697 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
702 reg = readl(mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
703 reg &= ~(0x1 << 7); s5p_mfc_set_enc_params()
704 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
709 reg = readl(mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
710 reg |= (0x1 << 7); s5p_mfc_set_enc_params()
711 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
718 reg = readl(mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
719 reg |= (0x1 << 8); s5p_mfc_set_enc_params()
720 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
725 reg = 0; s5p_mfc_set_enc_params()
727 reg |= (1 << 31); s5p_mfc_set_enc_params()
729 reg |= ((p->pad_cr & 0xFF) << 16); s5p_mfc_set_enc_params()
731 reg |= ((p->pad_cb & 0xFF) << 8); s5p_mfc_set_enc_params()
733 reg |= p->pad_luma & 0xFF; s5p_mfc_set_enc_params()
734 writel(reg, mfc_regs->e_padding_ctrl); s5p_mfc_set_enc_params()
738 reg = 0; s5p_mfc_set_enc_params()
740 reg |= ((p->rc_frame & 0x1) << 9); s5p_mfc_set_enc_params()
741 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params()
759 reg = readl(mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
760 reg &= ~(0x1 << 2); s5p_mfc_set_enc_params()
761 reg |= ((p->seq_hdr_mode & 0x1) << 2); s5p_mfc_set_enc_params()
764 reg &= ~(0x3); s5p_mfc_set_enc_params()
765 reg |= (p->frame_skip_mode & 0x3); s5p_mfc_set_enc_params()
766 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
769 reg = readl(mfc_regs->e_rc_config); s5p_mfc_set_enc_params()
770 reg &= ~(0x1 << 10); s5p_mfc_set_enc_params()
771 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params()
774 reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK); s5p_mfc_set_enc_params()
775 writel(reg, mfc_regs->e_mv_hor_range); s5p_mfc_set_enc_params()
777 reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK); s5p_mfc_set_enc_params()
778 writel(reg, mfc_regs->e_mv_ver_range); s5p_mfc_set_enc_params()
804 unsigned int reg = 0; s5p_mfc_set_enc_params_h264() local
812 reg = readl(mfc_regs->e_gop_config); s5p_mfc_set_enc_params_h264()
813 reg &= ~(0x3 << 16); s5p_mfc_set_enc_params_h264()
814 reg |= ((p->num_b_frame & 0x3) << 16); s5p_mfc_set_enc_params_h264()
815 writel(reg, mfc_regs->e_gop_config); s5p_mfc_set_enc_params_h264()
818 reg = 0; s5p_mfc_set_enc_params_h264()
820 reg |= ((p_h264->level & 0xFF) << 8); s5p_mfc_set_enc_params_h264()
822 reg |= p_h264->profile & 0x3F; s5p_mfc_set_enc_params_h264()
823 writel(reg, mfc_regs->e_picture_profile); s5p_mfc_set_enc_params_h264()
826 reg = readl(mfc_regs->e_rc_config); s5p_mfc_set_enc_params_h264()
828 reg &= ~(0x1 << 8); s5p_mfc_set_enc_params_h264()
829 reg |= ((p->rc_mb & 0x1) << 8); s5p_mfc_set_enc_params_h264()
830 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_h264()
833 reg &= ~(0x3F); s5p_mfc_set_enc_params_h264()
834 reg |= p_h264->rc_frame_qp & 0x3F; s5p_mfc_set_enc_params_h264()
835 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_h264()
838 reg = 0; s5p_mfc_set_enc_params_h264()
840 reg |= ((p_h264->rc_max_qp & 0x3F) << 8); s5p_mfc_set_enc_params_h264()
842 reg |= p_h264->rc_min_qp & 0x3F; s5p_mfc_set_enc_params_h264()
843 writel(reg, mfc_regs->e_rc_qp_bound); s5p_mfc_set_enc_params_h264()
848 reg = 0; s5p_mfc_set_enc_params_h264()
849 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16); s5p_mfc_set_enc_params_h264()
850 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8); s5p_mfc_set_enc_params_h264()
851 reg |= p_h264->rc_frame_qp & 0x3F; s5p_mfc_set_enc_params_h264()
852 writel(reg, mfc_regs->e_fixed_picture_qp); s5p_mfc_set_enc_params_h264()
857 reg = 0; s5p_mfc_set_enc_params_h264()
858 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); s5p_mfc_set_enc_params_h264()
859 reg |= p->rc_framerate_denom & 0xFFFF; s5p_mfc_set_enc_params_h264()
860 writel(reg, mfc_regs->e_rc_frame_rate); s5p_mfc_set_enc_params_h264()
874 reg = 0; s5p_mfc_set_enc_params_h264()
875 reg |= ((p_h264->interlace & 0x1) << 3); s5p_mfc_set_enc_params_h264()
876 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
888 reg = readl(mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
889 reg &= ~(0x3 << 1); s5p_mfc_set_enc_params_h264()
890 reg |= ((p_h264->loop_filter_mode & 0x3) << 1); s5p_mfc_set_enc_params_h264()
891 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
895 reg = 0x10; s5p_mfc_set_enc_params_h264()
896 reg |= (0xFF - p_h264->loop_filter_alpha) + 1; s5p_mfc_set_enc_params_h264()
898 reg = 0x00; s5p_mfc_set_enc_params_h264()
899 reg |= (p_h264->loop_filter_alpha & 0xF); s5p_mfc_set_enc_params_h264()
901 writel(reg, mfc_regs->e_h264_lf_alpha_offset); s5p_mfc_set_enc_params_h264()
905 reg = 0x10; s5p_mfc_set_enc_params_h264()
906 reg |= (0xFF - p_h264->loop_filter_beta) + 1; s5p_mfc_set_enc_params_h264()
908 reg = 0x00; s5p_mfc_set_enc_params_h264()
909 reg |= (p_h264->loop_filter_beta & 0xF); s5p_mfc_set_enc_params_h264()
911 writel(reg, mfc_regs->e_h264_lf_beta_offset); s5p_mfc_set_enc_params_h264()
914 reg = readl(mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
915 reg &= ~(0x1); s5p_mfc_set_enc_params_h264()
916 reg |= p_h264->entropy_mode & 0x1; s5p_mfc_set_enc_params_h264()
917 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
920 reg = readl(mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
921 reg &= ~(0x1 << 7); s5p_mfc_set_enc_params_h264()
922 reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7); s5p_mfc_set_enc_params_h264()
923 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
926 reg = readl(mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
927 reg &= ~(0x3 << 12); s5p_mfc_set_enc_params_h264()
928 reg |= ((p_h264->_8x8_transform & 0x3) << 12); s5p_mfc_set_enc_params_h264()
929 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
934 reg = 0; s5p_mfc_set_enc_params_h264()
936 reg |= ((p_h264->rc_mb_dark & 0x1) << 3); s5p_mfc_set_enc_params_h264()
938 reg |= ((p_h264->rc_mb_smooth & 0x1) << 2); s5p_mfc_set_enc_params_h264()
940 reg |= ((p_h264->rc_mb_static & 0x1) << 1); s5p_mfc_set_enc_params_h264()
942 reg |= p_h264->rc_mb_activity & 0x1; s5p_mfc_set_enc_params_h264()
943 writel(reg, mfc_regs->e_mb_rc_config); s5p_mfc_set_enc_params_h264()
948 reg &= ~(0x1 << 5); s5p_mfc_set_enc_params_h264()
949 reg |= ((p_h264->vui_sar & 0x1) << 5); s5p_mfc_set_enc_params_h264()
950 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
956 reg = 0; s5p_mfc_set_enc_params_h264()
957 reg |= p_h264->vui_sar_idc & 0xFF; s5p_mfc_set_enc_params_h264()
958 writel(reg, mfc_regs->e_aspect_ratio); s5p_mfc_set_enc_params_h264()
961 reg = 0; s5p_mfc_set_enc_params_h264()
962 reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16; s5p_mfc_set_enc_params_h264()
963 reg |= p_h264->vui_ext_sar_height & 0xFFFF; s5p_mfc_set_enc_params_h264()
964 writel(reg, mfc_regs->e_extended_sar); s5p_mfc_set_enc_params_h264()
971 reg &= ~(0x1 << 4); s5p_mfc_set_enc_params_h264()
972 reg |= ((p_h264->open_gop & 0x1) << 4); s5p_mfc_set_enc_params_h264()
973 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
978 reg = 0; s5p_mfc_set_enc_params_h264()
979 reg |= p_h264->open_gop_size & 0xFFFF; s5p_mfc_set_enc_params_h264()
980 writel(reg, mfc_regs->e_h264_i_period); s5p_mfc_set_enc_params_h264()
985 reg &= ~(0x3 << 9); s5p_mfc_set_enc_params_h264()
986 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
990 reg &= ~(0x1 << 14); s5p_mfc_set_enc_params_h264()
991 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
995 reg &= ~(0x1 << 6); s5p_mfc_set_enc_params_h264()
996 reg |= ((p_h264->aso & 0x1) << 6); s5p_mfc_set_enc_params_h264()
997 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
1001 reg &= ~(0x1 << 8); s5p_mfc_set_enc_params_h264()
1002 reg |= ((p_h264->open_gop & 0x1) << 8); s5p_mfc_set_enc_params_h264()
1003 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
1004 reg = 0; s5p_mfc_set_enc_params_h264()
1006 reg |= (p_h264->hier_qp_type & 0x1) << 0x3; s5p_mfc_set_enc_params_h264()
1007 reg |= p_h264->hier_qp_layer & 0x7; s5p_mfc_set_enc_params_h264()
1008 writel(reg, mfc_regs->e_h264_num_t_layer); s5p_mfc_set_enc_params_h264()
1018 writel(reg, mfc_regs->e_h264_num_t_layer); s5p_mfc_set_enc_params_h264()
1022 reg &= ~(0x1 << 25); s5p_mfc_set_enc_params_h264()
1023 reg |= ((p_h264->sei_frame_packing & 0x1) << 25); s5p_mfc_set_enc_params_h264()
1024 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
1026 reg = 0; s5p_mfc_set_enc_params_h264()
1028 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2); s5p_mfc_set_enc_params_h264()
1030 reg |= p_h264->sei_fp_arrangement_type & 0x3; s5p_mfc_set_enc_params_h264()
1031 writel(reg, mfc_regs->e_h264_frame_packing_sei_info); s5p_mfc_set_enc_params_h264()
1085 unsigned int reg = 0; s5p_mfc_set_enc_params_mpeg4() local
1092 reg = readl(mfc_regs->e_gop_config); s5p_mfc_set_enc_params_mpeg4()
1093 reg &= ~(0x3 << 16); s5p_mfc_set_enc_params_mpeg4()
1094 reg |= ((p->num_b_frame & 0x3) << 16); s5p_mfc_set_enc_params_mpeg4()
1095 writel(reg, mfc_regs->e_gop_config); s5p_mfc_set_enc_params_mpeg4()
1098 reg = 0; s5p_mfc_set_enc_params_mpeg4()
1100 reg |= ((p_mpeg4->level & 0xFF) << 8); s5p_mfc_set_enc_params_mpeg4()
1102 reg |= p_mpeg4->profile & 0x3F; s5p_mfc_set_enc_params_mpeg4()
1103 writel(reg, mfc_regs->e_picture_profile); s5p_mfc_set_enc_params_mpeg4()
1106 reg = readl(mfc_regs->e_rc_config); s5p_mfc_set_enc_params_mpeg4()
1108 reg &= ~(0x1 << 8); s5p_mfc_set_enc_params_mpeg4()
1109 reg |= ((p->rc_mb & 0x1) << 8); s5p_mfc_set_enc_params_mpeg4()
1110 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_mpeg4()
1113 reg &= ~(0x3F); s5p_mfc_set_enc_params_mpeg4()
1114 reg |= p_mpeg4->rc_frame_qp & 0x3F; s5p_mfc_set_enc_params_mpeg4()
1115 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_mpeg4()
1118 reg = 0; s5p_mfc_set_enc_params_mpeg4()
1120 reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8); s5p_mfc_set_enc_params_mpeg4()
1122 reg |= p_mpeg4->rc_min_qp & 0x3F; s5p_mfc_set_enc_params_mpeg4()
1123 writel(reg, mfc_regs->e_rc_qp_bound); s5p_mfc_set_enc_params_mpeg4()
1128 reg = 0; s5p_mfc_set_enc_params_mpeg4()
1129 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16); s5p_mfc_set_enc_params_mpeg4()
1130 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8); s5p_mfc_set_enc_params_mpeg4()
1131 reg |= p_mpeg4->rc_frame_qp & 0x3F; s5p_mfc_set_enc_params_mpeg4()
1132 writel(reg, mfc_regs->e_fixed_picture_qp); s5p_mfc_set_enc_params_mpeg4()
1137 reg = 0; s5p_mfc_set_enc_params_mpeg4()
1138 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); s5p_mfc_set_enc_params_mpeg4()
1139 reg |= p->rc_framerate_denom & 0xFFFF; s5p_mfc_set_enc_params_mpeg4()
1140 writel(reg, mfc_regs->e_rc_frame_rate); s5p_mfc_set_enc_params_mpeg4()
1167 unsigned int reg = 0; s5p_mfc_set_enc_params_h263() local
1174 reg = 0; s5p_mfc_set_enc_params_h263()
1176 reg |= (0x1 << 4); s5p_mfc_set_enc_params_h263()
1177 writel(reg, mfc_regs->e_picture_profile); s5p_mfc_set_enc_params_h263()
1180 reg = readl(mfc_regs->e_rc_config); s5p_mfc_set_enc_params_h263()
1182 reg &= ~(0x1 << 8); s5p_mfc_set_enc_params_h263()
1183 reg |= ((p->rc_mb & 0x1) << 8); s5p_mfc_set_enc_params_h263()
1184 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_h263()
1187 reg &= ~(0x3F); s5p_mfc_set_enc_params_h263()
1188 reg |= p_h263->rc_frame_qp & 0x3F; s5p_mfc_set_enc_params_h263()
1189 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_h263()
1192 reg = 0; s5p_mfc_set_enc_params_h263()
1194 reg |= ((p_h263->rc_max_qp & 0x3F) << 8); s5p_mfc_set_enc_params_h263()
1196 reg |= p_h263->rc_min_qp & 0x3F; s5p_mfc_set_enc_params_h263()
1197 writel(reg, mfc_regs->e_rc_qp_bound); s5p_mfc_set_enc_params_h263()
1202 reg = 0; s5p_mfc_set_enc_params_h263()
1203 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16); s5p_mfc_set_enc_params_h263()
1204 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8); s5p_mfc_set_enc_params_h263()
1205 reg |= p_h263->rc_frame_qp & 0x3F; s5p_mfc_set_enc_params_h263()
1206 writel(reg, mfc_regs->e_fixed_picture_qp); s5p_mfc_set_enc_params_h263()
1211 reg = 0; s5p_mfc_set_enc_params_h263()
1212 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); s5p_mfc_set_enc_params_h263()
1213 reg |= p->rc_framerate_denom & 0xFFFF; s5p_mfc_set_enc_params_h263()
1214 writel(reg, mfc_regs->e_rc_frame_rate); s5p_mfc_set_enc_params_h263()
1237 unsigned int reg = 0; s5p_mfc_set_enc_params_vp8() local
1245 reg = readl(mfc_regs->e_gop_config); s5p_mfc_set_enc_params_vp8()
1246 reg &= ~(0x3 << 16); s5p_mfc_set_enc_params_vp8()
1247 reg |= ((p->num_b_frame & 0x3) << 16); s5p_mfc_set_enc_params_vp8()
1248 writel(reg, mfc_regs->e_gop_config); s5p_mfc_set_enc_params_vp8()
1251 reg = p_vp8->profile & 0x3; s5p_mfc_set_enc_params_vp8()
1252 writel(reg, mfc_regs->e_picture_profile); s5p_mfc_set_enc_params_vp8()
1255 reg = readl(mfc_regs->e_rc_config); s5p_mfc_set_enc_params_vp8()
1257 reg &= ~(0x1 << 8); s5p_mfc_set_enc_params_vp8()
1258 reg |= ((p->rc_mb & 0x1) << 8); s5p_mfc_set_enc_params_vp8()
1259 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_vp8()
1263 reg = 0; s5p_mfc_set_enc_params_vp8()
1264 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); s5p_mfc_set_enc_params_vp8()
1265 reg |= p->rc_framerate_denom & 0xFFFF; s5p_mfc_set_enc_params_vp8()
1266 writel(reg, mfc_regs->e_rc_frame_rate); s5p_mfc_set_enc_params_vp8()
1270 reg &= ~(0x7F); s5p_mfc_set_enc_params_vp8()
1271 reg |= p_vp8->rc_frame_qp & 0x7F; s5p_mfc_set_enc_params_vp8()
1272 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_vp8()
1277 reg = 0; s5p_mfc_set_enc_params_vp8()
1278 reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8); s5p_mfc_set_enc_params_vp8()
1279 reg |= p_vp8->rc_frame_qp & 0x7F; s5p_mfc_set_enc_params_vp8()
1280 writel(reg, mfc_regs->e_fixed_picture_qp); s5p_mfc_set_enc_params_vp8()
1284 reg = ((p_vp8->rc_max_qp & 0x7F) << 8); s5p_mfc_set_enc_params_vp8()
1286 reg |= p_vp8->rc_min_qp & 0x7F; s5p_mfc_set_enc_params_vp8()
1287 writel(reg, mfc_regs->e_rc_qp_bound); s5p_mfc_set_enc_params_vp8()
1299 reg = 0; s5p_mfc_set_enc_params_vp8()
1300 reg |= (p_vp8->imd_4x4 & 0x1) << 10; s5p_mfc_set_enc_params_vp8()
1315 reg |= (val & 0xF) << 3; s5p_mfc_set_enc_params_vp8()
1316 reg |= (p_vp8->num_ref & 0x2); s5p_mfc_set_enc_params_vp8()
1317 writel(reg, mfc_regs->e_vp8_options); s5p_mfc_set_enc_params_vp8()
1329 unsigned int reg = 0; s5p_mfc_init_decode_v6() local
1341 reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6); s5p_mfc_init_decode_v6()
1344 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6); s5p_mfc_init_decode_v6()
1349 writel(reg, mfc_regs->d_dec_options); s5p_mfc_init_decode_v6()
1350 reg = 0; s5p_mfc_init_decode_v6()
1357 reg |= (ctx->loop_filter_mpeg4 << s5p_mfc_init_decode_v6()
1361 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6); s5p_mfc_init_decode_v6()
1364 writel(reg, mfc_regs->d_init_buffer_options); s5p_mfc_init_decode_v6()
1366 writel(reg, mfc_regs->d_dec_options); s5p_mfc_init_decode_v6()
2022 #define S5P_MFC_REG_ADDR(dev, reg) ((dev)->regs_base + (reg)) s5p_mfc_init_regs_v6_plus()
/linux-4.1.27/drivers/media/i2c/
H A Dadv7183.c84 static inline int adv7183_read(struct v4l2_subdev *sd, unsigned char reg) adv7183_read() argument
88 return i2c_smbus_read_byte_data(client, reg); adv7183_read()
91 static inline int adv7183_write(struct v4l2_subdev *sd, unsigned char reg, adv7183_write() argument
96 return i2c_smbus_write_byte_data(client, reg, value); adv7183_write()
102 unsigned char reg, data; adv7183_writeregs() local
111 reg = *regs++; adv7183_writeregs()
115 adv7183_write(sd, reg, data); adv7183_writeregs()
212 int reg; adv7183_s_std() local
214 reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF; adv7183_s_std()
216 reg |= 0x60; adv7183_s_std()
218 reg |= 0x70; adv7183_s_std()
220 reg |= 0x90; adv7183_s_std()
222 reg |= 0xA0; adv7183_s_std()
224 reg |= 0xC0; adv7183_s_std()
226 reg |= 0x80; adv7183_s_std()
228 reg |= 0x50; adv7183_s_std()
230 reg |= 0xE0; adv7183_s_std()
233 adv7183_write(sd, ADV7183_IN_CTRL, reg); adv7183_s_std()
242 int reg; adv7183_reset() local
244 reg = adv7183_read(sd, ADV7183_POW_MANAGE) | 0x80; adv7183_reset()
245 adv7183_write(sd, ADV7183_POW_MANAGE, reg); adv7183_reset()
255 int reg; adv7183_s_routing() local
262 reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF0; adv7183_s_routing()
265 reg |= 0x1; adv7183_s_routing()
268 reg |= 0x2; adv7183_s_routing()
271 reg |= 0x3; adv7183_s_routing()
274 reg |= 0x4; adv7183_s_routing()
277 reg |= 0x5; adv7183_s_routing()
280 reg |= 0xB; adv7183_s_routing()
283 reg |= 0xC; adv7183_s_routing()
286 reg |= 0xD; adv7183_s_routing()
289 reg |= 0xE; adv7183_s_routing()
292 reg |= 0xF; adv7183_s_routing()
295 reg |= 0x6; adv7183_s_routing()
298 reg |= 0x7; adv7183_s_routing()
301 reg |= 0x8; adv7183_s_routing()
304 reg |= 0x9; adv7183_s_routing()
307 reg |= 0xA; adv7183_s_routing()
312 adv7183_write(sd, ADV7183_IN_CTRL, reg); adv7183_s_routing()
317 reg = adv7183_read(sd, ADV7183_OUT_CTRL) & 0xC0; adv7183_s_routing()
320 reg |= 0x9; adv7183_s_routing()
323 reg |= 0xC; adv7183_s_routing()
326 adv7183_write(sd, ADV7183_OUT_CTRL, reg); adv7183_s_routing()
364 int reg; adv7183_querystd() local
367 reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF; adv7183_querystd()
368 adv7183_write(sd, ADV7183_IN_CTRL, reg); adv7183_querystd()
374 reg = adv7183_read(sd, ADV7183_STATUS_1); adv7183_querystd()
375 switch ((reg >> 0x4) & 0x7) { adv7183_querystd()
412 int reg; adv7183_g_input_status() local
415 reg = adv7183_read(sd, ADV7183_STATUS_1); adv7183_g_input_status()
416 if (reg < 0) adv7183_g_input_status()
417 return reg; adv7183_g_input_status()
418 if (reg & 0x1) adv7183_g_input_status()
484 static int adv7183_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) adv7183_g_register() argument
486 reg->val = adv7183_read(sd, reg->reg & 0xff); adv7183_g_register()
487 reg->size = 1; adv7183_g_register()
491 static int adv7183_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) adv7183_s_register() argument
493 adv7183_write(sd, reg->reg & 0xff, reg->val & 0xff); adv7183_s_register()
/linux-4.1.27/drivers/media/dvb-frontends/
H A Dstb0899_drv.c225 static int _stb0899_read_reg(struct stb0899_state *state, unsigned int reg) _stb0899_read_reg() argument
229 u8 b0[] = { reg >> 8, reg & 0xff }; _stb0899_read_reg()
251 reg, ret); _stb0899_read_reg()
257 reg, buf); _stb0899_read_reg()
262 int stb0899_read_reg(struct stb0899_state *state, unsigned int reg) stb0899_read_reg() argument
266 result = _stb0899_read_reg(state, reg); stb0899_read_reg()
272 if ((reg != 0xf2ff) && (reg != 0xf6ff) && stb0899_read_reg()
273 (((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600))) stb0899_read_reg()
274 _stb0899_read_reg(state, (reg | 0x00ff)); stb0899_read_reg()
452 int stb0899_read_regs(struct stb0899_state *state, unsigned int reg, u8 *buf, u32 count) stb0899_read_regs() argument
456 u8 b0[] = { reg >> 8, reg & 0xff }; stb0899_read_regs()
476 __func__, reg, count, status); stb0899_read_regs()
484 if ((reg != 0xf2ff) && (reg != 0xf6ff) && stb0899_read_regs()
485 (((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600))) stb0899_read_regs()
486 _stb0899_read_reg(state, (reg | 0x00ff)); stb0899_read_regs()
491 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg); stb0899_read_regs()
503 int stb0899_write_regs(struct stb0899_state *state, unsigned int reg, u8 *data, u32 count) stb0899_write_regs() argument
516 "%s: i2c wr reg=%04x: len=%d is too big!\n", stb0899_write_regs()
517 KBUILD_MODNAME, reg, count); stb0899_write_regs()
521 buf[0] = reg >> 8; stb0899_write_regs()
522 buf[1] = reg & 0xff; stb0899_write_regs()
528 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg); stb0899_write_regs()
540 if ((((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600))) stb0899_write_regs()
541 stb0899_read_reg(state, (reg | 0x00ff)); stb0899_write_regs()
546 reg, data[0], count, ret); stb0899_write_regs()
553 int stb0899_write_reg(struct stb0899_state *state, unsigned int reg, u8 data) stb0899_write_reg() argument
555 return stb0899_write_regs(state, reg, &data, 1); stb0899_write_reg()
651 u32 reg; stb0899_init_calc() local
667 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL); stb0899_init_calc()
668 STB0899_SETFIELD_VAL(IF_GAIN_INIT, reg, internal->agc_gain); stb0899_init_calc()
669 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg); stb0899_init_calc()
671 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, RRC_ALPHA); stb0899_init_calc()
672 internal->rrc_alpha = STB0899_GETFIELD(RRC_ALPHA, reg); stb0899_init_calc()
688 u8 reg = 0; stb0899_wait_diseqc_fifo_empty() local
692 reg = stb0899_read_reg(state, STB0899_DISSTATUS); stb0899_wait_diseqc_fifo_empty()
693 if (!STB0899_GETFIELD(FIFOFULL, reg)) stb0899_wait_diseqc_fifo_empty()
707 u8 reg, i; stb0899_send_diseqc_msg() local
713 reg = stb0899_read_reg(state, STB0899_DISCNTRL1); stb0899_send_diseqc_msg()
714 STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 1); stb0899_send_diseqc_msg()
715 stb0899_write_reg(state, STB0899_DISCNTRL1, reg); stb0899_send_diseqc_msg()
723 reg = stb0899_read_reg(state, STB0899_DISCNTRL1); stb0899_send_diseqc_msg()
724 STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0); stb0899_send_diseqc_msg()
725 stb0899_write_reg(state, STB0899_DISCNTRL1, reg); stb0899_send_diseqc_msg()
732 u8 reg = 0; stb0899_wait_diseqc_rxidle() local
735 while (!STB0899_GETFIELD(RXEND, reg)) { stb0899_wait_diseqc_rxidle()
736 reg = stb0899_read_reg(state, STB0899_DISRX_ST0); stb0899_wait_diseqc_rxidle()
750 u8 reg, length = 0, i; stb0899_recv_slave_reply() local
756 reg = stb0899_read_reg(state, STB0899_DISRX_ST0); stb0899_recv_slave_reply()
757 if (STB0899_GETFIELD(RXEND, reg)) { stb0899_recv_slave_reply()
759 reg = stb0899_read_reg(state, STB0899_DISRX_ST1); stb0899_recv_slave_reply()
760 length = STB0899_GETFIELD(FIFOBYTENBR, reg); stb0899_recv_slave_reply()
781 u8 reg = 0; stb0899_wait_diseqc_txidle() local
784 while (!STB0899_GETFIELD(TXIDLE, reg)) { stb0899_wait_diseqc_txidle()
785 reg = stb0899_read_reg(state, STB0899_DISSTATUS); stb0899_wait_diseqc_txidle()
798 u8 reg, old_state; stb0899_send_diseqc_burst() local
804 reg = stb0899_read_reg(state, STB0899_DISCNTRL1); stb0899_send_diseqc_burst()
805 old_state = reg; stb0899_send_diseqc_burst()
807 STB0899_SETFIELD_VAL(DISEQCMODE, reg, 0x03); stb0899_send_diseqc_burst()
808 STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x01); stb0899_send_diseqc_burst()
809 stb0899_write_reg(state, STB0899_DISCNTRL1, reg); stb0899_send_diseqc_burst()
820 reg = stb0899_read_reg(state, STB0899_DISCNTRL1); stb0899_send_diseqc_burst()
821 STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x00); stb0899_send_diseqc_burst()
822 stb0899_write_reg(state, STB0899_DISCNTRL1, reg); stb0899_send_diseqc_burst()
838 u8 f22_tx, reg; stb0899_diseqc_init() local
841 reg = stb0899_read_reg(state, STB0899_DISCNTRL2); stb0899_diseqc_init()
842 STB0899_SETFIELD_VAL(ONECHIP_TRX, reg, 0); stb0899_diseqc_init()
843 stb0899_write_reg(state, STB0899_DISCNTRL2, reg); stb0899_diseqc_init()
846 reg = stb0899_read_reg(state, STB0899_DISCNTRL1); stb0899_diseqc_init()
847 STB0899_SETFIELD_VAL(DISEQCRESET, reg, 1); stb0899_diseqc_init()
848 stb0899_write_reg(state, STB0899_DISCNTRL1, reg); stb0899_diseqc_init()
850 reg = stb0899_read_reg(state, STB0899_DISCNTRL1); stb0899_diseqc_init()
851 STB0899_SETFIELD_VAL(DISEQCRESET, reg, 0); stb0899_diseqc_init()
852 stb0899_write_reg(state, STB0899_DISCNTRL1, reg); stb0899_diseqc_init()
866 u8 reg; stb0899_sleep()
971 u32 reg; stb0899_read_signal_strength() local
977 reg = stb0899_read_reg(state, STB0899_VSTATUS); stb0899_read_signal_strength()
978 if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) { stb0899_read_signal_strength()
980 reg = stb0899_read_reg(state, STB0899_AGCIQIN); stb0899_read_signal_strength()
981 val = (s32)(s8)STB0899_GETFIELD(AGCIQVALUE, reg); stb0899_read_signal_strength()
992 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_GAIN); stb0899_read_signal_strength()
993 val = STB0899_GETFIELD(IF_AGC_GAIN, reg); stb0899_read_signal_strength()
1016 u32 reg; stb0899_read_snr() local
1019 reg = stb0899_read_reg(state, STB0899_VSTATUS); stb0899_read_snr()
1024 if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) { stb0899_read_snr()
1037 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1); stb0899_read_snr()
1038 quant = STB0899_GETFIELD(UWP_ESN0_QUANT, reg); stb0899_read_snr()
1039 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2); stb0899_read_snr()
1040 est = STB0899_GETFIELD(ESN0_EST, reg); stb0899_read_snr()
1070 u8 reg; stb0899_read_status() local
1078 reg = stb0899_read_reg(state, STB0899_VSTATUS); stb0899_read_status()
1079 if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) { stb0899_read_status()
1083 reg = stb0899_read_reg(state, STB0899_PLPARM); stb0899_read_status()
1084 if (STB0899_GETFIELD(VITCURPUN, reg)) { stb0899_read_status()
1096 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2); stb0899_read_status()
1097 if (STB0899_GETFIELD(UWP_LOCK, reg) && STB0899_GETFIELD(CSM_LOCK, reg)) { stb0899_read_status()
1102 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1); stb0899_read_status()
1103 if (STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg)) { stb0899_read_status()
1109 if (STB0899_GETFIELD(CONTINUOUS_STREAM, reg)) { stb0899_read_status()
1114 if (STB0899_GETFIELD(ACCEPTED_STREAM, reg)) { stb0899_read_status()
1213 u8 div, reg; stb0899_set_tone() local
1224 reg = stb0899_read_reg(state, STB0899_ACRPRESC); stb0899_set_tone()
1225 STB0899_SETFIELD_VAL(ACRPRESC, reg, 0x03); stb0899_set_tone()
1226 stb0899_write_reg(state, STB0899_ACRPRESC, reg); stb0899_set_tone()
1283 dprintk(state->verbose, FE_DEBUG, 1, "ID reg=[0x%02x]", id); stb0899_get_dev_id()
1308 u8 reg; stb0899_set_delivery() local
1318 reg = stb0899_read_reg(state, STB0899_FECM); stb0899_set_delivery()
1319 STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 0); stb0899_set_delivery()
1320 STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 1); stb0899_set_delivery()
1321 stb0899_write_reg(state, STB0899_FECM, reg); stb0899_set_delivery()
1328 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_set_delivery()
1329 STB0899_SETFIELD_VAL(FRESLDPC, reg, 1); stb0899_set_delivery()
1330 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_set_delivery()
1346 reg = stb0899_read_reg(state, STB0899_FECM); stb0899_set_delivery()
1347 STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 0); stb0899_set_delivery()
1348 STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 0); stb0899_set_delivery()
1349 stb0899_write_reg(state, STB0899_FECM, reg); stb0899_set_delivery()
1356 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_set_delivery()
1357 STB0899_SETFIELD_VAL(FRESLDPC, reg, 0); stb0899_set_delivery()
1358 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_set_delivery()
1374 reg = stb0899_read_reg(state, STB0899_FECM); stb0899_set_delivery()
1375 STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 1); stb0899_set_delivery()
1376 STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 1); stb0899_set_delivery()
1377 stb0899_write_reg(state, STB0899_FECM, reg); stb0899_set_delivery()
1383 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_set_delivery()
1384 STB0899_SETFIELD_VAL(FRESLDPC, reg, 1); stb0899_set_delivery()
1385 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_set_delivery()
1416 u32 reg; stb0899_set_iterations() local
1426 reg = STB0899_READ_S2REG(STB0899_S2FEC, MAX_ITER); stb0899_set_iterations()
1427 STB0899_SETFIELD_VAL(MAX_ITERATIONS, reg, iter_scale); stb0899_set_iterations()
1428 stb0899_write_s2reg(state, STB0899_S2FEC, STB0899_BASE_MAX_ITER, STB0899_OFF0_MAX_ITER, reg); stb0899_set_iterations()
H A Dstb0899_algo.c178 u8 reg; stb0899_check_tmg() local
184 reg = stb0899_read_reg(state, STB0899_TLIR); stb0899_check_tmg()
185 lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg); stb0899_check_tmg()
253 u8 reg; stb0899_check_carrier() local
257 reg = stb0899_read_reg(state, STB0899_CFD); stb0899_check_carrier()
258 STB0899_SETFIELD_VAL(CFD_ON, reg, 1); stb0899_check_carrier()
259 stb0899_write_reg(state, STB0899_CFD, reg); stb0899_check_carrier()
261 reg = stb0899_read_reg(state, STB0899_DSTATUS); stb0899_check_carrier()
262 dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg); stb0899_check_carrier()
263 if (STB0899_GETFIELD(CARRIER_FOUND, reg)) { stb0899_check_carrier()
285 u8 reg; stb0899_search_carrier() local
291 reg = stb0899_read_reg(state, STB0899_CFD); stb0899_search_carrier()
292 STB0899_SETFIELD_VAL(CFD_ON, reg, 1); stb0899_search_carrier()
293 stb0899_write_reg(state, STB0899_CFD, reg); stb0899_search_carrier()
306 reg = stb0899_read_reg(state, STB0899_CFD); stb0899_search_carrier()
307 STB0899_SETFIELD_VAL(CFD_ON, reg, 1); stb0899_search_carrier()
308 stb0899_write_reg(state, STB0899_CFD, reg); stb0899_search_carrier()
340 u8 reg; stb0899_check_data() local
345 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_check_data()
346 STB0899_SETFIELD_VAL(FRESACS, reg, 1); stb0899_check_data()
347 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_check_data()
349 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_check_data()
350 STB0899_SETFIELD_VAL(FRESACS, reg, 0); stb0899_check_data()
351 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_check_data()
368 reg = stb0899_read_reg(state, STB0899_VSTATUS); stb0899_check_data()
369 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg); stb0899_check_data()
370 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg); stb0899_check_data()
393 u8 reg; stb0899_search_data() local
412 reg = stb0899_read_reg(state, STB0899_CFD); stb0899_search_data()
413 STB0899_SETFIELD_VAL(CFD_ON, reg, 1); stb0899_search_data()
414 stb0899_write_reg(state, STB0899_CFD, reg); stb0899_search_data()
431 reg = stb0899_read_reg(state, STB0899_IQSWAP); stb0899_search_data()
432 if (STB0899_GETFIELD(SYM, reg)) stb0899_search_data()
507 u8 bclc, reg; stb0899_dvbs_algo() local
574 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_dvbs_algo()
575 STB0899_SETFIELD_VAL(FRESRS, reg, 1); stb0899_dvbs_algo()
576 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_dvbs_algo()
582 reg = stb0899_read_reg(state, STB0899_DEMAPVIT); stb0899_dvbs_algo()
583 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60); stb0899_dvbs_algo()
584 stb0899_write_reg(state, STB0899_DEMAPVIT, reg); stb0899_dvbs_algo()
596 reg = stb0899_read_reg(state, STB0899_CFD); stb0899_dvbs_algo()
597 STB0899_SETFIELD_VAL(CFD_ON, reg, 1); stb0899_dvbs_algo()
598 stb0899_write_reg(state, STB0899_CFD, reg); stb0899_dvbs_algo()
651 reg = stb0899_read_reg(state, STB0899_PLPARM); stb0899_dvbs_algo()
652 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg); stb0899_dvbs_algo()
682 reg = stb0899_read_reg(state, STB0899_BCLC); stb0899_dvbs_algo()
686 STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]); stb0899_dvbs_algo()
687 stb0899_write_reg(state, STB0899_BCLC, reg); stb0899_dvbs_algo()
691 STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]); stb0899_dvbs_algo()
692 stb0899_write_reg(state, STB0899_BCLC, reg); stb0899_dvbs_algo()
696 STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]); stb0899_dvbs_algo()
697 stb0899_write_reg(state, STB0899_BCLC, reg); stb0899_dvbs_algo()
701 STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]); stb0899_dvbs_algo()
702 stb0899_write_reg(state, STB0899_BCLC, reg); stb0899_dvbs_algo()
711 STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]); stb0899_dvbs_algo()
712 stb0899_write_reg(state, STB0899_BCLC, reg); stb0899_dvbs_algo()
719 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_dvbs_algo()
720 STB0899_SETFIELD_VAL(FRESRS, reg, 0); stb0899_dvbs_algo()
721 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_dvbs_algo()
724 reg = stb0899_read_reg(state, STB0899_CFD); stb0899_dvbs_algo()
725 STB0899_SETFIELD_VAL(CFD_ON, reg, 0); stb0899_dvbs_algo()
726 stb0899_write_reg(state, STB0899_CFD, reg); stb0899_dvbs_algo()
742 u32 uwp1, uwp2, uwp3, reg; stb0899_dvbs2_config_uwp() local
763 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO); stb0899_dvbs2_config_uwp()
764 STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout); stb0899_dvbs2_config_uwp()
765 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg); stb0899_dvbs2_config_uwp()
774 u32 reg; stb0899_dvbs2_config_csm_auto() local
776 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1); stb0899_dvbs2_config_csm_auto()
777 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1); stb0899_dvbs2_config_csm_auto()
778 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg); stb0899_dvbs2_config_csm_auto()
854 u32 correction, freq_adj, band_lim, decim_cntrl, reg; stb0899_dvbs2_set_srate() local
890 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL); stb0899_dvbs2_set_srate()
891 STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction); stb0899_dvbs2_set_srate()
892 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg); stb0899_dvbs2_set_srate()
912 u32 reg; stb0899_dvbs2_set_btr_loopbw() local
948 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN); stb0899_dvbs2_set_btr_loopbw()
949 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft); stb0899_dvbs2_set_btr_loopbw()
950 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0); stb0899_dvbs2_set_btr_loopbw()
951 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft); stb0899_dvbs2_set_btr_loopbw()
952 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1); stb0899_dvbs2_set_btr_loopbw()
953 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft); stb0899_dvbs2_set_btr_loopbw()
954 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg); stb0899_dvbs2_set_btr_loopbw()
967 u32 reg; stb0899_dvbs2_set_carr_freq() local
971 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ); stb0899_dvbs2_set_carr_freq()
972 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq); stb0899_dvbs2_set_carr_freq()
973 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); stb0899_dvbs2_set_carr_freq()
984 u32 range, reg; stb0899_dvbs2_init_calc() local
1015 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2); stb0899_dvbs2_init_calc()
1016 STB0899_SETFIELD_VAL(ZIGZAG, reg, 1); stb0899_dvbs2_init_calc()
1017 STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps); stb0899_dvbs2_init_calc()
1018 STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size); stb0899_dvbs2_init_calc()
1019 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg); stb0899_dvbs2_init_calc()
1028 u32 reg; stb0899_dvbs2_btr_init() local
1031 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL); stb0899_dvbs2_btr_init()
1032 STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1); stb0899_dvbs2_btr_init()
1033 STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1); stb0899_dvbs2_btr_init()
1034 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg); stb0899_dvbs2_btr_init()
1051 u32 reg = 0; stb0899_dvbs2_reacquire() local
1054 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1); stb0899_dvbs2_reacquire()
1055 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg); stb0899_dvbs2_reacquire()
1068 reg = 0; stb0899_dvbs2_reacquire()
1069 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0); stb0899_dvbs2_reacquire()
1070 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg); stb0899_dvbs2_reacquire()
1082 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL); stb0899_dvbs2_reacquire()
1083 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0); stb0899_dvbs2_reacquire()
1084 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0); stb0899_dvbs2_reacquire()
1085 STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05); stb0899_dvbs2_reacquire()
1086 STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01); stb0899_dvbs2_reacquire()
1087 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); stb0899_dvbs2_reacquire()
1100 u32 reg; stb0899_dvbs2_get_dmd_status() local
1103 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS); stb0899_dvbs2_get_dmd_status()
1104 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg); stb0899_dvbs2_get_dmd_status()
1105 if (STB0899_GETFIELD(IF_AGC_LOCK, reg)) stb0899_dvbs2_get_dmd_status()
1107 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2); stb0899_dvbs2_get_dmd_status()
1108 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg); stb0899_dvbs2_get_dmd_status()
1109 uwp = STB0899_GETFIELD(UWP_LOCK, reg); stb0899_dvbs2_get_dmd_status()
1110 csm = STB0899_GETFIELD(CSM_LOCK, reg); stb0899_dvbs2_get_dmd_status()
1134 u8 reg; stb0899_dvbs2_get_data_lock() local
1137 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1); stb0899_dvbs2_get_data_lock()
1138 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg); stb0899_dvbs2_get_data_lock()
1139 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg); stb0899_dvbs2_get_data_lock()
1286 u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg; stb0899_dvbs2_get_srate() local
1294 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL); stb0899_dvbs2_get_srate()
1295 decimRate = STB0899_GETFIELD(DECIM_RATE, reg); stb0899_dvbs2_get_srate()
1322 u32 reg, csm1; stb0899_dvbs2_algo() local
1348 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_dvbs2_algo()
1349 STB0899_SETFIELD_VAL(FRESRS, reg, 1); stb0899_dvbs2_algo()
1350 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_dvbs2_algo()
1365 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL); stb0899_dvbs2_algo()
1366 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4); stb0899_dvbs2_algo()
1367 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32); stb0899_dvbs2_algo()
1368 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg); stb0899_dvbs2_algo()
1370 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2); stb0899_dvbs2_algo()
1371 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0); stb0899_dvbs2_algo()
1372 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg); stb0899_dvbs2_algo()
1377 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2); stb0899_dvbs2_algo()
1380 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0); stb0899_dvbs2_algo()
1383 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1); stb0899_dvbs2_algo()
1386 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg); stb0899_dvbs2_algo()
1404 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ); stb0899_dvbs2_algo()
1405 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq); stb0899_dvbs2_algo()
1406 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); stb0899_dvbs2_algo()
1414 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2); stb0899_dvbs2_algo()
1415 iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg); stb0899_dvbs2_algo()
1417 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum); stb0899_dvbs2_algo()
1418 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg); stb0899_dvbs2_algo()
1434 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ); stb0899_dvbs2_algo()
1435 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq); stb0899_dvbs2_algo()
1436 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); stb0899_dvbs2_algo()
1450 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2); stb0899_dvbs2_algo()
1451 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2; stb0899_dvbs2_algo()
1452 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01; stb0899_dvbs2_algo()
1481 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL); stb0899_dvbs2_algo()
1482 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1); stb0899_dvbs2_algo()
1483 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); stb0899_dvbs2_algo()
1487 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL); stb0899_dvbs2_algo()
1488 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02); stb0899_dvbs2_algo()
1489 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); stb0899_dvbs2_algo()
1500 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2); stb0899_dvbs2_algo()
1501 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg)) stb0899_dvbs2_algo()
1509 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2); stb0899_dvbs2_algo()
1510 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2; stb0899_dvbs2_algo()
1511 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01; stb0899_dvbs2_algo()
1512 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01; stb0899_dvbs2_algo()
1515 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL); stb0899_dvbs2_algo()
1516 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3); stb0899_dvbs2_algo()
1520 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16); stb0899_dvbs2_algo()
1522 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg); stb0899_dvbs2_algo()
1524 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2); stb0899_dvbs2_algo()
1525 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7); stb0899_dvbs2_algo()
1526 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg); stb0899_dvbs2_algo()
1530 reg = stb0899_read_reg(state, STB0899_TSTRES); stb0899_dvbs2_algo()
1531 STB0899_SETFIELD_VAL(FRESRS, reg, 0); stb0899_dvbs2_algo()
1532 stb0899_write_reg(state, STB0899_TSTRES, reg); stb0899_dvbs2_algo()
/linux-4.1.27/arch/powerpc/sysdev/
H A Dscom.c58 u64 reg, cnt; scom_map_device() local
67 * We support "scom-reg" properties for adding scom registers scom_map_device()
70 * We also support the simple "reg" property if the device is scom_map_device()
73 * In case both exist, "scom-reg" takes precedence. scom_map_device()
75 prop = of_get_property(dev, "scom-reg", &size); scom_map_device()
78 prop = of_get_property(dev, "reg", &size); scom_map_device()
89 reg = of_read_number(&prop[index * cells * 2], cells); scom_map_device()
92 ret = scom_map(parent, reg, cnt); scom_map_device()
113 u64 reg, reg_cnt, val; scom_debug_read() local
119 reg = off >> 3; scom_debug_read()
122 map = scom_map(ent->dn, reg, reg_cnt); scom_debug_read()
126 for (reg = 0; reg < reg_cnt; reg++) { scom_debug_read()
127 rc = scom_read(map, reg, &val); scom_debug_read()
150 u64 reg, reg_cnt, val; scom_debug_write() local
156 reg = off >> 3; scom_debug_write()
159 map = scom_map(ent->dn, reg, reg_cnt); scom_debug_write()
163 for (reg = 0; reg < reg_cnt; reg++) { scom_debug_write()
166 rc = scom_write(map, reg, val); scom_debug_write()
/linux-4.1.27/arch/m32r/kernel/
H A Dentry.S84 #define R4(reg) @reg
85 #define R5(reg) @(0x04,reg)
86 #define R6(reg) @(0x08,reg)
87 #define PTREGS(reg) @(0x0C,reg)
88 #define R0(reg) @(0x10,reg)
89 #define R1(reg) @(0x14,reg)
90 #define R2(reg) @(0x18,reg)
91 #define R3(reg) @(0x1C,reg)
92 #define R7(reg) @(0x20,reg)
93 #define R8(reg) @(0x24,reg)
94 #define R9(reg) @(0x28,reg)
95 #define R10(reg) @(0x2C,reg)
96 #define R11(reg) @(0x30,reg)
97 #define R12(reg) @(0x34,reg)
98 #define SYSCALL_NR(reg) @(0x38,reg)
99 #define ACC0H(reg) @(0x3C,reg)
100 #define ACC0L(reg) @(0x40,reg)
101 #define ACC1H(reg) @(0x44,reg)
102 #define ACC1L(reg) @(0x48,reg)
103 #define PSW(reg) @(0x4C,reg)
104 #define BPC(reg) @(0x50,reg)
105 #define BBPSW(reg) @(0x54,reg)
106 #define BBPC(reg) @(0x58,reg)
107 #define SPU(reg) @(0x5C,reg)
108 #define FP(reg) @(0x60,reg) /* FP = R13 */
109 #define LR(reg) @(0x64,reg)
110 #define SP(reg) @(0x68,reg)
111 #define ORIG_R0(reg) @(0x6C,reg)
123 #define GET_THREAD_INFO(reg) GET_THREAD_INFO reg
124 .macro GET_THREAD_INFO reg
125 ldi \reg, #-THREAD_SIZE
126 and \reg, sp
/linux-4.1.27/arch/mips/include/asm/mach-pnx833x/
H A Dpnx833x.h33 #define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field)
34 #define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field)
37 #define PNX_FIELD(cpu, val, reg, field) \
38 (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \
39 PNX##cpu##_##reg##_##field##_SHIFT)
40 #define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field)
41 #define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field)
42 #define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field)
45 #define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field)
46 #define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field)
47 #define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field)
50 #define PNX_WRITEFIELD(cpu, val, reg, field) \
51 (PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \
52 ((val) << PNX##cpu##_##reg##_##field##_SHIFT))
53 #define PNX833X_WRITEFIELD(val, reg, field) \
54 PNX_WRITEFIELD(833X, val, reg, field)
55 #define PNX8330_WRITEFIELD(val, reg, field) \
56 PNX_WRITEFIELD(8330, val, reg, field)
57 #define PNX8335_WRITEFIELD(val, reg, field) \
58 PNX_WRITEFIELD(8335, val, reg, field)
/linux-4.1.27/arch/arm64/kvm/
H A Dguest.c49 static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) get_core_reg() argument
57 __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr; get_core_reg()
63 off = core_reg_offset_from_id(reg->id); get_core_reg()
65 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs) get_core_reg()
68 if (copy_to_user(uaddr, ((u32 *)regs) + off, KVM_REG_SIZE(reg->id))) get_core_reg()
74 static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) set_core_reg() argument
76 __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr; set_core_reg()
85 off = core_reg_offset_from_id(reg->id); set_core_reg()
87 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs) set_core_reg()
90 if (KVM_REG_SIZE(reg->id) > sizeof(tmp)) set_core_reg()
93 if (copy_from_user(valp, uaddr, KVM_REG_SIZE(reg->id))) { set_core_reg()
117 memcpy((u32 *)regs + off, valp, KVM_REG_SIZE(reg->id)); set_core_reg()
168 static int set_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) set_timer_reg() argument
170 void __user *uaddr = (void __user *)(long)reg->addr; set_timer_reg()
174 ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id)); set_timer_reg()
178 return kvm_arm_timer_set_reg(vcpu, reg->id, val); set_timer_reg()
181 static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) get_timer_reg() argument
183 void __user *uaddr = (void __user *)(long)reg->addr; get_timer_reg()
186 val = kvm_arm_timer_get_reg(vcpu, reg->id); get_timer_reg()
187 return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0; get_timer_reg()
226 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) kvm_arm_get_reg() argument
229 if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32) kvm_arm_get_reg()
233 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE) kvm_arm_get_reg()
234 return get_core_reg(vcpu, reg); kvm_arm_get_reg()
236 if (is_timer_reg(reg->id)) kvm_arm_get_reg()
237 return get_timer_reg(vcpu, reg); kvm_arm_get_reg()
239 return kvm_arm_sys_reg_get_reg(vcpu, reg); kvm_arm_get_reg()
242 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) kvm_arm_set_reg() argument
245 if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32) kvm_arm_set_reg()
249 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE) kvm_arm_set_reg()
250 return set_core_reg(vcpu, reg); kvm_arm_set_reg()
252 if (is_timer_reg(reg->id)) kvm_arm_set_reg()
253 return set_timer_reg(vcpu, reg); kvm_arm_set_reg()
255 return kvm_arm_sys_reg_set_reg(vcpu, reg); kvm_arm_set_reg()
/linux-4.1.27/drivers/mmc/host/
H A Dsdhci-pltfm.h40 static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg) sdhci_be32bs_readl() argument
42 return in_be32(host->ioaddr + reg); sdhci_be32bs_readl()
45 static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg) sdhci_be32bs_readw() argument
47 return in_be16(host->ioaddr + (reg ^ 0x2)); sdhci_be32bs_readw()
50 static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg) sdhci_be32bs_readb() argument
52 return in_8(host->ioaddr + (reg ^ 0x3)); sdhci_be32bs_readb()
56 u32 val, int reg) sdhci_be32bs_writel()
58 out_be32(host->ioaddr + reg, val); sdhci_be32bs_writel()
62 u16 val, int reg) sdhci_be32bs_writew()
65 int base = reg & ~0x3; sdhci_be32bs_writew()
66 int shift = (reg & 0x2) * 8; sdhci_be32bs_writew()
68 switch (reg) { sdhci_be32bs_writew()
85 static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg) sdhci_be32bs_writeb() argument
87 int base = reg & ~0x3; sdhci_be32bs_writeb()
88 int shift = (reg & 0x3) * 8; sdhci_be32bs_writeb()
55 sdhci_be32bs_writel(struct sdhci_host *host, u32 val, int reg) sdhci_be32bs_writel() argument
61 sdhci_be32bs_writew(struct sdhci_host *host, u16 val, int reg) sdhci_be32bs_writew() argument
/linux-4.1.27/drivers/cpufreq/
H A Ds5pv210-cpufreq.c201 void __iomem *reg = NULL; s5pv210_set_refresh() local
204 reg = (dmc_base[0] + 0x30); s5pv210_set_refresh()
206 reg = (dmc_base[1] + 0x30); s5pv210_set_refresh()
221 __raw_writel(tmp1, reg); s5pv210_set_refresh()
226 unsigned long reg; s5pv210_target() local
302 reg = __raw_readl(S5P_CLK_DIV2); s5pv210_target()
303 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK); s5pv210_target()
304 reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) | s5pv210_target()
306 __raw_writel(reg, S5P_CLK_DIV2); s5pv210_target()
310 reg = __raw_readl(S5P_CLKDIV_STAT0); s5pv210_target()
311 } while (reg & ((1 << 16) | (1 << 17))); s5pv210_target()
317 reg = __raw_readl(S5P_CLK_SRC2); s5pv210_target()
318 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK); s5pv210_target()
319 reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) | s5pv210_target()
321 __raw_writel(reg, S5P_CLK_SRC2); s5pv210_target()
324 reg = __raw_readl(S5P_CLKMUX_STAT1); s5pv210_target()
325 } while (reg & ((1 << 7) | (1 << 3))); s5pv210_target()
336 reg = __raw_readl(S5P_CLK_SRC0); s5pv210_target()
337 reg &= ~(S5P_CLKSRC0_MUX200_MASK); s5pv210_target()
338 reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT); s5pv210_target()
339 __raw_writel(reg, S5P_CLK_SRC0); s5pv210_target()
342 reg = __raw_readl(S5P_CLKMUX_STAT0); s5pv210_target()
343 } while (reg & (0x1 << 18)); s5pv210_target()
348 reg = __raw_readl(S5P_CLK_DIV0); s5pv210_target()
350 reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK | s5pv210_target()
355 reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) | s5pv210_target()
364 __raw_writel(reg, S5P_CLK_DIV0); s5pv210_target()
367 reg = __raw_readl(S5P_CLKDIV_STAT0); s5pv210_target()
368 } while (reg & 0xff); s5pv210_target()
371 reg = __raw_readl(S5P_ARM_MCS_CON); s5pv210_target()
372 reg &= ~0x3; s5pv210_target()
374 reg |= 0x3; s5pv210_target()
376 reg |= 0x1; s5pv210_target()
378 __raw_writel(reg, S5P_ARM_MCS_CON); s5pv210_target()
395 reg = __raw_readl(S5P_APLL_CON); s5pv210_target()
396 } while (!(reg & (0x1 << 29))); s5pv210_target()
403 reg = __raw_readl(S5P_CLK_SRC2); s5pv210_target()
404 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK); s5pv210_target()
405 reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) | s5pv210_target()
407 __raw_writel(reg, S5P_CLK_SRC2); s5pv210_target()
410 reg = __raw_readl(S5P_CLKMUX_STAT1); s5pv210_target()
411 } while (reg & ((1 << 7) | (1 << 3))); s5pv210_target()
417 reg = __raw_readl(S5P_CLK_DIV2); s5pv210_target()
418 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK); s5pv210_target()
419 reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) | s5pv210_target()
421 __raw_writel(reg, S5P_CLK_DIV2); s5pv210_target()
425 reg = __raw_readl(S5P_CLKDIV_STAT0); s5pv210_target()
426 } while (reg & ((1 << 16) | (1 << 17))); s5pv210_target()
429 reg = __raw_readl(S5P_CLK_SRC0); s5pv210_target()
430 reg &= ~(S5P_CLKSRC0_MUX200_MASK); s5pv210_target()
431 reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT); s5pv210_target()
432 __raw_writel(reg, S5P_CLK_SRC0); s5pv210_target()
435 reg = __raw_readl(S5P_CLKMUX_STAT0); s5pv210_target()
436 } while (reg & (0x1 << 18)); s5pv210_target()
452 reg = __raw_readl(S5P_CLK_DIV6); s5pv210_target()
453 reg &= ~S5P_CLKDIV6_ONEDRAM_MASK; s5pv210_target()
454 reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT); s5pv210_target()
455 __raw_writel(reg, S5P_CLK_DIV6); s5pv210_target()
458 reg = __raw_readl(S5P_CLKDIV_STAT1); s5pv210_target()
459 } while (reg & (1 << 15)); s5pv210_target()
/linux-4.1.27/arch/alpha/oprofile/
H A Dop_model_ev6.c20 ev6_reg_setup(struct op_register_config *reg, ev6_reg_setup() argument
33 reg->mux_select = ctl; ev6_reg_setup()
39 reg->proc_mode = 0; ev6_reg_setup()
58 reg->reset_values = reset; ev6_reg_setup()
59 reg->need_reset = need_reset; ev6_reg_setup()
67 struct op_register_config *reg = x; ev6_cpu_setup() local
69 wrperfmon(2, reg->mux_select); ev6_cpu_setup()
70 wrperfmon(3, reg->proc_mode); ev6_cpu_setup()
71 wrperfmon(6, reg->reset_values | 3); ev6_cpu_setup()
79 ev6_reset_ctr(struct op_register_config *reg, unsigned long ctr) ev6_reset_ctr() argument
81 wrperfmon(6, reg->reset_values | (1 << ctr)); ev6_reset_ctr()
/linux-4.1.27/drivers/rtc/
H A Drtc-m48t35.c44 struct m48t35_rtc __iomem *reg; member in struct:m48t35_priv
62 control = readb(&priv->reg->control); m48t35_read_time()
63 writeb(control | M48T35_RTC_READ, &priv->reg->control); m48t35_read_time()
64 tm->tm_sec = readb(&priv->reg->sec); m48t35_read_time()
65 tm->tm_min = readb(&priv->reg->min); m48t35_read_time()
66 tm->tm_hour = readb(&priv->reg->hour); m48t35_read_time()
67 tm->tm_mday = readb(&priv->reg->date); m48t35_read_time()
68 tm->tm_mon = readb(&priv->reg->month); m48t35_read_time()
69 tm->tm_year = readb(&priv->reg->year); m48t35_read_time()
70 writeb(control, &priv->reg->control); m48t35_read_time()
127 control = readb(&priv->reg->control); m48t35_set_time()
128 writeb(control | M48T35_RTC_SET, &priv->reg->control); m48t35_set_time()
129 writeb(yrs, &priv->reg->year); m48t35_set_time()
130 writeb(mon, &priv->reg->month); m48t35_set_time()
131 writeb(day, &priv->reg->date); m48t35_set_time()
132 writeb(hrs, &priv->reg->hour); m48t35_set_time()
133 writeb(min, &priv->reg->min); m48t35_set_time()
134 writeb(sec, &priv->reg->sec); m48t35_set_time()
135 writeb(control, &priv->reg->control); m48t35_set_time()
168 priv->reg = devm_ioremap(&pdev->dev, priv->baseaddr, priv->size); m48t35_probe()
169 if (!priv->reg) m48t35_probe()

Completed in 6831 milliseconds

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