1/*
2 * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/of.h>
10#include <linux/mm.h>
11
12#include <asm/cacheflush.h>
13
14#include <dt-bindings/memory/tegra30-mc.h>
15
16#include "mc.h"
17
18static const struct tegra_mc_client tegra30_mc_clients[] = {
19	{
20		.id = 0x00,
21		.name = "ptcr",
22		.swgroup = TEGRA_SWGROUP_PTC,
23	}, {
24		.id = 0x01,
25		.name = "display0a",
26		.swgroup = TEGRA_SWGROUP_DC,
27		.smmu = {
28			.reg = 0x228,
29			.bit = 1,
30		},
31		.la = {
32			.reg = 0x2e8,
33			.shift = 0,
34			.mask = 0xff,
35			.def = 0x4e,
36		},
37	}, {
38		.id = 0x02,
39		.name = "display0ab",
40		.swgroup = TEGRA_SWGROUP_DCB,
41		.smmu = {
42			.reg = 0x228,
43			.bit = 2,
44		},
45		.la = {
46			.reg = 0x2f4,
47			.shift = 0,
48			.mask = 0xff,
49			.def = 0x4e,
50		},
51	}, {
52		.id = 0x03,
53		.name = "display0b",
54		.swgroup = TEGRA_SWGROUP_DC,
55		.smmu = {
56			.reg = 0x228,
57			.bit = 3,
58		},
59		.la = {
60			.reg = 0x2e8,
61			.shift = 16,
62			.mask = 0xff,
63			.def = 0x4e,
64		},
65	}, {
66		.id = 0x04,
67		.name = "display0bb",
68		.swgroup = TEGRA_SWGROUP_DCB,
69		.smmu = {
70			.reg = 0x228,
71			.bit = 4,
72		},
73		.la = {
74			.reg = 0x2f4,
75			.shift = 16,
76			.mask = 0xff,
77			.def = 0x4e,
78		},
79	}, {
80		.id = 0x05,
81		.name = "display0c",
82		.swgroup = TEGRA_SWGROUP_DC,
83		.smmu = {
84			.reg = 0x228,
85			.bit = 5,
86		},
87		.la = {
88			.reg = 0x2ec,
89			.shift = 0,
90			.mask = 0xff,
91			.def = 0x4e,
92		},
93	}, {
94		.id = 0x06,
95		.name = "display0cb",
96		.swgroup = TEGRA_SWGROUP_DCB,
97		.smmu = {
98			.reg = 0x228,
99			.bit = 6,
100		},
101		.la = {
102			.reg = 0x2f8,
103			.shift = 0,
104			.mask = 0xff,
105			.def = 0x4e,
106		},
107	}, {
108		.id = 0x07,
109		.name = "display1b",
110		.swgroup = TEGRA_SWGROUP_DC,
111		.smmu = {
112			.reg = 0x228,
113			.bit = 7,
114		},
115		.la = {
116			.reg = 0x2ec,
117			.shift = 16,
118			.mask = 0xff,
119			.def = 0x4e,
120		},
121	}, {
122		.id = 0x08,
123		.name = "display1bb",
124		.swgroup = TEGRA_SWGROUP_DCB,
125		.smmu = {
126			.reg = 0x228,
127			.bit = 8,
128		},
129		.la = {
130			.reg = 0x2f8,
131			.shift = 16,
132			.mask = 0xff,
133			.def = 0x4e,
134		},
135	}, {
136		.id = 0x09,
137		.name = "eppup",
138		.swgroup = TEGRA_SWGROUP_EPP,
139		.smmu = {
140			.reg = 0x228,
141			.bit = 9,
142		},
143		.la = {
144			.reg = 0x300,
145			.shift = 0,
146			.mask = 0xff,
147			.def = 0x17,
148		},
149	}, {
150		.id = 0x0a,
151		.name = "g2pr",
152		.swgroup = TEGRA_SWGROUP_G2,
153		.smmu = {
154			.reg = 0x228,
155			.bit = 10,
156		},
157		.la = {
158			.reg = 0x308,
159			.shift = 0,
160			.mask = 0xff,
161			.def = 0x09,
162		},
163	}, {
164		.id = 0x0b,
165		.name = "g2sr",
166		.swgroup = TEGRA_SWGROUP_G2,
167		.smmu = {
168			.reg = 0x228,
169			.bit = 11,
170		},
171		.la = {
172			.reg = 0x308,
173			.shift = 16,
174			.mask = 0xff,
175			.def = 0x09,
176		},
177	}, {
178		.id = 0x0c,
179		.name = "mpeunifbr",
180		.swgroup = TEGRA_SWGROUP_MPE,
181		.smmu = {
182			.reg = 0x228,
183			.bit = 12,
184		},
185		.la = {
186			.reg = 0x328,
187			.shift = 0,
188			.mask = 0xff,
189			.def = 0x50,
190		},
191	}, {
192		.id = 0x0d,
193		.name = "viruv",
194		.swgroup = TEGRA_SWGROUP_VI,
195		.smmu = {
196			.reg = 0x228,
197			.bit = 13,
198		},
199		.la = {
200			.reg = 0x364,
201			.shift = 0,
202			.mask = 0xff,
203			.def = 0x2c,
204		},
205	}, {
206		.id = 0x0e,
207		.name = "afir",
208		.swgroup = TEGRA_SWGROUP_AFI,
209		.smmu = {
210			.reg = 0x228,
211			.bit = 14,
212		},
213		.la = {
214			.reg = 0x2e0,
215			.shift = 0,
216			.mask = 0xff,
217			.def = 0x10,
218		},
219	}, {
220		.id = 0x0f,
221		.name = "avpcarm7r",
222		.swgroup = TEGRA_SWGROUP_AVPC,
223		.smmu = {
224			.reg = 0x228,
225			.bit = 15,
226		},
227		.la = {
228			.reg = 0x2e4,
229			.shift = 0,
230			.mask = 0xff,
231			.def = 0x04,
232		},
233	}, {
234		.id = 0x10,
235		.name = "displayhc",
236		.swgroup = TEGRA_SWGROUP_DC,
237		.smmu = {
238			.reg = 0x228,
239			.bit = 16,
240		},
241		.la = {
242			.reg = 0x2f0,
243			.shift = 0,
244			.mask = 0xff,
245			.def = 0xff,
246		},
247	}, {
248		.id = 0x11,
249		.name = "displayhcb",
250		.swgroup = TEGRA_SWGROUP_DCB,
251		.smmu = {
252			.reg = 0x228,
253			.bit = 17,
254		},
255		.la = {
256			.reg = 0x2fc,
257			.shift = 0,
258			.mask = 0xff,
259			.def = 0xff,
260		},
261	}, {
262		.id = 0x12,
263		.name = "fdcdrd",
264		.swgroup = TEGRA_SWGROUP_NV,
265		.smmu = {
266			.reg = 0x228,
267			.bit = 18,
268		},
269		.la = {
270			.reg = 0x334,
271			.shift = 0,
272			.mask = 0xff,
273			.def = 0x0a,
274		},
275	}, {
276		.id = 0x13,
277		.name = "fdcdrd2",
278		.swgroup = TEGRA_SWGROUP_NV2,
279		.smmu = {
280			.reg = 0x228,
281			.bit = 19,
282		},
283		.la = {
284			.reg = 0x33c,
285			.shift = 0,
286			.mask = 0xff,
287			.def = 0x0a,
288		},
289	}, {
290		.id = 0x14,
291		.name = "g2dr",
292		.swgroup = TEGRA_SWGROUP_G2,
293		.smmu = {
294			.reg = 0x228,
295			.bit = 20,
296		},
297		.la = {
298			.reg = 0x30c,
299			.shift = 0,
300			.mask = 0xff,
301			.def = 0x0a,
302		},
303	}, {
304		.id = 0x15,
305		.name = "hdar",
306		.swgroup = TEGRA_SWGROUP_HDA,
307		.smmu = {
308			.reg = 0x228,
309			.bit = 21,
310		},
311		.la = {
312			.reg = 0x318,
313			.shift = 0,
314			.mask = 0xff,
315			.def = 0xff,
316		},
317	}, {
318		.id = 0x16,
319		.name = "host1xdmar",
320		.swgroup = TEGRA_SWGROUP_HC,
321		.smmu = {
322			.reg = 0x228,
323			.bit = 22,
324		},
325		.la = {
326			.reg = 0x310,
327			.shift = 0,
328			.mask = 0xff,
329			.def = 0x05,
330		},
331	}, {
332		.id = 0x17,
333		.name = "host1xr",
334		.swgroup = TEGRA_SWGROUP_HC,
335		.smmu = {
336			.reg = 0x228,
337			.bit = 23,
338		},
339		.la = {
340			.reg = 0x310,
341			.shift = 16,
342			.mask = 0xff,
343			.def = 0x50,
344		},
345	}, {
346		.id = 0x18,
347		.name = "idxsrd",
348		.swgroup = TEGRA_SWGROUP_NV,
349		.smmu = {
350			.reg = 0x228,
351			.bit = 24,
352		},
353		.la = {
354			.reg = 0x334,
355			.shift = 16,
356			.mask = 0xff,
357			.def = 0x13,
358		},
359	}, {
360		.id = 0x19,
361		.name = "idxsrd2",
362		.swgroup = TEGRA_SWGROUP_NV2,
363		.smmu = {
364			.reg = 0x228,
365			.bit = 25,
366		},
367		.la = {
368			.reg = 0x33c,
369			.shift = 16,
370			.mask = 0xff,
371			.def = 0x13,
372		},
373	}, {
374		.id = 0x1a,
375		.name = "mpe_ipred",
376		.swgroup = TEGRA_SWGROUP_MPE,
377		.smmu = {
378			.reg = 0x228,
379			.bit = 26,
380		},
381		.la = {
382			.reg = 0x328,
383			.shift = 16,
384			.mask = 0xff,
385			.def = 0x80,
386		},
387	}, {
388		.id = 0x1b,
389		.name = "mpeamemrd",
390		.swgroup = TEGRA_SWGROUP_MPE,
391		.smmu = {
392			.reg = 0x228,
393			.bit = 27,
394		},
395		.la = {
396			.reg = 0x32c,
397			.shift = 0,
398			.mask = 0xff,
399			.def = 0x42,
400		},
401	}, {
402		.id = 0x1c,
403		.name = "mpecsrd",
404		.swgroup = TEGRA_SWGROUP_MPE,
405		.smmu = {
406			.reg = 0x228,
407			.bit = 28,
408		},
409		.la = {
410			.reg = 0x32c,
411			.shift = 16,
412			.mask = 0xff,
413			.def = 0xff,
414		},
415	}, {
416		.id = 0x1d,
417		.name = "ppcsahbdmar",
418		.swgroup = TEGRA_SWGROUP_PPCS,
419		.smmu = {
420			.reg = 0x228,
421			.bit = 29,
422		},
423		.la = {
424			.reg = 0x344,
425			.shift = 0,
426			.mask = 0xff,
427			.def = 0x10,
428		},
429	}, {
430		.id = 0x1e,
431		.name = "ppcsahbslvr",
432		.swgroup = TEGRA_SWGROUP_PPCS,
433		.smmu = {
434			.reg = 0x228,
435			.bit = 30,
436		},
437		.la = {
438			.reg = 0x344,
439			.shift = 16,
440			.mask = 0xff,
441			.def = 0x12,
442		},
443	}, {
444		.id = 0x1f,
445		.name = "satar",
446		.swgroup = TEGRA_SWGROUP_SATA,
447		.smmu = {
448			.reg = 0x228,
449			.bit = 31,
450		},
451		.la = {
452			.reg = 0x350,
453			.shift = 0,
454			.mask = 0xff,
455			.def = 0x33,
456		},
457	}, {
458		.id = 0x20,
459		.name = "texsrd",
460		.swgroup = TEGRA_SWGROUP_NV,
461		.smmu = {
462			.reg = 0x22c,
463			.bit = 0,
464		},
465		.la = {
466			.reg = 0x338,
467			.shift = 0,
468			.mask = 0xff,
469			.def = 0x13,
470		},
471	}, {
472		.id = 0x21,
473		.name = "texsrd2",
474		.swgroup = TEGRA_SWGROUP_NV2,
475		.smmu = {
476			.reg = 0x22c,
477			.bit = 1,
478		},
479		.la = {
480			.reg = 0x340,
481			.shift = 0,
482			.mask = 0xff,
483			.def = 0x13,
484		},
485	}, {
486		.id = 0x22,
487		.name = "vdebsevr",
488		.swgroup = TEGRA_SWGROUP_VDE,
489		.smmu = {
490			.reg = 0x22c,
491			.bit = 2,
492		},
493		.la = {
494			.reg = 0x354,
495			.shift = 0,
496			.mask = 0xff,
497			.def = 0xff,
498		},
499	}, {
500		.id = 0x23,
501		.name = "vdember",
502		.swgroup = TEGRA_SWGROUP_VDE,
503		.smmu = {
504			.reg = 0x22c,
505			.bit = 3,
506		},
507		.la = {
508			.reg = 0x354,
509			.shift = 16,
510			.mask = 0xff,
511			.def = 0xd0,
512		},
513	}, {
514		.id = 0x24,
515		.name = "vdemcer",
516		.swgroup = TEGRA_SWGROUP_VDE,
517		.smmu = {
518			.reg = 0x22c,
519			.bit = 4,
520		},
521		.la = {
522			.reg = 0x358,
523			.shift = 0,
524			.mask = 0xff,
525			.def = 0x2a,
526		},
527	}, {
528		.id = 0x25,
529		.name = "vdetper",
530		.swgroup = TEGRA_SWGROUP_VDE,
531		.smmu = {
532			.reg = 0x22c,
533			.bit = 5,
534		},
535		.la = {
536			.reg = 0x358,
537			.shift = 16,
538			.mask = 0xff,
539			.def = 0x74,
540		},
541	}, {
542		.id = 0x26,
543		.name = "mpcorelpr",
544		.swgroup = TEGRA_SWGROUP_MPCORELP,
545		.la = {
546			.reg = 0x324,
547			.shift = 0,
548			.mask = 0xff,
549			.def = 0x04,
550		},
551	}, {
552		.id = 0x27,
553		.name = "mpcorer",
554		.swgroup = TEGRA_SWGROUP_MPCORE,
555		.la = {
556			.reg = 0x320,
557			.shift = 0,
558			.mask = 0xff,
559			.def = 0x04,
560		},
561	}, {
562		.id = 0x28,
563		.name = "eppu",
564		.swgroup = TEGRA_SWGROUP_EPP,
565		.smmu = {
566			.reg = 0x22c,
567			.bit = 8,
568		},
569		.la = {
570			.reg = 0x300,
571			.shift = 16,
572			.mask = 0xff,
573			.def = 0x6c,
574		},
575	}, {
576		.id = 0x29,
577		.name = "eppv",
578		.swgroup = TEGRA_SWGROUP_EPP,
579		.smmu = {
580			.reg = 0x22c,
581			.bit = 9,
582		},
583		.la = {
584			.reg = 0x304,
585			.shift = 0,
586			.mask = 0xff,
587			.def = 0x6c,
588		},
589	}, {
590		.id = 0x2a,
591		.name = "eppy",
592		.swgroup = TEGRA_SWGROUP_EPP,
593		.smmu = {
594			.reg = 0x22c,
595			.bit = 10,
596		},
597		.la = {
598			.reg = 0x304,
599			.shift = 16,
600			.mask = 0xff,
601			.def = 0x6c,
602		},
603	}, {
604		.id = 0x2b,
605		.name = "mpeunifbw",
606		.swgroup = TEGRA_SWGROUP_MPE,
607		.smmu = {
608			.reg = 0x22c,
609			.bit = 11,
610		},
611		.la = {
612			.reg = 0x330,
613			.shift = 0,
614			.mask = 0xff,
615			.def = 0x13,
616		},
617	}, {
618		.id = 0x2c,
619		.name = "viwsb",
620		.swgroup = TEGRA_SWGROUP_VI,
621		.smmu = {
622			.reg = 0x22c,
623			.bit = 12,
624		},
625		.la = {
626			.reg = 0x364,
627			.shift = 16,
628			.mask = 0xff,
629			.def = 0x12,
630		},
631	}, {
632		.id = 0x2d,
633		.name = "viwu",
634		.swgroup = TEGRA_SWGROUP_VI,
635		.smmu = {
636			.reg = 0x22c,
637			.bit = 13,
638		},
639		.la = {
640			.reg = 0x368,
641			.shift = 0,
642			.mask = 0xff,
643			.def = 0xb2,
644		},
645	}, {
646		.id = 0x2e,
647		.name = "viwv",
648		.swgroup = TEGRA_SWGROUP_VI,
649		.smmu = {
650			.reg = 0x22c,
651			.bit = 14,
652		},
653		.la = {
654			.reg = 0x368,
655			.shift = 16,
656			.mask = 0xff,
657			.def = 0xb2,
658		},
659	}, {
660		.id = 0x2f,
661		.name = "viwy",
662		.swgroup = TEGRA_SWGROUP_VI,
663		.smmu = {
664			.reg = 0x22c,
665			.bit = 15,
666		},
667		.la = {
668			.reg = 0x36c,
669			.shift = 0,
670			.mask = 0xff,
671			.def = 0x12,
672		},
673	}, {
674		.id = 0x30,
675		.name = "g2dw",
676		.swgroup = TEGRA_SWGROUP_G2,
677		.smmu = {
678			.reg = 0x22c,
679			.bit = 16,
680		},
681		.la = {
682			.reg = 0x30c,
683			.shift = 16,
684			.mask = 0xff,
685			.def = 0x9,
686		},
687	}, {
688		.id = 0x31,
689		.name = "afiw",
690		.swgroup = TEGRA_SWGROUP_AFI,
691		.smmu = {
692			.reg = 0x22c,
693			.bit = 17,
694		},
695		.la = {
696			.reg = 0x2e0,
697			.shift = 16,
698			.mask = 0xff,
699			.def = 0x0c,
700		},
701	}, {
702		.id = 0x32,
703		.name = "avpcarm7w",
704		.swgroup = TEGRA_SWGROUP_AVPC,
705		.smmu = {
706			.reg = 0x22c,
707			.bit = 18,
708		},
709		.la = {
710			.reg = 0x2e4,
711			.shift = 16,
712			.mask = 0xff,
713			.def = 0x0e,
714		},
715	}, {
716		.id = 0x33,
717		.name = "fdcdwr",
718		.swgroup = TEGRA_SWGROUP_NV,
719		.smmu = {
720			.reg = 0x22c,
721			.bit = 19,
722		},
723		.la = {
724			.reg = 0x338,
725			.shift = 16,
726			.mask = 0xff,
727			.def = 0x0a,
728		},
729	}, {
730		.id = 0x34,
731		.name = "fdcwr2",
732		.swgroup = TEGRA_SWGROUP_NV2,
733		.smmu = {
734			.reg = 0x22c,
735			.bit = 20,
736		},
737		.la = {
738			.reg = 0x340,
739			.shift = 16,
740			.mask = 0xff,
741			.def = 0x0a,
742		},
743	}, {
744		.id = 0x35,
745		.name = "hdaw",
746		.swgroup = TEGRA_SWGROUP_HDA,
747		.smmu = {
748			.reg = 0x22c,
749			.bit = 21,
750		},
751		.la = {
752			.reg = 0x318,
753			.shift = 16,
754			.mask = 0xff,
755			.def = 0xff,
756		},
757	}, {
758		.id = 0x36,
759		.name = "host1xw",
760		.swgroup = TEGRA_SWGROUP_HC,
761		.smmu = {
762			.reg = 0x22c,
763			.bit = 22,
764		},
765		.la = {
766			.reg = 0x314,
767			.shift = 0,
768			.mask = 0xff,
769			.def = 0x10,
770		},
771	}, {
772		.id = 0x37,
773		.name = "ispw",
774		.swgroup = TEGRA_SWGROUP_ISP,
775		.smmu = {
776			.reg = 0x22c,
777			.bit = 23,
778		},
779		.la = {
780			.reg = 0x31c,
781			.shift = 0,
782			.mask = 0xff,
783			.def = 0xff,
784		},
785	}, {
786		.id = 0x38,
787		.name = "mpcorelpw",
788		.swgroup = TEGRA_SWGROUP_MPCORELP,
789		.la = {
790			.reg = 0x324,
791			.shift = 16,
792			.mask = 0xff,
793			.def = 0x0e,
794		},
795	}, {
796		.id = 0x39,
797		.name = "mpcorew",
798		.swgroup = TEGRA_SWGROUP_MPCORE,
799		.la = {
800			.reg = 0x320,
801			.shift = 16,
802			.mask = 0xff,
803			.def = 0x0e,
804		},
805	}, {
806		.id = 0x3a,
807		.name = "mpecswr",
808		.swgroup = TEGRA_SWGROUP_MPE,
809		.smmu = {
810			.reg = 0x22c,
811			.bit = 26,
812		},
813		.la = {
814			.reg = 0x330,
815			.shift = 16,
816			.mask = 0xff,
817			.def = 0xff,
818		},
819	}, {
820		.id = 0x3b,
821		.name = "ppcsahbdmaw",
822		.swgroup = TEGRA_SWGROUP_PPCS,
823		.smmu = {
824			.reg = 0x22c,
825			.bit = 27,
826		},
827		.la = {
828			.reg = 0x348,
829			.shift = 0,
830			.mask = 0xff,
831			.def = 0x10,
832		},
833	}, {
834		.id = 0x3c,
835		.name = "ppcsahbslvw",
836		.swgroup = TEGRA_SWGROUP_PPCS,
837		.smmu = {
838			.reg = 0x22c,
839			.bit = 28,
840		},
841		.la = {
842			.reg = 0x348,
843			.shift = 16,
844			.mask = 0xff,
845			.def = 0x06,
846		},
847	}, {
848		.id = 0x3d,
849		.name = "sataw",
850		.swgroup = TEGRA_SWGROUP_SATA,
851		.smmu = {
852			.reg = 0x22c,
853			.bit = 29,
854		},
855		.la = {
856			.reg = 0x350,
857			.shift = 16,
858			.mask = 0xff,
859			.def = 0x33,
860		},
861	}, {
862		.id = 0x3e,
863		.name = "vdebsevw",
864		.swgroup = TEGRA_SWGROUP_VDE,
865		.smmu = {
866			.reg = 0x22c,
867			.bit = 30,
868		},
869		.la = {
870			.reg = 0x35c,
871			.shift = 0,
872			.mask = 0xff,
873			.def = 0xff,
874		},
875	}, {
876		.id = 0x3f,
877		.name = "vdedbgw",
878		.swgroup = TEGRA_SWGROUP_VDE,
879		.smmu = {
880			.reg = 0x22c,
881			.bit = 31,
882		},
883		.la = {
884			.reg = 0x35c,
885			.shift = 16,
886			.mask = 0xff,
887			.def = 0xff,
888		},
889	}, {
890		.id = 0x40,
891		.name = "vdembew",
892		.swgroup = TEGRA_SWGROUP_VDE,
893		.smmu = {
894			.reg = 0x230,
895			.bit = 0,
896		},
897		.la = {
898			.reg = 0x360,
899			.shift = 0,
900			.mask = 0xff,
901			.def = 0x42,
902		},
903	}, {
904		.id = 0x41,
905		.name = "vdetpmw",
906		.swgroup = TEGRA_SWGROUP_VDE,
907		.smmu = {
908			.reg = 0x230,
909			.bit = 1,
910		},
911		.la = {
912			.reg = 0x360,
913			.shift = 16,
914			.mask = 0xff,
915			.def = 0x2a,
916		},
917	},
918};
919
920static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
921	{ .swgroup = TEGRA_SWGROUP_DC,   .reg = 0x240 },
922	{ .swgroup = TEGRA_SWGROUP_DCB,  .reg = 0x244 },
923	{ .swgroup = TEGRA_SWGROUP_EPP,  .reg = 0x248 },
924	{ .swgroup = TEGRA_SWGROUP_G2,   .reg = 0x24c },
925	{ .swgroup = TEGRA_SWGROUP_MPE,  .reg = 0x264 },
926	{ .swgroup = TEGRA_SWGROUP_VI,   .reg = 0x280 },
927	{ .swgroup = TEGRA_SWGROUP_AFI,  .reg = 0x238 },
928	{ .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
929	{ .swgroup = TEGRA_SWGROUP_NV,   .reg = 0x268 },
930	{ .swgroup = TEGRA_SWGROUP_NV2,  .reg = 0x26c },
931	{ .swgroup = TEGRA_SWGROUP_HDA,  .reg = 0x254 },
932	{ .swgroup = TEGRA_SWGROUP_HC,   .reg = 0x250 },
933	{ .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
934	{ .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
935	{ .swgroup = TEGRA_SWGROUP_VDE,  .reg = 0x27c },
936	{ .swgroup = TEGRA_SWGROUP_ISP,  .reg = 0x258 },
937};
938
939static void tegra30_flush_dcache(struct page *page, unsigned long offset,
940				 size_t size)
941{
942	phys_addr_t phys = page_to_phys(page) + offset;
943	void *virt = page_address(page) + offset;
944
945	__cpuc_flush_dcache_area(virt, size);
946	outer_flush_range(phys, phys + size);
947}
948
949static const struct tegra_smmu_ops tegra30_smmu_ops = {
950	.flush_dcache = tegra30_flush_dcache,
951};
952
953static const struct tegra_smmu_soc tegra30_smmu_soc = {
954	.clients = tegra30_mc_clients,
955	.num_clients = ARRAY_SIZE(tegra30_mc_clients),
956	.swgroups = tegra30_swgroups,
957	.num_swgroups = ARRAY_SIZE(tegra30_swgroups),
958	.supports_round_robin_arbitration = false,
959	.supports_request_limit = false,
960	.num_tlb_lines = 16,
961	.num_asids = 4,
962	.ops = &tegra30_smmu_ops,
963};
964
965const struct tegra_mc_soc tegra30_mc_soc = {
966	.clients = tegra30_mc_clients,
967	.num_clients = ARRAY_SIZE(tegra30_mc_clients),
968	.num_address_bits = 32,
969	.atom_size = 16,
970	.smmu = &tegra30_smmu_soc,
971};
972