1/* 2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 6 7 Based on the original rt2800pci.c and rt2800usb.c. 8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 14 <http://rt2x00.serialmonkey.com> 15 16 This program is free software; you can redistribute it and/or modify 17 it under the terms of the GNU General Public License as published by 18 the Free Software Foundation; either version 2 of the License, or 19 (at your option) any later version. 20 21 This program is distributed in the hope that it will be useful, 22 but WITHOUT ANY WARRANTY; without even the implied warranty of 23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 GNU General Public License for more details. 25 26 You should have received a copy of the GNU General Public License 27 along with this program; if not, see <http://www.gnu.org/licenses/>. 28 */ 29 30/* 31 Module: rt2800lib 32 Abstract: rt2800 generic device routines. 33 */ 34 35#include <linux/crc-ccitt.h> 36#include <linux/kernel.h> 37#include <linux/module.h> 38#include <linux/slab.h> 39 40#include "rt2x00.h" 41#include "rt2800lib.h" 42#include "rt2800.h" 43 44/* 45 * Register access. 46 * All access to the CSR registers will go through the methods 47 * rt2800_register_read and rt2800_register_write. 48 * BBP and RF register require indirect register access, 49 * and use the CSR registers BBPCSR and RFCSR to achieve this. 50 * These indirect registers work with busy bits, 51 * and we will try maximal REGISTER_BUSY_COUNT times to access 52 * the register while taking a REGISTER_BUSY_DELAY us delay 53 * between each attampt. When the busy bit is still set at that time, 54 * the access attempt is considered to have failed, 55 * and we will print an error. 56 * The _lock versions must be used if you already hold the csr_mutex 57 */ 58#define WAIT_FOR_BBP(__dev, __reg) \ 59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 60#define WAIT_FOR_RFCSR(__dev, __reg) \ 61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 62#define WAIT_FOR_RF(__dev, __reg) \ 63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 64#define WAIT_FOR_MCU(__dev, __reg) \ 65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 66 H2M_MAILBOX_CSR_OWNER, (__reg)) 67 68static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 69{ 70 /* check for rt2872 on SoC */ 71 if (!rt2x00_is_soc(rt2x00dev) || 72 !rt2x00_rt(rt2x00dev, RT2872)) 73 return false; 74 75 /* we know for sure that these rf chipsets are used on rt305x boards */ 76 if (rt2x00_rf(rt2x00dev, RF3020) || 77 rt2x00_rf(rt2x00dev, RF3021) || 78 rt2x00_rf(rt2x00dev, RF3022)) 79 return true; 80 81 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 82 return false; 83} 84 85static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 86 const unsigned int word, const u8 value) 87{ 88 u32 reg; 89 90 mutex_lock(&rt2x00dev->csr_mutex); 91 92 /* 93 * Wait until the BBP becomes available, afterwards we 94 * can safely write the new data into the register. 95 */ 96 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 97 reg = 0; 98 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 99 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 100 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 101 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 102 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 103 104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 105 } 106 107 mutex_unlock(&rt2x00dev->csr_mutex); 108} 109 110static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, 111 const unsigned int word, u8 *value) 112{ 113 u32 reg; 114 115 mutex_lock(&rt2x00dev->csr_mutex); 116 117 /* 118 * Wait until the BBP becomes available, afterwards we 119 * can safely write the read request into the register. 120 * After the data has been written, we wait until hardware 121 * returns the correct value, if at any time the register 122 * doesn't become available in time, reg will be 0xffffffff 123 * which means we return 0xff to the caller. 124 */ 125 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 126 reg = 0; 127 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 128 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 129 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 130 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 131 132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 133 134 WAIT_FOR_BBP(rt2x00dev, ®); 135 } 136 137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 138 139 mutex_unlock(&rt2x00dev->csr_mutex); 140} 141 142static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 143 const unsigned int word, const u8 value) 144{ 145 u32 reg; 146 147 mutex_lock(&rt2x00dev->csr_mutex); 148 149 /* 150 * Wait until the RFCSR becomes available, afterwards we 151 * can safely write the new data into the register. 152 */ 153 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 154 reg = 0; 155 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 157 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 158 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 159 160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 161 } 162 163 mutex_unlock(&rt2x00dev->csr_mutex); 164} 165 166static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 167 const unsigned int word, u8 *value) 168{ 169 u32 reg; 170 171 mutex_lock(&rt2x00dev->csr_mutex); 172 173 /* 174 * Wait until the RFCSR becomes available, afterwards we 175 * can safely write the read request into the register. 176 * After the data has been written, we wait until hardware 177 * returns the correct value, if at any time the register 178 * doesn't become available in time, reg will be 0xffffffff 179 * which means we return 0xff to the caller. 180 */ 181 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 182 reg = 0; 183 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 184 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 185 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 186 187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 188 189 WAIT_FOR_RFCSR(rt2x00dev, ®); 190 } 191 192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 193 194 mutex_unlock(&rt2x00dev->csr_mutex); 195} 196 197static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 198 const unsigned int word, const u32 value) 199{ 200 u32 reg; 201 202 mutex_lock(&rt2x00dev->csr_mutex); 203 204 /* 205 * Wait until the RF becomes available, afterwards we 206 * can safely write the new data into the register. 207 */ 208 if (WAIT_FOR_RF(rt2x00dev, ®)) { 209 reg = 0; 210 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 211 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 212 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 213 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 214 215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 216 rt2x00_rf_write(rt2x00dev, word, value); 217 } 218 219 mutex_unlock(&rt2x00dev->csr_mutex); 220} 221 222static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 223 [EEPROM_CHIP_ID] = 0x0000, 224 [EEPROM_VERSION] = 0x0001, 225 [EEPROM_MAC_ADDR_0] = 0x0002, 226 [EEPROM_MAC_ADDR_1] = 0x0003, 227 [EEPROM_MAC_ADDR_2] = 0x0004, 228 [EEPROM_NIC_CONF0] = 0x001a, 229 [EEPROM_NIC_CONF1] = 0x001b, 230 [EEPROM_FREQ] = 0x001d, 231 [EEPROM_LED_AG_CONF] = 0x001e, 232 [EEPROM_LED_ACT_CONF] = 0x001f, 233 [EEPROM_LED_POLARITY] = 0x0020, 234 [EEPROM_NIC_CONF2] = 0x0021, 235 [EEPROM_LNA] = 0x0022, 236 [EEPROM_RSSI_BG] = 0x0023, 237 [EEPROM_RSSI_BG2] = 0x0024, 238 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 239 [EEPROM_RSSI_A] = 0x0025, 240 [EEPROM_RSSI_A2] = 0x0026, 241 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 242 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 243 [EEPROM_TXPOWER_DELTA] = 0x0028, 244 [EEPROM_TXPOWER_BG1] = 0x0029, 245 [EEPROM_TXPOWER_BG2] = 0x0030, 246 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 247 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 248 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 249 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 250 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 251 [EEPROM_TXPOWER_A1] = 0x003c, 252 [EEPROM_TXPOWER_A2] = 0x0053, 253 [EEPROM_TSSI_BOUND_A1] = 0x006a, 254 [EEPROM_TSSI_BOUND_A2] = 0x006b, 255 [EEPROM_TSSI_BOUND_A3] = 0x006c, 256 [EEPROM_TSSI_BOUND_A4] = 0x006d, 257 [EEPROM_TSSI_BOUND_A5] = 0x006e, 258 [EEPROM_TXPOWER_BYRATE] = 0x006f, 259 [EEPROM_BBP_START] = 0x0078, 260}; 261 262static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 263 [EEPROM_CHIP_ID] = 0x0000, 264 [EEPROM_VERSION] = 0x0001, 265 [EEPROM_MAC_ADDR_0] = 0x0002, 266 [EEPROM_MAC_ADDR_1] = 0x0003, 267 [EEPROM_MAC_ADDR_2] = 0x0004, 268 [EEPROM_NIC_CONF0] = 0x001a, 269 [EEPROM_NIC_CONF1] = 0x001b, 270 [EEPROM_NIC_CONF2] = 0x001c, 271 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 272 [EEPROM_FREQ] = 0x0022, 273 [EEPROM_LED_AG_CONF] = 0x0023, 274 [EEPROM_LED_ACT_CONF] = 0x0024, 275 [EEPROM_LED_POLARITY] = 0x0025, 276 [EEPROM_LNA] = 0x0026, 277 [EEPROM_EXT_LNA2] = 0x0027, 278 [EEPROM_RSSI_BG] = 0x0028, 279 [EEPROM_RSSI_BG2] = 0x0029, 280 [EEPROM_RSSI_A] = 0x002a, 281 [EEPROM_RSSI_A2] = 0x002b, 282 [EEPROM_TXPOWER_BG1] = 0x0030, 283 [EEPROM_TXPOWER_BG2] = 0x0037, 284 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 285 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 286 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 287 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 288 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 289 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 290 [EEPROM_TXPOWER_A1] = 0x004b, 291 [EEPROM_TXPOWER_A2] = 0x0065, 292 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 293 [EEPROM_TSSI_BOUND_A1] = 0x009a, 294 [EEPROM_TSSI_BOUND_A2] = 0x009b, 295 [EEPROM_TSSI_BOUND_A3] = 0x009c, 296 [EEPROM_TSSI_BOUND_A4] = 0x009d, 297 [EEPROM_TSSI_BOUND_A5] = 0x009e, 298 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 299}; 300 301static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 302 const enum rt2800_eeprom_word word) 303{ 304 const unsigned int *map; 305 unsigned int index; 306 307 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 308 "%s: invalid EEPROM word %d\n", 309 wiphy_name(rt2x00dev->hw->wiphy), word)) 310 return 0; 311 312 if (rt2x00_rt(rt2x00dev, RT3593)) 313 map = rt2800_eeprom_map_ext; 314 else 315 map = rt2800_eeprom_map; 316 317 index = map[word]; 318 319 /* Index 0 is valid only for EEPROM_CHIP_ID. 320 * Otherwise it means that the offset of the 321 * given word is not initialized in the map, 322 * or that the field is not usable on the 323 * actual chipset. 324 */ 325 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 326 "%s: invalid access of EEPROM word %d\n", 327 wiphy_name(rt2x00dev->hw->wiphy), word); 328 329 return index; 330} 331 332static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 333 const enum rt2800_eeprom_word word) 334{ 335 unsigned int index; 336 337 index = rt2800_eeprom_word_index(rt2x00dev, word); 338 return rt2x00_eeprom_addr(rt2x00dev, index); 339} 340 341static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 342 const enum rt2800_eeprom_word word, u16 *data) 343{ 344 unsigned int index; 345 346 index = rt2800_eeprom_word_index(rt2x00dev, word); 347 rt2x00_eeprom_read(rt2x00dev, index, data); 348} 349 350static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 351 const enum rt2800_eeprom_word word, u16 data) 352{ 353 unsigned int index; 354 355 index = rt2800_eeprom_word_index(rt2x00dev, word); 356 rt2x00_eeprom_write(rt2x00dev, index, data); 357} 358 359static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 360 const enum rt2800_eeprom_word array, 361 unsigned int offset, 362 u16 *data) 363{ 364 unsigned int index; 365 366 index = rt2800_eeprom_word_index(rt2x00dev, array); 367 rt2x00_eeprom_read(rt2x00dev, index + offset, data); 368} 369 370static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 371{ 372 u32 reg; 373 int i, count; 374 375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); 376 if (rt2x00_get_field32(reg, WLAN_EN)) 377 return 0; 378 379 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 380 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 381 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 382 rt2x00_set_field32(®, WLAN_EN, 1); 383 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 384 385 udelay(REGISTER_BUSY_DELAY); 386 387 count = 0; 388 do { 389 /* 390 * Check PLL_LD & XTAL_RDY. 391 */ 392 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 393 rt2800_register_read(rt2x00dev, CMB_CTRL, ®); 394 if (rt2x00_get_field32(reg, PLL_LD) && 395 rt2x00_get_field32(reg, XTAL_RDY)) 396 break; 397 udelay(REGISTER_BUSY_DELAY); 398 } 399 400 if (i >= REGISTER_BUSY_COUNT) { 401 402 if (count >= 10) 403 return -EIO; 404 405 rt2800_register_write(rt2x00dev, 0x58, 0x018); 406 udelay(REGISTER_BUSY_DELAY); 407 rt2800_register_write(rt2x00dev, 0x58, 0x418); 408 udelay(REGISTER_BUSY_DELAY); 409 rt2800_register_write(rt2x00dev, 0x58, 0x618); 410 udelay(REGISTER_BUSY_DELAY); 411 count++; 412 } else { 413 count = 0; 414 } 415 416 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); 417 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 418 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 419 rt2x00_set_field32(®, WLAN_RESET, 1); 420 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 421 udelay(10); 422 rt2x00_set_field32(®, WLAN_RESET, 0); 423 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 424 udelay(10); 425 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 426 } while (count != 0); 427 428 return 0; 429} 430 431void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 432 const u8 command, const u8 token, 433 const u8 arg0, const u8 arg1) 434{ 435 u32 reg; 436 437 /* 438 * SOC devices don't support MCU requests. 439 */ 440 if (rt2x00_is_soc(rt2x00dev)) 441 return; 442 443 mutex_lock(&rt2x00dev->csr_mutex); 444 445 /* 446 * Wait until the MCU becomes available, afterwards we 447 * can safely write the new data into the register. 448 */ 449 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 450 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 451 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 452 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 453 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 454 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 455 456 reg = 0; 457 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 458 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 459 } 460 461 mutex_unlock(&rt2x00dev->csr_mutex); 462} 463EXPORT_SYMBOL_GPL(rt2800_mcu_request); 464 465int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 466{ 467 unsigned int i = 0; 468 u32 reg; 469 470 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 471 rt2800_register_read(rt2x00dev, MAC_CSR0, ®); 472 if (reg && reg != ~0) 473 return 0; 474 msleep(1); 475 } 476 477 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 478 return -EBUSY; 479} 480EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 481 482int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 483{ 484 unsigned int i; 485 u32 reg; 486 487 /* 488 * Some devices are really slow to respond here. Wait a whole second 489 * before timing out. 490 */ 491 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 492 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); 493 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 494 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 495 return 0; 496 497 msleep(10); 498 } 499 500 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 501 return -EACCES; 502} 503EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 504 505void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 506{ 507 u32 reg; 508 509 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); 510 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 511 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 512 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 513 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 514 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 515 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 516} 517EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 518 519void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 520 unsigned short *txwi_size, 521 unsigned short *rxwi_size) 522{ 523 switch (rt2x00dev->chip.rt) { 524 case RT3593: 525 *txwi_size = TXWI_DESC_SIZE_4WORDS; 526 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 527 break; 528 529 case RT5592: 530 *txwi_size = TXWI_DESC_SIZE_5WORDS; 531 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 532 break; 533 534 default: 535 *txwi_size = TXWI_DESC_SIZE_4WORDS; 536 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 537 break; 538 } 539} 540EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 541 542static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 543{ 544 u16 fw_crc; 545 u16 crc; 546 547 /* 548 * The last 2 bytes in the firmware array are the crc checksum itself, 549 * this means that we should never pass those 2 bytes to the crc 550 * algorithm. 551 */ 552 fw_crc = (data[len - 2] << 8 | data[len - 1]); 553 554 /* 555 * Use the crc ccitt algorithm. 556 * This will return the same value as the legacy driver which 557 * used bit ordering reversion on the both the firmware bytes 558 * before input input as well as on the final output. 559 * Obviously using crc ccitt directly is much more efficient. 560 */ 561 crc = crc_ccitt(~0, data, len - 2); 562 563 /* 564 * There is a small difference between the crc-itu-t + bitrev and 565 * the crc-ccitt crc calculation. In the latter method the 2 bytes 566 * will be swapped, use swab16 to convert the crc to the correct 567 * value. 568 */ 569 crc = swab16(crc); 570 571 return fw_crc == crc; 572} 573 574int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 575 const u8 *data, const size_t len) 576{ 577 size_t offset = 0; 578 size_t fw_len; 579 bool multiple; 580 581 /* 582 * PCI(e) & SOC devices require firmware with a length 583 * of 8kb. USB devices require firmware files with a length 584 * of 4kb. Certain USB chipsets however require different firmware, 585 * which Ralink only provides attached to the original firmware 586 * file. Thus for USB devices, firmware files have a length 587 * which is a multiple of 4kb. The firmware for rt3290 chip also 588 * have a length which is a multiple of 4kb. 589 */ 590 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 591 fw_len = 4096; 592 else 593 fw_len = 8192; 594 595 multiple = true; 596 /* 597 * Validate the firmware length 598 */ 599 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 600 return FW_BAD_LENGTH; 601 602 /* 603 * Check if the chipset requires one of the upper parts 604 * of the firmware. 605 */ 606 if (rt2x00_is_usb(rt2x00dev) && 607 !rt2x00_rt(rt2x00dev, RT2860) && 608 !rt2x00_rt(rt2x00dev, RT2872) && 609 !rt2x00_rt(rt2x00dev, RT3070) && 610 ((len / fw_len) == 1)) 611 return FW_BAD_VERSION; 612 613 /* 614 * 8kb firmware files must be checked as if it were 615 * 2 separate firmware files. 616 */ 617 while (offset < len) { 618 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 619 return FW_BAD_CRC; 620 621 offset += fw_len; 622 } 623 624 return FW_OK; 625} 626EXPORT_SYMBOL_GPL(rt2800_check_firmware); 627 628int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 629 const u8 *data, const size_t len) 630{ 631 unsigned int i; 632 u32 reg; 633 int retval; 634 635 if (rt2x00_rt(rt2x00dev, RT3290)) { 636 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 637 if (retval) 638 return -EBUSY; 639 } 640 641 /* 642 * If driver doesn't wake up firmware here, 643 * rt2800_load_firmware will hang forever when interface is up again. 644 */ 645 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 646 647 /* 648 * Wait for stable hardware. 649 */ 650 if (rt2800_wait_csr_ready(rt2x00dev)) 651 return -EBUSY; 652 653 if (rt2x00_is_pci(rt2x00dev)) { 654 if (rt2x00_rt(rt2x00dev, RT3290) || 655 rt2x00_rt(rt2x00dev, RT3572) || 656 rt2x00_rt(rt2x00dev, RT5390) || 657 rt2x00_rt(rt2x00dev, RT5392)) { 658 rt2800_register_read(rt2x00dev, AUX_CTRL, ®); 659 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 660 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 661 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 662 } 663 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 664 } 665 666 rt2800_disable_wpdma(rt2x00dev); 667 668 /* 669 * Write firmware to the device. 670 */ 671 rt2800_drv_write_firmware(rt2x00dev, data, len); 672 673 /* 674 * Wait for device to stabilize. 675 */ 676 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 677 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); 678 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 679 break; 680 msleep(1); 681 } 682 683 if (i == REGISTER_BUSY_COUNT) { 684 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 685 return -EBUSY; 686 } 687 688 /* 689 * Disable DMA, will be reenabled later when enabling 690 * the radio. 691 */ 692 rt2800_disable_wpdma(rt2x00dev); 693 694 /* 695 * Initialize firmware. 696 */ 697 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 698 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 699 if (rt2x00_is_usb(rt2x00dev)) { 700 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 701 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 702 } 703 msleep(1); 704 705 return 0; 706} 707EXPORT_SYMBOL_GPL(rt2800_load_firmware); 708 709void rt2800_write_tx_data(struct queue_entry *entry, 710 struct txentry_desc *txdesc) 711{ 712 __le32 *txwi = rt2800_drv_get_txwi(entry); 713 u32 word; 714 int i; 715 716 /* 717 * Initialize TX Info descriptor 718 */ 719 rt2x00_desc_read(txwi, 0, &word); 720 rt2x00_set_field32(&word, TXWI_W0_FRAG, 721 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 722 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 723 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 724 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 725 rt2x00_set_field32(&word, TXWI_W0_TS, 726 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 727 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 728 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 729 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 730 txdesc->u.ht.mpdu_density); 731 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 732 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 733 rt2x00_set_field32(&word, TXWI_W0_BW, 734 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 735 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 736 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 737 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 738 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 739 rt2x00_desc_write(txwi, 0, word); 740 741 rt2x00_desc_read(txwi, 1, &word); 742 rt2x00_set_field32(&word, TXWI_W1_ACK, 743 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 744 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 745 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 746 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 747 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 748 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 749 txdesc->key_idx : txdesc->u.ht.wcid); 750 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 751 txdesc->length); 752 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 753 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 754 rt2x00_desc_write(txwi, 1, word); 755 756 /* 757 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 758 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 759 * When TXD_W3_WIV is set to 1 it will use the IV data 760 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 761 * crypto entry in the registers should be used to encrypt the frame. 762 * 763 * Nulify all remaining words as well, we don't know how to program them. 764 */ 765 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 766 _rt2x00_desc_write(txwi, i, 0); 767} 768EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 769 770static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 771{ 772 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 773 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 774 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 775 u16 eeprom; 776 u8 offset0; 777 u8 offset1; 778 u8 offset2; 779 780 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { 781 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom); 782 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 783 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 784 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); 785 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 786 } else { 787 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom); 788 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 789 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 790 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); 791 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 792 } 793 794 /* 795 * Convert the value from the descriptor into the RSSI value 796 * If the value in the descriptor is 0, it is considered invalid 797 * and the default (extremely low) rssi value is assumed 798 */ 799 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 800 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 801 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 802 803 /* 804 * mac80211 only accepts a single RSSI value. Calculating the 805 * average doesn't deliver a fair answer either since -60:-60 would 806 * be considered equally good as -50:-70 while the second is the one 807 * which gives less energy... 808 */ 809 rssi0 = max(rssi0, rssi1); 810 return (int)max(rssi0, rssi2); 811} 812 813void rt2800_process_rxwi(struct queue_entry *entry, 814 struct rxdone_entry_desc *rxdesc) 815{ 816 __le32 *rxwi = (__le32 *) entry->skb->data; 817 u32 word; 818 819 rt2x00_desc_read(rxwi, 0, &word); 820 821 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 822 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 823 824 rt2x00_desc_read(rxwi, 1, &word); 825 826 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 827 rxdesc->flags |= RX_FLAG_SHORT_GI; 828 829 if (rt2x00_get_field32(word, RXWI_W1_BW)) 830 rxdesc->flags |= RX_FLAG_40MHZ; 831 832 /* 833 * Detect RX rate, always use MCS as signal type. 834 */ 835 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 836 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 837 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 838 839 /* 840 * Mask of 0x8 bit to remove the short preamble flag. 841 */ 842 if (rxdesc->rate_mode == RATE_MODE_CCK) 843 rxdesc->signal &= ~0x8; 844 845 rt2x00_desc_read(rxwi, 2, &word); 846 847 /* 848 * Convert descriptor AGC value to RSSI value. 849 */ 850 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 851 /* 852 * Remove RXWI descriptor from start of the buffer. 853 */ 854 skb_pull(entry->skb, entry->queue->winfo_size); 855} 856EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 857 858void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi) 859{ 860 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 861 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 862 struct txdone_entry_desc txdesc; 863 u32 word; 864 u16 mcs, real_mcs; 865 int aggr, ampdu; 866 867 /* 868 * Obtain the status about this packet. 869 */ 870 txdesc.flags = 0; 871 rt2x00_desc_read(txwi, 0, &word); 872 873 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 874 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 875 876 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 877 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 878 879 /* 880 * If a frame was meant to be sent as a single non-aggregated MPDU 881 * but ended up in an aggregate the used tx rate doesn't correlate 882 * with the one specified in the TXWI as the whole aggregate is sent 883 * with the same rate. 884 * 885 * For example: two frames are sent to rt2x00, the first one sets 886 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 887 * and requests MCS15. If the hw aggregates both frames into one 888 * AMDPU the tx status for both frames will contain MCS7 although 889 * the frame was sent successfully. 890 * 891 * Hence, replace the requested rate with the real tx rate to not 892 * confuse the rate control algortihm by providing clearly wrong 893 * data. 894 */ 895 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) { 896 skbdesc->tx_rate_idx = real_mcs; 897 mcs = real_mcs; 898 } 899 900 if (aggr == 1 || ampdu == 1) 901 __set_bit(TXDONE_AMPDU, &txdesc.flags); 902 903 /* 904 * Ralink has a retry mechanism using a global fallback 905 * table. We setup this fallback table to try the immediate 906 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 907 * always contains the MCS used for the last transmission, be 908 * it successful or not. 909 */ 910 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 911 /* 912 * Transmission succeeded. The number of retries is 913 * mcs - real_mcs 914 */ 915 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 916 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 917 } else { 918 /* 919 * Transmission failed. The number of retries is 920 * always 7 in this case (for a total number of 8 921 * frames sent). 922 */ 923 __set_bit(TXDONE_FAILURE, &txdesc.flags); 924 txdesc.retry = rt2x00dev->long_retry; 925 } 926 927 /* 928 * the frame was retried at least once 929 * -> hw used fallback rates 930 */ 931 if (txdesc.retry) 932 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 933 934 rt2x00lib_txdone(entry, &txdesc); 935} 936EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 937 938static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 939 unsigned int index) 940{ 941 return HW_BEACON_BASE(index); 942} 943 944static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 945 unsigned int index) 946{ 947 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 948} 949 950static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 951{ 952 struct data_queue *queue = rt2x00dev->bcn; 953 struct queue_entry *entry; 954 int i, bcn_num = 0; 955 u64 off, reg = 0; 956 u32 bssid_dw1; 957 958 /* 959 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 960 */ 961 for (i = 0; i < queue->limit; i++) { 962 entry = &queue->entries[i]; 963 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 964 continue; 965 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 966 reg |= off << (8 * bcn_num); 967 bcn_num++; 968 } 969 970 WARN_ON_ONCE(bcn_num != rt2x00dev->intf_beaconing); 971 972 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 973 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 974 975 /* 976 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 977 */ 978 rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1); 979 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 980 bcn_num > 0 ? bcn_num - 1 : 0); 981 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 982} 983 984void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 985{ 986 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 987 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 988 unsigned int beacon_base; 989 unsigned int padding_len; 990 u32 orig_reg, reg; 991 const int txwi_desc_size = entry->queue->winfo_size; 992 993 /* 994 * Disable beaconing while we are reloading the beacon data, 995 * otherwise we might be sending out invalid data. 996 */ 997 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); 998 orig_reg = reg; 999 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1000 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1001 1002 /* 1003 * Add space for the TXWI in front of the skb. 1004 */ 1005 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1006 1007 /* 1008 * Register descriptor details in skb frame descriptor. 1009 */ 1010 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1011 skbdesc->desc = entry->skb->data; 1012 skbdesc->desc_len = txwi_desc_size; 1013 1014 /* 1015 * Add the TXWI for the beacon to the skb. 1016 */ 1017 rt2800_write_tx_data(entry, txdesc); 1018 1019 /* 1020 * Dump beacon to userspace through debugfs. 1021 */ 1022 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); 1023 1024 /* 1025 * Write entire beacon with TXWI and padding to register. 1026 */ 1027 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1028 if (padding_len && skb_pad(entry->skb, padding_len)) { 1029 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1030 /* skb freed by skb_pad() on failure */ 1031 entry->skb = NULL; 1032 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1033 return; 1034 } 1035 1036 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1037 1038 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1039 entry->skb->len + padding_len); 1040 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1041 1042 /* 1043 * Change global beacons settings. 1044 */ 1045 rt2800_update_beacons_setup(rt2x00dev); 1046 1047 /* 1048 * Restore beaconing state. 1049 */ 1050 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1051 1052 /* 1053 * Clean up beacon skb. 1054 */ 1055 dev_kfree_skb_any(entry->skb); 1056 entry->skb = NULL; 1057} 1058EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1059 1060static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1061 unsigned int index) 1062{ 1063 int i; 1064 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1065 unsigned int beacon_base; 1066 1067 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1068 1069 /* 1070 * For the Beacon base registers we only need to clear 1071 * the whole TXWI which (when set to 0) will invalidate 1072 * the entire beacon. 1073 */ 1074 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1075 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1076} 1077 1078void rt2800_clear_beacon(struct queue_entry *entry) 1079{ 1080 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1081 u32 orig_reg, reg; 1082 1083 /* 1084 * Disable beaconing while we are reloading the beacon data, 1085 * otherwise we might be sending out invalid data. 1086 */ 1087 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg); 1088 reg = orig_reg; 1089 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1090 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1091 1092 /* 1093 * Clear beacon. 1094 */ 1095 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1096 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1097 1098 /* 1099 * Change global beacons settings. 1100 */ 1101 rt2800_update_beacons_setup(rt2x00dev); 1102 /* 1103 * Restore beaconing state. 1104 */ 1105 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1106} 1107EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1108 1109#ifdef CONFIG_RT2X00_LIB_DEBUGFS 1110const struct rt2x00debug rt2800_rt2x00debug = { 1111 .owner = THIS_MODULE, 1112 .csr = { 1113 .read = rt2800_register_read, 1114 .write = rt2800_register_write, 1115 .flags = RT2X00DEBUGFS_OFFSET, 1116 .word_base = CSR_REG_BASE, 1117 .word_size = sizeof(u32), 1118 .word_count = CSR_REG_SIZE / sizeof(u32), 1119 }, 1120 .eeprom = { 1121 /* NOTE: The local EEPROM access functions can't 1122 * be used here, use the generic versions instead. 1123 */ 1124 .read = rt2x00_eeprom_read, 1125 .write = rt2x00_eeprom_write, 1126 .word_base = EEPROM_BASE, 1127 .word_size = sizeof(u16), 1128 .word_count = EEPROM_SIZE / sizeof(u16), 1129 }, 1130 .bbp = { 1131 .read = rt2800_bbp_read, 1132 .write = rt2800_bbp_write, 1133 .word_base = BBP_BASE, 1134 .word_size = sizeof(u8), 1135 .word_count = BBP_SIZE / sizeof(u8), 1136 }, 1137 .rf = { 1138 .read = rt2x00_rf_read, 1139 .write = rt2800_rf_write, 1140 .word_base = RF_BASE, 1141 .word_size = sizeof(u32), 1142 .word_count = RF_SIZE / sizeof(u32), 1143 }, 1144 .rfcsr = { 1145 .read = rt2800_rfcsr_read, 1146 .write = rt2800_rfcsr_write, 1147 .word_base = RFCSR_BASE, 1148 .word_size = sizeof(u8), 1149 .word_count = RFCSR_SIZE / sizeof(u8), 1150 }, 1151}; 1152EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1153#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1154 1155int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1156{ 1157 u32 reg; 1158 1159 if (rt2x00_rt(rt2x00dev, RT3290)) { 1160 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); 1161 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1162 } else { 1163 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 1164 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1165 } 1166} 1167EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1168 1169#ifdef CONFIG_RT2X00_LIB_LEDS 1170static void rt2800_brightness_set(struct led_classdev *led_cdev, 1171 enum led_brightness brightness) 1172{ 1173 struct rt2x00_led *led = 1174 container_of(led_cdev, struct rt2x00_led, led_dev); 1175 unsigned int enabled = brightness != LED_OFF; 1176 unsigned int bg_mode = 1177 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); 1178 unsigned int polarity = 1179 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1180 EEPROM_FREQ_LED_POLARITY); 1181 unsigned int ledmode = 1182 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1183 EEPROM_FREQ_LED_MODE); 1184 u32 reg; 1185 1186 /* Check for SoC (SOC devices don't support MCU requests) */ 1187 if (rt2x00_is_soc(led->rt2x00dev)) { 1188 rt2800_register_read(led->rt2x00dev, LED_CFG, ®); 1189 1190 /* Set LED Polarity */ 1191 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1192 1193 /* Set LED Mode */ 1194 if (led->type == LED_TYPE_RADIO) { 1195 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1196 enabled ? 3 : 0); 1197 } else if (led->type == LED_TYPE_ASSOC) { 1198 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1199 enabled ? 3 : 0); 1200 } else if (led->type == LED_TYPE_QUALITY) { 1201 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1202 enabled ? 3 : 0); 1203 } 1204 1205 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1206 1207 } else { 1208 if (led->type == LED_TYPE_RADIO) { 1209 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1210 enabled ? 0x20 : 0); 1211 } else if (led->type == LED_TYPE_ASSOC) { 1212 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1213 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1214 } else if (led->type == LED_TYPE_QUALITY) { 1215 /* 1216 * The brightness is divided into 6 levels (0 - 5), 1217 * The specs tell us the following levels: 1218 * 0, 1 ,3, 7, 15, 31 1219 * to determine the level in a simple way we can simply 1220 * work with bitshifting: 1221 * (1 << level) - 1 1222 */ 1223 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1224 (1 << brightness / (LED_FULL / 6)) - 1, 1225 polarity); 1226 } 1227 } 1228} 1229 1230static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1231 struct rt2x00_led *led, enum led_type type) 1232{ 1233 led->rt2x00dev = rt2x00dev; 1234 led->type = type; 1235 led->led_dev.brightness_set = rt2800_brightness_set; 1236 led->flags = LED_INITIALIZED; 1237} 1238#endif /* CONFIG_RT2X00_LIB_LEDS */ 1239 1240/* 1241 * Configuration handlers. 1242 */ 1243static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1244 const u8 *address, 1245 int wcid) 1246{ 1247 struct mac_wcid_entry wcid_entry; 1248 u32 offset; 1249 1250 offset = MAC_WCID_ENTRY(wcid); 1251 1252 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1253 if (address) 1254 memcpy(wcid_entry.mac, address, ETH_ALEN); 1255 1256 rt2800_register_multiwrite(rt2x00dev, offset, 1257 &wcid_entry, sizeof(wcid_entry)); 1258} 1259 1260static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1261{ 1262 u32 offset; 1263 offset = MAC_WCID_ATTR_ENTRY(wcid); 1264 rt2800_register_write(rt2x00dev, offset, 0); 1265} 1266 1267static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1268 int wcid, u32 bssidx) 1269{ 1270 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1271 u32 reg; 1272 1273 /* 1274 * The BSS Idx numbers is split in a main value of 3 bits, 1275 * and a extended field for adding one additional bit to the value. 1276 */ 1277 rt2800_register_read(rt2x00dev, offset, ®); 1278 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1279 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1280 (bssidx & 0x8) >> 3); 1281 rt2800_register_write(rt2x00dev, offset, reg); 1282} 1283 1284static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1285 struct rt2x00lib_crypto *crypto, 1286 struct ieee80211_key_conf *key) 1287{ 1288 struct mac_iveiv_entry iveiv_entry; 1289 u32 offset; 1290 u32 reg; 1291 1292 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1293 1294 if (crypto->cmd == SET_KEY) { 1295 rt2800_register_read(rt2x00dev, offset, ®); 1296 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1297 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1298 /* 1299 * Both the cipher as the BSS Idx numbers are split in a main 1300 * value of 3 bits, and a extended field for adding one additional 1301 * bit to the value. 1302 */ 1303 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1304 (crypto->cipher & 0x7)); 1305 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1306 (crypto->cipher & 0x8) >> 3); 1307 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1308 rt2800_register_write(rt2x00dev, offset, reg); 1309 } else { 1310 /* Delete the cipher without touching the bssidx */ 1311 rt2800_register_read(rt2x00dev, offset, ®); 1312 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1313 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1314 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1315 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1316 rt2800_register_write(rt2x00dev, offset, reg); 1317 } 1318 1319 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1320 1321 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1322 if ((crypto->cipher == CIPHER_TKIP) || 1323 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1324 (crypto->cipher == CIPHER_AES)) 1325 iveiv_entry.iv[3] |= 0x20; 1326 iveiv_entry.iv[3] |= key->keyidx << 6; 1327 rt2800_register_multiwrite(rt2x00dev, offset, 1328 &iveiv_entry, sizeof(iveiv_entry)); 1329} 1330 1331int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1332 struct rt2x00lib_crypto *crypto, 1333 struct ieee80211_key_conf *key) 1334{ 1335 struct hw_key_entry key_entry; 1336 struct rt2x00_field32 field; 1337 u32 offset; 1338 u32 reg; 1339 1340 if (crypto->cmd == SET_KEY) { 1341 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1342 1343 memcpy(key_entry.key, crypto->key, 1344 sizeof(key_entry.key)); 1345 memcpy(key_entry.tx_mic, crypto->tx_mic, 1346 sizeof(key_entry.tx_mic)); 1347 memcpy(key_entry.rx_mic, crypto->rx_mic, 1348 sizeof(key_entry.rx_mic)); 1349 1350 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1351 rt2800_register_multiwrite(rt2x00dev, offset, 1352 &key_entry, sizeof(key_entry)); 1353 } 1354 1355 /* 1356 * The cipher types are stored over multiple registers 1357 * starting with SHARED_KEY_MODE_BASE each word will have 1358 * 32 bits and contains the cipher types for 2 bssidx each. 1359 * Using the correct defines correctly will cause overhead, 1360 * so just calculate the correct offset. 1361 */ 1362 field.bit_offset = 4 * (key->hw_key_idx % 8); 1363 field.bit_mask = 0x7 << field.bit_offset; 1364 1365 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1366 1367 rt2800_register_read(rt2x00dev, offset, ®); 1368 rt2x00_set_field32(®, field, 1369 (crypto->cmd == SET_KEY) * crypto->cipher); 1370 rt2800_register_write(rt2x00dev, offset, reg); 1371 1372 /* 1373 * Update WCID information 1374 */ 1375 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1376 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1377 crypto->bssidx); 1378 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1379 1380 return 0; 1381} 1382EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1383 1384static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev) 1385{ 1386 struct mac_wcid_entry wcid_entry; 1387 int idx; 1388 u32 offset; 1389 1390 /* 1391 * Search for the first free WCID entry and return the corresponding 1392 * index. 1393 * 1394 * Make sure the WCID starts _after_ the last possible shared key 1395 * entry (>32). 1396 * 1397 * Since parts of the pairwise key table might be shared with 1398 * the beacon frame buffers 6 & 7 we should only write into the 1399 * first 222 entries. 1400 */ 1401 for (idx = 33; idx <= 222; idx++) { 1402 offset = MAC_WCID_ENTRY(idx); 1403 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry, 1404 sizeof(wcid_entry)); 1405 if (is_broadcast_ether_addr(wcid_entry.mac)) 1406 return idx; 1407 } 1408 1409 /* 1410 * Use -1 to indicate that we don't have any more space in the WCID 1411 * table. 1412 */ 1413 return -1; 1414} 1415 1416int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1417 struct rt2x00lib_crypto *crypto, 1418 struct ieee80211_key_conf *key) 1419{ 1420 struct hw_key_entry key_entry; 1421 u32 offset; 1422 1423 if (crypto->cmd == SET_KEY) { 1424 /* 1425 * Allow key configuration only for STAs that are 1426 * known by the hw. 1427 */ 1428 if (crypto->wcid < 0) 1429 return -ENOSPC; 1430 key->hw_key_idx = crypto->wcid; 1431 1432 memcpy(key_entry.key, crypto->key, 1433 sizeof(key_entry.key)); 1434 memcpy(key_entry.tx_mic, crypto->tx_mic, 1435 sizeof(key_entry.tx_mic)); 1436 memcpy(key_entry.rx_mic, crypto->rx_mic, 1437 sizeof(key_entry.rx_mic)); 1438 1439 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1440 rt2800_register_multiwrite(rt2x00dev, offset, 1441 &key_entry, sizeof(key_entry)); 1442 } 1443 1444 /* 1445 * Update WCID information 1446 */ 1447 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1448 1449 return 0; 1450} 1451EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1452 1453int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif, 1454 struct ieee80211_sta *sta) 1455{ 1456 int wcid; 1457 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1458 1459 /* 1460 * Find next free WCID. 1461 */ 1462 wcid = rt2800_find_wcid(rt2x00dev); 1463 1464 /* 1465 * Store selected wcid even if it is invalid so that we can 1466 * later decide if the STA is uploaded into the hw. 1467 */ 1468 sta_priv->wcid = wcid; 1469 1470 /* 1471 * No space left in the device, however, we can still communicate 1472 * with the STA -> No error. 1473 */ 1474 if (wcid < 0) 1475 return 0; 1476 1477 /* 1478 * Clean up WCID attributes and write STA address to the device. 1479 */ 1480 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1481 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1482 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1483 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1484 return 0; 1485} 1486EXPORT_SYMBOL_GPL(rt2800_sta_add); 1487 1488int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid) 1489{ 1490 /* 1491 * Remove WCID entry, no need to clean the attributes as they will 1492 * get renewed when the WCID is reused. 1493 */ 1494 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1495 1496 return 0; 1497} 1498EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1499 1500void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1501 const unsigned int filter_flags) 1502{ 1503 u32 reg; 1504 1505 /* 1506 * Start configuration steps. 1507 * Note that the version error will always be dropped 1508 * and broadcast frames will always be accepted since 1509 * there is no filter for it at this time. 1510 */ 1511 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); 1512 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1513 !(filter_flags & FIF_FCSFAIL)); 1514 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1515 !(filter_flags & FIF_PLCPFAIL)); 1516 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1517 !(filter_flags & FIF_PROMISC_IN_BSS)); 1518 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1519 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1520 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1521 !(filter_flags & FIF_ALLMULTI)); 1522 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1523 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1524 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1525 !(filter_flags & FIF_CONTROL)); 1526 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1527 !(filter_flags & FIF_CONTROL)); 1528 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1529 !(filter_flags & FIF_CONTROL)); 1530 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1531 !(filter_flags & FIF_CONTROL)); 1532 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1533 !(filter_flags & FIF_CONTROL)); 1534 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1535 !(filter_flags & FIF_PSPOLL)); 1536 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1537 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1538 !(filter_flags & FIF_CONTROL)); 1539 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1540 !(filter_flags & FIF_CONTROL)); 1541 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1542} 1543EXPORT_SYMBOL_GPL(rt2800_config_filter); 1544 1545void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1546 struct rt2x00intf_conf *conf, const unsigned int flags) 1547{ 1548 u32 reg; 1549 bool update_bssid = false; 1550 1551 if (flags & CONFIG_UPDATE_TYPE) { 1552 /* 1553 * Enable synchronisation. 1554 */ 1555 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); 1556 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1557 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1558 1559 if (conf->sync == TSF_SYNC_AP_NONE) { 1560 /* 1561 * Tune beacon queue transmit parameters for AP mode 1562 */ 1563 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); 1564 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1565 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1566 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1567 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1568 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1569 } else { 1570 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); 1571 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1572 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1573 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1574 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1575 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1576 } 1577 } 1578 1579 if (flags & CONFIG_UPDATE_MAC) { 1580 if (flags & CONFIG_UPDATE_TYPE && 1581 conf->sync == TSF_SYNC_AP_NONE) { 1582 /* 1583 * The BSSID register has to be set to our own mac 1584 * address in AP mode. 1585 */ 1586 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 1587 update_bssid = true; 1588 } 1589 1590 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 1591 reg = le32_to_cpu(conf->mac[1]); 1592 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 1593 conf->mac[1] = cpu_to_le32(reg); 1594 } 1595 1596 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 1597 conf->mac, sizeof(conf->mac)); 1598 } 1599 1600 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 1601 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 1602 reg = le32_to_cpu(conf->bssid[1]); 1603 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 1604 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 1605 conf->bssid[1] = cpu_to_le32(reg); 1606 } 1607 1608 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 1609 conf->bssid, sizeof(conf->bssid)); 1610 } 1611} 1612EXPORT_SYMBOL_GPL(rt2800_config_intf); 1613 1614static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 1615 struct rt2x00lib_erp *erp) 1616{ 1617 bool any_sta_nongf = !!(erp->ht_opmode & 1618 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 1619 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 1620 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 1621 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 1622 u32 reg; 1623 1624 /* default protection rate for HT20: OFDM 24M */ 1625 mm20_rate = gf20_rate = 0x4004; 1626 1627 /* default protection rate for HT40: duplicate OFDM 24M */ 1628 mm40_rate = gf40_rate = 0x4084; 1629 1630 switch (protection) { 1631 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 1632 /* 1633 * All STAs in this BSS are HT20/40 but there might be 1634 * STAs not supporting greenfield mode. 1635 * => Disable protection for HT transmissions. 1636 */ 1637 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 1638 1639 break; 1640 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 1641 /* 1642 * All STAs in this BSS are HT20 or HT20/40 but there 1643 * might be STAs not supporting greenfield mode. 1644 * => Protect all HT40 transmissions. 1645 */ 1646 mm20_mode = gf20_mode = 0; 1647 mm40_mode = gf40_mode = 2; 1648 1649 break; 1650 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 1651 /* 1652 * Nonmember protection: 1653 * According to 802.11n we _should_ protect all 1654 * HT transmissions (but we don't have to). 1655 * 1656 * But if cts_protection is enabled we _shall_ protect 1657 * all HT transmissions using a CCK rate. 1658 * 1659 * And if any station is non GF we _shall_ protect 1660 * GF transmissions. 1661 * 1662 * We decide to protect everything 1663 * -> fall through to mixed mode. 1664 */ 1665 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 1666 /* 1667 * Legacy STAs are present 1668 * => Protect all HT transmissions. 1669 */ 1670 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2; 1671 1672 /* 1673 * If erp protection is needed we have to protect HT 1674 * transmissions with CCK 11M long preamble. 1675 */ 1676 if (erp->cts_protection) { 1677 /* don't duplicate RTS/CTS in CCK mode */ 1678 mm20_rate = mm40_rate = 0x0003; 1679 gf20_rate = gf40_rate = 0x0003; 1680 } 1681 break; 1682 } 1683 1684 /* check for STAs not supporting greenfield mode */ 1685 if (any_sta_nongf) 1686 gf20_mode = gf40_mode = 2; 1687 1688 /* Update HT protection config */ 1689 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); 1690 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 1691 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 1692 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 1693 1694 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); 1695 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 1696 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 1697 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 1698 1699 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); 1700 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 1701 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 1702 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 1703 1704 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); 1705 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 1706 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 1707 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 1708} 1709 1710void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 1711 u32 changed) 1712{ 1713 u32 reg; 1714 1715 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 1716 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); 1717 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1718 !!erp->short_preamble); 1719 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1720 !!erp->short_preamble); 1721 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 1722 } 1723 1724 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 1725 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); 1726 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 1727 erp->cts_protection ? 2 : 0); 1728 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 1729 } 1730 1731 if (changed & BSS_CHANGED_BASIC_RATES) { 1732 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 1733 erp->basic_rates); 1734 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 1735 } 1736 1737 if (changed & BSS_CHANGED_ERP_SLOT) { 1738 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); 1739 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 1740 erp->slot_time); 1741 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 1742 1743 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); 1744 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 1745 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 1746 } 1747 1748 if (changed & BSS_CHANGED_BEACON_INT) { 1749 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); 1750 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1751 erp->beacon_int * 16); 1752 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1753 } 1754 1755 if (changed & BSS_CHANGED_HT) 1756 rt2800_config_ht_opmode(rt2x00dev, erp); 1757} 1758EXPORT_SYMBOL_GPL(rt2800_config_erp); 1759 1760static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 1761{ 1762 u32 reg; 1763 u16 eeprom; 1764 u8 led_ctrl, led_g_mode, led_r_mode; 1765 1766 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); 1767 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { 1768 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 1769 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 1770 } else { 1771 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 1772 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 1773 } 1774 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 1775 1776 rt2800_register_read(rt2x00dev, LED_CFG, ®); 1777 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 1778 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 1779 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 1780 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 1781 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); 1782 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 1783 if (led_ctrl == 0 || led_ctrl > 0x40) { 1784 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 1785 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 1786 rt2800_register_write(rt2x00dev, LED_CFG, reg); 1787 } else { 1788 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 1789 (led_g_mode << 2) | led_r_mode, 1); 1790 } 1791 } 1792} 1793 1794static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 1795 enum antenna ant) 1796{ 1797 u32 reg; 1798 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 1799 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 1800 1801 if (rt2x00_is_pci(rt2x00dev)) { 1802 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®); 1803 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 1804 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 1805 } else if (rt2x00_is_usb(rt2x00dev)) 1806 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 1807 eesk_pin, 0); 1808 1809 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 1810 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 1811 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 1812 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 1813} 1814 1815void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 1816{ 1817 u8 r1; 1818 u8 r3; 1819 u16 eeprom; 1820 1821 rt2800_bbp_read(rt2x00dev, 1, &r1); 1822 rt2800_bbp_read(rt2x00dev, 3, &r3); 1823 1824 if (rt2x00_rt(rt2x00dev, RT3572) && 1825 rt2x00_has_cap_bt_coexist(rt2x00dev)) 1826 rt2800_config_3572bt_ant(rt2x00dev); 1827 1828 /* 1829 * Configure the TX antenna. 1830 */ 1831 switch (ant->tx_chain_num) { 1832 case 1: 1833 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 1834 break; 1835 case 2: 1836 if (rt2x00_rt(rt2x00dev, RT3572) && 1837 rt2x00_has_cap_bt_coexist(rt2x00dev)) 1838 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 1839 else 1840 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 1841 break; 1842 case 3: 1843 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 1844 break; 1845 } 1846 1847 /* 1848 * Configure the RX antenna. 1849 */ 1850 switch (ant->rx_chain_num) { 1851 case 1: 1852 if (rt2x00_rt(rt2x00dev, RT3070) || 1853 rt2x00_rt(rt2x00dev, RT3090) || 1854 rt2x00_rt(rt2x00dev, RT3352) || 1855 rt2x00_rt(rt2x00dev, RT3390)) { 1856 rt2800_eeprom_read(rt2x00dev, 1857 EEPROM_NIC_CONF1, &eeprom); 1858 if (rt2x00_get_field16(eeprom, 1859 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 1860 rt2800_set_ant_diversity(rt2x00dev, 1861 rt2x00dev->default_ant.rx); 1862 } 1863 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 1864 break; 1865 case 2: 1866 if (rt2x00_rt(rt2x00dev, RT3572) && 1867 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 1868 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 1869 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1870 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); 1871 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 1872 } else { 1873 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 1874 } 1875 break; 1876 case 3: 1877 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 1878 break; 1879 } 1880 1881 rt2800_bbp_write(rt2x00dev, 3, r3); 1882 rt2800_bbp_write(rt2x00dev, 1, r1); 1883 1884 if (rt2x00_rt(rt2x00dev, RT3593)) { 1885 if (ant->rx_chain_num == 1) 1886 rt2800_bbp_write(rt2x00dev, 86, 0x00); 1887 else 1888 rt2800_bbp_write(rt2x00dev, 86, 0x46); 1889 } 1890} 1891EXPORT_SYMBOL_GPL(rt2800_config_ant); 1892 1893static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 1894 struct rt2x00lib_conf *libconf) 1895{ 1896 u16 eeprom; 1897 short lna_gain; 1898 1899 if (libconf->rf.channel <= 14) { 1900 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); 1901 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 1902 } else if (libconf->rf.channel <= 64) { 1903 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom); 1904 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 1905 } else if (libconf->rf.channel <= 128) { 1906 if (rt2x00_rt(rt2x00dev, RT3593)) { 1907 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom); 1908 lna_gain = rt2x00_get_field16(eeprom, 1909 EEPROM_EXT_LNA2_A1); 1910 } else { 1911 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom); 1912 lna_gain = rt2x00_get_field16(eeprom, 1913 EEPROM_RSSI_BG2_LNA_A1); 1914 } 1915 } else { 1916 if (rt2x00_rt(rt2x00dev, RT3593)) { 1917 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom); 1918 lna_gain = rt2x00_get_field16(eeprom, 1919 EEPROM_EXT_LNA2_A2); 1920 } else { 1921 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom); 1922 lna_gain = rt2x00_get_field16(eeprom, 1923 EEPROM_RSSI_A2_LNA_A2); 1924 } 1925 } 1926 1927 rt2x00dev->lna_gain = lna_gain; 1928} 1929 1930#define FREQ_OFFSET_BOUND 0x5f 1931 1932static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev) 1933{ 1934 u8 freq_offset, prev_freq_offset; 1935 u8 rfcsr, prev_rfcsr; 1936 1937 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 1938 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 1939 1940 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 1941 prev_rfcsr = rfcsr; 1942 1943 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 1944 if (rfcsr == prev_rfcsr) 1945 return; 1946 1947 if (rt2x00_is_usb(rt2x00dev)) { 1948 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 1949 freq_offset, prev_rfcsr); 1950 return; 1951 } 1952 1953 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 1954 while (prev_freq_offset != freq_offset) { 1955 if (prev_freq_offset < freq_offset) 1956 prev_freq_offset++; 1957 else 1958 prev_freq_offset--; 1959 1960 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 1961 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 1962 1963 usleep_range(1000, 1500); 1964 } 1965} 1966 1967static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 1968 struct ieee80211_conf *conf, 1969 struct rf_channel *rf, 1970 struct channel_info *info) 1971{ 1972 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 1973 1974 if (rt2x00dev->default_ant.tx_chain_num == 1) 1975 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 1976 1977 if (rt2x00dev->default_ant.rx_chain_num == 1) { 1978 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 1979 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 1980 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 1981 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 1982 1983 if (rf->channel > 14) { 1984 /* 1985 * When TX power is below 0, we should increase it by 7 to 1986 * make it a positive value (Minimum value is -7). 1987 * However this means that values between 0 and 7 have 1988 * double meaning, and we should set a 7DBm boost flag. 1989 */ 1990 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 1991 (info->default_power1 >= 0)); 1992 1993 if (info->default_power1 < 0) 1994 info->default_power1 += 7; 1995 1996 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 1997 1998 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 1999 (info->default_power2 >= 0)); 2000 2001 if (info->default_power2 < 0) 2002 info->default_power2 += 7; 2003 2004 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2005 } else { 2006 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2007 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2008 } 2009 2010 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2011 2012 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2013 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2014 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2015 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2016 2017 udelay(200); 2018 2019 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2020 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2021 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2022 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2023 2024 udelay(200); 2025 2026 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2027 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2028 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2029 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2030} 2031 2032static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2033 struct ieee80211_conf *conf, 2034 struct rf_channel *rf, 2035 struct channel_info *info) 2036{ 2037 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2038 u8 rfcsr, calib_tx, calib_rx; 2039 2040 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2041 2042 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 2043 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2044 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2045 2046 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 2047 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2048 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2049 2050 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 2051 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2052 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2053 2054 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); 2055 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2056 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2057 2058 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2059 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2060 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2061 rt2x00dev->default_ant.rx_chain_num <= 1); 2062 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2063 rt2x00dev->default_ant.rx_chain_num <= 2); 2064 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2065 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2066 rt2x00dev->default_ant.tx_chain_num <= 1); 2067 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2068 rt2x00dev->default_ant.tx_chain_num <= 2); 2069 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2070 2071 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); 2072 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2073 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2074 2075 if (rt2x00_rt(rt2x00dev, RT3390)) { 2076 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2077 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2078 } else { 2079 if (conf_is_ht40(conf)) { 2080 calib_tx = drv_data->calibration_bw40; 2081 calib_rx = drv_data->calibration_bw40; 2082 } else { 2083 calib_tx = drv_data->calibration_bw20; 2084 calib_rx = drv_data->calibration_bw20; 2085 } 2086 } 2087 2088 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr); 2089 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2090 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2091 2092 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr); 2093 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2094 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2095 2096 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 2097 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2098 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2099 2100 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 2101 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2102 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2103 msleep(1); 2104 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2105 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2106} 2107 2108static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2109 struct ieee80211_conf *conf, 2110 struct rf_channel *rf, 2111 struct channel_info *info) 2112{ 2113 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2114 u8 rfcsr; 2115 u32 reg; 2116 2117 if (rf->channel <= 14) { 2118 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2119 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2120 } else { 2121 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2122 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2123 } 2124 2125 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2126 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2127 2128 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 2129 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2130 if (rf->channel <= 14) 2131 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2132 else 2133 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2134 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2135 2136 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr); 2137 if (rf->channel <= 14) 2138 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2139 else 2140 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2141 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2142 2143 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 2144 if (rf->channel <= 14) { 2145 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2146 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2147 info->default_power1); 2148 } else { 2149 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2150 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2151 (info->default_power1 & 0x3) | 2152 ((info->default_power1 & 0xC) << 1)); 2153 } 2154 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2155 2156 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); 2157 if (rf->channel <= 14) { 2158 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2159 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2160 info->default_power2); 2161 } else { 2162 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2163 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2164 (info->default_power2 & 0x3) | 2165 ((info->default_power2 & 0xC) << 1)); 2166 } 2167 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2168 2169 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2170 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2171 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2172 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2173 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2174 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2175 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2176 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2177 if (rf->channel <= 14) { 2178 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2179 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2180 } 2181 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2182 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2183 } else { 2184 switch (rt2x00dev->default_ant.tx_chain_num) { 2185 case 1: 2186 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2187 case 2: 2188 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2189 break; 2190 } 2191 2192 switch (rt2x00dev->default_ant.rx_chain_num) { 2193 case 1: 2194 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2195 case 2: 2196 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2197 break; 2198 } 2199 } 2200 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2201 2202 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); 2203 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2204 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2205 2206 if (conf_is_ht40(conf)) { 2207 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2208 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2209 } else { 2210 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2211 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2212 } 2213 2214 if (rf->channel <= 14) { 2215 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2216 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2217 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2218 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2219 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2220 rfcsr = 0x4c; 2221 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2222 drv_data->txmixer_gain_24g); 2223 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2224 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2225 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2226 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2227 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2228 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2229 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2230 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2231 } else { 2232 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 2233 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2234 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2235 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2236 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2237 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2238 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2239 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2240 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2241 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2242 rfcsr = 0x7a; 2243 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2244 drv_data->txmixer_gain_5g); 2245 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2246 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2247 if (rf->channel <= 64) { 2248 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2249 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2250 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2251 } else if (rf->channel <= 128) { 2252 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2253 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2254 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2255 } else { 2256 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2257 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2258 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2259 } 2260 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2261 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2262 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2263 } 2264 2265 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 2266 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2267 if (rf->channel <= 14) 2268 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2269 else 2270 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2271 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2272 2273 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 2274 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2275 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2276} 2277 2278static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2279 struct ieee80211_conf *conf, 2280 struct rf_channel *rf, 2281 struct channel_info *info) 2282{ 2283 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2284 u8 txrx_agc_fc; 2285 u8 txrx_h20m; 2286 u8 rfcsr; 2287 u8 bbp; 2288 const bool txbf_enabled = false; /* TODO */ 2289 2290 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2291 rt2800_bbp_read(rt2x00dev, 109, &bbp); 2292 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2293 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2294 rt2800_bbp_write(rt2x00dev, 109, bbp); 2295 2296 rt2800_bbp_read(rt2x00dev, 110, &bbp); 2297 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2298 rt2800_bbp_write(rt2x00dev, 110, bbp); 2299 2300 if (rf->channel <= 14) { 2301 /* Restore BBP 25 & 26 for 2.4 GHz */ 2302 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2303 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2304 } else { 2305 /* Hard code BBP 25 & 26 for 5GHz */ 2306 2307 /* Enable IQ Phase correction */ 2308 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2309 /* Setup IQ Phase correction value */ 2310 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2311 } 2312 2313 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2314 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2315 2316 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2317 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2318 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2319 2320 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2321 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2322 if (rf->channel <= 14) 2323 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2324 else 2325 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2326 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2327 2328 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr); 2329 if (rf->channel <= 14) { 2330 rfcsr = 0; 2331 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2332 info->default_power1 & 0x1f); 2333 } else { 2334 if (rt2x00_is_usb(rt2x00dev)) 2335 rfcsr = 0x40; 2336 2337 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2338 ((info->default_power1 & 0x18) << 1) | 2339 (info->default_power1 & 7)); 2340 } 2341 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2342 2343 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr); 2344 if (rf->channel <= 14) { 2345 rfcsr = 0; 2346 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2347 info->default_power2 & 0x1f); 2348 } else { 2349 if (rt2x00_is_usb(rt2x00dev)) 2350 rfcsr = 0x40; 2351 2352 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2353 ((info->default_power2 & 0x18) << 1) | 2354 (info->default_power2 & 7)); 2355 } 2356 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2357 2358 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr); 2359 if (rf->channel <= 14) { 2360 rfcsr = 0; 2361 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2362 info->default_power3 & 0x1f); 2363 } else { 2364 if (rt2x00_is_usb(rt2x00dev)) 2365 rfcsr = 0x40; 2366 2367 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2368 ((info->default_power3 & 0x18) << 1) | 2369 (info->default_power3 & 7)); 2370 } 2371 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2372 2373 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2374 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2375 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2376 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2377 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2378 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2379 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2380 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2381 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2382 2383 switch (rt2x00dev->default_ant.tx_chain_num) { 2384 case 3: 2385 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2386 /* fallthrough */ 2387 case 2: 2388 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2389 /* fallthrough */ 2390 case 1: 2391 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2392 break; 2393 } 2394 2395 switch (rt2x00dev->default_ant.rx_chain_num) { 2396 case 3: 2397 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2398 /* fallthrough */ 2399 case 2: 2400 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2401 /* fallthrough */ 2402 case 1: 2403 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2404 break; 2405 } 2406 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2407 2408 rt2800_adjust_freq_offset(rt2x00dev); 2409 2410 if (conf_is_ht40(conf)) { 2411 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2412 RFCSR24_TX_AGC_FC); 2413 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2414 RFCSR24_TX_H20M); 2415 } else { 2416 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2417 RFCSR24_TX_AGC_FC); 2418 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2419 RFCSR24_TX_H20M); 2420 } 2421 2422 /* NOTE: the reference driver does not writes the new value 2423 * back to RFCSR 32 2424 */ 2425 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr); 2426 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2427 2428 if (rf->channel <= 14) 2429 rfcsr = 0xa0; 2430 else 2431 rfcsr = 0x80; 2432 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2433 2434 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 2435 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2436 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2437 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2438 2439 /* Band selection */ 2440 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr); 2441 if (rf->channel <= 14) 2442 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2443 else 2444 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2445 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2446 2447 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr); 2448 if (rf->channel <= 14) 2449 rfcsr = 0x3c; 2450 else 2451 rfcsr = 0x20; 2452 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2453 2454 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 2455 if (rf->channel <= 14) 2456 rfcsr = 0x1a; 2457 else 2458 rfcsr = 0x12; 2459 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2460 2461 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 2462 if (rf->channel >= 1 && rf->channel <= 14) 2463 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2464 else if (rf->channel >= 36 && rf->channel <= 64) 2465 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2466 else if (rf->channel >= 100 && rf->channel <= 128) 2467 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2468 else 2469 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2470 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2471 2472 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 2473 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2474 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2475 2476 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2477 2478 if (rf->channel <= 14) { 2479 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2480 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2481 } else { 2482 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2483 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2484 } 2485 2486 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); 2487 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2488 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2489 2490 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); 2491 if (rf->channel <= 14) { 2492 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2493 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2494 } else { 2495 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2496 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2497 } 2498 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2499 2500 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); 2501 if (rf->channel <= 14) 2502 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2503 else 2504 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2505 2506 if (txbf_enabled) 2507 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2508 2509 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2510 2511 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); 2512 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2513 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2514 2515 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr); 2516 if (rf->channel <= 14) 2517 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2518 else 2519 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2520 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2521 2522 if (rf->channel <= 14) { 2523 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2524 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2525 } else { 2526 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2527 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2528 } 2529 2530 /* Initiate VCO calibration */ 2531 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 2532 if (rf->channel <= 14) { 2533 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2534 } else { 2535 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 2536 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 2537 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 2538 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 2539 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 2540 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2541 } 2542 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2543 2544 if (rf->channel >= 1 && rf->channel <= 14) { 2545 rfcsr = 0x23; 2546 if (txbf_enabled) 2547 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2548 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2549 2550 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 2551 } else if (rf->channel >= 36 && rf->channel <= 64) { 2552 rfcsr = 0x36; 2553 if (txbf_enabled) 2554 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2555 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 2556 2557 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 2558 } else if (rf->channel >= 100 && rf->channel <= 128) { 2559 rfcsr = 0x32; 2560 if (txbf_enabled) 2561 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2562 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2563 2564 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 2565 } else { 2566 rfcsr = 0x30; 2567 if (txbf_enabled) 2568 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2569 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2570 2571 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 2572 } 2573} 2574 2575#define POWER_BOUND 0x27 2576#define POWER_BOUND_5G 0x2b 2577 2578static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 2579 struct ieee80211_conf *conf, 2580 struct rf_channel *rf, 2581 struct channel_info *info) 2582{ 2583 u8 rfcsr; 2584 2585 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2586 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2587 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2588 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2589 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2590 2591 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); 2592 if (info->default_power1 > POWER_BOUND) 2593 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2594 else 2595 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2596 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2597 2598 rt2800_adjust_freq_offset(rt2x00dev); 2599 2600 if (rf->channel <= 14) { 2601 if (rf->channel == 6) 2602 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 2603 else 2604 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 2605 2606 if (rf->channel >= 1 && rf->channel <= 6) 2607 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 2608 else if (rf->channel >= 7 && rf->channel <= 11) 2609 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 2610 else if (rf->channel >= 12 && rf->channel <= 14) 2611 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 2612 } 2613} 2614 2615static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 2616 struct ieee80211_conf *conf, 2617 struct rf_channel *rf, 2618 struct channel_info *info) 2619{ 2620 u8 rfcsr; 2621 2622 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2623 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2624 2625 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 2626 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 2627 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 2628 2629 if (info->default_power1 > POWER_BOUND) 2630 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 2631 else 2632 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 2633 2634 if (info->default_power2 > POWER_BOUND) 2635 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 2636 else 2637 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 2638 2639 rt2800_adjust_freq_offset(rt2x00dev); 2640 2641 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2642 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2643 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2644 2645 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 2646 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2647 else 2648 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2649 2650 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 2651 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2652 else 2653 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2654 2655 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2656 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2657 2658 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2659 2660 rt2800_rfcsr_write(rt2x00dev, 31, 80); 2661} 2662 2663static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 2664 struct ieee80211_conf *conf, 2665 struct rf_channel *rf, 2666 struct channel_info *info) 2667{ 2668 u8 rfcsr; 2669 2670 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2671 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2672 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2673 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 2674 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2675 2676 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); 2677 if (info->default_power1 > POWER_BOUND) 2678 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 2679 else 2680 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2681 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2682 2683 if (rt2x00_rt(rt2x00dev, RT5392)) { 2684 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); 2685 if (info->default_power2 > POWER_BOUND) 2686 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 2687 else 2688 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 2689 info->default_power2); 2690 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2691 } 2692 2693 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2694 if (rt2x00_rt(rt2x00dev, RT5392)) { 2695 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2696 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2697 } 2698 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2699 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2700 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2701 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2702 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2703 2704 rt2800_adjust_freq_offset(rt2x00dev); 2705 2706 if (rf->channel <= 14) { 2707 int idx = rf->channel-1; 2708 2709 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2710 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 2711 /* r55/r59 value array of channel 1~14 */ 2712 static const char r55_bt_rev[] = {0x83, 0x83, 2713 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 2714 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 2715 static const char r59_bt_rev[] = {0x0e, 0x0e, 2716 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 2717 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 2718 2719 rt2800_rfcsr_write(rt2x00dev, 55, 2720 r55_bt_rev[idx]); 2721 rt2800_rfcsr_write(rt2x00dev, 59, 2722 r59_bt_rev[idx]); 2723 } else { 2724 static const char r59_bt[] = {0x8b, 0x8b, 0x8b, 2725 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 2726 0x88, 0x88, 0x86, 0x85, 0x84}; 2727 2728 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 2729 } 2730 } else { 2731 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 2732 static const char r55_nonbt_rev[] = {0x23, 0x23, 2733 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 2734 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 2735 static const char r59_nonbt_rev[] = {0x07, 0x07, 2736 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 2737 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 2738 2739 rt2800_rfcsr_write(rt2x00dev, 55, 2740 r55_nonbt_rev[idx]); 2741 rt2800_rfcsr_write(rt2x00dev, 59, 2742 r59_nonbt_rev[idx]); 2743 } else if (rt2x00_rt(rt2x00dev, RT5390) || 2744 rt2x00_rt(rt2x00dev, RT5392)) { 2745 static const char r59_non_bt[] = {0x8f, 0x8f, 2746 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 2747 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 2748 2749 rt2800_rfcsr_write(rt2x00dev, 59, 2750 r59_non_bt[idx]); 2751 } 2752 } 2753 } 2754} 2755 2756static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 2757 struct ieee80211_conf *conf, 2758 struct rf_channel *rf, 2759 struct channel_info *info) 2760{ 2761 u8 rfcsr, ep_reg; 2762 u32 reg; 2763 int power_bound; 2764 2765 /* TODO */ 2766 const bool is_11b = false; 2767 const bool is_type_ep = false; 2768 2769 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 2770 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 2771 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 2772 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 2773 2774 /* Order of values on rf_channel entry: N, K, mod, R */ 2775 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 2776 2777 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr); 2778 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 2779 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 2780 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 2781 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 2782 2783 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr); 2784 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 2785 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 2786 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2787 2788 if (rf->channel <= 14) { 2789 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 2790 /* FIXME: RF11 owerwrite ? */ 2791 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 2792 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 2793 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 2794 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 2795 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 2796 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 2797 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 2798 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 2799 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 2800 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 2801 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 2802 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 2803 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 2804 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 2805 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 2806 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 2807 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 2808 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 2809 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 2810 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 2811 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 2812 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 2813 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 2814 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 2815 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 2816 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 2817 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 2818 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 2819 2820 /* TODO RF27 <- tssi */ 2821 2822 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 2823 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2824 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 2825 2826 if (is_11b) { 2827 /* CCK */ 2828 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 2829 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 2830 if (is_type_ep) 2831 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 2832 else 2833 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 2834 } else { 2835 /* OFDM */ 2836 if (is_type_ep) 2837 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 2838 else 2839 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 2840 } 2841 2842 power_bound = POWER_BOUND; 2843 ep_reg = 0x2; 2844 } else { 2845 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 2846 /* FIMXE: RF11 overwrite */ 2847 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 2848 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 2849 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 2850 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 2851 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 2852 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 2853 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 2854 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 2855 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 2856 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 2857 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 2858 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 2859 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 2860 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 2861 2862 /* TODO RF27 <- tssi */ 2863 2864 if (rf->channel >= 36 && rf->channel <= 64) { 2865 2866 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 2867 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 2868 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 2869 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 2870 if (rf->channel <= 50) 2871 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 2872 else if (rf->channel >= 52) 2873 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 2874 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 2875 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 2876 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 2877 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 2878 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 2879 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 2880 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 2881 if (rf->channel <= 50) { 2882 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 2883 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 2884 } else if (rf->channel >= 52) { 2885 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 2886 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 2887 } 2888 2889 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 2890 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 2891 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 2892 2893 } else if (rf->channel >= 100 && rf->channel <= 165) { 2894 2895 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 2896 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 2897 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 2898 if (rf->channel <= 153) { 2899 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 2900 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 2901 } else if (rf->channel >= 155) { 2902 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 2903 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 2904 } 2905 if (rf->channel <= 138) { 2906 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 2907 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 2908 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 2909 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 2910 } else if (rf->channel >= 140) { 2911 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 2912 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 2913 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 2914 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 2915 } 2916 if (rf->channel <= 124) 2917 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 2918 else if (rf->channel >= 126) 2919 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 2920 if (rf->channel <= 138) 2921 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 2922 else if (rf->channel >= 140) 2923 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 2924 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 2925 if (rf->channel <= 138) 2926 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 2927 else if (rf->channel >= 140) 2928 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 2929 if (rf->channel <= 128) 2930 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 2931 else if (rf->channel >= 130) 2932 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 2933 if (rf->channel <= 116) 2934 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 2935 else if (rf->channel >= 118) 2936 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 2937 if (rf->channel <= 138) 2938 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 2939 else if (rf->channel >= 140) 2940 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 2941 if (rf->channel <= 116) 2942 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 2943 else if (rf->channel >= 118) 2944 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 2945 } 2946 2947 power_bound = POWER_BOUND_5G; 2948 ep_reg = 0x3; 2949 } 2950 2951 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr); 2952 if (info->default_power1 > power_bound) 2953 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 2954 else 2955 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2956 if (is_type_ep) 2957 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 2958 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2959 2960 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); 2961 if (info->default_power2 > power_bound) 2962 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 2963 else 2964 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 2965 if (is_type_ep) 2966 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 2967 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2968 2969 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2970 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2971 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2972 2973 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 2974 rt2x00dev->default_ant.tx_chain_num >= 1); 2975 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2976 rt2x00dev->default_ant.tx_chain_num == 2); 2977 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2978 2979 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 2980 rt2x00dev->default_ant.rx_chain_num >= 1); 2981 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2982 rt2x00dev->default_ant.rx_chain_num == 2); 2983 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2984 2985 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2986 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 2987 2988 if (conf_is_ht40(conf)) 2989 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 2990 else 2991 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 2992 2993 if (!is_11b) { 2994 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 2995 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 2996 } 2997 2998 /* TODO proper frequency adjustment */ 2999 rt2800_adjust_freq_offset(rt2x00dev); 3000 3001 /* TODO merge with others */ 3002 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 3003 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3004 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3005 3006 /* BBP settings */ 3007 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3008 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3009 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3010 3011 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3012 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3013 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3014 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3015 3016 /* GLRT band configuration */ 3017 rt2800_bbp_write(rt2x00dev, 195, 128); 3018 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3019 rt2800_bbp_write(rt2x00dev, 195, 129); 3020 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3021 rt2800_bbp_write(rt2x00dev, 195, 130); 3022 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3023 rt2800_bbp_write(rt2x00dev, 195, 131); 3024 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3025 rt2800_bbp_write(rt2x00dev, 195, 133); 3026 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3027 rt2800_bbp_write(rt2x00dev, 195, 124); 3028 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3029} 3030 3031static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3032 const unsigned int word, 3033 const u8 value) 3034{ 3035 u8 chain, reg; 3036 3037 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3038 rt2800_bbp_read(rt2x00dev, 27, ®); 3039 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3040 rt2800_bbp_write(rt2x00dev, 27, reg); 3041 3042 rt2800_bbp_write(rt2x00dev, word, value); 3043 } 3044} 3045 3046static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3047{ 3048 u8 cal; 3049 3050 /* TX0 IQ Gain */ 3051 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3052 if (channel <= 14) 3053 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3054 else if (channel >= 36 && channel <= 64) 3055 cal = rt2x00_eeprom_byte(rt2x00dev, 3056 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3057 else if (channel >= 100 && channel <= 138) 3058 cal = rt2x00_eeprom_byte(rt2x00dev, 3059 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3060 else if (channel >= 140 && channel <= 165) 3061 cal = rt2x00_eeprom_byte(rt2x00dev, 3062 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3063 else 3064 cal = 0; 3065 rt2800_bbp_write(rt2x00dev, 159, cal); 3066 3067 /* TX0 IQ Phase */ 3068 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3069 if (channel <= 14) 3070 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 3071 else if (channel >= 36 && channel <= 64) 3072 cal = rt2x00_eeprom_byte(rt2x00dev, 3073 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 3074 else if (channel >= 100 && channel <= 138) 3075 cal = rt2x00_eeprom_byte(rt2x00dev, 3076 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 3077 else if (channel >= 140 && channel <= 165) 3078 cal = rt2x00_eeprom_byte(rt2x00dev, 3079 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 3080 else 3081 cal = 0; 3082 rt2800_bbp_write(rt2x00dev, 159, cal); 3083 3084 /* TX1 IQ Gain */ 3085 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 3086 if (channel <= 14) 3087 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 3088 else if (channel >= 36 && channel <= 64) 3089 cal = rt2x00_eeprom_byte(rt2x00dev, 3090 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 3091 else if (channel >= 100 && channel <= 138) 3092 cal = rt2x00_eeprom_byte(rt2x00dev, 3093 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 3094 else if (channel >= 140 && channel <= 165) 3095 cal = rt2x00_eeprom_byte(rt2x00dev, 3096 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 3097 else 3098 cal = 0; 3099 rt2800_bbp_write(rt2x00dev, 159, cal); 3100 3101 /* TX1 IQ Phase */ 3102 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 3103 if (channel <= 14) 3104 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 3105 else if (channel >= 36 && channel <= 64) 3106 cal = rt2x00_eeprom_byte(rt2x00dev, 3107 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 3108 else if (channel >= 100 && channel <= 138) 3109 cal = rt2x00_eeprom_byte(rt2x00dev, 3110 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 3111 else if (channel >= 140 && channel <= 165) 3112 cal = rt2x00_eeprom_byte(rt2x00dev, 3113 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 3114 else 3115 cal = 0; 3116 rt2800_bbp_write(rt2x00dev, 159, cal); 3117 3118 /* FIXME: possible RX0, RX1 callibration ? */ 3119 3120 /* RF IQ compensation control */ 3121 rt2800_bbp_write(rt2x00dev, 158, 0x04); 3122 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 3123 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3124 3125 /* RF IQ imbalance compensation control */ 3126 rt2800_bbp_write(rt2x00dev, 158, 0x03); 3127 cal = rt2x00_eeprom_byte(rt2x00dev, 3128 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 3129 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3130} 3131 3132static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 3133 unsigned int channel, 3134 char txpower) 3135{ 3136 if (rt2x00_rt(rt2x00dev, RT3593)) 3137 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 3138 3139 if (channel <= 14) 3140 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 3141 3142 if (rt2x00_rt(rt2x00dev, RT3593)) 3143 return clamp_t(char, txpower, MIN_A_TXPOWER_3593, 3144 MAX_A_TXPOWER_3593); 3145 else 3146 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 3147} 3148 3149static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 3150 struct ieee80211_conf *conf, 3151 struct rf_channel *rf, 3152 struct channel_info *info) 3153{ 3154 u32 reg; 3155 unsigned int tx_pin; 3156 u8 bbp, rfcsr; 3157 3158 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3159 info->default_power1); 3160 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3161 info->default_power2); 3162 if (rt2x00dev->default_ant.tx_chain_num > 2) 3163 info->default_power3 = 3164 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 3165 info->default_power3); 3166 3167 switch (rt2x00dev->chip.rf) { 3168 case RF2020: 3169 case RF3020: 3170 case RF3021: 3171 case RF3022: 3172 case RF3320: 3173 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 3174 break; 3175 case RF3052: 3176 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 3177 break; 3178 case RF3053: 3179 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 3180 break; 3181 case RF3290: 3182 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 3183 break; 3184 case RF3322: 3185 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 3186 break; 3187 case RF3070: 3188 case RF5360: 3189 case RF5362: 3190 case RF5370: 3191 case RF5372: 3192 case RF5390: 3193 case RF5392: 3194 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 3195 break; 3196 case RF5592: 3197 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 3198 break; 3199 default: 3200 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 3201 } 3202 3203 if (rt2x00_rf(rt2x00dev, RF3070) || 3204 rt2x00_rf(rt2x00dev, RF3290) || 3205 rt2x00_rf(rt2x00dev, RF3322) || 3206 rt2x00_rf(rt2x00dev, RF5360) || 3207 rt2x00_rf(rt2x00dev, RF5362) || 3208 rt2x00_rf(rt2x00dev, RF5370) || 3209 rt2x00_rf(rt2x00dev, RF5372) || 3210 rt2x00_rf(rt2x00dev, RF5390) || 3211 rt2x00_rf(rt2x00dev, RF5392)) { 3212 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 3213 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0); 3214 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0); 3215 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3216 3217 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 3218 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3219 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3220 } 3221 3222 /* 3223 * Change BBP settings 3224 */ 3225 if (rt2x00_rt(rt2x00dev, RT3352)) { 3226 rt2800_bbp_write(rt2x00dev, 27, 0x0); 3227 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3228 rt2800_bbp_write(rt2x00dev, 27, 0x20); 3229 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 3230 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 3231 if (rf->channel > 14) { 3232 /* Disable CCK Packet detection on 5GHz */ 3233 rt2800_bbp_write(rt2x00dev, 70, 0x00); 3234 } else { 3235 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3236 } 3237 3238 if (conf_is_ht40(conf)) 3239 rt2800_bbp_write(rt2x00dev, 105, 0x04); 3240 else 3241 rt2800_bbp_write(rt2x00dev, 105, 0x34); 3242 3243 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3244 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3245 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3246 rt2800_bbp_write(rt2x00dev, 77, 0x98); 3247 } else { 3248 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3249 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3250 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3251 rt2800_bbp_write(rt2x00dev, 86, 0); 3252 } 3253 3254 if (rf->channel <= 14) { 3255 if (!rt2x00_rt(rt2x00dev, RT5390) && 3256 !rt2x00_rt(rt2x00dev, RT5392)) { 3257 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 3258 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3259 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3260 } else { 3261 if (rt2x00_rt(rt2x00dev, RT3593)) 3262 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3263 else 3264 rt2800_bbp_write(rt2x00dev, 82, 0x84); 3265 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3266 } 3267 if (rt2x00_rt(rt2x00dev, RT3593)) 3268 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 3269 } 3270 3271 } else { 3272 if (rt2x00_rt(rt2x00dev, RT3572)) 3273 rt2800_bbp_write(rt2x00dev, 82, 0x94); 3274 else if (rt2x00_rt(rt2x00dev, RT3593)) 3275 rt2800_bbp_write(rt2x00dev, 82, 0x82); 3276 else 3277 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 3278 3279 if (rt2x00_rt(rt2x00dev, RT3593)) 3280 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 3281 3282 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 3283 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3284 else 3285 rt2800_bbp_write(rt2x00dev, 75, 0x50); 3286 } 3287 3288 rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®); 3289 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 3290 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 3291 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 3292 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 3293 3294 if (rt2x00_rt(rt2x00dev, RT3572)) 3295 rt2800_rfcsr_write(rt2x00dev, 8, 0); 3296 3297 tx_pin = 0; 3298 3299 switch (rt2x00dev->default_ant.tx_chain_num) { 3300 case 3: 3301 /* Turn on tertiary PAs */ 3302 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 3303 rf->channel > 14); 3304 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 3305 rf->channel <= 14); 3306 /* fall-through */ 3307 case 2: 3308 /* Turn on secondary PAs */ 3309 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 3310 rf->channel > 14); 3311 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 3312 rf->channel <= 14); 3313 /* fall-through */ 3314 case 1: 3315 /* Turn on primary PAs */ 3316 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 3317 rf->channel > 14); 3318 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 3319 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 3320 else 3321 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 3322 rf->channel <= 14); 3323 break; 3324 } 3325 3326 switch (rt2x00dev->default_ant.rx_chain_num) { 3327 case 3: 3328 /* Turn on tertiary LNAs */ 3329 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); 3330 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); 3331 /* fall-through */ 3332 case 2: 3333 /* Turn on secondary LNAs */ 3334 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 3335 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 3336 /* fall-through */ 3337 case 1: 3338 /* Turn on primary LNAs */ 3339 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); 3340 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 3341 break; 3342 } 3343 3344 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 3345 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 3346 3347 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 3348 3349 if (rt2x00_rt(rt2x00dev, RT3572)) { 3350 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 3351 3352 /* AGC init */ 3353 if (rf->channel <= 14) 3354 reg = 0x1c + (2 * rt2x00dev->lna_gain); 3355 else 3356 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3357 3358 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3359 } 3360 3361 if (rt2x00_rt(rt2x00dev, RT3593)) { 3362 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 3363 3364 /* Band selection */ 3365 if (rt2x00_is_usb(rt2x00dev) || 3366 rt2x00_is_pcie(rt2x00dev)) { 3367 /* GPIO #8 controls all paths */ 3368 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 3369 if (rf->channel <= 14) 3370 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 3371 else 3372 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 3373 } 3374 3375 /* LNA PE control. */ 3376 if (rt2x00_is_usb(rt2x00dev)) { 3377 /* GPIO #4 controls PE0 and PE1, 3378 * GPIO #7 controls PE2 3379 */ 3380 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3381 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 3382 3383 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3384 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 3385 } else if (rt2x00_is_pcie(rt2x00dev)) { 3386 /* GPIO #4 controls PE0, PE1 and PE2 */ 3387 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 3388 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 3389 } 3390 3391 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 3392 3393 /* AGC init */ 3394 if (rf->channel <= 14) 3395 reg = 0x1c + 2 * rt2x00dev->lna_gain; 3396 else 3397 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 3398 3399 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3400 3401 usleep_range(1000, 1500); 3402 } 3403 3404 if (rt2x00_rt(rt2x00dev, RT5592)) { 3405 rt2800_bbp_write(rt2x00dev, 195, 141); 3406 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a); 3407 3408 /* AGC init */ 3409 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain; 3410 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 3411 3412 rt2800_iq_calibrate(rt2x00dev, rf->channel); 3413 } 3414 3415 rt2800_bbp_read(rt2x00dev, 4, &bbp); 3416 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 3417 rt2800_bbp_write(rt2x00dev, 4, bbp); 3418 3419 rt2800_bbp_read(rt2x00dev, 3, &bbp); 3420 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 3421 rt2800_bbp_write(rt2x00dev, 3, bbp); 3422 3423 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 3424 if (conf_is_ht40(conf)) { 3425 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 3426 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3427 rt2800_bbp_write(rt2x00dev, 73, 0x16); 3428 } else { 3429 rt2800_bbp_write(rt2x00dev, 69, 0x16); 3430 rt2800_bbp_write(rt2x00dev, 70, 0x08); 3431 rt2800_bbp_write(rt2x00dev, 73, 0x11); 3432 } 3433 } 3434 3435 msleep(1); 3436 3437 /* 3438 * Clear channel statistic counters 3439 */ 3440 rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®); 3441 rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®); 3442 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®); 3443 3444 /* 3445 * Clear update flag 3446 */ 3447 if (rt2x00_rt(rt2x00dev, RT3352)) { 3448 rt2800_bbp_read(rt2x00dev, 49, &bbp); 3449 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 3450 rt2800_bbp_write(rt2x00dev, 49, bbp); 3451 } 3452} 3453 3454static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 3455{ 3456 u8 tssi_bounds[9]; 3457 u8 current_tssi; 3458 u16 eeprom; 3459 u8 step; 3460 int i; 3461 3462 /* 3463 * First check if temperature compensation is supported. 3464 */ 3465 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 3466 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 3467 return 0; 3468 3469 /* 3470 * Read TSSI boundaries for temperature compensation from 3471 * the EEPROM. 3472 * 3473 * Array idx 0 1 2 3 4 5 6 7 8 3474 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 3475 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 3476 */ 3477 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { 3478 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom); 3479 tssi_bounds[0] = rt2x00_get_field16(eeprom, 3480 EEPROM_TSSI_BOUND_BG1_MINUS4); 3481 tssi_bounds[1] = rt2x00_get_field16(eeprom, 3482 EEPROM_TSSI_BOUND_BG1_MINUS3); 3483 3484 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom); 3485 tssi_bounds[2] = rt2x00_get_field16(eeprom, 3486 EEPROM_TSSI_BOUND_BG2_MINUS2); 3487 tssi_bounds[3] = rt2x00_get_field16(eeprom, 3488 EEPROM_TSSI_BOUND_BG2_MINUS1); 3489 3490 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom); 3491 tssi_bounds[4] = rt2x00_get_field16(eeprom, 3492 EEPROM_TSSI_BOUND_BG3_REF); 3493 tssi_bounds[5] = rt2x00_get_field16(eeprom, 3494 EEPROM_TSSI_BOUND_BG3_PLUS1); 3495 3496 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom); 3497 tssi_bounds[6] = rt2x00_get_field16(eeprom, 3498 EEPROM_TSSI_BOUND_BG4_PLUS2); 3499 tssi_bounds[7] = rt2x00_get_field16(eeprom, 3500 EEPROM_TSSI_BOUND_BG4_PLUS3); 3501 3502 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom); 3503 tssi_bounds[8] = rt2x00_get_field16(eeprom, 3504 EEPROM_TSSI_BOUND_BG5_PLUS4); 3505 3506 step = rt2x00_get_field16(eeprom, 3507 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 3508 } else { 3509 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom); 3510 tssi_bounds[0] = rt2x00_get_field16(eeprom, 3511 EEPROM_TSSI_BOUND_A1_MINUS4); 3512 tssi_bounds[1] = rt2x00_get_field16(eeprom, 3513 EEPROM_TSSI_BOUND_A1_MINUS3); 3514 3515 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom); 3516 tssi_bounds[2] = rt2x00_get_field16(eeprom, 3517 EEPROM_TSSI_BOUND_A2_MINUS2); 3518 tssi_bounds[3] = rt2x00_get_field16(eeprom, 3519 EEPROM_TSSI_BOUND_A2_MINUS1); 3520 3521 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom); 3522 tssi_bounds[4] = rt2x00_get_field16(eeprom, 3523 EEPROM_TSSI_BOUND_A3_REF); 3524 tssi_bounds[5] = rt2x00_get_field16(eeprom, 3525 EEPROM_TSSI_BOUND_A3_PLUS1); 3526 3527 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom); 3528 tssi_bounds[6] = rt2x00_get_field16(eeprom, 3529 EEPROM_TSSI_BOUND_A4_PLUS2); 3530 tssi_bounds[7] = rt2x00_get_field16(eeprom, 3531 EEPROM_TSSI_BOUND_A4_PLUS3); 3532 3533 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom); 3534 tssi_bounds[8] = rt2x00_get_field16(eeprom, 3535 EEPROM_TSSI_BOUND_A5_PLUS4); 3536 3537 step = rt2x00_get_field16(eeprom, 3538 EEPROM_TSSI_BOUND_A5_AGC_STEP); 3539 } 3540 3541 /* 3542 * Check if temperature compensation is supported. 3543 */ 3544 if (tssi_bounds[4] == 0xff || step == 0xff) 3545 return 0; 3546 3547 /* 3548 * Read current TSSI (BBP 49). 3549 */ 3550 rt2800_bbp_read(rt2x00dev, 49, ¤t_tssi); 3551 3552 /* 3553 * Compare TSSI value (BBP49) with the compensation boundaries 3554 * from the EEPROM and increase or decrease tx power. 3555 */ 3556 for (i = 0; i <= 3; i++) { 3557 if (current_tssi > tssi_bounds[i]) 3558 break; 3559 } 3560 3561 if (i == 4) { 3562 for (i = 8; i >= 5; i--) { 3563 if (current_tssi < tssi_bounds[i]) 3564 break; 3565 } 3566 } 3567 3568 return (i - 4) * step; 3569} 3570 3571static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 3572 enum ieee80211_band band) 3573{ 3574 u16 eeprom; 3575 u8 comp_en; 3576 u8 comp_type; 3577 int comp_value = 0; 3578 3579 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom); 3580 3581 /* 3582 * HT40 compensation not required. 3583 */ 3584 if (eeprom == 0xffff || 3585 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 3586 return 0; 3587 3588 if (band == IEEE80211_BAND_2GHZ) { 3589 comp_en = rt2x00_get_field16(eeprom, 3590 EEPROM_TXPOWER_DELTA_ENABLE_2G); 3591 if (comp_en) { 3592 comp_type = rt2x00_get_field16(eeprom, 3593 EEPROM_TXPOWER_DELTA_TYPE_2G); 3594 comp_value = rt2x00_get_field16(eeprom, 3595 EEPROM_TXPOWER_DELTA_VALUE_2G); 3596 if (!comp_type) 3597 comp_value = -comp_value; 3598 } 3599 } else { 3600 comp_en = rt2x00_get_field16(eeprom, 3601 EEPROM_TXPOWER_DELTA_ENABLE_5G); 3602 if (comp_en) { 3603 comp_type = rt2x00_get_field16(eeprom, 3604 EEPROM_TXPOWER_DELTA_TYPE_5G); 3605 comp_value = rt2x00_get_field16(eeprom, 3606 EEPROM_TXPOWER_DELTA_VALUE_5G); 3607 if (!comp_type) 3608 comp_value = -comp_value; 3609 } 3610 } 3611 3612 return comp_value; 3613} 3614 3615static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 3616 int power_level, int max_power) 3617{ 3618 int delta; 3619 3620 if (rt2x00_has_cap_power_limit(rt2x00dev)) 3621 return 0; 3622 3623 /* 3624 * XXX: We don't know the maximum transmit power of our hardware since 3625 * the EEPROM doesn't expose it. We only know that we are calibrated 3626 * to 100% tx power. 3627 * 3628 * Hence, we assume the regulatory limit that cfg80211 calulated for 3629 * the current channel is our maximum and if we are requested to lower 3630 * the value we just reduce our tx power accordingly. 3631 */ 3632 delta = power_level - max_power; 3633 return min(delta, 0); 3634} 3635 3636static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 3637 enum ieee80211_band band, int power_level, 3638 u8 txpower, int delta) 3639{ 3640 u16 eeprom; 3641 u8 criterion; 3642 u8 eirp_txpower; 3643 u8 eirp_txpower_criterion; 3644 u8 reg_limit; 3645 3646 if (rt2x00_rt(rt2x00dev, RT3593)) 3647 return min_t(u8, txpower, 0xc); 3648 3649 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 3650 /* 3651 * Check if eirp txpower exceed txpower_limit. 3652 * We use OFDM 6M as criterion and its eirp txpower 3653 * is stored at EEPROM_EIRP_MAX_TX_POWER. 3654 * .11b data rate need add additional 4dbm 3655 * when calculating eirp txpower. 3656 */ 3657 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3658 1, &eeprom); 3659 criterion = rt2x00_get_field16(eeprom, 3660 EEPROM_TXPOWER_BYRATE_RATE0); 3661 3662 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, 3663 &eeprom); 3664 3665 if (band == IEEE80211_BAND_2GHZ) 3666 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 3667 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 3668 else 3669 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 3670 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 3671 3672 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 3673 (is_rate_b ? 4 : 0) + delta; 3674 3675 reg_limit = (eirp_txpower > power_level) ? 3676 (eirp_txpower - power_level) : 0; 3677 } else 3678 reg_limit = 0; 3679 3680 txpower = max(0, txpower + delta - reg_limit); 3681 return min_t(u8, txpower, 0xc); 3682} 3683 3684 3685enum { 3686 TX_PWR_CFG_0_IDX, 3687 TX_PWR_CFG_1_IDX, 3688 TX_PWR_CFG_2_IDX, 3689 TX_PWR_CFG_3_IDX, 3690 TX_PWR_CFG_4_IDX, 3691 TX_PWR_CFG_5_IDX, 3692 TX_PWR_CFG_6_IDX, 3693 TX_PWR_CFG_7_IDX, 3694 TX_PWR_CFG_8_IDX, 3695 TX_PWR_CFG_9_IDX, 3696 TX_PWR_CFG_0_EXT_IDX, 3697 TX_PWR_CFG_1_EXT_IDX, 3698 TX_PWR_CFG_2_EXT_IDX, 3699 TX_PWR_CFG_3_EXT_IDX, 3700 TX_PWR_CFG_4_EXT_IDX, 3701 TX_PWR_CFG_IDX_COUNT, 3702}; 3703 3704static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 3705 struct ieee80211_channel *chan, 3706 int power_level) 3707{ 3708 u8 txpower; 3709 u16 eeprom; 3710 u32 regs[TX_PWR_CFG_IDX_COUNT]; 3711 unsigned int offset; 3712 enum ieee80211_band band = chan->band; 3713 int delta; 3714 int i; 3715 3716 memset(regs, '\0', sizeof(regs)); 3717 3718 /* TODO: adapt TX power reduction from the rt28xx code */ 3719 3720 /* calculate temperature compensation delta */ 3721 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 3722 3723 if (band == IEEE80211_BAND_5GHZ) 3724 offset = 16; 3725 else 3726 offset = 0; 3727 3728 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 3729 offset += 8; 3730 3731 /* read the next four txpower values */ 3732 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3733 offset, &eeprom); 3734 3735 /* CCK 1MBS,2MBS */ 3736 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3737 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 3738 txpower, delta); 3739 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3740 TX_PWR_CFG_0_CCK1_CH0, txpower); 3741 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3742 TX_PWR_CFG_0_CCK1_CH1, txpower); 3743 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 3744 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 3745 3746 /* CCK 5.5MBS,11MBS */ 3747 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3748 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 3749 txpower, delta); 3750 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3751 TX_PWR_CFG_0_CCK5_CH0, txpower); 3752 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3753 TX_PWR_CFG_0_CCK5_CH1, txpower); 3754 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 3755 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 3756 3757 /* OFDM 6MBS,9MBS */ 3758 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3759 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3760 txpower, delta); 3761 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3762 TX_PWR_CFG_0_OFDM6_CH0, txpower); 3763 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3764 TX_PWR_CFG_0_OFDM6_CH1, txpower); 3765 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 3766 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 3767 3768 /* OFDM 12MBS,18MBS */ 3769 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 3770 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3771 txpower, delta); 3772 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3773 TX_PWR_CFG_0_OFDM12_CH0, txpower); 3774 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 3775 TX_PWR_CFG_0_OFDM12_CH1, txpower); 3776 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 3777 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 3778 3779 /* read the next four txpower values */ 3780 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3781 offset + 1, &eeprom); 3782 3783 /* OFDM 24MBS,36MBS */ 3784 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3785 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3786 txpower, delta); 3787 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3788 TX_PWR_CFG_1_OFDM24_CH0, txpower); 3789 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3790 TX_PWR_CFG_1_OFDM24_CH1, txpower); 3791 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 3792 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 3793 3794 /* OFDM 48MBS */ 3795 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3796 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3797 txpower, delta); 3798 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3799 TX_PWR_CFG_1_OFDM48_CH0, txpower); 3800 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3801 TX_PWR_CFG_1_OFDM48_CH1, txpower); 3802 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 3803 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 3804 3805 /* OFDM 54MBS */ 3806 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3807 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3808 txpower, delta); 3809 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3810 TX_PWR_CFG_7_OFDM54_CH0, txpower); 3811 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3812 TX_PWR_CFG_7_OFDM54_CH1, txpower); 3813 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3814 TX_PWR_CFG_7_OFDM54_CH2, txpower); 3815 3816 /* read the next four txpower values */ 3817 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3818 offset + 2, &eeprom); 3819 3820 /* MCS 0,1 */ 3821 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3822 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3823 txpower, delta); 3824 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3825 TX_PWR_CFG_1_MCS0_CH0, txpower); 3826 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3827 TX_PWR_CFG_1_MCS0_CH1, txpower); 3828 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 3829 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 3830 3831 /* MCS 2,3 */ 3832 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3833 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3834 txpower, delta); 3835 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3836 TX_PWR_CFG_1_MCS2_CH0, txpower); 3837 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 3838 TX_PWR_CFG_1_MCS2_CH1, txpower); 3839 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 3840 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 3841 3842 /* MCS 4,5 */ 3843 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3844 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3845 txpower, delta); 3846 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3847 TX_PWR_CFG_2_MCS4_CH0, txpower); 3848 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3849 TX_PWR_CFG_2_MCS4_CH1, txpower); 3850 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 3851 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 3852 3853 /* MCS 6 */ 3854 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 3855 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3856 txpower, delta); 3857 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3858 TX_PWR_CFG_2_MCS6_CH0, txpower); 3859 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3860 TX_PWR_CFG_2_MCS6_CH1, txpower); 3861 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 3862 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 3863 3864 /* read the next four txpower values */ 3865 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3866 offset + 3, &eeprom); 3867 3868 /* MCS 7 */ 3869 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3870 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3871 txpower, delta); 3872 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3873 TX_PWR_CFG_7_MCS7_CH0, txpower); 3874 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3875 TX_PWR_CFG_7_MCS7_CH1, txpower); 3876 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 3877 TX_PWR_CFG_7_MCS7_CH2, txpower); 3878 3879 /* MCS 8,9 */ 3880 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3881 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3882 txpower, delta); 3883 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3884 TX_PWR_CFG_2_MCS8_CH0, txpower); 3885 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3886 TX_PWR_CFG_2_MCS8_CH1, txpower); 3887 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 3888 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 3889 3890 /* MCS 10,11 */ 3891 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3892 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3893 txpower, delta); 3894 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3895 TX_PWR_CFG_2_MCS10_CH0, txpower); 3896 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 3897 TX_PWR_CFG_2_MCS10_CH1, txpower); 3898 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 3899 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 3900 3901 /* MCS 12,13 */ 3902 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 3903 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3904 txpower, delta); 3905 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 3906 TX_PWR_CFG_3_MCS12_CH0, txpower); 3907 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 3908 TX_PWR_CFG_3_MCS12_CH1, txpower); 3909 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 3910 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 3911 3912 /* read the next four txpower values */ 3913 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3914 offset + 4, &eeprom); 3915 3916 /* MCS 14 */ 3917 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3918 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3919 txpower, delta); 3920 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 3921 TX_PWR_CFG_3_MCS14_CH0, txpower); 3922 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 3923 TX_PWR_CFG_3_MCS14_CH1, txpower); 3924 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 3925 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 3926 3927 /* MCS 15 */ 3928 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3929 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3930 txpower, delta); 3931 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 3932 TX_PWR_CFG_8_MCS15_CH0, txpower); 3933 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 3934 TX_PWR_CFG_8_MCS15_CH1, txpower); 3935 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 3936 TX_PWR_CFG_8_MCS15_CH2, txpower); 3937 3938 /* MCS 16,17 */ 3939 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3940 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3941 txpower, delta); 3942 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3943 TX_PWR_CFG_5_MCS16_CH0, txpower); 3944 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3945 TX_PWR_CFG_5_MCS16_CH1, txpower); 3946 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3947 TX_PWR_CFG_5_MCS16_CH2, txpower); 3948 3949 /* MCS 18,19 */ 3950 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 3951 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3952 txpower, delta); 3953 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3954 TX_PWR_CFG_5_MCS18_CH0, txpower); 3955 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3956 TX_PWR_CFG_5_MCS18_CH1, txpower); 3957 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 3958 TX_PWR_CFG_5_MCS18_CH2, txpower); 3959 3960 /* read the next four txpower values */ 3961 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3962 offset + 5, &eeprom); 3963 3964 /* MCS 20,21 */ 3965 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 3966 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3967 txpower, delta); 3968 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 3969 TX_PWR_CFG_6_MCS20_CH0, txpower); 3970 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 3971 TX_PWR_CFG_6_MCS20_CH1, txpower); 3972 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 3973 TX_PWR_CFG_6_MCS20_CH2, txpower); 3974 3975 /* MCS 22 */ 3976 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 3977 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3978 txpower, delta); 3979 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 3980 TX_PWR_CFG_6_MCS22_CH0, txpower); 3981 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 3982 TX_PWR_CFG_6_MCS22_CH1, txpower); 3983 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 3984 TX_PWR_CFG_6_MCS22_CH2, txpower); 3985 3986 /* MCS 23 */ 3987 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 3988 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 3989 txpower, delta); 3990 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 3991 TX_PWR_CFG_8_MCS23_CH0, txpower); 3992 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 3993 TX_PWR_CFG_8_MCS23_CH1, txpower); 3994 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 3995 TX_PWR_CFG_8_MCS23_CH2, txpower); 3996 3997 /* read the next four txpower values */ 3998 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 3999 offset + 6, &eeprom); 4000 4001 /* STBC, MCS 0,1 */ 4002 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4003 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4004 txpower, delta); 4005 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4006 TX_PWR_CFG_3_STBC0_CH0, txpower); 4007 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4008 TX_PWR_CFG_3_STBC0_CH1, txpower); 4009 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4010 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 4011 4012 /* STBC, MCS 2,3 */ 4013 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4014 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4015 txpower, delta); 4016 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4017 TX_PWR_CFG_3_STBC2_CH0, txpower); 4018 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4019 TX_PWR_CFG_3_STBC2_CH1, txpower); 4020 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4021 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 4022 4023 /* STBC, MCS 4,5 */ 4024 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4025 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4026 txpower, delta); 4027 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 4028 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 4029 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 4030 txpower); 4031 4032 /* STBC, MCS 6 */ 4033 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4034 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4035 txpower, delta); 4036 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 4037 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 4038 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 4039 txpower); 4040 4041 /* read the next four txpower values */ 4042 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4043 offset + 7, &eeprom); 4044 4045 /* STBC, MCS 7 */ 4046 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4047 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4048 txpower, delta); 4049 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4050 TX_PWR_CFG_9_STBC7_CH0, txpower); 4051 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4052 TX_PWR_CFG_9_STBC7_CH1, txpower); 4053 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4054 TX_PWR_CFG_9_STBC7_CH2, txpower); 4055 4056 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 4057 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 4058 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 4059 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 4060 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 4061 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 4062 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 4063 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 4064 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 4065 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 4066 4067 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 4068 regs[TX_PWR_CFG_0_EXT_IDX]); 4069 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 4070 regs[TX_PWR_CFG_1_EXT_IDX]); 4071 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 4072 regs[TX_PWR_CFG_2_EXT_IDX]); 4073 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 4074 regs[TX_PWR_CFG_3_EXT_IDX]); 4075 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 4076 regs[TX_PWR_CFG_4_EXT_IDX]); 4077 4078 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 4079 rt2x00_dbg(rt2x00dev, 4080 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 4081 (band == IEEE80211_BAND_5GHZ) ? '5' : '2', 4082 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 4083 '4' : '2', 4084 (i > TX_PWR_CFG_9_IDX) ? 4085 (i - TX_PWR_CFG_9_IDX - 1) : i, 4086 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 4087 (unsigned long) regs[i]); 4088} 4089 4090/* 4091 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 4092 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 4093 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 4094 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 4095 * Reference per rate transmit power values are located in the EEPROM at 4096 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 4097 * current conditions (i.e. band, bandwidth, temperature, user settings). 4098 */ 4099static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 4100 struct ieee80211_channel *chan, 4101 int power_level) 4102{ 4103 u8 txpower, r1; 4104 u16 eeprom; 4105 u32 reg, offset; 4106 int i, is_rate_b, delta, power_ctrl; 4107 enum ieee80211_band band = chan->band; 4108 4109 /* 4110 * Calculate HT40 compensation. For 40MHz we need to add or subtract 4111 * value read from EEPROM (different for 2GHz and for 5GHz). 4112 */ 4113 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 4114 4115 /* 4116 * Calculate temperature compensation. Depends on measurement of current 4117 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 4118 * to temperature or maybe other factors) is smaller or bigger than 4119 * expected. We adjust it, based on TSSI reference and boundaries values 4120 * provided in EEPROM. 4121 */ 4122 switch (rt2x00dev->chip.rt) { 4123 case RT2860: 4124 case RT2872: 4125 case RT2883: 4126 case RT3070: 4127 case RT3071: 4128 case RT3090: 4129 case RT3572: 4130 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 4131 break; 4132 default: 4133 /* TODO: temperature compensation code for other chips. */ 4134 break; 4135 } 4136 4137 /* 4138 * Decrease power according to user settings, on devices with unknown 4139 * maximum tx power. For other devices we take user power_level into 4140 * consideration on rt2800_compensate_txpower(). 4141 */ 4142 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 4143 chan->max_power); 4144 4145 /* 4146 * BBP_R1 controls TX power for all rates, it allow to set the following 4147 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 4148 * 4149 * TODO: we do not use +6 dBm option to do not increase power beyond 4150 * regulatory limit, however this could be utilized for devices with 4151 * CAPABILITY_POWER_LIMIT. 4152 */ 4153 if (delta <= -12) { 4154 power_ctrl = 2; 4155 delta += 12; 4156 } else if (delta <= -6) { 4157 power_ctrl = 1; 4158 delta += 6; 4159 } else { 4160 power_ctrl = 0; 4161 } 4162 rt2800_bbp_read(rt2x00dev, 1, &r1); 4163 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 4164 rt2800_bbp_write(rt2x00dev, 1, r1); 4165 4166 offset = TX_PWR_CFG_0; 4167 4168 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 4169 /* just to be safe */ 4170 if (offset > TX_PWR_CFG_4) 4171 break; 4172 4173 rt2800_register_read(rt2x00dev, offset, ®); 4174 4175 /* read the next four txpower values */ 4176 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4177 i, &eeprom); 4178 4179 is_rate_b = i ? 0 : 1; 4180 /* 4181 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 4182 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 4183 * TX_PWR_CFG_4: unknown 4184 */ 4185 txpower = rt2x00_get_field16(eeprom, 4186 EEPROM_TXPOWER_BYRATE_RATE0); 4187 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4188 power_level, txpower, delta); 4189 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 4190 4191 /* 4192 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 4193 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 4194 * TX_PWR_CFG_4: unknown 4195 */ 4196 txpower = rt2x00_get_field16(eeprom, 4197 EEPROM_TXPOWER_BYRATE_RATE1); 4198 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4199 power_level, txpower, delta); 4200 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 4201 4202 /* 4203 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 4204 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 4205 * TX_PWR_CFG_4: unknown 4206 */ 4207 txpower = rt2x00_get_field16(eeprom, 4208 EEPROM_TXPOWER_BYRATE_RATE2); 4209 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4210 power_level, txpower, delta); 4211 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 4212 4213 /* 4214 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 4215 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 4216 * TX_PWR_CFG_4: unknown 4217 */ 4218 txpower = rt2x00_get_field16(eeprom, 4219 EEPROM_TXPOWER_BYRATE_RATE3); 4220 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4221 power_level, txpower, delta); 4222 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 4223 4224 /* read the next four txpower values */ 4225 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4226 i + 1, &eeprom); 4227 4228 is_rate_b = 0; 4229 /* 4230 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 4231 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 4232 * TX_PWR_CFG_4: unknown 4233 */ 4234 txpower = rt2x00_get_field16(eeprom, 4235 EEPROM_TXPOWER_BYRATE_RATE0); 4236 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4237 power_level, txpower, delta); 4238 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 4239 4240 /* 4241 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 4242 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 4243 * TX_PWR_CFG_4: unknown 4244 */ 4245 txpower = rt2x00_get_field16(eeprom, 4246 EEPROM_TXPOWER_BYRATE_RATE1); 4247 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4248 power_level, txpower, delta); 4249 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 4250 4251 /* 4252 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 4253 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 4254 * TX_PWR_CFG_4: unknown 4255 */ 4256 txpower = rt2x00_get_field16(eeprom, 4257 EEPROM_TXPOWER_BYRATE_RATE2); 4258 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4259 power_level, txpower, delta); 4260 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 4261 4262 /* 4263 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 4264 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 4265 * TX_PWR_CFG_4: unknown 4266 */ 4267 txpower = rt2x00_get_field16(eeprom, 4268 EEPROM_TXPOWER_BYRATE_RATE3); 4269 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 4270 power_level, txpower, delta); 4271 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 4272 4273 rt2800_register_write(rt2x00dev, offset, reg); 4274 4275 /* next TX_PWR_CFG register */ 4276 offset += 4; 4277 } 4278} 4279 4280static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 4281 struct ieee80211_channel *chan, 4282 int power_level) 4283{ 4284 if (rt2x00_rt(rt2x00dev, RT3593)) 4285 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 4286 else 4287 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 4288} 4289 4290void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 4291{ 4292 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 4293 rt2x00dev->tx_power); 4294} 4295EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 4296 4297void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 4298{ 4299 u32 tx_pin; 4300 u8 rfcsr; 4301 4302 /* 4303 * A voltage-controlled oscillator(VCO) is an electronic oscillator 4304 * designed to be controlled in oscillation frequency by a voltage 4305 * input. Maybe the temperature will affect the frequency of 4306 * oscillation to be shifted. The VCO calibration will be called 4307 * periodically to adjust the frequency to be precision. 4308 */ 4309 4310 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); 4311 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 4312 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4313 4314 switch (rt2x00dev->chip.rf) { 4315 case RF2020: 4316 case RF3020: 4317 case RF3021: 4318 case RF3022: 4319 case RF3320: 4320 case RF3052: 4321 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); 4322 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 4323 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 4324 break; 4325 case RF3053: 4326 case RF3070: 4327 case RF3290: 4328 case RF5360: 4329 case RF5362: 4330 case RF5370: 4331 case RF5372: 4332 case RF5390: 4333 case RF5392: 4334 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); 4335 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 4336 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 4337 break; 4338 default: 4339 return; 4340 } 4341 4342 mdelay(1); 4343 4344 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); 4345 if (rt2x00dev->rf_channel <= 14) { 4346 switch (rt2x00dev->default_ant.tx_chain_num) { 4347 case 3: 4348 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 4349 /* fall through */ 4350 case 2: 4351 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 4352 /* fall through */ 4353 case 1: 4354 default: 4355 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 4356 break; 4357 } 4358 } else { 4359 switch (rt2x00dev->default_ant.tx_chain_num) { 4360 case 3: 4361 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 4362 /* fall through */ 4363 case 2: 4364 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 4365 /* fall through */ 4366 case 1: 4367 default: 4368 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 4369 break; 4370 } 4371 } 4372 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4373 4374} 4375EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 4376 4377static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 4378 struct rt2x00lib_conf *libconf) 4379{ 4380 u32 reg; 4381 4382 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); 4383 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 4384 libconf->conf->short_frame_max_tx_count); 4385 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 4386 libconf->conf->long_frame_max_tx_count); 4387 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 4388} 4389 4390static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 4391 struct rt2x00lib_conf *libconf) 4392{ 4393 enum dev_state state = 4394 (libconf->conf->flags & IEEE80211_CONF_PS) ? 4395 STATE_SLEEP : STATE_AWAKE; 4396 u32 reg; 4397 4398 if (state == STATE_SLEEP) { 4399 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 4400 4401 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); 4402 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 4403 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 4404 libconf->conf->listen_interval - 1); 4405 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 4406 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 4407 4408 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 4409 } else { 4410 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); 4411 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 4412 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 4413 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 4414 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 4415 4416 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 4417 } 4418} 4419 4420void rt2800_config(struct rt2x00_dev *rt2x00dev, 4421 struct rt2x00lib_conf *libconf, 4422 const unsigned int flags) 4423{ 4424 /* Always recalculate LNA gain before changing configuration */ 4425 rt2800_config_lna_gain(rt2x00dev, libconf); 4426 4427 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 4428 rt2800_config_channel(rt2x00dev, libconf->conf, 4429 &libconf->rf, &libconf->channel); 4430 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 4431 libconf->conf->power_level); 4432 } 4433 if (flags & IEEE80211_CONF_CHANGE_POWER) 4434 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 4435 libconf->conf->power_level); 4436 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 4437 rt2800_config_retry_limit(rt2x00dev, libconf); 4438 if (flags & IEEE80211_CONF_CHANGE_PS) 4439 rt2800_config_ps(rt2x00dev, libconf); 4440} 4441EXPORT_SYMBOL_GPL(rt2800_config); 4442 4443/* 4444 * Link tuning 4445 */ 4446void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 4447{ 4448 u32 reg; 4449 4450 /* 4451 * Update FCS error count from register. 4452 */ 4453 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); 4454 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 4455} 4456EXPORT_SYMBOL_GPL(rt2800_link_stats); 4457 4458static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 4459{ 4460 u8 vgc; 4461 4462 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { 4463 if (rt2x00_rt(rt2x00dev, RT3070) || 4464 rt2x00_rt(rt2x00dev, RT3071) || 4465 rt2x00_rt(rt2x00dev, RT3090) || 4466 rt2x00_rt(rt2x00dev, RT3290) || 4467 rt2x00_rt(rt2x00dev, RT3390) || 4468 rt2x00_rt(rt2x00dev, RT3572) || 4469 rt2x00_rt(rt2x00dev, RT3593) || 4470 rt2x00_rt(rt2x00dev, RT5390) || 4471 rt2x00_rt(rt2x00dev, RT5392) || 4472 rt2x00_rt(rt2x00dev, RT5592)) 4473 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 4474 else 4475 vgc = 0x2e + rt2x00dev->lna_gain; 4476 } else { /* 5GHZ band */ 4477 if (rt2x00_rt(rt2x00dev, RT3593)) 4478 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 4479 else if (rt2x00_rt(rt2x00dev, RT5592)) 4480 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 4481 else { 4482 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4483 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 4484 else 4485 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 4486 } 4487 } 4488 4489 return vgc; 4490} 4491 4492static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 4493 struct link_qual *qual, u8 vgc_level) 4494{ 4495 if (qual->vgc_level != vgc_level) { 4496 if (rt2x00_rt(rt2x00dev, RT3572) || 4497 rt2x00_rt(rt2x00dev, RT3593)) { 4498 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 4499 vgc_level); 4500 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 4501 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 4502 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 4503 } else { 4504 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 4505 } 4506 4507 qual->vgc_level = vgc_level; 4508 qual->vgc_level_reg = vgc_level; 4509 } 4510} 4511 4512void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 4513{ 4514 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 4515} 4516EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 4517 4518void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 4519 const u32 count) 4520{ 4521 u8 vgc; 4522 4523 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 4524 return; 4525 4526 /* When RSSI is better than a certain threshold, increase VGC 4527 * with a chip specific value in order to improve the balance 4528 * between sensibility and noise isolation. 4529 */ 4530 4531 vgc = rt2800_get_default_vgc(rt2x00dev); 4532 4533 switch (rt2x00dev->chip.rt) { 4534 case RT3572: 4535 case RT3593: 4536 if (qual->rssi > -65) { 4537 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) 4538 vgc += 0x20; 4539 else 4540 vgc += 0x10; 4541 } 4542 break; 4543 4544 case RT5592: 4545 if (qual->rssi > -65) 4546 vgc += 0x20; 4547 break; 4548 4549 default: 4550 if (qual->rssi > -80) 4551 vgc += 0x10; 4552 break; 4553 } 4554 4555 rt2800_set_vgc(rt2x00dev, qual, vgc); 4556} 4557EXPORT_SYMBOL_GPL(rt2800_link_tuner); 4558 4559/* 4560 * Initialization functions. 4561 */ 4562static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 4563{ 4564 u32 reg; 4565 u16 eeprom; 4566 unsigned int i; 4567 int ret; 4568 4569 rt2800_disable_wpdma(rt2x00dev); 4570 4571 ret = rt2800_drv_init_registers(rt2x00dev); 4572 if (ret) 4573 return ret; 4574 4575 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 4576 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 4577 4578 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 4579 4580 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); 4581 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 4582 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 4583 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 4584 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 4585 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 4586 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 4587 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 4588 4589 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 4590 4591 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); 4592 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 4593 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 4594 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 4595 4596 if (rt2x00_rt(rt2x00dev, RT3290)) { 4597 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); 4598 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 4599 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 4600 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 4601 } 4602 4603 rt2800_register_read(rt2x00dev, CMB_CTRL, ®); 4604 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 4605 rt2x00_set_field32(®, LDO0_EN, 1); 4606 rt2x00_set_field32(®, LDO_BGSEL, 3); 4607 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 4608 } 4609 4610 rt2800_register_read(rt2x00dev, OSC_CTRL, ®); 4611 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 4612 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 4613 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 4614 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 4615 4616 rt2800_register_read(rt2x00dev, COEX_CFG0, ®); 4617 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 4618 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 4619 4620 rt2800_register_read(rt2x00dev, COEX_CFG2, ®); 4621 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 4622 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 4623 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 4624 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 4625 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 4626 4627 rt2800_register_read(rt2x00dev, PLL_CTRL, ®); 4628 rt2x00_set_field32(®, PLL_CONTROL, 1); 4629 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 4630 } 4631 4632 if (rt2x00_rt(rt2x00dev, RT3071) || 4633 rt2x00_rt(rt2x00dev, RT3090) || 4634 rt2x00_rt(rt2x00dev, RT3290) || 4635 rt2x00_rt(rt2x00dev, RT3390)) { 4636 4637 if (rt2x00_rt(rt2x00dev, RT3290)) 4638 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 4639 0x00000404); 4640 else 4641 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 4642 0x00000400); 4643 4644 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4645 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 4646 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 4647 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 4648 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, 4649 &eeprom); 4650 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 4651 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4652 0x0000002c); 4653 else 4654 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4655 0x0000000f); 4656 } else { 4657 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4658 } 4659 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 4660 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 4661 4662 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 4663 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4664 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 4665 } else { 4666 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4667 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4668 } 4669 } else if (rt2800_is_305x_soc(rt2x00dev)) { 4670 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 4671 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4672 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 4673 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 4674 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 4675 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4676 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4677 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 4678 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 4679 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4680 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 4681 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 4682 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 4683 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 4684 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, 4685 &eeprom); 4686 if (rt2x00_get_field16(eeprom, 4687 EEPROM_NIC_CONF1_DAC_TEST)) 4688 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4689 0x0000001f); 4690 else 4691 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4692 0x0000000f); 4693 } else { 4694 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 4695 0x00000000); 4696 } 4697 } else if (rt2x00_rt(rt2x00dev, RT5390) || 4698 rt2x00_rt(rt2x00dev, RT5392) || 4699 rt2x00_rt(rt2x00dev, RT5592)) { 4700 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 4701 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4702 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 4703 } else { 4704 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 4705 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 4706 } 4707 4708 rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); 4709 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 4710 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 4711 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 4712 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 4713 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 4714 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 4715 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 4716 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 4717 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 4718 4719 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); 4720 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 4721 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 4722 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 4723 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 4724 4725 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); 4726 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 4727 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 4728 rt2x00_rt(rt2x00dev, RT2883) || 4729 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) 4730 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2); 4731 else 4732 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1); 4733 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0); 4734 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0); 4735 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 4736 4737 rt2800_register_read(rt2x00dev, LED_CFG, ®); 4738 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 4739 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 4740 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 4741 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 4742 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 4743 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 4744 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 4745 rt2800_register_write(rt2x00dev, LED_CFG, reg); 4746 4747 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 4748 4749 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); 4750 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15); 4751 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31); 4752 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 4753 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 4754 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 4755 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 4756 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 4757 4758 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); 4759 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 4760 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 4761 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0); 4762 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 4763 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1); 4764 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 4765 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 4766 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 4767 4768 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); 4769 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 4770 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 4771 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 4772 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 4773 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4774 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4775 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 4776 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4777 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 4778 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 4779 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 4780 4781 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); 4782 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 4783 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 4784 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 4785 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 4786 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4787 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4788 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 4789 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4790 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 4791 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 4792 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 4793 4794 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); 4795 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 4796 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0); 4797 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 4798 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); 4799 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4800 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4801 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 4802 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4803 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 4804 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 4805 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 4806 4807 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); 4808 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 4809 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0); 4810 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 4811 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); 4812 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4813 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4814 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 4815 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4816 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 4817 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 4818 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 4819 4820 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); 4821 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 4822 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0); 4823 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 4824 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); 4825 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4826 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4827 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 4828 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4829 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 4830 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 4831 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 4832 4833 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); 4834 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 4835 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0); 4836 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 4837 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); 4838 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 4839 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 4840 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 4841 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 4842 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 4843 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 4844 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 4845 4846 if (rt2x00_is_usb(rt2x00dev)) { 4847 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 4848 4849 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); 4850 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 4851 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 4852 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 4853 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 4854 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 4855 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 4856 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 4857 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 4858 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 4859 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 4860 } 4861 4862 /* 4863 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 4864 * although it is reserved. 4865 */ 4866 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®); 4867 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 4868 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 4869 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 4870 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 4871 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 4872 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 4873 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 4874 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 4875 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 4876 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 4877 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 4878 4879 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 4880 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 4881 4882 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); 4883 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); 4884 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 4885 IEEE80211_MAX_RTS_THRESHOLD); 4886 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0); 4887 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 4888 4889 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 4890 4891 /* 4892 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 4893 * time should be set to 16. However, the original Ralink driver uses 4894 * 16 for both and indeed using a value of 10 for CCK SIFS results in 4895 * connection problems with 11g + CTS protection. Hence, use the same 4896 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 4897 */ 4898 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); 4899 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 4900 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 4901 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 4902 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 4903 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 4904 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 4905 4906 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 4907 4908 /* 4909 * ASIC will keep garbage value after boot, clear encryption keys. 4910 */ 4911 for (i = 0; i < 4; i++) 4912 rt2800_register_write(rt2x00dev, 4913 SHARED_KEY_MODE_ENTRY(i), 0); 4914 4915 for (i = 0; i < 256; i++) { 4916 rt2800_config_wcid(rt2x00dev, NULL, i); 4917 rt2800_delete_wcid_attr(rt2x00dev, i); 4918 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 4919 } 4920 4921 /* 4922 * Clear all beacons 4923 */ 4924 for (i = 0; i < 8; i++) 4925 rt2800_clear_beacon_register(rt2x00dev, i); 4926 4927 if (rt2x00_is_usb(rt2x00dev)) { 4928 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); 4929 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 4930 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 4931 } else if (rt2x00_is_pcie(rt2x00dev)) { 4932 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); 4933 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 4934 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 4935 } 4936 4937 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®); 4938 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 4939 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 4940 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 4941 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 4942 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 4943 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 4944 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 4945 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 4946 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 4947 4948 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®); 4949 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 4950 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 4951 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 4952 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 4953 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 4954 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 4955 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 4956 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 4957 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 4958 4959 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®); 4960 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 4961 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 4962 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 4963 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 4964 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 4965 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 4966 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 4967 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 4968 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 4969 4970 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®); 4971 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 4972 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 4973 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 4974 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 4975 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 4976 4977 /* 4978 * Do not force the BA window size, we use the TXWI to set it 4979 */ 4980 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®); 4981 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 4982 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 4983 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 4984 4985 /* 4986 * We must clear the error counters. 4987 * These registers are cleared on read, 4988 * so we may pass a useless variable to store the value. 4989 */ 4990 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); 4991 rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®); 4992 rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®); 4993 rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®); 4994 rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®); 4995 rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®); 4996 4997 /* 4998 * Setup leadtime for pre tbtt interrupt to 6ms 4999 */ 5000 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®); 5001 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 5002 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 5003 5004 /* 5005 * Set up channel statistics timer 5006 */ 5007 rt2800_register_read(rt2x00dev, CH_TIME_CFG, ®); 5008 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 5009 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 5010 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 5011 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 5012 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 5013 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 5014 5015 return 0; 5016} 5017 5018static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) 5019{ 5020 unsigned int i; 5021 u32 reg; 5022 5023 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5024 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®); 5025 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) 5026 return 0; 5027 5028 udelay(REGISTER_BUSY_DELAY); 5029 } 5030 5031 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 5032 return -EACCES; 5033} 5034 5035static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 5036{ 5037 unsigned int i; 5038 u8 value; 5039 5040 /* 5041 * BBP was enabled after firmware was loaded, 5042 * but we need to reactivate it now. 5043 */ 5044 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 5045 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 5046 msleep(1); 5047 5048 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 5049 rt2800_bbp_read(rt2x00dev, 0, &value); 5050 if ((value != 0xff) && (value != 0x00)) 5051 return 0; 5052 udelay(REGISTER_BUSY_DELAY); 5053 } 5054 5055 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 5056 return -EACCES; 5057} 5058 5059static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 5060{ 5061 u8 value; 5062 5063 rt2800_bbp_read(rt2x00dev, 4, &value); 5064 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 5065 rt2800_bbp_write(rt2x00dev, 4, value); 5066} 5067 5068static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 5069{ 5070 rt2800_bbp_write(rt2x00dev, 142, 1); 5071 rt2800_bbp_write(rt2x00dev, 143, 57); 5072} 5073 5074static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 5075{ 5076 const u8 glrt_table[] = { 5077 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 5078 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 5079 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 5080 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 5081 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 5082 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 5083 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 5084 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 5085 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 5086 }; 5087 int i; 5088 5089 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 5090 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 5091 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 5092 } 5093}; 5094 5095static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 5096{ 5097 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 5098 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5099 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 5100 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5101 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5102 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5103 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5104 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5105 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 5106 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5107 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5108 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5109 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5110 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5111 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5112 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5113} 5114 5115static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 5116{ 5117 u16 eeprom; 5118 u8 value; 5119 5120 rt2800_bbp_read(rt2x00dev, 138, &value); 5121 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 5122 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 5123 value |= 0x20; 5124 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 5125 value &= ~0x02; 5126 rt2800_bbp_write(rt2x00dev, 138, value); 5127} 5128 5129static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 5130{ 5131 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5132 5133 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5134 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5135 5136 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5137 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5138 5139 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5140 5141 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 5142 rt2800_bbp_write(rt2x00dev, 80, 0x08); 5143 5144 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5145 5146 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5147 5148 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5149 5150 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5151 5152 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5153 5154 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5155 5156 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5157 5158 rt2800_bbp_write(rt2x00dev, 105, 0x01); 5159 5160 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5161} 5162 5163static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 5164{ 5165 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5166 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5167 5168 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 5169 rt2800_bbp_write(rt2x00dev, 69, 0x16); 5170 rt2800_bbp_write(rt2x00dev, 73, 0x12); 5171 } else { 5172 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5173 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5174 } 5175 5176 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5177 5178 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5179 5180 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5181 5182 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5183 5184 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 5185 rt2800_bbp_write(rt2x00dev, 84, 0x19); 5186 else 5187 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5188 5189 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5190 5191 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5192 5193 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5194 5195 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5196 5197 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5198 5199 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5200} 5201 5202static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 5203{ 5204 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5205 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5206 5207 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5208 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5209 5210 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5211 5212 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5213 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5214 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5215 5216 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5217 5218 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5219 5220 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5221 5222 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5223 5224 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5225 5226 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5227 5228 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 5229 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 5230 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 5231 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5232 else 5233 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5234 5235 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5236 5237 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5238 5239 if (rt2x00_rt(rt2x00dev, RT3071) || 5240 rt2x00_rt(rt2x00dev, RT3090)) 5241 rt2800_disable_unused_dac_adc(rt2x00dev); 5242} 5243 5244static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 5245{ 5246 u8 value; 5247 5248 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5249 5250 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5251 5252 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5253 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5254 5255 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 5256 5257 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5258 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5259 rt2800_bbp_write(rt2x00dev, 75, 0x46); 5260 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5261 5262 rt2800_bbp_write(rt2x00dev, 77, 0x58); 5263 5264 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5265 5266 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 5267 rt2800_bbp_write(rt2x00dev, 79, 0x18); 5268 rt2800_bbp_write(rt2x00dev, 80, 0x09); 5269 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5270 5271 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5272 5273 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 5274 5275 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 5276 5277 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5278 5279 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5280 5281 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5282 5283 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5284 5285 rt2800_bbp_write(rt2x00dev, 104, 0x92); 5286 5287 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 5288 5289 rt2800_bbp_write(rt2x00dev, 106, 0x03); 5290 5291 rt2800_bbp_write(rt2x00dev, 128, 0x12); 5292 5293 rt2800_bbp_write(rt2x00dev, 67, 0x24); 5294 rt2800_bbp_write(rt2x00dev, 143, 0x04); 5295 rt2800_bbp_write(rt2x00dev, 142, 0x99); 5296 rt2800_bbp_write(rt2x00dev, 150, 0x30); 5297 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 5298 rt2800_bbp_write(rt2x00dev, 152, 0x20); 5299 rt2800_bbp_write(rt2x00dev, 153, 0x34); 5300 rt2800_bbp_write(rt2x00dev, 154, 0x40); 5301 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 5302 rt2800_bbp_write(rt2x00dev, 253, 0x04); 5303 5304 rt2800_bbp_read(rt2x00dev, 47, &value); 5305 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 5306 rt2800_bbp_write(rt2x00dev, 47, value); 5307 5308 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 5309 rt2800_bbp_read(rt2x00dev, 3, &value); 5310 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 5311 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 5312 rt2800_bbp_write(rt2x00dev, 3, value); 5313} 5314 5315static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 5316{ 5317 rt2800_bbp_write(rt2x00dev, 3, 0x00); 5318 rt2800_bbp_write(rt2x00dev, 4, 0x50); 5319 5320 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5321 5322 rt2800_bbp_write(rt2x00dev, 47, 0x48); 5323 5324 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5325 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5326 5327 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 5328 5329 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5330 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5331 rt2800_bbp_write(rt2x00dev, 75, 0x46); 5332 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5333 5334 rt2800_bbp_write(rt2x00dev, 77, 0x59); 5335 5336 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5337 5338 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 5339 rt2800_bbp_write(rt2x00dev, 80, 0x08); 5340 rt2800_bbp_write(rt2x00dev, 81, 0x37); 5341 5342 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5343 5344 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5345 5346 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5347 5348 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5349 5350 rt2800_bbp_write(rt2x00dev, 88, 0x90); 5351 5352 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5353 5354 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5355 5356 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5357 5358 rt2800_bbp_write(rt2x00dev, 104, 0x92); 5359 5360 rt2800_bbp_write(rt2x00dev, 105, 0x34); 5361 5362 rt2800_bbp_write(rt2x00dev, 106, 0x05); 5363 5364 rt2800_bbp_write(rt2x00dev, 120, 0x50); 5365 5366 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 5367 5368 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 5369 /* Set ITxBF timeout to 0x9c40=1000msec */ 5370 rt2800_bbp_write(rt2x00dev, 179, 0x02); 5371 rt2800_bbp_write(rt2x00dev, 180, 0x00); 5372 rt2800_bbp_write(rt2x00dev, 182, 0x40); 5373 rt2800_bbp_write(rt2x00dev, 180, 0x01); 5374 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 5375 rt2800_bbp_write(rt2x00dev, 179, 0x00); 5376 /* Reprogram the inband interface to put right values in RXWI */ 5377 rt2800_bbp_write(rt2x00dev, 142, 0x04); 5378 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 5379 rt2800_bbp_write(rt2x00dev, 142, 0x06); 5380 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 5381 rt2800_bbp_write(rt2x00dev, 142, 0x07); 5382 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 5383 rt2800_bbp_write(rt2x00dev, 142, 0x08); 5384 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 5385 5386 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 5387} 5388 5389static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 5390{ 5391 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5392 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5393 5394 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5395 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5396 5397 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5398 5399 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5400 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5401 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5402 5403 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5404 5405 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5406 5407 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5408 5409 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5410 5411 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5412 5413 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5414 5415 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 5416 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5417 else 5418 rt2800_bbp_write(rt2x00dev, 103, 0x00); 5419 5420 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5421 5422 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5423 5424 rt2800_disable_unused_dac_adc(rt2x00dev); 5425} 5426 5427static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 5428{ 5429 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5430 5431 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5432 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5433 5434 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5435 rt2800_bbp_write(rt2x00dev, 73, 0x10); 5436 5437 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5438 5439 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5440 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5441 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5442 5443 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5444 5445 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 5446 5447 rt2800_bbp_write(rt2x00dev, 84, 0x99); 5448 5449 rt2800_bbp_write(rt2x00dev, 86, 0x00); 5450 5451 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5452 5453 rt2800_bbp_write(rt2x00dev, 92, 0x00); 5454 5455 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5456 5457 rt2800_bbp_write(rt2x00dev, 105, 0x05); 5458 5459 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5460 5461 rt2800_disable_unused_dac_adc(rt2x00dev); 5462} 5463 5464static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 5465{ 5466 rt2800_init_bbp_early(rt2x00dev); 5467 5468 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5469 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5470 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5471 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 5472 5473 rt2800_bbp_write(rt2x00dev, 84, 0x19); 5474 5475 /* Enable DC filter */ 5476 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 5477 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5478} 5479 5480static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 5481{ 5482 int ant, div_mode; 5483 u16 eeprom; 5484 u8 value; 5485 5486 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5487 5488 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5489 5490 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 5491 rt2800_bbp_write(rt2x00dev, 66, 0x38); 5492 5493 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 5494 5495 rt2800_bbp_write(rt2x00dev, 69, 0x12); 5496 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5497 rt2800_bbp_write(rt2x00dev, 75, 0x46); 5498 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5499 5500 rt2800_bbp_write(rt2x00dev, 77, 0x59); 5501 5502 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 5503 5504 rt2800_bbp_write(rt2x00dev, 79, 0x13); 5505 rt2800_bbp_write(rt2x00dev, 80, 0x05); 5506 rt2800_bbp_write(rt2x00dev, 81, 0x33); 5507 5508 rt2800_bbp_write(rt2x00dev, 82, 0x62); 5509 5510 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 5511 5512 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 5513 5514 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5515 5516 if (rt2x00_rt(rt2x00dev, RT5392)) 5517 rt2800_bbp_write(rt2x00dev, 88, 0x90); 5518 5519 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5520 5521 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5522 5523 if (rt2x00_rt(rt2x00dev, RT5392)) { 5524 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 5525 rt2800_bbp_write(rt2x00dev, 98, 0x12); 5526 } 5527 5528 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5529 5530 rt2800_bbp_write(rt2x00dev, 104, 0x92); 5531 5532 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 5533 5534 if (rt2x00_rt(rt2x00dev, RT5390)) 5535 rt2800_bbp_write(rt2x00dev, 106, 0x03); 5536 else if (rt2x00_rt(rt2x00dev, RT5392)) 5537 rt2800_bbp_write(rt2x00dev, 106, 0x12); 5538 else 5539 WARN_ON(1); 5540 5541 rt2800_bbp_write(rt2x00dev, 128, 0x12); 5542 5543 if (rt2x00_rt(rt2x00dev, RT5392)) { 5544 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 5545 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 5546 } 5547 5548 rt2800_disable_unused_dac_adc(rt2x00dev); 5549 5550 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 5551 div_mode = rt2x00_get_field16(eeprom, 5552 EEPROM_NIC_CONF1_ANT_DIVERSITY); 5553 ant = (div_mode == 3) ? 1 : 0; 5554 5555 /* check if this is a Bluetooth combo card */ 5556 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 5557 u32 reg; 5558 5559 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 5560 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 5561 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 5562 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 5563 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 5564 if (ant == 0) 5565 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 5566 else if (ant == 1) 5567 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 5568 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 5569 } 5570 5571 /* This chip has hardware antenna diversity*/ 5572 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) { 5573 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 5574 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 5575 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 5576 } 5577 5578 rt2800_bbp_read(rt2x00dev, 152, &value); 5579 if (ant == 0) 5580 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 5581 else 5582 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 5583 rt2800_bbp_write(rt2x00dev, 152, value); 5584 5585 rt2800_init_freq_calibration(rt2x00dev); 5586} 5587 5588static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 5589{ 5590 int ant, div_mode; 5591 u16 eeprom; 5592 u8 value; 5593 5594 rt2800_init_bbp_early(rt2x00dev); 5595 5596 rt2800_bbp_read(rt2x00dev, 105, &value); 5597 rt2x00_set_field8(&value, BBP105_MLD, 5598 rt2x00dev->default_ant.rx_chain_num == 2); 5599 rt2800_bbp_write(rt2x00dev, 105, value); 5600 5601 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5602 5603 rt2800_bbp_write(rt2x00dev, 20, 0x06); 5604 rt2800_bbp_write(rt2x00dev, 31, 0x08); 5605 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 5606 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 5607 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 5608 rt2800_bbp_write(rt2x00dev, 70, 0x05); 5609 rt2800_bbp_write(rt2x00dev, 73, 0x13); 5610 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 5611 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 5612 rt2800_bbp_write(rt2x00dev, 76, 0x28); 5613 rt2800_bbp_write(rt2x00dev, 77, 0x59); 5614 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 5615 rt2800_bbp_write(rt2x00dev, 86, 0x38); 5616 rt2800_bbp_write(rt2x00dev, 88, 0x90); 5617 rt2800_bbp_write(rt2x00dev, 91, 0x04); 5618 rt2800_bbp_write(rt2x00dev, 92, 0x02); 5619 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 5620 rt2800_bbp_write(rt2x00dev, 98, 0x12); 5621 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 5622 rt2800_bbp_write(rt2x00dev, 104, 0x92); 5623 /* FIXME BBP105 owerwrite */ 5624 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 5625 rt2800_bbp_write(rt2x00dev, 106, 0x35); 5626 rt2800_bbp_write(rt2x00dev, 128, 0x12); 5627 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 5628 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 5629 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 5630 5631 /* Initialize GLRT (Generalized Likehood Radio Test) */ 5632 rt2800_init_bbp_5592_glrt(rt2x00dev); 5633 5634 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5635 5636 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 5637 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 5638 ant = (div_mode == 3) ? 1 : 0; 5639 rt2800_bbp_read(rt2x00dev, 152, &value); 5640 if (ant == 0) { 5641 /* Main antenna */ 5642 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 5643 } else { 5644 /* Auxiliary antenna */ 5645 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 5646 } 5647 rt2800_bbp_write(rt2x00dev, 152, value); 5648 5649 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 5650 rt2800_bbp_read(rt2x00dev, 254, &value); 5651 rt2x00_set_field8(&value, BBP254_BIT7, 1); 5652 rt2800_bbp_write(rt2x00dev, 254, value); 5653 } 5654 5655 rt2800_init_freq_calibration(rt2x00dev); 5656 5657 rt2800_bbp_write(rt2x00dev, 84, 0x19); 5658 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 5659 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 5660} 5661 5662static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 5663{ 5664 unsigned int i; 5665 u16 eeprom; 5666 u8 reg_id; 5667 u8 value; 5668 5669 if (rt2800_is_305x_soc(rt2x00dev)) 5670 rt2800_init_bbp_305x_soc(rt2x00dev); 5671 5672 switch (rt2x00dev->chip.rt) { 5673 case RT2860: 5674 case RT2872: 5675 case RT2883: 5676 rt2800_init_bbp_28xx(rt2x00dev); 5677 break; 5678 case RT3070: 5679 case RT3071: 5680 case RT3090: 5681 rt2800_init_bbp_30xx(rt2x00dev); 5682 break; 5683 case RT3290: 5684 rt2800_init_bbp_3290(rt2x00dev); 5685 break; 5686 case RT3352: 5687 rt2800_init_bbp_3352(rt2x00dev); 5688 break; 5689 case RT3390: 5690 rt2800_init_bbp_3390(rt2x00dev); 5691 break; 5692 case RT3572: 5693 rt2800_init_bbp_3572(rt2x00dev); 5694 break; 5695 case RT3593: 5696 rt2800_init_bbp_3593(rt2x00dev); 5697 return; 5698 case RT5390: 5699 case RT5392: 5700 rt2800_init_bbp_53xx(rt2x00dev); 5701 break; 5702 case RT5592: 5703 rt2800_init_bbp_5592(rt2x00dev); 5704 return; 5705 } 5706 5707 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 5708 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i, 5709 &eeprom); 5710 5711 if (eeprom != 0xffff && eeprom != 0x0000) { 5712 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 5713 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 5714 rt2800_bbp_write(rt2x00dev, reg_id, value); 5715 } 5716 } 5717} 5718 5719static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 5720{ 5721 u32 reg; 5722 5723 rt2800_register_read(rt2x00dev, OPT_14_CSR, ®); 5724 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 5725 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 5726} 5727 5728static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 5729 u8 filter_target) 5730{ 5731 unsigned int i; 5732 u8 bbp; 5733 u8 rfcsr; 5734 u8 passband; 5735 u8 stopband; 5736 u8 overtuned = 0; 5737 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 5738 5739 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 5740 5741 rt2800_bbp_read(rt2x00dev, 4, &bbp); 5742 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 5743 rt2800_bbp_write(rt2x00dev, 4, bbp); 5744 5745 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr); 5746 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 5747 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 5748 5749 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 5750 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 5751 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 5752 5753 /* 5754 * Set power & frequency of passband test tone 5755 */ 5756 rt2800_bbp_write(rt2x00dev, 24, 0); 5757 5758 for (i = 0; i < 100; i++) { 5759 rt2800_bbp_write(rt2x00dev, 25, 0x90); 5760 msleep(1); 5761 5762 rt2800_bbp_read(rt2x00dev, 55, &passband); 5763 if (passband) 5764 break; 5765 } 5766 5767 /* 5768 * Set power & frequency of stopband test tone 5769 */ 5770 rt2800_bbp_write(rt2x00dev, 24, 0x06); 5771 5772 for (i = 0; i < 100; i++) { 5773 rt2800_bbp_write(rt2x00dev, 25, 0x90); 5774 msleep(1); 5775 5776 rt2800_bbp_read(rt2x00dev, 55, &stopband); 5777 5778 if ((passband - stopband) <= filter_target) { 5779 rfcsr24++; 5780 overtuned += ((passband - stopband) == filter_target); 5781 } else 5782 break; 5783 5784 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 5785 } 5786 5787 rfcsr24 -= !!overtuned; 5788 5789 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 5790 return rfcsr24; 5791} 5792 5793static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 5794 const unsigned int rf_reg) 5795{ 5796 u8 rfcsr; 5797 5798 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr); 5799 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 5800 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 5801 msleep(1); 5802 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 5803 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 5804} 5805 5806static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 5807{ 5808 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5809 u8 filter_tgt_bw20; 5810 u8 filter_tgt_bw40; 5811 u8 rfcsr, bbp; 5812 5813 /* 5814 * TODO: sync filter_tgt values with vendor driver 5815 */ 5816 if (rt2x00_rt(rt2x00dev, RT3070)) { 5817 filter_tgt_bw20 = 0x16; 5818 filter_tgt_bw40 = 0x19; 5819 } else { 5820 filter_tgt_bw20 = 0x13; 5821 filter_tgt_bw40 = 0x15; 5822 } 5823 5824 drv_data->calibration_bw20 = 5825 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 5826 drv_data->calibration_bw40 = 5827 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 5828 5829 /* 5830 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 5831 */ 5832 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25); 5833 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26); 5834 5835 /* 5836 * Set back to initial state 5837 */ 5838 rt2800_bbp_write(rt2x00dev, 24, 0); 5839 5840 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 5841 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 5842 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 5843 5844 /* 5845 * Set BBP back to BW20 5846 */ 5847 rt2800_bbp_read(rt2x00dev, 4, &bbp); 5848 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 5849 rt2800_bbp_write(rt2x00dev, 4, bbp); 5850} 5851 5852static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 5853{ 5854 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5855 u8 min_gain, rfcsr, bbp; 5856 u16 eeprom; 5857 5858 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 5859 5860 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 5861 if (rt2x00_rt(rt2x00dev, RT3070) || 5862 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5863 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5864 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5865 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 5866 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 5867 } 5868 5869 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 5870 if (drv_data->txmixer_gain_24g >= min_gain) { 5871 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 5872 drv_data->txmixer_gain_24g); 5873 } 5874 5875 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 5876 5877 if (rt2x00_rt(rt2x00dev, RT3090)) { 5878 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 5879 rt2800_bbp_read(rt2x00dev, 138, &bbp); 5880 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 5881 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 5882 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 5883 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 5884 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 5885 rt2800_bbp_write(rt2x00dev, 138, bbp); 5886 } 5887 5888 if (rt2x00_rt(rt2x00dev, RT3070)) { 5889 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr); 5890 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 5891 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 5892 else 5893 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 5894 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 5895 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 5896 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 5897 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 5898 } else if (rt2x00_rt(rt2x00dev, RT3071) || 5899 rt2x00_rt(rt2x00dev, RT3090) || 5900 rt2x00_rt(rt2x00dev, RT3390)) { 5901 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 5902 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 5903 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 5904 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 5905 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 5906 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 5907 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 5908 5909 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr); 5910 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 5911 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 5912 5913 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr); 5914 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 5915 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 5916 5917 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr); 5918 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 5919 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 5920 } 5921} 5922 5923static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 5924{ 5925 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5926 u8 rfcsr; 5927 u8 tx_gain; 5928 5929 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr); 5930 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 5931 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 5932 5933 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr); 5934 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 5935 RFCSR17_TXMIXER_GAIN); 5936 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 5937 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 5938 5939 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr); 5940 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 5941 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 5942 5943 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr); 5944 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 5945 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 5946 5947 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 5948 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 5949 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 5950 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 5951 5952 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 5953 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 5954 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 5955 5956 /* TODO: enable stream mode */ 5957} 5958 5959static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 5960{ 5961 u8 reg; 5962 u16 eeprom; 5963 5964 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 5965 rt2800_bbp_read(rt2x00dev, 138, ®); 5966 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 5967 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 5968 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 5969 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 5970 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 5971 rt2800_bbp_write(rt2x00dev, 138, reg); 5972 5973 rt2800_rfcsr_read(rt2x00dev, 38, ®); 5974 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 5975 rt2800_rfcsr_write(rt2x00dev, 38, reg); 5976 5977 rt2800_rfcsr_read(rt2x00dev, 39, ®); 5978 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 5979 rt2800_rfcsr_write(rt2x00dev, 39, reg); 5980 5981 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 5982 5983 rt2800_rfcsr_read(rt2x00dev, 30, ®); 5984 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 5985 rt2800_rfcsr_write(rt2x00dev, 30, reg); 5986} 5987 5988static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 5989{ 5990 rt2800_rf_init_calibration(rt2x00dev, 30); 5991 5992 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 5993 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 5994 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 5995 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 5996 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 5997 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 5998 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 5999 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 6000 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 6001 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 6002 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 6003 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 6004 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 6005 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 6006 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 6007 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 6008 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 6009 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 6010 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 6011 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 6012 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 6013 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 6014 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 6015 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 6016 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 6017 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 6018 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 6019 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 6020 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 6021 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 6022 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 6023 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 6024} 6025 6026static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 6027{ 6028 u8 rfcsr; 6029 u16 eeprom; 6030 u32 reg; 6031 6032 /* XXX vendor driver do this only for 3070 */ 6033 rt2800_rf_init_calibration(rt2x00dev, 30); 6034 6035 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 6036 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 6037 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 6038 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 6039 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 6040 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 6041 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 6042 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 6043 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 6044 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 6045 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 6046 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 6047 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 6048 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 6049 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 6050 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 6051 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 6052 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 6053 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 6054 6055 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 6056 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6057 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6058 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6059 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6060 } else if (rt2x00_rt(rt2x00dev, RT3071) || 6061 rt2x00_rt(rt2x00dev, RT3090)) { 6062 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 6063 6064 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 6065 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 6066 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 6067 6068 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6069 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6070 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 6071 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 6072 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, 6073 &eeprom); 6074 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 6075 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6076 else 6077 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 6078 } 6079 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6080 6081 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); 6082 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 6083 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 6084 } 6085 6086 rt2800_rx_filter_calibration(rt2x00dev); 6087 6088 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 6089 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 6090 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 6091 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6092 6093 rt2800_led_open_drain_enable(rt2x00dev); 6094 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6095} 6096 6097static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 6098{ 6099 u8 rfcsr; 6100 6101 rt2800_rf_init_calibration(rt2x00dev, 2); 6102 6103 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 6104 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 6105 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 6106 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 6107 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 6108 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 6109 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 6110 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 6111 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 6112 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 6113 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 6114 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 6115 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6116 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 6117 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 6118 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 6119 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 6120 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6121 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6122 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 6123 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 6124 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 6125 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 6126 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 6127 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 6128 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 6129 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 6130 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 6131 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 6132 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 6133 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 6134 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 6135 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 6136 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 6137 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 6138 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 6139 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 6140 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 6141 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 6142 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 6143 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 6144 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 6145 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 6146 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 6147 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 6148 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 6149 6150 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr); 6151 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 6152 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 6153 6154 rt2800_led_open_drain_enable(rt2x00dev); 6155 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6156} 6157 6158static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 6159{ 6160 rt2800_rf_init_calibration(rt2x00dev, 30); 6161 6162 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 6163 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 6164 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 6165 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 6166 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 6167 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 6168 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 6169 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 6170 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 6171 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 6172 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 6173 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 6174 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 6175 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 6176 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 6177 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 6178 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 6179 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 6180 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 6181 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 6182 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 6183 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 6184 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 6185 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 6186 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 6187 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 6188 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6189 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 6190 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 6191 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6192 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6193 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 6194 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 6195 rt2800_rfcsr_write(rt2x00dev, 34, 0x01); 6196 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 6197 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 6198 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 6199 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 6200 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 6201 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 6202 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b); 6203 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); 6204 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 6205 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 6206 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 6207 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 6208 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 6209 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 6210 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 6211 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d); 6212 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f); 6213 rt2800_rfcsr_write(rt2x00dev, 52, 0x00); 6214 rt2800_rfcsr_write(rt2x00dev, 53, 0x52); 6215 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b); 6216 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f); 6217 rt2800_rfcsr_write(rt2x00dev, 56, 0x00); 6218 rt2800_rfcsr_write(rt2x00dev, 57, 0x52); 6219 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b); 6220 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 6221 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 6222 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 6223 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 6224 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 6225 6226 rt2800_rx_filter_calibration(rt2x00dev); 6227 rt2800_led_open_drain_enable(rt2x00dev); 6228 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6229} 6230 6231static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 6232{ 6233 u32 reg; 6234 6235 rt2800_rf_init_calibration(rt2x00dev, 30); 6236 6237 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 6238 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 6239 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 6240 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 6241 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 6242 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 6243 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 6244 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 6245 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 6246 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 6247 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 6248 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 6249 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 6250 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 6251 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 6252 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 6253 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 6254 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 6255 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 6256 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 6257 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 6258 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 6259 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 6260 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 6261 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 6262 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 6263 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 6264 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 6265 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 6266 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 6267 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 6268 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 6269 6270 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); 6271 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 6272 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 6273 6274 rt2800_rx_filter_calibration(rt2x00dev); 6275 6276 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 6277 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6278 6279 rt2800_led_open_drain_enable(rt2x00dev); 6280 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6281} 6282 6283static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 6284{ 6285 u8 rfcsr; 6286 u32 reg; 6287 6288 rt2800_rf_init_calibration(rt2x00dev, 30); 6289 6290 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 6291 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 6292 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 6293 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 6294 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 6295 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 6296 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 6297 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 6298 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 6299 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 6300 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 6301 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 6302 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 6303 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 6304 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 6305 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 6306 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 6307 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 6308 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 6309 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 6310 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 6311 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 6312 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 6313 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 6314 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 6315 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 6316 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 6317 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 6318 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 6319 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 6320 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 6321 6322 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 6323 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 6324 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 6325 6326 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6327 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6328 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6329 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6330 msleep(1); 6331 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6332 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 6333 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6334 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6335 6336 rt2800_rx_filter_calibration(rt2x00dev); 6337 rt2800_led_open_drain_enable(rt2x00dev); 6338 rt2800_normal_mode_setup_3xxx(rt2x00dev); 6339} 6340 6341static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 6342{ 6343 u8 bbp; 6344 bool txbf_enabled = false; /* FIXME */ 6345 6346 rt2800_bbp_read(rt2x00dev, 105, &bbp); 6347 if (rt2x00dev->default_ant.rx_chain_num == 1) 6348 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 6349 else 6350 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 6351 rt2800_bbp_write(rt2x00dev, 105, bbp); 6352 6353 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6354 6355 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6356 rt2800_bbp_write(rt2x00dev, 82, 0x82); 6357 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6358 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6359 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6360 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6361 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6362 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6363 6364 if (txbf_enabled) 6365 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6366 else 6367 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 6368 6369 /* SNR mapping */ 6370 rt2800_bbp_write(rt2x00dev, 142, 6); 6371 rt2800_bbp_write(rt2x00dev, 143, 160); 6372 rt2800_bbp_write(rt2x00dev, 142, 7); 6373 rt2800_bbp_write(rt2x00dev, 143, 161); 6374 rt2800_bbp_write(rt2x00dev, 142, 8); 6375 rt2800_bbp_write(rt2x00dev, 143, 162); 6376 6377 /* ADC/DAC control */ 6378 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6379 6380 /* RX AGC energy lower bound in log2 */ 6381 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6382 6383 /* FIXME: BBP 105 owerwrite? */ 6384 rt2800_bbp_write(rt2x00dev, 105, 0x04); 6385 6386} 6387 6388static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 6389{ 6390 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6391 u32 reg; 6392 u8 rfcsr; 6393 6394 /* Disable GPIO #4 and #7 function for LAN PE control */ 6395 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); 6396 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 6397 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 6398 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 6399 6400 /* Initialize default register values */ 6401 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 6402 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 6403 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 6404 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 6405 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 6406 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 6407 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 6408 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 6409 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 6410 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 6411 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 6412 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6413 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6414 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6415 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 6416 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 6417 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 6418 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 6419 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 6420 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 6421 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 6422 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 6423 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 6424 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 6425 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 6426 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 6427 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 6428 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 6429 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 6430 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 6431 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 6432 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 6433 6434 /* Initiate calibration */ 6435 /* TODO: use rt2800_rf_init_calibration ? */ 6436 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr); 6437 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 6438 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 6439 6440 rt2800_adjust_freq_offset(rt2x00dev); 6441 6442 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr); 6443 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 6444 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 6445 6446 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6447 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 6448 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 6449 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6450 usleep_range(1000, 1500); 6451 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); 6452 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 6453 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 6454 6455 /* Set initial values for RX filter calibration */ 6456 drv_data->calibration_bw20 = 0x1f; 6457 drv_data->calibration_bw40 = 0x2f; 6458 6459 /* Save BBP 25 & 26 values for later use in channel switching */ 6460 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25); 6461 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26); 6462 6463 rt2800_led_open_drain_enable(rt2x00dev); 6464 rt2800_normal_mode_setup_3593(rt2x00dev); 6465 6466 rt3593_post_bbp_init(rt2x00dev); 6467 6468 /* TODO: enable stream mode support */ 6469} 6470 6471static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 6472{ 6473 rt2800_rf_init_calibration(rt2x00dev, 2); 6474 6475 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 6476 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 6477 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 6478 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 6479 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6480 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 6481 else 6482 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 6483 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 6484 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 6485 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 6486 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 6487 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 6488 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 6489 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 6490 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 6491 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 6492 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 6493 6494 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 6495 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 6496 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6497 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 6498 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 6499 if (rt2x00_is_usb(rt2x00dev) && 6500 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6501 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 6502 else 6503 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 6504 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 6505 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 6506 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 6507 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 6508 6509 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6510 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6511 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 6512 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 6513 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 6514 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 6515 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 6516 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 6517 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 6518 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 6519 6520 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 6521 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 6522 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 6523 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 6524 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 6525 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 6526 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6527 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 6528 else 6529 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 6530 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 6531 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 6532 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 6533 6534 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 6535 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6536 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 6537 else 6538 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 6539 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 6540 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 6541 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 6542 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 6543 else 6544 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 6545 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 6546 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 6547 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 6548 6549 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 6550 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 6551 if (rt2x00_is_usb(rt2x00dev)) 6552 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 6553 else 6554 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 6555 } else { 6556 if (rt2x00_is_usb(rt2x00dev)) 6557 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 6558 else 6559 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 6560 } 6561 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 6562 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 6563 6564 rt2800_normal_mode_setup_5xxx(rt2x00dev); 6565 6566 rt2800_led_open_drain_enable(rt2x00dev); 6567} 6568 6569static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 6570{ 6571 rt2800_rf_init_calibration(rt2x00dev, 2); 6572 6573 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 6574 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 6575 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 6576 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 6577 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 6578 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 6579 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 6580 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 6581 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 6582 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 6583 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 6584 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 6585 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 6586 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 6587 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 6588 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 6589 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 6590 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 6591 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 6592 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 6593 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 6594 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 6595 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 6596 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 6597 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 6598 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 6599 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 6600 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 6601 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 6602 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 6603 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 6604 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 6605 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 6606 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 6607 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 6608 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 6609 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 6610 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 6611 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 6612 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 6613 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 6614 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 6615 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 6616 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 6617 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 6618 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 6619 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 6620 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 6621 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 6622 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 6623 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 6624 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 6625 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 6626 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 6627 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 6628 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 6629 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 6630 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 6631 6632 rt2800_normal_mode_setup_5xxx(rt2x00dev); 6633 6634 rt2800_led_open_drain_enable(rt2x00dev); 6635} 6636 6637static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 6638{ 6639 rt2800_rf_init_calibration(rt2x00dev, 30); 6640 6641 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 6642 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 6643 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 6644 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 6645 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 6646 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 6647 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 6648 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 6649 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 6650 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 6651 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 6652 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 6653 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 6654 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 6655 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 6656 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 6657 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 6658 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 6659 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 6660 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 6661 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 6662 6663 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 6664 msleep(1); 6665 6666 rt2800_adjust_freq_offset(rt2x00dev); 6667 6668 /* Enable DC filter */ 6669 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 6670 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6671 6672 rt2800_normal_mode_setup_5xxx(rt2x00dev); 6673 6674 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 6675 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 6676 6677 rt2800_led_open_drain_enable(rt2x00dev); 6678} 6679 6680static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 6681{ 6682 if (rt2800_is_305x_soc(rt2x00dev)) { 6683 rt2800_init_rfcsr_305x_soc(rt2x00dev); 6684 return; 6685 } 6686 6687 switch (rt2x00dev->chip.rt) { 6688 case RT3070: 6689 case RT3071: 6690 case RT3090: 6691 rt2800_init_rfcsr_30xx(rt2x00dev); 6692 break; 6693 case RT3290: 6694 rt2800_init_rfcsr_3290(rt2x00dev); 6695 break; 6696 case RT3352: 6697 rt2800_init_rfcsr_3352(rt2x00dev); 6698 break; 6699 case RT3390: 6700 rt2800_init_rfcsr_3390(rt2x00dev); 6701 break; 6702 case RT3572: 6703 rt2800_init_rfcsr_3572(rt2x00dev); 6704 break; 6705 case RT3593: 6706 rt2800_init_rfcsr_3593(rt2x00dev); 6707 break; 6708 case RT5390: 6709 rt2800_init_rfcsr_5390(rt2x00dev); 6710 break; 6711 case RT5392: 6712 rt2800_init_rfcsr_5392(rt2x00dev); 6713 break; 6714 case RT5592: 6715 rt2800_init_rfcsr_5592(rt2x00dev); 6716 break; 6717 } 6718} 6719 6720int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 6721{ 6722 u32 reg; 6723 u16 word; 6724 6725 /* 6726 * Initialize MAC registers. 6727 */ 6728 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 6729 rt2800_init_registers(rt2x00dev))) 6730 return -EIO; 6731 6732 /* 6733 * Wait BBP/RF to wake up. 6734 */ 6735 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev))) 6736 return -EIO; 6737 6738 /* 6739 * Send signal during boot time to initialize firmware. 6740 */ 6741 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 6742 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 6743 if (rt2x00_is_usb(rt2x00dev)) 6744 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 6745 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 6746 msleep(1); 6747 6748 /* 6749 * Make sure BBP is up and running. 6750 */ 6751 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 6752 return -EIO; 6753 6754 /* 6755 * Initialize BBP/RF registers. 6756 */ 6757 rt2800_init_bbp(rt2x00dev); 6758 rt2800_init_rfcsr(rt2x00dev); 6759 6760 if (rt2x00_is_usb(rt2x00dev) && 6761 (rt2x00_rt(rt2x00dev, RT3070) || 6762 rt2x00_rt(rt2x00dev, RT3071) || 6763 rt2x00_rt(rt2x00dev, RT3572))) { 6764 udelay(200); 6765 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 6766 udelay(10); 6767 } 6768 6769 /* 6770 * Enable RX. 6771 */ 6772 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); 6773 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 6774 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 6775 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 6776 6777 udelay(50); 6778 6779 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); 6780 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 6781 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 6782 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2); 6783 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 6784 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 6785 6786 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); 6787 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 6788 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 6789 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 6790 6791 /* 6792 * Initialize LED control 6793 */ 6794 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word); 6795 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 6796 word & 0xff, (word >> 8) & 0xff); 6797 6798 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word); 6799 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 6800 word & 0xff, (word >> 8) & 0xff); 6801 6802 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word); 6803 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 6804 word & 0xff, (word >> 8) & 0xff); 6805 6806 return 0; 6807} 6808EXPORT_SYMBOL_GPL(rt2800_enable_radio); 6809 6810void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 6811{ 6812 u32 reg; 6813 6814 rt2800_disable_wpdma(rt2x00dev); 6815 6816 /* Wait for DMA, ignore error */ 6817 rt2800_wait_wpdma_ready(rt2x00dev); 6818 6819 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); 6820 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 6821 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 6822 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 6823} 6824EXPORT_SYMBOL_GPL(rt2800_disable_radio); 6825 6826int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 6827{ 6828 u32 reg; 6829 u16 efuse_ctrl_reg; 6830 6831 if (rt2x00_rt(rt2x00dev, RT3290)) 6832 efuse_ctrl_reg = EFUSE_CTRL_3290; 6833 else 6834 efuse_ctrl_reg = EFUSE_CTRL; 6835 6836 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, ®); 6837 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 6838} 6839EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 6840 6841static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 6842{ 6843 u32 reg; 6844 u16 efuse_ctrl_reg; 6845 u16 efuse_data0_reg; 6846 u16 efuse_data1_reg; 6847 u16 efuse_data2_reg; 6848 u16 efuse_data3_reg; 6849 6850 if (rt2x00_rt(rt2x00dev, RT3290)) { 6851 efuse_ctrl_reg = EFUSE_CTRL_3290; 6852 efuse_data0_reg = EFUSE_DATA0_3290; 6853 efuse_data1_reg = EFUSE_DATA1_3290; 6854 efuse_data2_reg = EFUSE_DATA2_3290; 6855 efuse_data3_reg = EFUSE_DATA3_3290; 6856 } else { 6857 efuse_ctrl_reg = EFUSE_CTRL; 6858 efuse_data0_reg = EFUSE_DATA0; 6859 efuse_data1_reg = EFUSE_DATA1; 6860 efuse_data2_reg = EFUSE_DATA2; 6861 efuse_data3_reg = EFUSE_DATA3; 6862 } 6863 mutex_lock(&rt2x00dev->csr_mutex); 6864 6865 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, ®); 6866 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 6867 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 6868 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 6869 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 6870 6871 /* Wait until the EEPROM has been loaded */ 6872 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 6873 /* Apparently the data is read from end to start */ 6874 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, ®); 6875 /* The returned value is in CPU order, but eeprom is le */ 6876 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 6877 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, ®); 6878 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 6879 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, ®); 6880 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 6881 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, ®); 6882 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 6883 6884 mutex_unlock(&rt2x00dev->csr_mutex); 6885} 6886 6887int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 6888{ 6889 unsigned int i; 6890 6891 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 6892 rt2800_efuse_read(rt2x00dev, i); 6893 6894 return 0; 6895} 6896EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 6897 6898static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 6899{ 6900 u16 word; 6901 6902 if (rt2x00_rt(rt2x00dev, RT3593)) 6903 return 0; 6904 6905 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word); 6906 if ((word & 0x00ff) != 0x00ff) 6907 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 6908 6909 return 0; 6910} 6911 6912static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 6913{ 6914 u16 word; 6915 6916 if (rt2x00_rt(rt2x00dev, RT3593)) 6917 return 0; 6918 6919 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word); 6920 if ((word & 0x00ff) != 0x00ff) 6921 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 6922 6923 return 0; 6924} 6925 6926static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 6927{ 6928 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 6929 u16 word; 6930 u8 *mac; 6931 u8 default_lna_gain; 6932 int retval; 6933 6934 /* 6935 * Read the EEPROM. 6936 */ 6937 retval = rt2800_read_eeprom(rt2x00dev); 6938 if (retval) 6939 return retval; 6940 6941 /* 6942 * Start validation of the data that has been read. 6943 */ 6944 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 6945 if (!is_valid_ether_addr(mac)) { 6946 eth_random_addr(mac); 6947 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac); 6948 } 6949 6950 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word); 6951 if (word == 0xffff) { 6952 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 6953 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 6954 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 6955 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 6956 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 6957 } else if (rt2x00_rt(rt2x00dev, RT2860) || 6958 rt2x00_rt(rt2x00dev, RT2872)) { 6959 /* 6960 * There is a max of 2 RX streams for RT28x0 series 6961 */ 6962 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 6963 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 6964 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 6965 } 6966 6967 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word); 6968 if (word == 0xffff) { 6969 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 6970 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 6971 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 6972 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 6973 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 6974 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 6975 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 6976 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 6977 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 6978 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 6979 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 6980 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 6981 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 6982 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 6983 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 6984 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 6985 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 6986 } 6987 6988 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); 6989 if ((word & 0x00ff) == 0x00ff) { 6990 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 6991 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 6992 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 6993 } 6994 if ((word & 0xff00) == 0xff00) { 6995 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 6996 LED_MODE_TXRX_ACTIVITY); 6997 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 6998 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 6999 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 7000 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 7001 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 7002 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 7003 } 7004 7005 /* 7006 * During the LNA validation we are going to use 7007 * lna0 as correct value. Note that EEPROM_LNA 7008 * is never validated. 7009 */ 7010 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word); 7011 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 7012 7013 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word); 7014 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 7015 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 7016 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 7017 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 7018 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 7019 7020 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 7021 7022 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word); 7023 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 7024 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 7025 if (!rt2x00_rt(rt2x00dev, RT3593)) { 7026 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 7027 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 7028 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 7029 default_lna_gain); 7030 } 7031 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 7032 7033 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 7034 7035 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word); 7036 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 7037 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 7038 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 7039 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 7040 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 7041 7042 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word); 7043 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 7044 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 7045 if (!rt2x00_rt(rt2x00dev, RT3593)) { 7046 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 7047 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 7048 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 7049 default_lna_gain); 7050 } 7051 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 7052 7053 if (rt2x00_rt(rt2x00dev, RT3593)) { 7054 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word); 7055 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 7056 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 7057 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 7058 default_lna_gain); 7059 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 7060 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 7061 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 7062 default_lna_gain); 7063 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 7064 } 7065 7066 return 0; 7067} 7068 7069static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 7070{ 7071 u16 value; 7072 u16 eeprom; 7073 u16 rf; 7074 7075 /* 7076 * Read EEPROM word for configuration. 7077 */ 7078 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 7079 7080 /* 7081 * Identify RF chipset by EEPROM value 7082 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 7083 * RT53xx: defined in "EEPROM_CHIP_ID" field 7084 */ 7085 if (rt2x00_rt(rt2x00dev, RT3290) || 7086 rt2x00_rt(rt2x00dev, RT5390) || 7087 rt2x00_rt(rt2x00dev, RT5392)) 7088 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf); 7089 else 7090 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 7091 7092 switch (rf) { 7093 case RF2820: 7094 case RF2850: 7095 case RF2720: 7096 case RF2750: 7097 case RF3020: 7098 case RF2020: 7099 case RF3021: 7100 case RF3022: 7101 case RF3052: 7102 case RF3053: 7103 case RF3070: 7104 case RF3290: 7105 case RF3320: 7106 case RF3322: 7107 case RF5360: 7108 case RF5362: 7109 case RF5370: 7110 case RF5372: 7111 case RF5390: 7112 case RF5392: 7113 case RF5592: 7114 break; 7115 default: 7116 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 7117 rf); 7118 return -ENODEV; 7119 } 7120 7121 rt2x00_set_rf(rt2x00dev, rf); 7122 7123 /* 7124 * Identify default antenna configuration. 7125 */ 7126 rt2x00dev->default_ant.tx_chain_num = 7127 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 7128 rt2x00dev->default_ant.rx_chain_num = 7129 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 7130 7131 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); 7132 7133 if (rt2x00_rt(rt2x00dev, RT3070) || 7134 rt2x00_rt(rt2x00dev, RT3090) || 7135 rt2x00_rt(rt2x00dev, RT3352) || 7136 rt2x00_rt(rt2x00dev, RT3390)) { 7137 value = rt2x00_get_field16(eeprom, 7138 EEPROM_NIC_CONF1_ANT_DIVERSITY); 7139 switch (value) { 7140 case 0: 7141 case 1: 7142 case 2: 7143 rt2x00dev->default_ant.tx = ANTENNA_A; 7144 rt2x00dev->default_ant.rx = ANTENNA_A; 7145 break; 7146 case 3: 7147 rt2x00dev->default_ant.tx = ANTENNA_A; 7148 rt2x00dev->default_ant.rx = ANTENNA_B; 7149 break; 7150 } 7151 } else { 7152 rt2x00dev->default_ant.tx = ANTENNA_A; 7153 rt2x00dev->default_ant.rx = ANTENNA_A; 7154 } 7155 7156 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) { 7157 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 7158 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 7159 } 7160 7161 /* 7162 * Determine external LNA informations. 7163 */ 7164 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 7165 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 7166 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 7167 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 7168 7169 /* 7170 * Detect if this device has an hardware controlled radio. 7171 */ 7172 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 7173 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 7174 7175 /* 7176 * Detect if this device has Bluetooth co-existence. 7177 */ 7178 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 7179 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 7180 7181 /* 7182 * Read frequency offset and RF programming sequence. 7183 */ 7184 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); 7185 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 7186 7187 /* 7188 * Store led settings, for correct led behaviour. 7189 */ 7190#ifdef CONFIG_RT2X00_LIB_LEDS 7191 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 7192 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 7193 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 7194 7195 rt2x00dev->led_mcu_reg = eeprom; 7196#endif /* CONFIG_RT2X00_LIB_LEDS */ 7197 7198 /* 7199 * Check if support EIRP tx power limit feature. 7200 */ 7201 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom); 7202 7203 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 7204 EIRP_MAX_TX_POWER_LIMIT) 7205 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 7206 7207 return 0; 7208} 7209 7210/* 7211 * RF value list for rt28xx 7212 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 7213 */ 7214static const struct rf_channel rf_vals[] = { 7215 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 7216 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 7217 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 7218 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 7219 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 7220 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 7221 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 7222 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 7223 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 7224 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 7225 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 7226 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 7227 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 7228 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 7229 7230 /* 802.11 UNI / HyperLan 2 */ 7231 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 7232 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 7233 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 7234 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 7235 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 7236 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 7237 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 7238 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 7239 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 7240 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 7241 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 7242 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 7243 7244 /* 802.11 HyperLan 2 */ 7245 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 7246 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 7247 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 7248 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 7249 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 7250 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 7251 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 7252 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 7253 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 7254 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 7255 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 7256 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 7257 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 7258 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 7259 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 7260 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 7261 7262 /* 802.11 UNII */ 7263 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 7264 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 7265 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 7266 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 7267 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 7268 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 7269 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 7270 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 7271 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 7272 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 7273 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 7274 7275 /* 802.11 Japan */ 7276 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 7277 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 7278 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 7279 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 7280 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 7281 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 7282 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 7283}; 7284 7285/* 7286 * RF value list for rt3xxx 7287 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 7288 */ 7289static const struct rf_channel rf_vals_3x[] = { 7290 {1, 241, 2, 2 }, 7291 {2, 241, 2, 7 }, 7292 {3, 242, 2, 2 }, 7293 {4, 242, 2, 7 }, 7294 {5, 243, 2, 2 }, 7295 {6, 243, 2, 7 }, 7296 {7, 244, 2, 2 }, 7297 {8, 244, 2, 7 }, 7298 {9, 245, 2, 2 }, 7299 {10, 245, 2, 7 }, 7300 {11, 246, 2, 2 }, 7301 {12, 246, 2, 7 }, 7302 {13, 247, 2, 2 }, 7303 {14, 248, 2, 4 }, 7304 7305 /* 802.11 UNI / HyperLan 2 */ 7306 {36, 0x56, 0, 4}, 7307 {38, 0x56, 0, 6}, 7308 {40, 0x56, 0, 8}, 7309 {44, 0x57, 0, 0}, 7310 {46, 0x57, 0, 2}, 7311 {48, 0x57, 0, 4}, 7312 {52, 0x57, 0, 8}, 7313 {54, 0x57, 0, 10}, 7314 {56, 0x58, 0, 0}, 7315 {60, 0x58, 0, 4}, 7316 {62, 0x58, 0, 6}, 7317 {64, 0x58, 0, 8}, 7318 7319 /* 802.11 HyperLan 2 */ 7320 {100, 0x5b, 0, 8}, 7321 {102, 0x5b, 0, 10}, 7322 {104, 0x5c, 0, 0}, 7323 {108, 0x5c, 0, 4}, 7324 {110, 0x5c, 0, 6}, 7325 {112, 0x5c, 0, 8}, 7326 {116, 0x5d, 0, 0}, 7327 {118, 0x5d, 0, 2}, 7328 {120, 0x5d, 0, 4}, 7329 {124, 0x5d, 0, 8}, 7330 {126, 0x5d, 0, 10}, 7331 {128, 0x5e, 0, 0}, 7332 {132, 0x5e, 0, 4}, 7333 {134, 0x5e, 0, 6}, 7334 {136, 0x5e, 0, 8}, 7335 {140, 0x5f, 0, 0}, 7336 7337 /* 802.11 UNII */ 7338 {149, 0x5f, 0, 9}, 7339 {151, 0x5f, 0, 11}, 7340 {153, 0x60, 0, 1}, 7341 {157, 0x60, 0, 5}, 7342 {159, 0x60, 0, 7}, 7343 {161, 0x60, 0, 9}, 7344 {165, 0x61, 0, 1}, 7345 {167, 0x61, 0, 3}, 7346 {169, 0x61, 0, 5}, 7347 {171, 0x61, 0, 7}, 7348 {173, 0x61, 0, 9}, 7349}; 7350 7351static const struct rf_channel rf_vals_5592_xtal20[] = { 7352 /* Channel, N, K, mod, R */ 7353 {1, 482, 4, 10, 3}, 7354 {2, 483, 4, 10, 3}, 7355 {3, 484, 4, 10, 3}, 7356 {4, 485, 4, 10, 3}, 7357 {5, 486, 4, 10, 3}, 7358 {6, 487, 4, 10, 3}, 7359 {7, 488, 4, 10, 3}, 7360 {8, 489, 4, 10, 3}, 7361 {9, 490, 4, 10, 3}, 7362 {10, 491, 4, 10, 3}, 7363 {11, 492, 4, 10, 3}, 7364 {12, 493, 4, 10, 3}, 7365 {13, 494, 4, 10, 3}, 7366 {14, 496, 8, 10, 3}, 7367 {36, 172, 8, 12, 1}, 7368 {38, 173, 0, 12, 1}, 7369 {40, 173, 4, 12, 1}, 7370 {42, 173, 8, 12, 1}, 7371 {44, 174, 0, 12, 1}, 7372 {46, 174, 4, 12, 1}, 7373 {48, 174, 8, 12, 1}, 7374 {50, 175, 0, 12, 1}, 7375 {52, 175, 4, 12, 1}, 7376 {54, 175, 8, 12, 1}, 7377 {56, 176, 0, 12, 1}, 7378 {58, 176, 4, 12, 1}, 7379 {60, 176, 8, 12, 1}, 7380 {62, 177, 0, 12, 1}, 7381 {64, 177, 4, 12, 1}, 7382 {100, 183, 4, 12, 1}, 7383 {102, 183, 8, 12, 1}, 7384 {104, 184, 0, 12, 1}, 7385 {106, 184, 4, 12, 1}, 7386 {108, 184, 8, 12, 1}, 7387 {110, 185, 0, 12, 1}, 7388 {112, 185, 4, 12, 1}, 7389 {114, 185, 8, 12, 1}, 7390 {116, 186, 0, 12, 1}, 7391 {118, 186, 4, 12, 1}, 7392 {120, 186, 8, 12, 1}, 7393 {122, 187, 0, 12, 1}, 7394 {124, 187, 4, 12, 1}, 7395 {126, 187, 8, 12, 1}, 7396 {128, 188, 0, 12, 1}, 7397 {130, 188, 4, 12, 1}, 7398 {132, 188, 8, 12, 1}, 7399 {134, 189, 0, 12, 1}, 7400 {136, 189, 4, 12, 1}, 7401 {138, 189, 8, 12, 1}, 7402 {140, 190, 0, 12, 1}, 7403 {149, 191, 6, 12, 1}, 7404 {151, 191, 10, 12, 1}, 7405 {153, 192, 2, 12, 1}, 7406 {155, 192, 6, 12, 1}, 7407 {157, 192, 10, 12, 1}, 7408 {159, 193, 2, 12, 1}, 7409 {161, 193, 6, 12, 1}, 7410 {165, 194, 2, 12, 1}, 7411 {184, 164, 0, 12, 1}, 7412 {188, 164, 4, 12, 1}, 7413 {192, 165, 8, 12, 1}, 7414 {196, 166, 0, 12, 1}, 7415}; 7416 7417static const struct rf_channel rf_vals_5592_xtal40[] = { 7418 /* Channel, N, K, mod, R */ 7419 {1, 241, 2, 10, 3}, 7420 {2, 241, 7, 10, 3}, 7421 {3, 242, 2, 10, 3}, 7422 {4, 242, 7, 10, 3}, 7423 {5, 243, 2, 10, 3}, 7424 {6, 243, 7, 10, 3}, 7425 {7, 244, 2, 10, 3}, 7426 {8, 244, 7, 10, 3}, 7427 {9, 245, 2, 10, 3}, 7428 {10, 245, 7, 10, 3}, 7429 {11, 246, 2, 10, 3}, 7430 {12, 246, 7, 10, 3}, 7431 {13, 247, 2, 10, 3}, 7432 {14, 248, 4, 10, 3}, 7433 {36, 86, 4, 12, 1}, 7434 {38, 86, 6, 12, 1}, 7435 {40, 86, 8, 12, 1}, 7436 {42, 86, 10, 12, 1}, 7437 {44, 87, 0, 12, 1}, 7438 {46, 87, 2, 12, 1}, 7439 {48, 87, 4, 12, 1}, 7440 {50, 87, 6, 12, 1}, 7441 {52, 87, 8, 12, 1}, 7442 {54, 87, 10, 12, 1}, 7443 {56, 88, 0, 12, 1}, 7444 {58, 88, 2, 12, 1}, 7445 {60, 88, 4, 12, 1}, 7446 {62, 88, 6, 12, 1}, 7447 {64, 88, 8, 12, 1}, 7448 {100, 91, 8, 12, 1}, 7449 {102, 91, 10, 12, 1}, 7450 {104, 92, 0, 12, 1}, 7451 {106, 92, 2, 12, 1}, 7452 {108, 92, 4, 12, 1}, 7453 {110, 92, 6, 12, 1}, 7454 {112, 92, 8, 12, 1}, 7455 {114, 92, 10, 12, 1}, 7456 {116, 93, 0, 12, 1}, 7457 {118, 93, 2, 12, 1}, 7458 {120, 93, 4, 12, 1}, 7459 {122, 93, 6, 12, 1}, 7460 {124, 93, 8, 12, 1}, 7461 {126, 93, 10, 12, 1}, 7462 {128, 94, 0, 12, 1}, 7463 {130, 94, 2, 12, 1}, 7464 {132, 94, 4, 12, 1}, 7465 {134, 94, 6, 12, 1}, 7466 {136, 94, 8, 12, 1}, 7467 {138, 94, 10, 12, 1}, 7468 {140, 95, 0, 12, 1}, 7469 {149, 95, 9, 12, 1}, 7470 {151, 95, 11, 12, 1}, 7471 {153, 96, 1, 12, 1}, 7472 {155, 96, 3, 12, 1}, 7473 {157, 96, 5, 12, 1}, 7474 {159, 96, 7, 12, 1}, 7475 {161, 96, 9, 12, 1}, 7476 {165, 97, 1, 12, 1}, 7477 {184, 82, 0, 12, 1}, 7478 {188, 82, 4, 12, 1}, 7479 {192, 82, 8, 12, 1}, 7480 {196, 83, 0, 12, 1}, 7481}; 7482 7483static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 7484{ 7485 struct hw_mode_spec *spec = &rt2x00dev->spec; 7486 struct channel_info *info; 7487 char *default_power1; 7488 char *default_power2; 7489 char *default_power3; 7490 unsigned int i; 7491 u32 reg; 7492 7493 /* 7494 * Disable powersaving as default. 7495 */ 7496 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 7497 7498 /* 7499 * Initialize all hw fields. 7500 */ 7501 rt2x00dev->hw->flags = 7502 IEEE80211_HW_SIGNAL_DBM | 7503 IEEE80211_HW_SUPPORTS_PS | 7504 IEEE80211_HW_PS_NULLFUNC_STACK | 7505 IEEE80211_HW_AMPDU_AGGREGATION | 7506 IEEE80211_HW_REPORTS_TX_ACK_STATUS | 7507 IEEE80211_HW_SUPPORTS_HT_CCK_RATES; 7508 7509 /* 7510 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 7511 * unless we are capable of sending the buffered frames out after the 7512 * DTIM transmission using rt2x00lib_beacondone. This will send out 7513 * multicast and broadcast traffic immediately instead of buffering it 7514 * infinitly and thus dropping it after some time. 7515 */ 7516 if (!rt2x00_is_usb(rt2x00dev)) 7517 rt2x00dev->hw->flags |= 7518 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; 7519 7520 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 7521 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 7522 rt2800_eeprom_addr(rt2x00dev, 7523 EEPROM_MAC_ADDR_0)); 7524 7525 /* 7526 * As rt2800 has a global fallback table we cannot specify 7527 * more then one tx rate per frame but since the hw will 7528 * try several rates (based on the fallback table) we should 7529 * initialize max_report_rates to the maximum number of rates 7530 * we are going to try. Otherwise mac80211 will truncate our 7531 * reported tx rates and the rc algortihm will end up with 7532 * incorrect data. 7533 */ 7534 rt2x00dev->hw->max_rates = 1; 7535 rt2x00dev->hw->max_report_rates = 7; 7536 rt2x00dev->hw->max_rate_tries = 1; 7537 7538 /* 7539 * Initialize hw_mode information. 7540 */ 7541 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 7542 7543 switch (rt2x00dev->chip.rf) { 7544 case RF2720: 7545 case RF2820: 7546 spec->num_channels = 14; 7547 spec->channels = rf_vals; 7548 break; 7549 7550 case RF2750: 7551 case RF2850: 7552 spec->num_channels = ARRAY_SIZE(rf_vals); 7553 spec->channels = rf_vals; 7554 break; 7555 7556 case RF2020: 7557 case RF3020: 7558 case RF3021: 7559 case RF3022: 7560 case RF3070: 7561 case RF3290: 7562 case RF3320: 7563 case RF3322: 7564 case RF5360: 7565 case RF5362: 7566 case RF5370: 7567 case RF5372: 7568 case RF5390: 7569 case RF5392: 7570 spec->num_channels = 14; 7571 spec->channels = rf_vals_3x; 7572 break; 7573 7574 case RF3052: 7575 case RF3053: 7576 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 7577 spec->channels = rf_vals_3x; 7578 break; 7579 7580 case RF5592: 7581 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, ®); 7582 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 7583 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 7584 spec->channels = rf_vals_5592_xtal40; 7585 } else { 7586 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 7587 spec->channels = rf_vals_5592_xtal20; 7588 } 7589 break; 7590 } 7591 7592 if (WARN_ON_ONCE(!spec->channels)) 7593 return -ENODEV; 7594 7595 spec->supported_bands = SUPPORT_BAND_2GHZ; 7596 if (spec->num_channels > 14) 7597 spec->supported_bands |= SUPPORT_BAND_5GHZ; 7598 7599 /* 7600 * Initialize HT information. 7601 */ 7602 if (!rt2x00_rf(rt2x00dev, RF2020)) 7603 spec->ht.ht_supported = true; 7604 else 7605 spec->ht.ht_supported = false; 7606 7607 spec->ht.cap = 7608 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 7609 IEEE80211_HT_CAP_GRN_FLD | 7610 IEEE80211_HT_CAP_SGI_20 | 7611 IEEE80211_HT_CAP_SGI_40; 7612 7613 if (rt2x00dev->default_ant.tx_chain_num >= 2) 7614 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 7615 7616 spec->ht.cap |= rt2x00dev->default_ant.rx_chain_num << 7617 IEEE80211_HT_CAP_RX_STBC_SHIFT; 7618 7619 spec->ht.ampdu_factor = 3; 7620 spec->ht.ampdu_density = 4; 7621 spec->ht.mcs.tx_params = 7622 IEEE80211_HT_MCS_TX_DEFINED | 7623 IEEE80211_HT_MCS_TX_RX_DIFF | 7624 ((rt2x00dev->default_ant.tx_chain_num - 1) << 7625 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 7626 7627 switch (rt2x00dev->default_ant.rx_chain_num) { 7628 case 3: 7629 spec->ht.mcs.rx_mask[2] = 0xff; 7630 case 2: 7631 spec->ht.mcs.rx_mask[1] = 0xff; 7632 case 1: 7633 spec->ht.mcs.rx_mask[0] = 0xff; 7634 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 7635 break; 7636 } 7637 7638 /* 7639 * Create channel information array 7640 */ 7641 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 7642 if (!info) 7643 return -ENOMEM; 7644 7645 spec->channels_info = info; 7646 7647 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 7648 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 7649 7650 if (rt2x00dev->default_ant.tx_chain_num > 2) 7651 default_power3 = rt2800_eeprom_addr(rt2x00dev, 7652 EEPROM_EXT_TXPOWER_BG3); 7653 else 7654 default_power3 = NULL; 7655 7656 for (i = 0; i < 14; i++) { 7657 info[i].default_power1 = default_power1[i]; 7658 info[i].default_power2 = default_power2[i]; 7659 if (default_power3) 7660 info[i].default_power3 = default_power3[i]; 7661 } 7662 7663 if (spec->num_channels > 14) { 7664 default_power1 = rt2800_eeprom_addr(rt2x00dev, 7665 EEPROM_TXPOWER_A1); 7666 default_power2 = rt2800_eeprom_addr(rt2x00dev, 7667 EEPROM_TXPOWER_A2); 7668 7669 if (rt2x00dev->default_ant.tx_chain_num > 2) 7670 default_power3 = 7671 rt2800_eeprom_addr(rt2x00dev, 7672 EEPROM_EXT_TXPOWER_A3); 7673 else 7674 default_power3 = NULL; 7675 7676 for (i = 14; i < spec->num_channels; i++) { 7677 info[i].default_power1 = default_power1[i - 14]; 7678 info[i].default_power2 = default_power2[i - 14]; 7679 if (default_power3) 7680 info[i].default_power3 = default_power3[i - 14]; 7681 } 7682 } 7683 7684 switch (rt2x00dev->chip.rf) { 7685 case RF2020: 7686 case RF3020: 7687 case RF3021: 7688 case RF3022: 7689 case RF3320: 7690 case RF3052: 7691 case RF3053: 7692 case RF3070: 7693 case RF3290: 7694 case RF5360: 7695 case RF5362: 7696 case RF5370: 7697 case RF5372: 7698 case RF5390: 7699 case RF5392: 7700 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 7701 break; 7702 } 7703 7704 return 0; 7705} 7706 7707static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 7708{ 7709 u32 reg; 7710 u32 rt; 7711 u32 rev; 7712 7713 if (rt2x00_rt(rt2x00dev, RT3290)) 7714 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, ®); 7715 else 7716 rt2800_register_read(rt2x00dev, MAC_CSR0, ®); 7717 7718 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 7719 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 7720 7721 switch (rt) { 7722 case RT2860: 7723 case RT2872: 7724 case RT2883: 7725 case RT3070: 7726 case RT3071: 7727 case RT3090: 7728 case RT3290: 7729 case RT3352: 7730 case RT3390: 7731 case RT3572: 7732 case RT3593: 7733 case RT5390: 7734 case RT5392: 7735 case RT5592: 7736 break; 7737 default: 7738 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 7739 rt, rev); 7740 return -ENODEV; 7741 } 7742 7743 rt2x00_set_rt(rt2x00dev, rt, rev); 7744 7745 return 0; 7746} 7747 7748int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 7749{ 7750 int retval; 7751 u32 reg; 7752 7753 retval = rt2800_probe_rt(rt2x00dev); 7754 if (retval) 7755 return retval; 7756 7757 /* 7758 * Allocate eeprom data. 7759 */ 7760 retval = rt2800_validate_eeprom(rt2x00dev); 7761 if (retval) 7762 return retval; 7763 7764 retval = rt2800_init_eeprom(rt2x00dev); 7765 if (retval) 7766 return retval; 7767 7768 /* 7769 * Enable rfkill polling by setting GPIO direction of the 7770 * rfkill switch GPIO pin correctly. 7771 */ 7772 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); 7773 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 7774 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 7775 7776 /* 7777 * Initialize hw specifications. 7778 */ 7779 retval = rt2800_probe_hw_mode(rt2x00dev); 7780 if (retval) 7781 return retval; 7782 7783 /* 7784 * Set device capabilities. 7785 */ 7786 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 7787 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 7788 if (!rt2x00_is_usb(rt2x00dev)) 7789 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 7790 7791 /* 7792 * Set device requirements. 7793 */ 7794 if (!rt2x00_is_soc(rt2x00dev)) 7795 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 7796 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 7797 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 7798 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 7799 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 7800 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 7801 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 7802 if (rt2x00_is_usb(rt2x00dev)) 7803 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 7804 else { 7805 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 7806 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 7807 } 7808 7809 /* 7810 * Set the rssi offset. 7811 */ 7812 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 7813 7814 return 0; 7815} 7816EXPORT_SYMBOL_GPL(rt2800_probe_hw); 7817 7818/* 7819 * IEEE80211 stack callback functions. 7820 */ 7821void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32, 7822 u16 *iv16) 7823{ 7824 struct rt2x00_dev *rt2x00dev = hw->priv; 7825 struct mac_iveiv_entry iveiv_entry; 7826 u32 offset; 7827 7828 offset = MAC_IVEIV_ENTRY(hw_key_idx); 7829 rt2800_register_multiread(rt2x00dev, offset, 7830 &iveiv_entry, sizeof(iveiv_entry)); 7831 7832 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16)); 7833 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32)); 7834} 7835EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq); 7836 7837int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 7838{ 7839 struct rt2x00_dev *rt2x00dev = hw->priv; 7840 u32 reg; 7841 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 7842 7843 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); 7844 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 7845 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 7846 7847 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); 7848 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 7849 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 7850 7851 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); 7852 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 7853 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 7854 7855 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); 7856 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 7857 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 7858 7859 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); 7860 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 7861 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 7862 7863 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); 7864 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 7865 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 7866 7867 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); 7868 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 7869 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 7870 7871 return 0; 7872} 7873EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 7874 7875int rt2800_conf_tx(struct ieee80211_hw *hw, 7876 struct ieee80211_vif *vif, u16 queue_idx, 7877 const struct ieee80211_tx_queue_params *params) 7878{ 7879 struct rt2x00_dev *rt2x00dev = hw->priv; 7880 struct data_queue *queue; 7881 struct rt2x00_field32 field; 7882 int retval; 7883 u32 reg; 7884 u32 offset; 7885 7886 /* 7887 * First pass the configuration through rt2x00lib, that will 7888 * update the queue settings and validate the input. After that 7889 * we are free to update the registers based on the value 7890 * in the queue parameter. 7891 */ 7892 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); 7893 if (retval) 7894 return retval; 7895 7896 /* 7897 * We only need to perform additional register initialization 7898 * for WMM queues/ 7899 */ 7900 if (queue_idx >= 4) 7901 return 0; 7902 7903 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 7904 7905 /* Update WMM TXOP register */ 7906 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 7907 field.bit_offset = (queue_idx & 1) * 16; 7908 field.bit_mask = 0xffff << field.bit_offset; 7909 7910 rt2800_register_read(rt2x00dev, offset, ®); 7911 rt2x00_set_field32(®, field, queue->txop); 7912 rt2800_register_write(rt2x00dev, offset, reg); 7913 7914 /* Update WMM registers */ 7915 field.bit_offset = queue_idx * 4; 7916 field.bit_mask = 0xf << field.bit_offset; 7917 7918 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®); 7919 rt2x00_set_field32(®, field, queue->aifs); 7920 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 7921 7922 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®); 7923 rt2x00_set_field32(®, field, queue->cw_min); 7924 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 7925 7926 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®); 7927 rt2x00_set_field32(®, field, queue->cw_max); 7928 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 7929 7930 /* Update EDCA registers */ 7931 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 7932 7933 rt2800_register_read(rt2x00dev, offset, ®); 7934 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 7935 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 7936 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 7937 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 7938 rt2800_register_write(rt2x00dev, offset, reg); 7939 7940 return 0; 7941} 7942EXPORT_SYMBOL_GPL(rt2800_conf_tx); 7943 7944u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 7945{ 7946 struct rt2x00_dev *rt2x00dev = hw->priv; 7947 u64 tsf; 7948 u32 reg; 7949 7950 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®); 7951 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 7952 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®); 7953 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 7954 7955 return tsf; 7956} 7957EXPORT_SYMBOL_GPL(rt2800_get_tsf); 7958 7959int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 7960 enum ieee80211_ampdu_mlme_action action, 7961 struct ieee80211_sta *sta, u16 tid, u16 *ssn, 7962 u8 buf_size) 7963{ 7964 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 7965 int ret = 0; 7966 7967 /* 7968 * Don't allow aggregation for stations the hardware isn't aware 7969 * of because tx status reports for frames to an unknown station 7970 * always contain wcid=255 and thus we can't distinguish between 7971 * multiple stations which leads to unwanted situations when the 7972 * hw reorders frames due to aggregation. 7973 */ 7974 if (sta_priv->wcid < 0) 7975 return 1; 7976 7977 switch (action) { 7978 case IEEE80211_AMPDU_RX_START: 7979 case IEEE80211_AMPDU_RX_STOP: 7980 /* 7981 * The hw itself takes care of setting up BlockAck mechanisms. 7982 * So, we only have to allow mac80211 to nagotiate a BlockAck 7983 * agreement. Once that is done, the hw will BlockAck incoming 7984 * AMPDUs without further setup. 7985 */ 7986 break; 7987 case IEEE80211_AMPDU_TX_START: 7988 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 7989 break; 7990 case IEEE80211_AMPDU_TX_STOP_CONT: 7991 case IEEE80211_AMPDU_TX_STOP_FLUSH: 7992 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 7993 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 7994 break; 7995 case IEEE80211_AMPDU_TX_OPERATIONAL: 7996 break; 7997 default: 7998 rt2x00_warn((struct rt2x00_dev *)hw->priv, 7999 "Unknown AMPDU action\n"); 8000 } 8001 8002 return ret; 8003} 8004EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 8005 8006int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 8007 struct survey_info *survey) 8008{ 8009 struct rt2x00_dev *rt2x00dev = hw->priv; 8010 struct ieee80211_conf *conf = &hw->conf; 8011 u32 idle, busy, busy_ext; 8012 8013 if (idx != 0) 8014 return -ENOENT; 8015 8016 survey->channel = conf->chandef.chan; 8017 8018 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle); 8019 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy); 8020 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext); 8021 8022 if (idle || busy) { 8023 survey->filled = SURVEY_INFO_TIME | 8024 SURVEY_INFO_TIME_BUSY | 8025 SURVEY_INFO_TIME_EXT_BUSY; 8026 8027 survey->time = (idle + busy) / 1000; 8028 survey->time_busy = busy / 1000; 8029 survey->time_ext_busy = busy_ext / 1000; 8030 } 8031 8032 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 8033 survey->filled |= SURVEY_INFO_IN_USE; 8034 8035 return 0; 8036 8037} 8038EXPORT_SYMBOL_GPL(rt2800_get_survey); 8039 8040MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 8041MODULE_VERSION(DRV_VERSION); 8042MODULE_DESCRIPTION("Ralink RT2800 library"); 8043MODULE_LICENSE("GPL"); 8044