| /linux-4.1.27/arch/powerpc/platforms/ps3/ |
| H A D | hvcall.S | 31 std r0, 16(r1); \
36 ld r0, 16(r1); \
53 std r0, 16(r1); \
55 stdu r3, -8(r1); \
60 addi r1, r1, 8; \
61 ld r11, -8(r1); \
64 ld r0, 16(r1); \
72 std r0, 16(r1); \
74 std r3, -8(r1); \
75 stdu r4, -16(r1); \
80 addi r1, r1, 16; \
81 ld r11, -8(r1); \
83 ld r11, -16(r1); \
86 ld r0, 16(r1); \
94 std r0, 16(r1); \
96 std r3, -8(r1); \
97 std r4, -16(r1); \
98 stdu r5, -24(r1); \
103 addi r1, r1, 24; \
104 ld r11, -8(r1); \
106 ld r11, -16(r1); \
108 ld r11, -24(r1); \
111 ld r0, 16(r1); \
119 std r0, 16(r1); \
121 std r3, -8(r1); \
122 std r4, -16(r1); \
123 std r5, -24(r1); \
124 std r6, -32(r1); \
125 std r7, -40(r1); \
126 std r8, -48(r1); \
127 stdu r9, -56(r1); \
132 addi r1, r1, 56; \
133 ld r11, -8(r1); \
135 ld r11, -16(r1); \
137 ld r11, -24(r1); \
139 ld r11, -32(r1); \
141 ld r11, -40(r1); \
143 ld r11, -48(r1); \
145 ld r11, -56(r1); \
148 ld r0, 16(r1); \
156 std r0, 16(r1); \
158 stdu r4, -8(r1); \
163 addi r1, r1, 8; \
164 ld r11, -8(r1); \
167 ld r0, 16(r1); \
175 std r0, 16(r1); \
177 std r4, -8(r1); \
178 stdu r5, -16(r1); \
183 addi r1, r1, 16; \
184 ld r11, -8(r1); \
186 ld r11, -16(r1); \
189 ld r0, 16(r1); \
197 std r0, 16(r1); \
199 std r4, -8(r1); \
200 std r5, -16(r1); \
201 stdu r6, -24(r1); \
206 addi r1, r1, 24; \
207 ld r11, -8(r1); \
209 ld r11, -16(r1); \
211 ld r11, -24(r1); \
214 ld r0, 16(r1); \
222 std r0, 16(r1); \
224 std r4, -8(r1); \
225 std r5, -16(r1); \
226 std r6, -24(r1); \
227 stdu r7, -32(r1); \
232 addi r1, r1, 32; \
233 ld r11, -8(r1); \
235 ld r11, -16(r1); \
237 ld r11, -24(r1); \
239 ld r11, -32(r1); \
242 ld r0, 16(r1); \
250 std r0, 16(r1); \
252 std r4, -8(r1); \
253 std r5, -16(r1); \
254 std r6, -24(r1); \
255 std r7, -32(r1); \
256 stdu r8, -40(r1); \
261 addi r1, r1, 40; \
262 ld r11, -8(r1); \
264 ld r11, -16(r1); \
266 ld r11, -24(r1); \
268 ld r11, -32(r1); \
270 ld r11, -40(r1); \
273 ld r0, 16(r1); \
281 std r0, 16(r1); \
283 std r4, -8(r1); \
284 std r5, -16(r1); \
285 std r6, -24(r1); \
286 std r7, -32(r1); \
287 std r8, -40(r1); \
288 stdu r9, -48(r1); \
293 addi r1, r1, 48; \
294 ld r11, -8(r1); \
296 ld r11, -16(r1); \
298 ld r11, -24(r1); \
300 ld r11, -32(r1); \
302 ld r11, -40(r1); \
304 ld r11, -48(r1); \
307 ld r0, 16(r1); \
315 std r0, 16(r1); \
317 std r4, -8(r1); \
318 std r5, -16(r1); \
319 std r6, -24(r1); \
320 std r7, -32(r1); \
321 std r8, -40(r1); \
322 std r9, -48(r1); \
323 stdu r10, -56(r1); \
328 addi r1, r1, 56; \
329 ld r11, -8(r1); \
331 ld r11, -16(r1); \
333 ld r11, -24(r1); \
335 ld r11, -32(r1); \
337 ld r11, -40(r1); \
339 ld r11, -48(r1); \
341 ld r11, -56(r1); \
344 ld r0, 16(r1); \
352 std r0, 16(r1); \
354 stdu r5, -8(r1); \
359 addi r1, r1, 8; \
360 ld r11, -8(r1); \
363 ld r0, 16(r1); \
371 std r0, 16(r1); \
373 std r5, -8(r1); \
374 stdu r6, -16(r1); \
379 addi r1, r1, 16; \
380 ld r11, -8(r1); \
382 ld r11, -16(r1); \
385 ld r0, 16(r1); \
393 std r0, 16(r1); \
395 std r5, -8(r1); \
396 std r6, -16(r1); \
397 stdu r7, -24(r1); \
402 addi r1, r1, 24; \
403 ld r11, -8(r1); \
405 ld r11, -16(r1); \
407 ld r11, -24(r1); \
410 ld r0, 16(r1); \
418 std r0, 16(r1); \
420 std r5, -8(r1); \
421 std r6, -16(r1); \
422 std r7, -24(r1); \
423 stdu r8, -32(r1); \
428 addi r1, r1, 32; \
429 ld r11, -8(r1); \
431 ld r11, -16(r1); \
433 ld r11, -24(r1); \
435 ld r11, -32(r1); \
438 ld r0, 16(r1); \
446 std r0, 16(r1); \
448 std r5, -8(r1); \
449 std r6, -16(r1); \
450 std r7, -24(r1); \
451 std r8, -32(r1); \
452 stdu r9, -40(r1); \
457 addi r1, r1, 40; \
458 ld r11, -8(r1); \
460 ld r11, -16(r1); \
462 ld r11, -24(r1); \
464 ld r11, -32(r1); \
466 ld r11, -40(r1); \
469 ld r0, 16(r1); \
477 std r0, 16(r1); \
479 stdu r6, -8(r1); \
484 addi r1, r1, 8; \
485 ld r11, -8(r1); \
488 ld r0, 16(r1); \
496 std r0, 16(r1); \
498 std r6, -8(r1); \
499 stdu r7, -16(r1); \
504 addi r1, r1, 16; \
505 ld r11, -8(r1); \
507 ld r11, -16(r1); \
510 ld r0, 16(r1); \
518 std r0, 16(r1); \
520 std r6, -8(r1); \
521 std r7, -16(r1); \
522 stdu r8, -24(r1); \
527 addi r1, r1, 24; \
528 ld r11, -8(r1); \
530 ld r11, -16(r1); \
532 ld r11, -24(r1); \
535 ld r0, 16(r1); \
543 std r0, 16(r1); \
545 stdu r7, -8(r1); \
550 addi r1, r1, 8; \
551 ld r11, -8(r1); \
554 ld r0, 16(r1); \
562 std r0, 16(r1); \
564 std r7, -8(r1); \
565 stdu r8, -16(r1); \
570 addi r1, r1, 16; \
571 ld r11, -8(r1); \
573 ld r11, -16(r1); \
576 ld r0, 16(r1); \
584 std r0, 16(r1); \
586 std r7, -8(r1); \
587 std r8, -16(r1); \
588 stdu r9, -24(r1); \
593 addi r1, r1, 24; \
594 ld r11, -8(r1); \
596 ld r11, -16(r1); \
598 ld r11, -24(r1); \
601 ld r0, 16(r1); \
609 std r0, 16(r1); \
611 stdu r8, -8(r1); \
616 addi r1, r1, 8; \
617 ld r11, -8(r1); \
620 ld r0, 16(r1); \
628 std r0, 16(r1); \
630 std r8, -8(r1); \
631 stdu r9, -16(r1); \
636 addi r1, r1, 16; \
637 ld r11, -8(r1); \
639 ld r11, -16(r1); \
642 ld r0, 16(r1); \
650 std r0, 16(r1); \
652 std r8, -8(r1); \
653 std r9, -16(r1); \
654 stdu r10, -24(r1); \
659 addi r1, r1, 24; \
660 ld r11, -8(r1); \
662 ld r11, -16(r1); \
664 ld r11, -24(r1); \
667 ld r0, 16(r1); \
675 std r0, 16(r1); \
677 stdu r9, -8(r1); \
682 addi r1, r1, 8; \
683 ld r11, -8(r1); \
686 ld r0, 16(r1); \
694 std r0, 16(r1); \
696 std r9, -8(r1); \
697 stdu r10, -16(r1); \
702 addi r1, r1, 16; \
703 ld r11, -8(r1); \
705 ld r11, -16(r1); \
708 ld r0, 16(r1); \
716 std r0, 16(r1); \
718 std r9, -8(r1); \
719 stdu r10, -16(r1); \
724 addi r1, r1, 16; \
725 ld r11, -8(r1); \
727 ld r11, -16(r1); \
729 ld r11, 48+8*8(r1); \
732 ld r0, 16(r1); \
740 std r0, 16(r1); \
742 stdu r10, -8(r1); \
747 addi r1, r1, 8; \
748 ld r11, -8(r1); \
751 ld r0, 16(r1); \
759 std r0, 16(r1); \
761 std r10, 48+8*7(r1); \
766 ld r11, 48+8*7(r1); \
768 ld r11, 48+8*8(r1); \
770 ld r11, 48+8*9(r1); \
772 ld r11, 48+8*10(r1); \
774 ld r11, 48+8*11(r1); \
776 ld r11, 48+8*12(r1); \
779 ld r0, 16(r1); \
787 std r0, 16(r1); \
792 ld r11, 48+8*8(r1); \
795 ld r0, 16(r1); \
|
| /linux-4.1.27/tools/testing/selftests/powerpc/stringloops/asm/ |
| H A D | ppc_asm.h | 3 #ifndef r1
4 #define r1 sp macro
|
| /linux-4.1.27/arch/arm/boot/compressed/ |
| H A D | debug.S | 9 addruart r1, r2, r3
10 waituart r3, r1
11 senduart r0, r1
12 busyuart r3, r1
19 adr r1, 1f
20 ldmia r1, {r2, r3}
21 add r2, r2, r1
22 ldr r1, [r2, r3]
23 strb r0, [r1]
|
| H A D | ll_char_wr.S | 32 * r1 = char
43 mov r1, r1, lsl #3
60 orr r1, r1, #7
61 ldrb r7, [r6, r1]
70 sub r1, r1, #1 @ avoid using r7 directly after
72 ldrb r7, [r6, r1]
75 tst r1, #7 @ avoid using r7 directly after
77 subne r1, r1, #1
78 ldrneb r7, [r6, r1]
92 sub r1, r1, #1 @ avoid ip
95 ldrb r7, [r6, r1]
102 tst r1, #7 @ avoid ip
105 subne r1, r1, #1
106 ldrneb r7, [r6, r1]
114 add r6, r6, r1
|
| H A D | head-sharpsl.S | 28 mov r1, #0x10000000 @ Base address of TC6393 chip
30 ldrh r3, [r1, #8] @ Load TC6393XB Revison: This is 0x0003
42 ldr r1, .W100ADDR @ Base address of w100 chip + regs offset
45 str r6, [r1, #0x280] @ to SCRATCH_UMSK
51 str r6, [r1, #0x280] @ to SCRATCH_UMSK
53 ldr r6, [r1, #0] @ Load Chip ID
83 ldr r1, .SCOOP2ADDR
86 strh r6, [r1]
87 ldrh r6, [r1]
125 * Corrupts: r1
128 mov r1, #0x0c000000 @ Base address of NAND chip
129 ldrb r3, [r1, #24] @ Load FLASHCTL
132 strb r3, [r1, #24] @ Save to FLASHCTL
134 strb r2, [r1, #20] @ Save to FLASHIO
137 strb r3, [r1, #24] @ Save to FLASHCTL
139 strb r2, [r1, #20] @ Save to FLASHIO
141 strb r3, [r1, #24] @ Save to FLASHCTL
143 ldrb r3, [r1, #24] @ Load FLASHCTL
146 ldrb r2, [r1, #20] @ NAND Manufacturer ID
147 ldrb r3, [r1, #20] @ NAND Chip ID
|
| H A D | head.S | 81 mov r1, #\len
148 mov r7, r1 @ save architecture ID
221 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
228 sub r0, r0, r1 @ calculate the delta offset
281 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
283 ldr r1, =0xd00dfeed
285 cmp lr, r1
302 eor r1, r5, r5, ror #16
303 bic r1, r1, #0x00ff0000
305 eor r5, r5, r1, lsr #8
322 mov r1, r6
335 mov r1, r6
352 adr r1, wont_overwrite
353 sub r1, r6, r1
354 subs r1, r5, r1
355 addhi r9, r9, r1
361 eor r1, r5, r5, ror #16
362 bic r1, r1, #0x00ff0000
364 eor r5, r5, r1, lsr #8
468 orrs r1, r0, r5
487 1: ldr r1, [r11, #0] @ relocate entries in the GOT
488 add r1, r1, r0 @ This fixes up C references
489 cmp r1, r2 @ if entry >= bss_start &&
490 cmphs r3, r1 @ bss_end > entry
491 addhi r1, r1, r5 @ entry += dtb size
492 str r1, [r11], #4 @ next entry
506 1: ldr r1, [r11, #0] @ relocate entries in the GOT
507 cmp r1, r2 @ entry < bss_start ||
508 cmphs r3, r1 @ _end < entry
509 addlo r1, r1, r0 @ table. This fixes up the
510 str r1, [r11], #4 @ C references.
540 mov r1, sp @ malloc space above stack
546 mov r1, r7 @ restore architecture number
572 LC0: .word LC0 @ r1
604 * r0, r1, r2, r3, r9, r10, r12 corrupted
691 mov r1, #0x12 @ XN|U + section mapping
692 orr r1, r1, #3 << 10 @ AP=11
694 1: cmp r1, r9 @ if virt > start of RAM
695 cmphs r10, r1 @ && end of RAM > virt
696 bic r1, r1, #0x1c @ clear XN|U + C + B
697 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
698 orrhs r1, r1, r6 @ set RAM section settings
699 str r1, [r0], #4 @ 1:1 mapping
700 add r1, r1, #1048576
709 orr r1, r6, #0x04 @ ensure B is set for this
710 orr r1, r1, #3 << 10
713 orr r1, r1, r2, lsl #20
715 str r1, [r0], #4
716 add r1, r1, #1048576
717 str r1, [r0]
777 movne r1, #0xfffffffd @ domain 0 = client
781 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
811 mov r1, #-1
813 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
830 * r1 = corrupted
853 1: ldr r1, [r12, #0] @ get value
855 eor r1, r1, r9 @ (real ^ match)
856 tst r1, r2 @ & mask
1037 * r0, r1, r2, r3, r9, r12 corrupted
1097 * r1, r2, r3, r9, r10, r11, r12 corrupted
1112 mov r1, #7 << 5 @ 8 segments
1113 1: orr r3, r1, #63 << 26 @ 64 entries
1117 subs r1, r1, #1 << 5
1128 mov r1, #0
1129 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1130 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1131 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1135 mov r1, #0
1137 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1138 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1139 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1140 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1162 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1163 and r1, r1, #7 @ mask of the bits for current cache only
1164 cmp r1, #2 @ see what cache we have at this level
1168 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1169 and r2, r1, #7 @ extract the length of the cache lines
1172 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1175 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1222 mov r1, r3, lsr #18
1223 and r1, r1, #7
1225 mov r2, r2, lsl r1 @ base dcache size *2
1233 mov r1, pc
1234 bic r1, r1, #63 @ align to longest cache line
1235 add r2, r1, r2
1237 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1238 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1239 THUMB( add r1, r1, r11 )
1240 teq r1, r2
1243 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1244 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1245 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1252 mov r1, #0
1253 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1266 @ phex corrupts {r0, r1, r2, r3}
1269 strb r2, [r3, r1]
1270 1: subs r1, r1, #1
1278 strb r2, [r3, r1]
1281 @ puts corrupts {r0, r1, r2, r3}
1282 puts: loadsp r3, r1
1287 mov r1, #0x00020000
1288 3: subs r1, r1, #1
1296 @ putc corrupts {r0, r1, r2, r3}
1300 loadsp r3, r1
1303 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1309 mov r1, #8
1316 mov r1, #8
|
| /linux-4.1.27/arch/microblaze/kernel/ |
| H A D | mcount.S | 18 addik r1, r1, -120; \
19 swi r2, r1, 4; \
20 swi r3, r1, 8; \
21 swi r4, r1, 12; \
22 swi r5, r1, 116; \
23 swi r6, r1, 16; \
24 swi r7, r1, 20; \
25 swi r8, r1, 24; \
26 swi r9, r1, 28; \
27 swi r10, r1, 32; \
28 swi r11, r1, 36; \
29 swi r12, r1, 40; \
30 swi r13, r1, 44; \
31 swi r14, r1, 48; \
32 swi r16, r1, 52; \
33 swi r17, r1, 56; \
34 swi r18, r1, 60; \
35 swi r19, r1, 64; \
36 swi r20, r1, 68; \
37 swi r21, r1, 72; \
38 swi r22, r1, 76; \
39 swi r23, r1, 80; \
40 swi r24, r1, 84; \
41 swi r25, r1, 88; \
42 swi r26, r1, 92; \
43 swi r27, r1, 96; \
44 swi r28, r1, 100; \
45 swi r29, r1, 104; \
46 swi r30, r1, 108; \
47 swi r31, r1, 112;
50 lwi r2, r1, 4; \
51 lwi r3, r1, 8; \
52 lwi r4, r1, 12; \
53 lwi r5, r1, 116; \
54 lwi r6, r1, 16; \
55 lwi r7, r1, 20; \
56 lwi r8, r1, 24; \
57 lwi r9, r1, 28; \
58 lwi r10, r1, 32; \
59 lwi r11, r1, 36; \
60 lwi r12, r1, 40; \
61 lwi r13, r1, 44; \
62 lwi r14, r1, 48; \
63 lwi r16, r1, 52; \
64 lwi r17, r1, 56; \
65 lwi r18, r1, 60; \
66 lwi r19, r1, 64; \
67 lwi r20, r1, 68; \
68 lwi r21, r1, 72; \
69 lwi r22, r1, 76; \
70 lwi r23, r1, 80; \
71 lwi r24, r1, 84; \
72 lwi r25, r1, 88; \
73 lwi r26, r1, 92; \
74 lwi r27, r1, 96; \
75 lwi r28, r1, 100; \
76 lwi r29, r1, 104; \
77 lwi r30, r1, 108; \
78 lwi r31, r1, 112; \
79 addik r1, r1, 120;
93 swi r15, r1, 0;
112 addik r5, r1, 120; /* MS: load parent addr */
135 lwi r6, r1, 120; /* MS: load parent addr */
141 lwi r15, r1, 0;
152 swi r15, r1, 0;
|
| H A D | entry-nommu.S | 54 swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
60 addik r1, r1, (-PT_SIZE) /* room for pt_regs (delay slot) */
62 lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
63 lwi r1, r1, TS_THREAD_INFO /* get the thread info */
65 addik r1, r1, THREAD_SIZE - PT_SIZE
67 swi r11, r1, PT_MODE /* store the mode */
69 swi r2, r1, PT_R2
70 swi r3, r1, PT_R3
71 swi r4, r1, PT_R4
72 swi r5, r1, PT_R5
73 swi r6, r1, PT_R6
74 swi r7, r1, PT_R7
75 swi r8, r1, PT_R8
76 swi r9, r1, PT_R9
77 swi r10, r1, PT_R10
78 swi r11, r1, PT_R11
79 swi r12, r1, PT_R12
80 swi r13, r1, PT_R13
81 swi r14, r1, PT_R14
82 swi r14, r1, PT_PC
83 swi r15, r1, PT_R15
84 swi r16, r1, PT_R16
85 swi r17, r1, PT_R17
86 swi r18, r1, PT_R18
87 swi r19, r1, PT_R19
88 swi r20, r1, PT_R20
89 swi r21, r1, PT_R21
90 swi r22, r1, PT_R22
91 swi r23, r1, PT_R23
92 swi r24, r1, PT_R24
93 swi r25, r1, PT_R25
94 swi r26, r1, PT_R26
95 swi r27, r1, PT_R27
96 swi r28, r1, PT_R28
97 swi r29, r1, PT_R29
98 swi r30, r1, PT_R30
99 swi r31, r1, PT_R31
102 swi r11, r1, PT_MSR
104 swi r11, r1, PT_EAR
106 swi r11, r1, PT_ESR
108 swi r11, r1, PT_FSR
111 swi r11, r1, PT_R1
121 add r5, r0, r1
124 lwi r11, r1, PT_MODE
139 addk r5, r1, r0
149 lwi r11, r1, PT_MODE
156 lwi r11, r1, PT_FSR
158 lwi r11, r1, PT_ESR
160 lwi r11, r1, PT_EAR
162 lwi r11, r1, PT_MSR
165 lwi r31, r1, PT_R31
166 lwi r30, r1, PT_R30
167 lwi r29, r1, PT_R29
168 lwi r28, r1, PT_R28
169 lwi r27, r1, PT_R27
170 lwi r26, r1, PT_R26
171 lwi r25, r1, PT_R25
172 lwi r24, r1, PT_R24
173 lwi r23, r1, PT_R23
174 lwi r22, r1, PT_R22
175 lwi r21, r1, PT_R21
176 lwi r20, r1, PT_R20
177 lwi r19, r1, PT_R19
178 lwi r18, r1, PT_R18
179 lwi r17, r1, PT_R17
180 lwi r16, r1, PT_R16
181 lwi r15, r1, PT_R15
182 lwi r14, r1, PT_PC
183 lwi r13, r1, PT_R13
184 lwi r12, r1, PT_R12
185 lwi r11, r1, PT_R11
186 lwi r10, r1, PT_R10
187 lwi r9, r1, PT_R9
188 lwi r8, r1, PT_R8
189 lwi r7, r1, PT_R7
190 lwi r6, r1, PT_R6
191 lwi r5, r1, PT_R5
192 lwi r4, r1, PT_R4
193 lwi r3, r1, PT_R3
194 lwi r2, r1, PT_R2
195 lwi r1, r1, PT_R1
203 swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
209 addik r1, r1, (-PT_SIZE) /* Room for pt_regs (delay slot) */
211 lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
212 lwi r1, r1, TS_THREAD_INFO /* get the thread info */
214 addik r1, r1, THREAD_SIZE - PT_SIZE
216 swi r11, r1, PT_MODE /* store the mode */
219 swi r2, r1, PT_R2
220 swi r3, r1, PT_R3 /* r3: _always_ in clobber list; see unistd.h */
221 swi r4, r1, PT_R4 /* r4: _always_ in clobber list; see unistd.h */
222 swi r5, r1, PT_R5
223 swi r6, r1, PT_R6
224 swi r7, r1, PT_R7
225 swi r8, r1, PT_R8
226 swi r9, r1, PT_R9
227 swi r10, r1, PT_R10
228 swi r11, r1, PT_R11
230 swi r12, r1, PT_R12
231 swi r13, r1, PT_R13
233 swi r14, r1, PT_R14
236 swi r14, r1, PT_PC /* increment by 4 and store in pc */
237 swi r15, r1, PT_R15
238 swi r16, r1, PT_R16
239 swi r17, r1, PT_R17
240 swi r18, r1, PT_R18
241 swi r19, r1, PT_R19
242 swi r20, r1, PT_R20
243 swi r21, r1, PT_R21
244 swi r22, r1, PT_R22
245 swi r23, r1, PT_R23
246 swi r24, r1, PT_R24
247 swi r25, r1, PT_R25
248 swi r26, r1, PT_R26
249 swi r27, r1, PT_R27
250 swi r28, r1, PT_R28
251 swi r29, r1, PT_R29
252 swi r30, r1, PT_R30
253 swi r31, r1, PT_R31
262 swi r11, r1, PT_MSR
264 swi r11, r1, PT_EAR
266 swi r11, r1, PT_ESR
268 swi r11, r1, PT_FSR
271 swi r11, r1, PT_R1
302 swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
303 lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
304 lwi r1, r1, TS_THREAD_INFO /* get the thread info */
305 addik r1, r1, THREAD_SIZE - PT_SIZE /* get the kernel stack */
309 swi r11, r1, PT_MODE /* store the mode */
312 swi r2, r1, PT_R2
313 swi r3, r1, PT_R3 /* r3: _always_ in clobber list; see unistd.h */
314 swi r4, r1, PT_R4 /* r4: _always_ in clobber list; see unistd.h */
315 swi r5, r1, PT_R5
316 swi r6, r1, PT_R6
317 swi r7, r1, PT_R7
318 swi r8, r1, PT_R8
319 swi r9, r1, PT_R9
320 swi r10, r1, PT_R10
321 swi r11, r1, PT_R11
323 swi r12, r1, PT_R12
324 swi r13, r1, PT_R13
326 swi r14, r1, PT_R14
327 swi r14, r1, PT_PC /* Will return to interrupted instruction */
328 swi r15, r1, PT_R15
329 swi r16, r1, PT_R16
330 swi r17, r1, PT_R17
331 swi r18, r1, PT_R18
332 swi r19, r1, PT_R19
333 swi r20, r1, PT_R20
334 swi r21, r1, PT_R21
335 swi r22, r1, PT_R22
336 swi r23, r1, PT_R23
337 swi r24, r1, PT_R24
338 swi r25, r1, PT_R25
339 swi r26, r1, PT_R26
340 swi r27, r1, PT_R27
341 swi r28, r1, PT_R28
342 swi r29, r1, PT_R29
343 swi r30, r1, PT_R30
344 swi r31, r1, PT_R31
353 swi r11, r1, PT_MSR
355 swi r11, r1, PT_EAR
357 swi r11, r1, PT_ESR
359 swi r11, r1, PT_FSR
362 swi r11, r1, PT_R1
378 lwi r3, r1, PT_R3
379 lwi r4, r1, PT_R4
394 swi r1, r11, CC_R1
466 lwi r1, r11, CC_R1
475 swi r31, r1, PT_R31 /* save r31 in user context. */
490 lwi r11, r1, PT_MODE
514 swi r4, r1, PT_R4 /* return val */
515 swi r3, r1, PT_R3 /* return val */
527 lwi r18, r1, PT_MODE
531 lwi r18, r1, PT_FSR
533 lwi r18, r1, PT_ESR
535 lwi r18, r1, PT_EAR
537 lwi r18, r1, PT_MSR
540 lwi r31, r1, PT_R31
541 lwi r30, r1, PT_R30
542 lwi r29, r1, PT_R29
543 lwi r28, r1, PT_R28
544 lwi r27, r1, PT_R27
545 lwi r26, r1, PT_R26
546 lwi r25, r1, PT_R25
547 lwi r24, r1, PT_R24
548 lwi r23, r1, PT_R23
549 lwi r22, r1, PT_R22
550 lwi r21, r1, PT_R21
551 lwi r20, r1, PT_R20
552 lwi r19, r1, PT_R19
553 lwi r18, r1, PT_R18
554 lwi r17, r1, PT_R17
555 lwi r16, r1, PT_R16
556 lwi r15, r1, PT_R15
557 lwi r14, r1, PT_PC
558 lwi r13, r1, PT_R13
559 lwi r12, r1, PT_R12
560 lwi r11, r1, PT_R11
561 lwi r10, r1, PT_R10
562 lwi r9, r1, PT_R9
563 lwi r8, r1, PT_R8
564 lwi r7, r1, PT_R7
565 lwi r6, r1, PT_R6
566 lwi r5, r1, PT_R5
567 lwi r4, r1, PT_R4 /* return val */
568 lwi r3, r1, PT_R3 /* return val */
569 lwi r2, r1, PT_R2
570 lwi r1, r1, PT_R1
578 addk r5, r1, r0
|
| H A D | entry.S | 178 swi r2, r1, PT_R2; /* Save SDA */ \
179 swi r3, r1, PT_R3; \
180 swi r4, r1, PT_R4; \
181 swi r5, r1, PT_R5; \
182 swi r6, r1, PT_R6; \
183 swi r7, r1, PT_R7; \
184 swi r8, r1, PT_R8; \
185 swi r9, r1, PT_R9; \
186 swi r10, r1, PT_R10; \
187 swi r11, r1, PT_R11; /* save clobbered regs after rval */\
188 swi r12, r1, PT_R12; \
189 swi r13, r1, PT_R13; /* Save SDA2 */ \
190 swi r14, r1, PT_PC; /* PC, before IRQ/trap */ \
191 swi r15, r1, PT_R15; /* Save LP */ \
192 swi r16, r1, PT_R16; \
193 swi r17, r1, PT_R17; \
194 swi r18, r1, PT_R18; /* Save asm scratch reg */ \
195 swi r19, r1, PT_R19; \
196 swi r20, r1, PT_R20; \
197 swi r21, r1, PT_R21; \
198 swi r22, r1, PT_R22; \
199 swi r23, r1, PT_R23; \
200 swi r24, r1, PT_R24; \
201 swi r25, r1, PT_R25; \
202 swi r26, r1, PT_R26; \
203 swi r27, r1, PT_R27; \
204 swi r28, r1, PT_R28; \
205 swi r29, r1, PT_R29; \
206 swi r30, r1, PT_R30; \
207 swi r31, r1, PT_R31; /* Save current task reg */ \
209 swi r11, r1, PT_MSR;
212 lwi r11, r1, PT_MSR; \
214 lwi r2, r1, PT_R2; /* restore SDA */ \
215 lwi r3, r1, PT_R3; \
216 lwi r4, r1, PT_R4; \
217 lwi r5, r1, PT_R5; \
218 lwi r6, r1, PT_R6; \
219 lwi r7, r1, PT_R7; \
220 lwi r8, r1, PT_R8; \
221 lwi r9, r1, PT_R9; \
222 lwi r10, r1, PT_R10; \
223 lwi r11, r1, PT_R11; /* restore clobbered regs after rval */\
224 lwi r12, r1, PT_R12; \
225 lwi r13, r1, PT_R13; /* restore SDA2 */ \
226 lwi r14, r1, PT_PC; /* RESTORE_LINK PC, before IRQ/trap */\
227 lwi r15, r1, PT_R15; /* restore LP */ \
228 lwi r16, r1, PT_R16; \
229 lwi r17, r1, PT_R17; \
230 lwi r18, r1, PT_R18; /* restore asm scratch reg */ \
231 lwi r19, r1, PT_R19; \
232 lwi r20, r1, PT_R20; \
233 lwi r21, r1, PT_R21; \
234 lwi r22, r1, PT_R22; \
235 lwi r23, r1, PT_R23; \
236 lwi r24, r1, PT_R24; \
237 lwi r25, r1, PT_R25; \
238 lwi r26, r1, PT_R26; \
239 lwi r27, r1, PT_R27; \
240 lwi r28, r1, PT_R28; \
241 lwi r29, r1, PT_R29; \
242 lwi r30, r1, PT_R30; \
243 lwi r31, r1, PT_R31; /* Restore cur task reg */
246 swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* save stack */ \
248 mfs r1, rmsr; \
249 andi r1, r1, MSR_UMS; \
250 bnei r1, 1f; \
253 lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); \
255 /* tophys(r1,r1); */ \
256 /* addik r1, r1, -PT_SIZE; */ \
257 addik r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - PT_SIZE; \
260 swi r1, r1, PT_MODE; \
262 lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */\
263 tophys(r1,r1); \
264 lwi r1, r1, TS_THREAD_INFO; /* get the thread info */ \
266 /* addik r1, r1, THREAD_SIZE; */ \
267 /* tophys(r1,r1); */ \
268 /* addik r1, r1, -PT_SIZE; */ \
269 addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - PT_SIZE; \
272 swi r11, r1, PT_R1; /* Store user SP. */ \
273 swi r0, r1, PT_MODE; /* Was in user-mode. */ \
293 swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
296 lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */
297 tophys(r1,r1);
298 lwi r1, r1, TS_THREAD_INFO; /* get stack from task_struct */
300 addik r1, r1, THREAD_SIZE;
301 tophys(r1,r1);
303 addik r1, r1, -PT_SIZE; /* Make room on the stack. */
305 swi r0, r1, PT_R3
306 swi r0, r1, PT_R4
308 swi r0, r1, PT_MODE; /* Was in user-mode. */
310 swi r11, r1, PT_R1; /* Store user SP. */
314 swi r12, r1, PT_R0;
315 tovirt(r1,r1)
333 swi r3, r1, PT_R3
335 addik r5, r1, PT_R0
339 lwi r5, r1, PT_R5;
340 lwi r6, r1, PT_R6;
341 lwi r7, r1, PT_R7;
342 lwi r8, r1, PT_R8;
343 lwi r9, r1, PT_R9;
344 lwi r10, r1, PT_R10;
385 swi r3, r1, PT_R3
386 swi r4, r1, PT_R4
388 lwi r11, r1, PT_MODE;
400 addik r5, r1, PT_R0
419 addik r5, r1, 0; /* Arg 1: struct pt_regs *regs */
429 tophys(r1,r1);
431 addik r1, r1, PT_SIZE /* Clean up stack space. */
432 lwi r1, r1, PT_R1 - PT_SIZE;/* Restore user stack pointer. */
438 tophys(r1,r1);
440 addik r1, r1, PT_SIZE /* Clean up stack space. */
441 tovirt(r1,r1);
472 addik r5, r1, 0; /* add user context as 1st arg */
483 swi r17, r1, PT_PC;
484 tovirt(r1,r1)
493 addik r5, r1, 0 /* parameter struct pt_regs * regs */
519 swi r17, r1, PT_PC;
520 tovirt(r1,r1)
526 addik r7, r1, 0 /* parameter struct pt_regs * regs */
549 swi r17, r1, PT_PC;
550 tovirt(r1,r1)
556 addik r5, r1, 0 /* parameter struct pt_regs * regs */
561 swi r17, r1, PT_PC;
562 tovirt(r1,r1)
568 addik r5, r1, 0 /* parameter struct pt_regs * regs */
572 lwi r11, r1, PT_MODE;
604 addik r5, r1, 0; /* Arg 1: struct pt_regs *regs */
613 tophys(r1,r1);
616 addik r1, r1, PT_SIZE /* Clean up stack space. */
618 lwi r1, r1, PT_R1 - PT_SIZE; /* Restore user stack pointer. */
623 tophys(r1,r1);
625 addik r1, r1, PT_SIZE /* Clean up stack space. */
627 tovirt(r1,r1);
640 * The stack-pointer (r1) should have already been saved to the memory
646 swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP))
648 mfs r1, rmsr
650 andi r1, r1, MSR_UMS
651 bnei r1, 1f
654 lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP))
655 tophys(r1,r1); /* MS: I have in r1 physical address where stack is */
658 addik r1, r1, -PT_SIZE;
661 swi r1, r1, PT_MODE; /* 0 - user mode, 1 - kernel mode */
665 lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
666 tophys(r1,r1);
667 lwi r1, r1, TS_THREAD_INFO;
668 addik r1, r1, THREAD_SIZE;
669 tophys(r1,r1);
671 addik r1, r1, -PT_SIZE;
674 swi r0, r1, PT_MODE;
676 swi r11, r1, PT_R1;
680 tovirt(r1,r1)
683 addik r5, r1, 0;
687 lwi r11, r1, PT_MODE;
703 addik r5, r1, 0; /* Arg 1: struct pt_regs *regs */
714 tophys(r1,r1);
716 addik r1, r1, PT_SIZE /* MS: Clean up stack space. */
717 lwi r1, r1, PT_R1 - PT_SIZE;
742 tophys(r1,r1)
744 addik r1, r1, PT_SIZE /* MS: Clean up stack space. */
745 tovirt(r1,r1);
757 swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP))
759 mfs r1, rmsr
761 andi r1, r1, MSR_UMS
762 bnei r1, 1f
764 lwi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/
767 addik r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - PT_SIZE;
770 swi r0, r1, PT_R0; /* R0 must be saved too */
771 swi r14, r1, PT_R14 /* rewrite saved R14 value */
772 swi r16, r1, PT_PC; /* PC and r16 are the same */
775 swi r11, r1, PT_EAR;
777 swi r11, r1, PT_ESR;
779 swi r11, r1, PT_FSR;
783 addik r11, r1, CONFIG_KERNEL_START - CONFIG_KERNEL_BASE_ADDR + PT_SIZE;
784 swi r11, r1, PT_R1
786 tovirt(r1,r1)
788 addi r5, r1, 0 /* pass pt_reg address as the first arg */
798 1: lwi r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */
799 tophys(r1,r1);
800 lwi r1, r1, TS_THREAD_INFO; /* get the thread info */
801 addik r1, r1, THREAD_SIZE; /* calculate kernel stack pointer */
802 tophys(r1,r1);
804 addik r1, r1, -PT_SIZE; /* Make room on the stack. */
806 swi r16, r1, PT_PC; /* Save LP */
807 swi r0, r1, PT_MODE; /* Was in user-mode. */
809 swi r11, r1, PT_R1; /* Store user SP. */
811 tovirt(r1,r1)
813 addik r5, r1, 0;
821 lwi r11, r1, PT_MODE;
840 addik r5, r1, 0; /* Arg 1: struct pt_regs *regs */
848 tophys(r1,r1);
851 addik r1, r1, PT_SIZE /* Clean up stack space */
852 lwi r1, r1, PT_R1 - PT_SIZE; /* Restore user stack pointer */
859 tophys(r1,r1);
862 lwi r14, r1, PT_R14;
863 lwi r16, r1, PT_PC;
864 addik r1, r1, PT_SIZE; /* MS: Clean up stack space */
865 tovirt(r1,r1);
879 swi r1, r11, CC_R1
944 lwi r1, r11, CC_R1
|
| /linux-4.1.27/arch/powerpc/include/asm/ |
| H A D | ftrace.h | 13 stwu r1,-48(r1); \
14 stw r3, 12(r1); \
15 stw r4, 16(r1); \
16 stw r5, 20(r1); \
17 stw r6, 24(r1); \
19 lwz r4, 52(r1); \
21 stw r7, 28(r1); \
22 stw r8, 32(r1); \
23 stw r9, 36(r1); \
24 stw r10,40(r1); \
25 stw r3, 44(r1); \
26 stw r5, 8(r1)
29 lwz r6, 8(r1); \
30 lwz r0, 44(r1); \
31 lwz r3, 12(r1); \
33 lwz r4, 16(r1); \
35 lwz r5, 20(r1); \
36 lwz r6, 24(r1); \
37 lwz r0, 52(r1); \
38 lwz r7, 28(r1); \
39 lwz r8, 32(r1); \
41 lwz r9, 36(r1); \
42 lwz r10,40(r1); \
43 addi r1, r1, 48
|
| H A D | irqflags.h | 23 stdu r1, -STACK_FRAME_OVERHEAD(r1); \
24 std r0, 16(r1); \
25 stdu r1, -STACK_FRAME_OVERHEAD(r1); \
27 ld r1, 0(r1); \
28 ld r1, 0(r1);
|
| /linux-4.1.27/arch/m32r/lib/ |
| H A D | memset.S | 10 * val: r1
35 stb r1, @r4 || addi r4, #1
41 and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
42 sll3 r3, r1, #8
43 or r1, r3 || addi r4, #-4
44 sll3 r3, r1, #16
45 or r1, r3 || addi r2, #-4
47 st r1, @+r4 || addi r2, #-4
50 st r1, @+r4
57 and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
58 sll3 r3, r1, #8
59 or r1, r3 || addi r4, #-4
60 sll3 r3, r1, #16
61 or r1, r3 || ldi r5, #16
64 st r1, @+r4 || addi r2, #-16
65 st r1, @+r4 || cmpu r2, r5
66 st r1, @+r4
67 st r1, @+r4
84 addi r2, #-1 || stb r1, @r4+
88 addi r2, #-1 || stb r1, @r4
113 stb r1, @r4
121 and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
122 sll3 r3, r1, #8
123 or r1, r3
124 sll3 r3, r1, #16
125 or r1, r3
129 st r1, @+r4
133 st r1, @+r4
140 and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
141 sll3 r3, r1, #8
142 or r1, r3
143 sll3 r3, r1, #16
144 or r1, r3
149 st r1, @+r4
150 st r1, @+r4
152 st r1, @+r4
153 st r1, @+r4
170 stb r1, @r4
|
| H A D | ashxdi3.S | 9 ; input (r0,r1) src
12 ; output (r0,r1)
27 mv r1, r0 || srai r0, #31
29 sra r1, r2
33 mv r3, r0 || srl r1, r2
36 or r1, r3 || jmp r14
47 mv r0, r1 || addi r2, #-32
48 sll r0, r2 || ldi r1, #0
52 mv r3, r1 || sll r0, r2
53 sll r1, r2 || neg r2, r2
64 mv r1, r0 || addi r2, #-32
65 ldi r0, #0 || srl r1, r2
69 mv r3, r0 || srl r1, r2
72 or r1, r3 || jmp r14
84 mv r0, r1 || srai r1, #31
90 mv r3, r1 || srl r0, r2
91 sra r1, r2 || neg r2, r2
104 mv r1, r0 || addi r2, #-32
105 sll r1, r2 || ldi r0, #0
109 mv r3, r0 || sll r1, r2
112 or r1, r3 || jmp r14
121 mv r0, r1 || addi r2, #-32
122 ldi r1, #0 || srl r0, r2
126 mv r3, r1 || srl r0, r2
127 srl r1, r2 || neg r2, r2
145 mv r1, r0
148 sra r1, r2
153 srl r1, r2
157 or r1, r3
171 mv r0, r1
174 ldi r1, #0
178 mv r3, r1
180 sll r1, r2
195 mv r1, r0
198 srl r1, r2
203 srl r1, r2
207 or r1, r3
222 mv r0, r1
223 srai r1, #31
229 mv r3, r1
231 sra r1, r2
248 mv r1, r0
250 sll r1, r2
256 sll r1, r2
260 or r1, r3
272 mv r0, r1
273 ldi r1, #0
279 mv r3, r1
281 srl r1, r2
|
| H A D | memcpy.S | 10 * src: r1
24 or r7, r1 || cmpz r2
25 jc r14 || cmpeq r0, r1 ; return if r2=0
26 jc r14 ; return if r0=r1
35 ld r7, @r1+ || addi r3, #-1
41 ldb r7, @r1 || addi r1, #1
46 ldb r7, @r1 || addi r1, #1
63 or r7, r1
64 beq r0, r1, end_memcopy
74 ld r7, @r1+
81 ldb r7, @r1
82 addi r1, #1
|
| H A D | strlen.S | 28 ld r1, @r6+ || not r4, r0
32 ld r0, @r6+ || not r4, r1
33 sub r1, r5 || and r4, r7
34 and r4, r1 || addi r2, #4
43 ldb r1, @r6 || addi r6, #1
44 beqz r1, strlen_exit
51 ldb r1, @r6 || addi r6, #1
52 addi r0, #-1 || cmpz r1
75 ld r1, @r6+
84 not r4, r1 ; NOTE: If a null char. exists, return 0.
85 sub r1, r5 ; if ((x - 0x01010101) & ~x & 0x80808080)
87 and r4, r1
93 ldb r1, @r6
95 beqz r1, strlen_exit
104 ldb r1, @r6
107 beqz r1, strlen_exit
|
| /linux-4.1.27/arch/nios2/boot/compressed/ |
| H A D | head.S | 25 movia r1, NIOS2_ICACHE_SIZE
27 1: initi r1
28 sub r1, r1, r2
29 bgt r1, r0, 1b
31 movia r1, NIOS2_DCACHE_SIZE
33 1: initd 0(r1)
34 sub r1, r1, r2
35 bgt r1, r0, 1b
37 nextpc r1 /* Find out where we are */
40 beq r1, r2, finish_move /* We are running in correct address,
42 /* move code, r1: src, r2: dest, r3: last dest */
43 addi r1, r1, (_start - chkadr) /* Source */
46 1: ldw r8, 0(r1) /* load a word from [r1] */
48 addi r1, r1, 4 /* inc the src addr */
52 movia r1, NIOS2_DCACHE_SIZE
54 1: flushd 0(r1)
55 sub r1, r1, r2
56 bgt r1, r0, 1b
57 movia r1, finish_move
58 jmp r1 /* jmp to linked address */
63 movia r1, _end /* the .bss and _end. */
66 bne r1, r2, 1b
72 add sp, sp, r1
88 movia r1, NIOS2_DCACHE_SIZE
90 1: flushd 0(r1)
91 sub r1, r1, r2
92 bgt r1, r0, 1b
94 movia r1, NIOS2_ICACHE_SIZE
96 1: flushi r1
97 sub r1, r1, r2
98 bgt r1, r0, 1b
101 movia r1, (CONFIG_NIOS2_MEM_BASE | CONFIG_NIOS2_KERNEL_REGION_BASE)
102 jmp r1
|
| /linux-4.1.27/arch/sh/kernel/cpu/sh2a/ |
| H A D | ex.S | 23 mov.l r1,@-sp
25 mov #no,r1
31 extu.b r1,r1
33 extu.w r1,r1
42 mov.l r1,@-sp
44 mov #no,r1
49 extu.b r1,r1
51 add r0,r1
54 extu.w r1,r1
|
| H A D | entry.S | 41 ! r1
45 ! r1 = vector (pseudo EXPEVT / INTEVT / TRA)
61 mov.l r1,@-r15 ! TRA
75 mov r1,r9 ! r9 = interrupt vector
79 mov.l @r8+,r1
88 mov r1,r9 ! r9 = interrupt vector
92 mov.l @r8+,r1 ! old R1
163 mov.l @(OFF_SP,r0),r1
165 mov.l r3,@-r1
167 mov.l r3,@-r1
175 mov.l r1,@(8,r0)
213 mov.l @(OFF_SR,r0),r1
214 shll2 r1
215 shlr2 r1 ! clear MD bit
219 mov.l r1,@(4,r2) ! set sr
220 mov.l @(OFF_PC,r0),r1
221 mov.l r1,@r2 ! set pc
222 get_current_thread_info r0, r1
223 mov.l $current_thread_info,r1
224 mov.l r0,@r1
|
| /linux-4.1.27/arch/arm/kernel/ |
| H A D | debug.S | 47 mov r1, #8
52 mov r1, #4
57 mov r1, #2
59 add r3, r2, r1
60 mov r1, #0
61 strb r1, [r3]
62 1: and r1, r0, #15
64 cmp r1, #10
65 addlt r1, r1, #'0'
66 addge r1, r1, #'a' - 10
67 strb r1, [r3, #-1]!
81 addruart_current r3, r1, r2
84 senduart r1, r3
86 teq r1, #'\n'
87 moveq r1, #'\r'
90 ldrneb r1, [r0], #1
91 teqne r1, #0
97 addruart_current r3, r1, r2
98 mov r1, r0
107 str r3, [r1]
115 mov r1, r0
123 adr r1, hexbuf
124 strb r0, [r1]
134 str r2, [r1]
|
| H A D | iwmmxt.S | 91 ldr r1, [r3] @ get current Concan owner
108 teq r1, #0 @ test for last ownership
119 wstrw wCSSF, [r1, #MMX_WCSSF]
120 wstrw wCASF, [r1, #MMX_WCASF]
121 wstrw wCGR0, [r1, #MMX_WCGR0]
122 wstrw wCGR1, [r1, #MMX_WCGR1]
123 wstrw wCGR2, [r1, #MMX_WCGR2]
124 wstrw wCGR3, [r1, #MMX_WCGR3]
130 wstrd wR0, [r1, #MMX_WR0]
131 wstrd wR1, [r1, #MMX_WR1]
132 wstrd wR2, [r1, #MMX_WR2]
133 wstrd wR3, [r1, #MMX_WR3]
134 wstrd wR4, [r1, #MMX_WR4]
135 wstrd wR5, [r1, #MMX_WR5]
136 wstrd wR6, [r1, #MMX_WR6]
137 wstrd wR7, [r1, #MMX_WR7]
138 wstrd wR8, [r1, #MMX_WR8]
139 wstrd wR9, [r1, #MMX_WR9]
140 wstrd wR10, [r1, #MMX_WR10]
141 wstrd wR11, [r1, #MMX_WR11]
142 wstrd wR12, [r1, #MMX_WR12]
143 wstrd wR13, [r1, #MMX_WR13]
144 wstrd wR14, [r1, #MMX_WR14]
145 wstrd wR15, [r1, #MMX_WR15]
178 @ clear CUP/MUP (only if r1 != 0)
179 teq r1, #0
205 ldr r1, [r3] @ get current Concan owner
206 teq r1, #0 @ any current owner?
209 teqne r1, r2 @ or specified one?
244 * r1 = memory address where to store Concan state
263 mov r0, r1
264 mov r1, r2
282 * r1 = memory address where to get Concan state from
307 mov r0, r1
308 mov r1, #0 @ don't clear CUP/MUP
325 XSC(mrc p15, 0, r1, c15, c1, 0)
326 PJ4(mrc p15, 0, r1, c1, c0, 2)
328 XSC(tst r1, #0x3)
329 PJ4(tst r1, #0xf)
339 XSC(eor r1, r1, #0x3)
340 XSC(mcr p15, 0, r1, c15, c1, 0)
341 PJ4(eor r1, r1, #0xf)
342 PJ4(mcr p15, 0, r1, c1, c0, 2)
344 mrc p15, 0, r1, c2, c0, 0
345 sub pc, lr, r1, lsr #32 @ cpwait and return
361 ldr r1, [r3] @ get current Concan owner
362 eors r0, r0, r1 @ if equal...
|
| H A D | entry-v7m.S | 27 mrs r1, ipsr
46 ldr r1, =V7M_xPSR_EXCEPTIONNO
47 and r0, r1
49 mov r1, sp
51 @ routine called with r0 = irq number, r1 = struct pt_regs *
58 ldr r1, =BASEADDR_V7M_SCB
59 ldr r0, [r1, V7M_SCB_ICSR]
68 str r0, [r1, V7M_SCB_ICSR] @ raise PendSV
84 ldr r1, =BASEADDR_V7M_SCB
86 str r0, [r1, V7M_SCB_ICSR] @ clear PendSV
96 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
102 add ip, r1, #TI_CPU_SAVE
109 mov r1, #THREAD_NOTIFY_SWITCH
|
| /linux-4.1.27/arch/arc/lib/ |
| H A D | memcmp.S | 20 or r12,r0,r1
25 ld r5,[r1,0]
29 ld_s r12,[r1,4]
32 ld.a r5,[r1,8]
39 ld r5,[r1,4]
46 sub_s r1,r0,1
47 bic_s r1,r1,r0
48 norm r1,r1
50 and r1,r1,24
53 sub_s r1,r0,1
54 bic_s r1,r1,r0
55 norm r1,r1
57 and r1,r1,24
59 asl r2,r4,r1
60 asl r12,r5,r1
68 sub_s r1,r0,1
69 bic_s r1,r1,r0
70 norm r1,r1
72 and r1,r1,24
73 asl_s r2,r2,r1
74 asl_s r12,r12,r1
101 ldb r5,[r1,0]
105 ldb r12,[r1,1]
108 ldb.a r5,[r1,2]
114 ldb_s r12,[r1,1]
|
| H A D | memset.S | 17 extb_s r1,r1
18 asl r3,r1,8
20 or_s r1,r1,r3
23 stb r1,[r3,-1]
25 stw r1,[r3,-2]
29 stb.ab r1,[r4,1]
31 stw.ab r1,[r4,2]
34 asl r3,r1,16
36 or_s r1,r1,r3
38 st.ab r1,[r4,4]
46 stb.ab r1,[r4,1]
51 ; memzero: @r0 = mem, @r1 = size_t
52 ; memset: @r0 = mem, @r1 = char, @r2 = size_t
56 mov r2, r1
57 mov r1, 0
|
| H A D | strcpy-700.S | 22 or r2,r0,r1
26 ld_s r3,[r1,0]
28 bbit0.d r1,2,loop_start
37 ld.a r3,[r1,4]
40 ld.a r4,[r1,4]
52 r3z: bmsk.f r1,r3,7
55 r3z: lsr.f r1,r3,24
59 stb.ab r1,[r10,1]
64 ldb.ab r3,[r1,1]
|
| /linux-4.1.27/arch/unicore32/kernel/ |
| H A D | debug.S | 30 mov r1, #8
35 mov r1, #4
40 mov r1, #2
42 add r3, r2, r1
43 mov r1, #0
44 stb r1, [r3]
45 1: and r1, r0, #15
47 csub.a r1, #10
49 add r1, r1, #'0' - 'a' + 10
50 2: add r1, r1, #'a' - 10
51 stb.w r1, [r3+], #-1
64 senduart r1, r3
66 cxor.a r1, #'\n'
67 cmoveq r1, #'\r'
71 ldb.w r1, [r0]+, #1
72 cxor.a r1, #0
79 mov r1, r0
|
| H A D | debug-macro.S | 55 @ We assume r1 and r2 can be clobbered.
58 mov r1, #0x80
59 str r1, [\rx, #UART_LCR_OFFSET]
60 and r1, r2, #0xff00
61 mov r1, r1, lsr #8
62 str r1, [\rx, #UART_DLH_OFFSET]
63 and r1, r2, #0xff
64 str r1, [\rx, #UART_DLL_OFFSET]
65 mov r1, #0x7
66 str r1, [\rx, #UART_FCR_OFFSET]
67 mov r1, #0x3
68 str r1, [\rx, #UART_LCR_OFFSET]
69 mov r1, #0x0
70 str r1, [\rx, #UART_IER_OFFSET]
|
| H A D | sleep.S | 40 ldw r1, =sleep_save_sp
41 stw r0, [r1]
69 mov r1, #0
70 movc p0.c5, r1, #14
82 ldw r1, =(PKUNITY_PM_BASE)
86 stw r6, [r1+], #0x18
89 stw r6, [r1+], #0x1c
93 stw r8, [r1+], #0xc
97 stw r5, [r1+], #0x10
123 stw r6, [r1]
130 1: ldw r6, [r1+], #0x44
139 2: stw r7, [r1+], #0x4
141 stw r8, [r1]
170 mov r1, #0
171 movc p0.c6, r1, #6 @ invalidate I & D TLBs
172 movc p0.c5, r1, #28 @ invalidate I & D caches, BTB
|
| H A D | entry.S | 71 ldw r1, [sp+], #\offset + S_PSR @ get calling asr
73 mov.a bsr, r1 @ save in bsr_priv
76 ldm.w (r1 - r15), [sp]+ @ get calling r1 - r15
147 mov r1, sp
149 @ routine called with r0 = irq number, r1 = struct pt_regs *
161 stm (r1 - r15), [sp]+
165 ldm (r1 - r3), [r0]+
169 stw.w r1, [sp+], #-4 @ save the "real" r0 copied
172 mov r1, lr
178 @ r1 - lr_priv
192 stm (r1 - r15), [sp+]
196 ldm (r1 - r3), [r0]+
200 stw r1, [sp] @ save the "real" r0 copied
234 stm (r1 - r15), [sp+]
235 add r1, sp, #S_R16
236 stm (r16 - r28, sp, lr), [r1]+
248 mov r1, asr
272 @ the fault status register in r1.
274 movc r1, p0.c3, #0 @ get FSR
318 mov r1, asr
339 @ r1 - pointer to registers on stack
342 mov r1, #5
415 cff r1, s31 @ get fpu FPSCR
416 andn r2, r1, #0x08000000
423 @ r1 holds the FPSCR value
435 @ the fault status register in r1.
437 movc r1, p0.c3, #0 @ get FSR
468 mov r1, asr
477 mov r1, #5
478 enable_irq r1 @ Enable interrupts
494 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
498 add ip, r1, #TI_CPU_SAVE
503 add ip, r1, #TI_FPSTATE
531 disable_irq r1 @ disable interrupts
532 ldw r1, [tsk+], #TI_FLAGS
533 cand.a r1, #_TIF_WORK_MASK
545 cand.a r1, #_TIF_NEED_RESCHED
549 cand.a r1, #_TIF_SIGPENDING @ delivering a signal?
561 disable_irq r1 @ disable interrupts
563 ldw r1, [tsk+], #TI_FLAGS
564 cand.a r1, #_TIF_WORK_MASK
633 add r1, sp, #S_OFF
643 add r1, sp, #S_OFF
649 add r1, sp, #S_R0 + S_OFF @ pointer to regs
652 ldm (r0 - r3), [r1]+ @ have to reload r0 - r3
658 mov r1, sp
|
| /linux-4.1.27/arch/tile/lib/ |
| H A D | usercopy_32.S | 23 * strnlen_user_asm takes the pointer in r0, and the length bound in r1.
28 { bz r1, 2f; addi r3, r0, -1 } /* bias down to include NUL */
29 1: { lb_u r4, r0; addi r1, r1, -1 }
31 { bnzt r1, 1b; addi r0, r0, 1 }
45 * the userspace source pointer in r1, and the length bound (including
51 1: { lb_u r4, r1; addi r1, r1, 1; addi r2, r2, -1 }
70 * number of bytes to zero in r1.
76 { bz r1, 2f; or r2, r0, r1 }
79 1: { sb r0, zero; addi r0, r0, 1; addi r1, r1, -1 }
80 bnzt r1, 1b
81 2: { move r0, r1; jrp lr }
88 1: { sw r0, zero; addi r0, r0, 4; addi r1, r1, -4 }
89 bnzt r1, 1b
90 2: { move r0, r1; jrp lr }
99 * number of bytes to flush in r1.
103 bz r1, 2f
104 { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
105 { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
106 { and r0, r0, r2; and r1, r1, r2 }
107 { sub r1, r1, r0 }
108 1: { flush r0; addi r1, r1, -CHIP_FLUSH_STRIDE() }
109 { addi r0, r0, CHIP_FLUSH_STRIDE(); bnzt r1, 1b }
110 2: { move r0, r1; jrp lr }
119 * number of bytes to flush-invalidate in r1.
123 bz r1, 2f
124 { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
125 { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
126 { and r0, r0, r2; and r1, r1, r2 }
127 { sub r1, r1, r0 }
128 1: { finv r0; addi r1, r1, -CHIP_FINV_STRIDE() }
129 { addi r0, r0, CHIP_FINV_STRIDE(); bnzt r1, 1b }
130 2: { move r0, r1; jrp lr }
|
| H A D | usercopy_64.S | 23 * strnlen_user_asm takes the pointer in r0, and the length bound in r1.
28 { beqz r1, 2f; addi r3, r0, -1 } /* bias down to include NUL */
29 1: { ld1u r4, r0; addi r1, r1, -1 }
31 { bnezt r1, 1b; addi r0, r0, 1 }
45 * the userspace source pointer in r1, and the length bound (including
51 1: { ld1u r4, r1; addi r1, r1, 1; addi r2, r2, -1 }
70 * number of bytes to zero in r1.
76 { beqz r1, 2f; or r2, r0, r1 }
79 1: { st1 r0, zero; addi r0, r0, 1; addi r1, r1, -1 }
80 bnezt r1, 1b
81 2: { move r0, r1; jrp lr }
88 1: { st r0, zero; addi r0, r0, 8; addi r1, r1, -8 }
89 bnezt r1, 1b
90 2: { move r0, r1; jrp lr }
99 * number of bytes to flush in r1.
103 beqz r1, 2f
104 { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
105 { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
106 { and r0, r0, r2; and r1, r1, r2 }
107 { sub r1, r1, r0 }
108 1: { flush r0; addi r1, r1, -CHIP_FLUSH_STRIDE() }
109 { addi r0, r0, CHIP_FLUSH_STRIDE(); bnezt r1, 1b }
110 2: { move r0, r1; jrp lr }
119 * number of bytes to flush-invalidate in r1.
123 beqz r1, 2f
124 { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
125 { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
126 { and r0, r0, r2; and r1, r1, r2 }
127 { sub r1, r1, r0 }
128 1: { finv r0; addi r1, r1, -CHIP_FINV_STRIDE() }
129 { addi r0, r0, CHIP_FINV_STRIDE(); bnezt r1, 1b }
130 2: { move r0, r1; jrp lr }
|
| H A D | memcpy_32.S | 46 * the user source in r1, and the bytes to copy in r2.
67 * the kernel source in r1, and the bytes to copy in r2.
88 /* r0 is the dest, r1 is the source, r2 is the size. */
91 { sw sp, lr; move r23, r0; or r4, r0, r1 }
97 { move r24, r1; move r25, r2 }
108 { andi r6, r1, 63; j .Lcopy_many }
118 EX: { lw r3, r1; addi r1, r1, 4; slti_u r8, r2, 16 }
119 EX: { lw r4, r1; addi r1, r1, 4 }
127 EX: { lw r3, r1; addi r1, r1, 4 }
144 /* Copy words until r1 is cache-line-aligned. */
146 EX: { lw r3, r1; addi r1, r1, 4 }
147 { andi r6, r1, 63 }
152 { addi r3, r1, 60; andi r9, r9, -64 }
169 * - r1 points to start of src line 0
171 * - r3 contains r1 + 128 + 60 [pointer to end of source line 2]
175 * - r5 contains *(r1 + 60) [i.e. last word of source line 0]
176 * - r6 contains *(r1 + 64 + 60) [i.e. last word of source line 1]
182 { jal .Lcopy_line2; add r15, r1, r2 }
186 EX: { move r12, r5; lw r16, r1 }
193 EX: { move r12, r6; lw r16, r1 }
200 EX: { move r12, r7; lw r16, r1 }
212 * - r1 points to the source line.
217 * - r17 == r1 + 16.
222 * - r1 is incremented by 64, unless that would point to a word
255 { add r15, r1, r2 }
257 { slt_u r13, r3, r15; addi r17, r1, 16 }
262 EX: { lw r17, r17; addi r1, r1, 48; mvz r3, r13, r1 } /* r17 = WORD_4 */
271 EX: { lw r4, r1; addi r1, r1, 4; addi r20, r1, 16 } /* r4 = WORD_12 */
272 EX: { lw r8, r1; addi r1, r1, 4; slt_u r13, r20, r15 }/* r8 = WORD_13 */
273 EX: { lw r11, r1; addi r1, r1, -52; mvz r20, r13, r1 } /* r11 = WORD_14 */
278 EX: { lw r13, r1; addi r1, r1, 4; move zero, r16 } /* r13 = WORD_1 */
279 EX: { lw r14, r1; addi r1, r1, 4 } /* r14 = WORD_2 */
280 EX: { lw r15, r1; addi r1, r1, 8; addi r10, r0, 60 } /* r15 = WORD_3 */
285 EX: { lw r19, r1; addi r1, r1, 4; move zero, r17 } /* r19 = WORD_5 */
293 EX: { lw r10, r1; addi r1, r1, 4 } /* r10 = WORD_6 */
294 EX: { lw r12, r1; addi r1, r1, 4 } /* r12 = WORD_7 */
297 EX: { lw r18, r1; addi r1, r1, 4 } /* r18 = WORD_8 */
310 EX: { lw r13, r1; addi r1, r1, 4; move zero, r18 } /* r13 = WORD_9 */
311 EX: { lw r14, r1; addi r1, r1, 4 } /* r14 = WORD_10 */
312 EX: { lw r15, r1; move r1, r20 } /* r15 = WORD_11 */
348 { bz r4, .Ldest_is_word_aligned; add r18, r1, r2 }
358 EX: { lb_u r3, r1; addi r1, r1, 1; addi r4, r4, -1 }
360 { bnzt r4, .Lalign_dest_loop; andi r3, r1, 3 }
367 EX: { andi r8, r0, 63; lwadd_na r6, r1, 4}
376 * - r1 points 4 bytes past the load address corresponding to r0.
381 EX: { lwadd_na r7, r1, 4; slti_u r8, r2, 4 + 4 }
383 { dword_align r6, r7, r1; slti_u r9, r2, 64 + 4 }
390 * - r1 points 4 bytes past the load address corresponding to r0.
407 { addi r3, r1, 63 - 4; addi r8, r1, 64 + 63 - 4 }
409 { mvz r3, r8, r1; addi r8, r3, 64 }
411 { mvz r3, r8, r1; movei r17, 0 }
415 { prefetch r3; addi r15, r1, 60; addi r3, r3, 64 }
419 EX: { mvz r3, r8, r1; wh64 r0 }
435 lwadd_na r7, r1, 16
437 EX: { lwadd_na r11, r1, 12 }
438 EX: { lwadd_na r14, r1, -24 }
439 EX: { lwadd_na r8, r1, 4 }
440 EX: { lwadd_na r9, r1, 4 }
442 lwadd_na r10, r1, 8
446 EX: { lwadd_na r12, r1, 4; addi r17, r17, 1 }
447 EX: { lwadd_na r13, r1, 8; dword_align r6, r7, r1 }
448 EX: { swadd r0, r6, 4; dword_align r7, r8, r1 }
449 EX: { swadd r0, r7, 4; dword_align r8, r9, r1 }
450 EX: { swadd r0, r8, 4; dword_align r9, r10, r1 }
451 EX: { swadd r0, r9, 4; dword_align r10, r11, r1 }
452 EX: { swadd r0, r10, 4; dword_align r11, r12, r1 }
453 EX: { swadd r0, r11, 4; dword_align r12, r13, r1 }
454 EX: { swadd r0, r12, 4; dword_align r13, r14, r1 }
462 * - r1 points 4 bytes past the load address corresponding to r0.
471 /* Move r1 back to the point where it corresponds to r0. */
472 { addi r1, r1, -4 }
483 EX: { lb_u r3, r1; addi r1, r1, 1 }
500 * r2 (num remaining) is correct, but r0 (dst) and r1 (src)
510 /* Add this to the original r0 and r1 to get their new values. */
511 { add r0, r23, r3; add r1, r24, r3 }
518 .Lcfu: { lb_u r3, r1; addi r1, r1, 1 }
533 { lb_u r3, r1; addi r1, r1, 1 }
544 { lb_u r3, r1; addi r1, r1, 1 }
|
| /linux-4.1.27/arch/m32r/mm/ |
| H A D | mmu.S | 31 st r1, @-sp
36 ld r1, @(MESTS_offset, r3) ; r1: status (MESTS reg.)
38 st r1, @(MESTS_offset, r3) ; clear status (MESTS reg.)
39 and3 r1, r1, #(MESTS_IT)
40 bnez r1, 1f ; instruction TLB miss?
45 ;; r1 - r3: free
48 ;; r1: TLB entry base address
56 ldi r1, #-8192
59 and r1, sp
60 ld r1, @(16, r1) ; current_thread_info->cpu
61 slli r1, #2
62 add r2, r1
64 seth r1, #high(DTLB_BASE)
65 or3 r1, r1, #low(DTLB_BASE)
74 ;; r1 - r3: free
77 ;; r1: TLB entry base address
82 mvfc r1, bpc
83 and r1, r3
84 or r0, r1 ; r0: PFN + ASID
89 ldi r1, #-8192
92 and r1, sp
93 ld r1, @(16, r1) ; current_thread_info->cpu
94 slli r1, #2
95 add r2, r1
97 seth r1, #high(ITLB_BASE)
98 or3 r1, r1, #low(ITLB_BASE)
105 ;; r1: TLB entry base address
110 ;; r1: TLB entry address
113 ld r3, @r2 || srli r1, #3
116 srli r1, #3
118 add r1, r3
123 st r3, @r2 || slli r1, #3
126 slli r1, #3
132 ;; r1: TLB entry address
136 ;; r1: TLB entry address
178 ;; r1: TLB entry address
181 st r0, @r1 ; set_tlb_tag(entry++, address);
182 st r2, @+r1 ; set_tlb_data(entry, pte_data);
188 ld r1, @sp+
197 ;; r1: TLB entry address
201 ;; r1: TLB entry address
215 st r1, @-sp
223 ld r1, @(MESTS_offset,r3) ; r1: status (MESTS reg.)
224 st r1, @(MESTS_offset,r3) ; clear status (MESTS reg.)
225 and3 r1, r1, #(MESTS_IT)
226 beqz r1, 1f ; data TLB miss?
234 seth r1, #high(ITLB_BASE)
235 or3 r1, r1, #low(ITLB_BASE)
236 add r2, r1 ; r2: entry
248 seth r1, #high(DTLB_BASE)
249 or3 r1, r1, #low(DTLB_BASE)
250 add r2, r1 ; r2: entry
258 ; r1,r3,r4: (free)
260 ld24 r1, #(-MPTB-1)
261 not r1, r1
262 ld r1, @r1
265 add r3, r1 ; r3: pgd
267 ld r1, @r3 ; r1: pmd
268 beqz r1, 3f ; pmd_none(*pmd) ?
270 and3 r1, r1, #0x3ff
272 bne r1, r4, 3f ; pmd_bad(*pmd) ?
286 ld r1, @r4 ; r1: pte_data
287 and3 r3, r1, #2 ; _PAGE_PRESENT(=2) check
292 ; r0: address, r1: pte_data, r2: entry
302 st r1, @(4,r2) ; set_tlb_data(entry, pte_data);
307 ld r1, @sp+
314 ldi r1, #2 ; r1: pte_data = 0 | _PAGE_PRESENT(=2)
325 ldi r1, #0
326 st r1, @(MPSZ_offset,r0) ; Set MPSZ Reg(Page size 4KB:0 16KB:1 64KB:2)
327 ldi r1, #0
328 st r1, @(MASID_offset,r0) ; Set ASID Zero
333 seth r1, #high(DTLB_BASE) ; Set DTLB_BASE higher
334 or3 r1, r1, #low(DTLB_BASE) ; Set DTLB_BASE lower
338 addi r1, #-4
342 st r2, @+r1 ; VPA <- 0
343 st r2, @+r1 ; PPA <- 0
|
| H A D | page.S | 28 ld r4, @r1+
29 ld r5, @r1+
30 ld r6, @r1+
31 ld r7, @r1+
38 ld r4, @r1+
40 ld r5, @r1+
41 ld r6, @r1+
42 ld r7, @r1+
|
| /linux-4.1.27/arch/sh/lib/ |
| H A D | memmove.S | 30 mov #12,r1
31 cmp/gt r6,r1
44 mov r4,r1
46 and r2,r1
47 shll2 r1
50 add r1,r0
51 mov.l @r0,r1
52 jmp @r1
62 8: mov.b @r0+,r1
65 mov.b r1,@(r0,r4)
89 mov.b @r0+,r1
91 mov.b r1,@(r0,r4)
96 3: mov.l @r0+,r1
99 mov.l r1,@(r0,r4)
122 mov.b @r0+,r1
124 mov.b r1,@(r0,r4)
128 mov.l @(r0,r4),r1
133 shll8 r1
134 3: mov r1,r3 ! JIHG
136 mov.l @r0+,r1 ! NMLK
137 mov r1,r2
145 shlr8 r1
146 3: mov r1,r3 ! GHIJ
148 mov.l @r0+,r1 ! KLMN
149 mov r1,r2
175 mov.b @r0+,r1
176 mov.b r1,@(r0,r4)
182 3: mov.w @r0+,r1
185 mov.w r1,@(r0,r4)
192 mov.b @r0,r1
193 mov.b r1,@(r0,r4)
210 mov.b @r0+,r1
212 mov.b r1,@(r0,r4)
215 mov.l @(r0,r4),r1
220 shll16 r1
221 shll8 r1
222 3: mov r1,r3 ! JIHG
225 mov.l @r0+,r1 ! NMLK
226 mov r1,r2
233 shlr16 r1
234 shlr8 r1
235 3: mov r1,r3 ! GHIJ
238 mov.l @r0+,r1 ! KLMN
239 mov r1,r2
|
| H A D | memcpy.S | 21 mov #12,r1
22 cmp/gt r6,r1
34 mov r5,r1
36 and r2,r1
37 shll2 r1
40 add r1,r0
41 mov.l @r0,r1
42 jmp @r1
56 mov.b @(r0,r5),r1
58 mov.b r1,@-r0
75 mov.b @(r0,r5),r1
77 mov.b r1,@-r0
83 3: mov.l @(r0,r5),r1
86 mov.l r1,@-r0
106 mov.b @(r0,r5),r1
108 mov.b r1,@-r0
111 mov.l @(r0,r5),r1
117 3: mov r1,r3 ! RQPO
120 mov.l @(r0,r5),r1 ! NMLK
121 mov r1,r6
128 3: mov r1,r3 ! OPQR
131 mov.l @(r0,r5),r1 ! KLMN
132 mov r1,r6
155 mov.b @(r0,r5),r1
156 mov.b r1,@-r0
163 3: mov.w @(r0,r5),r1
166 mov.w r1,@-r0
172 mov.b @(r0,r5),r1
174 mov.b r1,@-r0
187 mov.b @(r0,r5),r1
189 mov.b r1,@-r0
193 mov.l @(r0,r5),r1
199 3: mov r1,r3 ! RQPO
201 mov.l @(r0,r5),r1 ! NMLK
202 mov r1,r6
210 3: mov r1,r3 ! OPQR
212 mov.l @(r0,r5),r1 ! KLMN
213 mov r1,r6
|
| H A D | checksum.S | 90 mov r5, r1
92 shld r0, r1
93 tst r1, r1
115 dt r1
118 ! here, we know r1==0
119 addc r1, r6 ! add carry to r6
126 mov r0, r1
127 shlr2 r1
133 dt r1
137 addc r1, r6 ! r1==0 here, so it means add carry-bit
144 mov #2, r1
145 cmp/hs r1, r5
149 cmp/eq r1, r5
221 mov r4,r1
222 and r0,r1
224 cmp/eq r1,r0
249 SRC( mov.b @r4+,r1 )
251 extu.b r1,r1
252 DST( mov.b r1,@r5 )
260 shll8 r1
262 or r1,r0
299 SRC( mov.l @r4+,r1 )
302 DST( mov.l r1,@(4,r5) )
303 addc r1,r7
306 SRC( mov.l @r4+,r1 )
309 DST( mov.l r1,@(12,r5) )
310 addc r1,r7
313 SRC( mov.l @r4+,r1 )
316 DST( mov.l r1,@(20,r5) )
317 addc r1,r7
320 SRC( mov.l @r4+,r1 )
323 DST( mov.l r1,@(28,r5) )
324 addc r1,r7
356 mov #2,r1
357 cmp/hs r1,r6
363 cmp/eq r1,r6
386 mov #-EFAULT,r1
387 mov.l r1,@r0
406 mov #-EFAULT,r1
407 mov.l r1,@r0
|
| H A D | copy_page.S | 20 * r0, r1, r2, r3, r4, r5, r6, r7 --- scratch
39 mov.l @r11+,r1
58 mov.l r1,@-r10
104 EX( mov.b @r5+,r1 )
107 EX( mov.b r1,@r4 )
112 2: mov #3,r1
114 and r4,r1
116 shll2 r1
118 mov.l @(r0,r1),r1
119 jmp @r1
154 mov.l 8000f,r1
156 jmp @r1
183 EX( mov.l @r5+,r1 )
185 EX( mov.l r1,@r4 )
191 EX( mov.l @r5+,r1 )
204 EX( mov.l r1,@(4,r4) )
221 EX( mov.l @r5+,r1 )
223 EX( mov.l r1,@r4 )
244 EX( mov.l @r5+,r1 )
250 xtrct r1,r0
251 xtrct r8,r1
256 EX( mov.l r1,@(4,r4) )
260 EX( mov.l @r5+,r1 )
263 xtrct r1,r10
264 xtrct r8,r1
268 EX( mov.l r1,@(20,r4) )
377 mov.l 8000f,r1
379 jmp @r1
|
| H A D | udivsi3_i4i.S | 63 mov.w c128_w, r1
67 cmp/hi r1,r5
68 extu.w r5,r1
70 cmp/eq r5,r1
73 mov r5,r1
77 mov.l r1,@-r15
86 mov.b @(r0,r5),r1
90 mov.b @(r0,r5),r1
94 mov.l @(r0,r1),r1
98 dmulu.l r1,r4
99 mov.b @(r0,r5),r1
109 shld r1,r0
126 mov r5,r1
131 mov.l r1,@-r15
134 mov.l zero_l,r1
138 mov.l r1,@-r15
140 mov.w m256_w,r1
144 and r1,r0
160 mov r0,r1
161 div1 r5,r1
165 div1 r5,r1
167 rotcl r0; div1 r5,r1
171 div1 r4,r1
183 but we effectively clobber only r1. */
187 mov.w c128_w, r1
193 cmp/hi r1,r5
209 mov.l zero_l,r1
212 mov.l r1,@-r15
238 mov.b @(r0,r5),r1
241 mov.l @(r0,r1),r1
243 dmulu.l r1,r4
244 mov.b @(r0,r5),r1
251 shld r1,r0
258 cmp/hi r1,r5
269 mov.l zero_l,r1
272 mov.l r1,@-r15
288 extu.b r0,r1
290 or r4,r1
293 rotcl r1
295 neg r1,r0
301 mov.l zero_l,r1
305 mov.l r1,@-r15
307 mov.w m256_w,r1
311 and r1,r0
321 mov r4,r1
322 shll8 r1
325 rotcl r1; div1 r5,r0
328 rotcl r1
|
| H A D | udiv_qrnnd.S | 41 /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */
52 extu.w r0,r1
55 0: rotcl r1
56 mulu.w r1,r5
64 add #-1,r1
66 1: add #-1,r1
72 swap.w r4,r1
73 xtrct r0,r1
75 mov r1,r0
77 mov #-1,r1
79 shlr16 r1
|
| H A D | mcount.S | 49 /* r1 = sp & (THREAD_SIZE - 1) */ \
50 mov #-1, r1; \
51 add r0, r1; \
52 and r15, r1; \
60 cmp/hi r2, r1; \
64 mov.l .L_ebss, r1; \
65 cmp/hi r1, r15; \
69 mov.l .L_init_thread_union, r1; \
70 cmp/hs r1, r15; \
74 add r0, r1; \
75 cmp/hs r1, r15; \
206 mov.l 2f, r1
207 jmp @r1
236 mov.l r1, @-r15
249 mov.l @r15+, r1
|
| /linux-4.1.27/crypto/ |
| H A D | serpent_generic.c | 237 u32 r0, r1, r2, r3, r4; __serpent_setkey() local
252 r1 = le32_to_cpu(k[4]); __serpent_setkey()
258 keyiter(le32_to_cpu(k[1]), r1, r0, r3, 1, 1); __serpent_setkey() local
259 keyiter(le32_to_cpu(k[2]), r2, r1, r4, 2, 2); __serpent_setkey() local
261 keyiter(le32_to_cpu(k[4]), r4, r3, r1, 4, 4); __serpent_setkey() local
263 keyiter(le32_to_cpu(k[6]), r1, r0, r3, 6, 6); __serpent_setkey() local
264 keyiter(le32_to_cpu(k[7]), r2, r1, r4, 7, 7); __serpent_setkey() local
267 keyiter(k[1], r4, r3, r1, 9, 9); __serpent_setkey()
269 keyiter(k[3], r1, r0, r3, 11, 11); __serpent_setkey()
270 keyiter(k[4], r2, r1, r4, 12, 12); __serpent_setkey()
272 keyiter(k[6], r4, r3, r1, 14, 14); __serpent_setkey()
274 keyiter(k[8], r1, r0, r3, 16, 16); __serpent_setkey()
275 keyiter(k[9], r2, r1, r4, 17, 17); __serpent_setkey()
277 keyiter(k[11], r4, r3, r1, 19, 19); __serpent_setkey()
279 keyiter(k[13], r1, r0, r3, 21, 21); __serpent_setkey()
280 keyiter(k[14], r2, r1, r4, 22, 22); __serpent_setkey()
282 keyiter(k[16], r4, r3, r1, 24, 24); __serpent_setkey()
284 keyiter(k[18], r1, r0, r3, 26, 26); __serpent_setkey()
285 keyiter(k[19], r2, r1, r4, 27, 27); __serpent_setkey()
287 keyiter(k[21], r4, r3, r1, 29, 29); __serpent_setkey()
289 keyiter(k[23], r1, r0, r3, 31, 31); __serpent_setkey()
293 keyiter(k[-26], r2, r1, r4, 32, -18); __serpent_setkey()
295 keyiter(k[-24], r4, r3, r1, 34, -16); __serpent_setkey()
297 keyiter(k[-22], r1, r0, r3, 36, -14); __serpent_setkey()
298 keyiter(k[-21], r2, r1, r4, 37, -13); __serpent_setkey()
300 keyiter(k[-19], r4, r3, r1, 39, -11); __serpent_setkey()
302 keyiter(k[-17], r1, r0, r3, 41, -9); __serpent_setkey()
303 keyiter(k[-16], r2, r1, r4, 42, -8); __serpent_setkey()
305 keyiter(k[-14], r4, r3, r1, 44, -6); __serpent_setkey()
307 keyiter(k[-12], r1, r0, r3, 46, -4); __serpent_setkey()
308 keyiter(k[-11], r2, r1, r4, 47, -3); __serpent_setkey()
310 keyiter(k[-9], r4, r3, r1, 49, -1); __serpent_setkey()
312 keyiter(k[-7], r1, r0, r3, 51, 1); __serpent_setkey()
313 keyiter(k[-6], r2, r1, r4, 52, 2); __serpent_setkey()
315 keyiter(k[-4], r4, r3, r1, 54, 4); __serpent_setkey()
317 keyiter(k[-2], r1, r0, r3, 56, 6); __serpent_setkey()
318 keyiter(k[-1], r2, r1, r4, 57, 7); __serpent_setkey()
320 keyiter(k[1], r4, r3, r1, 59, 9); __serpent_setkey()
322 keyiter(k[3], r1, r0, r3, 61, 11); __serpent_setkey()
323 keyiter(k[4], r2, r1, r4, 62, 12); __serpent_setkey()
325 keyiter(k[6], r4, r3, r1, 64, 14); __serpent_setkey()
327 keyiter(k[8], r1, r0, r3, 66, 16); __serpent_setkey()
328 keyiter(k[9], r2, r1, r4, 67, 17); __serpent_setkey()
330 keyiter(k[11], r4, r3, r1, 69, 19); __serpent_setkey()
332 keyiter(k[13], r1, r0, r3, 71, 21); __serpent_setkey()
333 keyiter(k[14], r2, r1, r4, 72, 22); __serpent_setkey()
335 keyiter(k[16], r4, r3, r1, 74, 24); __serpent_setkey()
337 keyiter(k[18], r1, r0, r3, 76, 26); __serpent_setkey()
338 keyiter(k[19], r2, r1, r4, 77, 27); __serpent_setkey()
340 keyiter(k[21], r4, r3, r1, 79, 29); __serpent_setkey()
342 keyiter(k[23], r1, r0, r3, 81, 31); __serpent_setkey()
346 keyiter(k[-26], r2, r1, r4, 82, -18); __serpent_setkey()
348 keyiter(k[-24], r4, r3, r1, 84, -16); __serpent_setkey()
350 keyiter(k[-22], r1, r0, r3, 86, -14); __serpent_setkey()
351 keyiter(k[-21], r2, r1, r4, 87, -13); __serpent_setkey()
353 keyiter(k[-19], r4, r3, r1, 89, -11); __serpent_setkey()
355 keyiter(k[-17], r1, r0, r3, 91, -9); __serpent_setkey()
356 keyiter(k[-16], r2, r1, r4, 92, -8); __serpent_setkey()
358 keyiter(k[-14], r4, r3, r1, 94, -6); __serpent_setkey()
360 keyiter(k[-12], r1, r0, r3, 96, -4); __serpent_setkey()
361 keyiter(k[-11], r2, r1, r4, 97, -3); __serpent_setkey()
363 keyiter(k[-9], r4, r3, r1, 99, -1); __serpent_setkey()
365 keyiter(k[-7], r1, r0, r3, 101, 1); __serpent_setkey()
366 keyiter(k[-6], r2, r1, r4, 102, 2); __serpent_setkey()
368 keyiter(k[-4], r4, r3, r1, 104, 4); __serpent_setkey()
370 keyiter(k[-2], r1, r0, r3, 106, 6); __serpent_setkey()
371 keyiter(k[-1], r2, r1, r4, 107, 7); __serpent_setkey()
373 keyiter(k[1], r4, r3, r1, 109, 9); __serpent_setkey()
375 keyiter(k[3], r1, r0, r3, 111, 11); __serpent_setkey()
376 keyiter(k[4], r2, r1, r4, 112, 12); __serpent_setkey()
378 keyiter(k[6], r4, r3, r1, 114, 14); __serpent_setkey()
380 keyiter(k[8], r1, r0, r3, 116, 16); __serpent_setkey()
381 keyiter(k[9], r2, r1, r4, 117, 17); __serpent_setkey()
383 keyiter(k[11], r4, r3, r1, 119, 19); __serpent_setkey()
385 keyiter(k[13], r1, r0, r3, 121, 21); __serpent_setkey()
386 keyiter(k[14], r2, r1, r4, 122, 22); __serpent_setkey()
388 keyiter(k[16], r4, r3, r1, 124, 24); __serpent_setkey()
390 keyiter(k[18], r1, r0, r3, 126, 26); __serpent_setkey()
391 keyiter(k[19], r2, r1, r4, 127, 27); __serpent_setkey()
393 keyiter(k[21], r4, r3, r1, 129, 29); __serpent_setkey()
395 keyiter(k[23], r1, r0, r3, 131, 31); __serpent_setkey()
399 S3(r3, r4, r0, r1, r2); store_and_load_keys(r1, r2, r4, r3, 28, 24); __serpent_setkey()
400 S4(r1, r2, r4, r3, r0); store_and_load_keys(r2, r4, r3, r0, 24, 20); __serpent_setkey()
401 S5(r2, r4, r3, r0, r1); store_and_load_keys(r1, r2, r4, r0, 20, 16); __serpent_setkey()
402 S6(r1, r2, r4, r0, r3); store_and_load_keys(r4, r3, r2, r0, 16, 12); __serpent_setkey()
403 S7(r4, r3, r2, r0, r1); store_and_load_keys(r1, r2, r0, r4, 12, 8); __serpent_setkey()
404 S0(r1, r2, r0, r4, r3); store_and_load_keys(r0, r2, r4, r1, 8, 4); __serpent_setkey()
405 S1(r0, r2, r4, r1, r3); store_and_load_keys(r3, r4, r1, r0, 4, 0); __serpent_setkey()
406 S2(r3, r4, r1, r0, r2); store_and_load_keys(r2, r4, r3, r0, 0, -4); __serpent_setkey()
407 S3(r2, r4, r3, r0, r1); store_and_load_keys(r0, r1, r4, r2, -4, -8); __serpent_setkey()
408 S4(r0, r1, r4, r2, r3); store_and_load_keys(r1, r4, r2, r3, -8, -12); __serpent_setkey()
409 S5(r1, r4, r2, r3, r0); store_and_load_keys(r0, r1, r4, r3, -12, -16); __serpent_setkey()
410 S6(r0, r1, r4, r3, r2); store_and_load_keys(r4, r2, r1, r3, -16, -20); __serpent_setkey()
411 S7(r4, r2, r1, r3, r0); store_and_load_keys(r0, r1, r3, r4, -20, -24); __serpent_setkey()
412 S0(r0, r1, r3, r4, r2); store_and_load_keys(r3, r1, r4, r0, -24, -28); __serpent_setkey()
414 S1(r3, r1, r4, r0, r2); store_and_load_keys(r2, r4, r0, r3, 22, 18); __serpent_setkey()
415 S2(r2, r4, r0, r3, r1); store_and_load_keys(r1, r4, r2, r3, 18, 14); __serpent_setkey()
416 S3(r1, r4, r2, r3, r0); store_and_load_keys(r3, r0, r4, r1, 14, 10); __serpent_setkey()
417 S4(r3, r0, r4, r1, r2); store_and_load_keys(r0, r4, r1, r2, 10, 6); __serpent_setkey()
418 S5(r0, r4, r1, r2, r3); store_and_load_keys(r3, r0, r4, r2, 6, 2); __serpent_setkey()
419 S6(r3, r0, r4, r2, r1); store_and_load_keys(r4, r1, r0, r2, 2, -2); __serpent_setkey()
420 S7(r4, r1, r0, r2, r3); store_and_load_keys(r3, r0, r2, r4, -2, -6); __serpent_setkey()
421 S0(r3, r0, r2, r4, r1); store_and_load_keys(r2, r0, r4, r3, -6, -10); __serpent_setkey()
422 S1(r2, r0, r4, r3, r1); store_and_load_keys(r1, r4, r3, r2, -10, -14); __serpent_setkey()
423 S2(r1, r4, r3, r2, r0); store_and_load_keys(r0, r4, r1, r2, -14, -18); __serpent_setkey()
424 S3(r0, r4, r1, r2, r3); store_and_load_keys(r2, r3, r4, r0, -18, -22); __serpent_setkey()
426 S4(r2, r3, r4, r0, r1); store_and_load_keys(r3, r4, r0, r1, 28, 24); __serpent_setkey()
427 S5(r3, r4, r0, r1, r2); store_and_load_keys(r2, r3, r4, r1, 24, 20); __serpent_setkey()
428 S6(r2, r3, r4, r1, r0); store_and_load_keys(r4, r0, r3, r1, 20, 16); __serpent_setkey()
429 S7(r4, r0, r3, r1, r2); store_and_load_keys(r2, r3, r1, r4, 16, 12); __serpent_setkey()
430 S0(r2, r3, r1, r4, r0); store_and_load_keys(r1, r3, r4, r2, 12, 8); __serpent_setkey()
431 S1(r1, r3, r4, r2, r0); store_and_load_keys(r0, r4, r2, r1, 8, 4); __serpent_setkey()
432 S2(r0, r4, r2, r1, r3); store_and_load_keys(r3, r4, r0, r1, 4, 0); __serpent_setkey()
433 S3(r3, r4, r0, r1, r2); storekeys(r1, r2, r4, r3, 0); __serpent_setkey()
450 u32 r0, r1, r2, r3, r4; __serpent_encrypt() local
458 r1 = le32_to_cpu(s[1]); __serpent_encrypt()
462 K(r0, r1, r2, r3, 0); __serpent_encrypt()
463 S0(r0, r1, r2, r3, r4); LK(r2, r1, r3, r0, r4, 1); __serpent_encrypt()
464 S1(r2, r1, r3, r0, r4); LK(r4, r3, r0, r2, r1, 2); __serpent_encrypt()
465 S2(r4, r3, r0, r2, r1); LK(r1, r3, r4, r2, r0, 3); __serpent_encrypt()
466 S3(r1, r3, r4, r2, r0); LK(r2, r0, r3, r1, r4, 4); __serpent_encrypt()
467 S4(r2, r0, r3, r1, r4); LK(r0, r3, r1, r4, r2, 5); __serpent_encrypt()
468 S5(r0, r3, r1, r4, r2); LK(r2, r0, r3, r4, r1, 6); __serpent_encrypt()
469 S6(r2, r0, r3, r4, r1); LK(r3, r1, r0, r4, r2, 7); __serpent_encrypt()
470 S7(r3, r1, r0, r4, r2); LK(r2, r0, r4, r3, r1, 8); __serpent_encrypt()
471 S0(r2, r0, r4, r3, r1); LK(r4, r0, r3, r2, r1, 9); __serpent_encrypt()
472 S1(r4, r0, r3, r2, r1); LK(r1, r3, r2, r4, r0, 10); __serpent_encrypt()
473 S2(r1, r3, r2, r4, r0); LK(r0, r3, r1, r4, r2, 11); __serpent_encrypt()
474 S3(r0, r3, r1, r4, r2); LK(r4, r2, r3, r0, r1, 12); __serpent_encrypt()
475 S4(r4, r2, r3, r0, r1); LK(r2, r3, r0, r1, r4, 13); __serpent_encrypt()
476 S5(r2, r3, r0, r1, r4); LK(r4, r2, r3, r1, r0, 14); __serpent_encrypt()
477 S6(r4, r2, r3, r1, r0); LK(r3, r0, r2, r1, r4, 15); __serpent_encrypt()
478 S7(r3, r0, r2, r1, r4); LK(r4, r2, r1, r3, r0, 16); __serpent_encrypt()
479 S0(r4, r2, r1, r3, r0); LK(r1, r2, r3, r4, r0, 17); __serpent_encrypt()
480 S1(r1, r2, r3, r4, r0); LK(r0, r3, r4, r1, r2, 18); __serpent_encrypt()
481 S2(r0, r3, r4, r1, r2); LK(r2, r3, r0, r1, r4, 19); __serpent_encrypt()
482 S3(r2, r3, r0, r1, r4); LK(r1, r4, r3, r2, r0, 20); __serpent_encrypt()
483 S4(r1, r4, r3, r2, r0); LK(r4, r3, r2, r0, r1, 21); __serpent_encrypt()
484 S5(r4, r3, r2, r0, r1); LK(r1, r4, r3, r0, r2, 22); __serpent_encrypt()
485 S6(r1, r4, r3, r0, r2); LK(r3, r2, r4, r0, r1, 23); __serpent_encrypt()
486 S7(r3, r2, r4, r0, r1); LK(r1, r4, r0, r3, r2, 24); __serpent_encrypt()
487 S0(r1, r4, r0, r3, r2); LK(r0, r4, r3, r1, r2, 25); __serpent_encrypt()
488 S1(r0, r4, r3, r1, r2); LK(r2, r3, r1, r0, r4, 26); __serpent_encrypt()
489 S2(r2, r3, r1, r0, r4); LK(r4, r3, r2, r0, r1, 27); __serpent_encrypt()
490 S3(r4, r3, r2, r0, r1); LK(r0, r1, r3, r4, r2, 28); __serpent_encrypt()
491 S4(r0, r1, r3, r4, r2); LK(r1, r3, r4, r2, r0, 29); __serpent_encrypt()
492 S5(r1, r3, r4, r2, r0); LK(r0, r1, r3, r2, r4, 30); __serpent_encrypt()
493 S6(r0, r1, r3, r2, r4); LK(r3, r4, r1, r2, r0, 31); __serpent_encrypt()
494 S7(r3, r4, r1, r2, r0); K(r0, r1, r2, r3, 32); __serpent_encrypt()
497 d[1] = cpu_to_le32(r1); __serpent_encrypt()
515 u32 r0, r1, r2, r3, r4; __serpent_decrypt() local
518 r1 = le32_to_cpu(s[1]); __serpent_decrypt()
522 K(r0, r1, r2, r3, 32); __serpent_decrypt()
523 SI7(r0, r1, r2, r3, r4); KL(r1, r3, r0, r4, r2, 31); __serpent_decrypt()
524 SI6(r1, r3, r0, r4, r2); KL(r0, r2, r4, r1, r3, 30); __serpent_decrypt()
525 SI5(r0, r2, r4, r1, r3); KL(r2, r3, r0, r4, r1, 29); __serpent_decrypt()
526 SI4(r2, r3, r0, r4, r1); KL(r2, r0, r1, r4, r3, 28); __serpent_decrypt()
527 SI3(r2, r0, r1, r4, r3); KL(r1, r2, r3, r4, r0, 27); __serpent_decrypt()
528 SI2(r1, r2, r3, r4, r0); KL(r2, r0, r4, r3, r1, 26); __serpent_decrypt()
529 SI1(r2, r0, r4, r3, r1); KL(r1, r0, r4, r3, r2, 25); __serpent_decrypt()
530 SI0(r1, r0, r4, r3, r2); KL(r4, r2, r0, r1, r3, 24); __serpent_decrypt()
531 SI7(r4, r2, r0, r1, r3); KL(r2, r1, r4, r3, r0, 23); __serpent_decrypt()
532 SI6(r2, r1, r4, r3, r0); KL(r4, r0, r3, r2, r1, 22); __serpent_decrypt()
533 SI5(r4, r0, r3, r2, r1); KL(r0, r1, r4, r3, r2, 21); __serpent_decrypt()
534 SI4(r0, r1, r4, r3, r2); KL(r0, r4, r2, r3, r1, 20); __serpent_decrypt()
535 SI3(r0, r4, r2, r3, r1); KL(r2, r0, r1, r3, r4, 19); __serpent_decrypt()
536 SI2(r2, r0, r1, r3, r4); KL(r0, r4, r3, r1, r2, 18); __serpent_decrypt()
537 SI1(r0, r4, r3, r1, r2); KL(r2, r4, r3, r1, r0, 17); __serpent_decrypt()
538 SI0(r2, r4, r3, r1, r0); KL(r3, r0, r4, r2, r1, 16); __serpent_decrypt()
539 SI7(r3, r0, r4, r2, r1); KL(r0, r2, r3, r1, r4, 15); __serpent_decrypt()
540 SI6(r0, r2, r3, r1, r4); KL(r3, r4, r1, r0, r2, 14); __serpent_decrypt()
541 SI5(r3, r4, r1, r0, r2); KL(r4, r2, r3, r1, r0, 13); __serpent_decrypt()
542 SI4(r4, r2, r3, r1, r0); KL(r4, r3, r0, r1, r2, 12); __serpent_decrypt()
543 SI3(r4, r3, r0, r1, r2); KL(r0, r4, r2, r1, r3, 11); __serpent_decrypt()
544 SI2(r0, r4, r2, r1, r3); KL(r4, r3, r1, r2, r0, 10); __serpent_decrypt()
545 SI1(r4, r3, r1, r2, r0); KL(r0, r3, r1, r2, r4, 9); __serpent_decrypt()
546 SI0(r0, r3, r1, r2, r4); KL(r1, r4, r3, r0, r2, 8); __serpent_decrypt()
547 SI7(r1, r4, r3, r0, r2); KL(r4, r0, r1, r2, r3, 7); __serpent_decrypt()
548 SI6(r4, r0, r1, r2, r3); KL(r1, r3, r2, r4, r0, 6); __serpent_decrypt()
549 SI5(r1, r3, r2, r4, r0); KL(r3, r0, r1, r2, r4, 5); __serpent_decrypt()
550 SI4(r3, r0, r1, r2, r4); KL(r3, r1, r4, r2, r0, 4); __serpent_decrypt()
551 SI3(r3, r1, r4, r2, r0); KL(r4, r3, r0, r2, r1, 3); __serpent_decrypt()
552 SI2(r4, r3, r0, r2, r1); KL(r3, r1, r2, r0, r4, 2); __serpent_decrypt()
553 SI1(r3, r1, r2, r0, r4); KL(r4, r1, r2, r0, r3, 1); __serpent_decrypt()
554 SI0(r4, r1, r2, r0, r3); K(r2, r3, r1, r4, 0); __serpent_decrypt()
558 d[2] = cpu_to_le32(r1); __serpent_decrypt()
|
| /linux-4.1.27/arch/arm/lib/ |
| H A D | bitops.h | 8 ands ip, r1, #3 variable
9 strneb r1, [ip] @ assert word-aligned variable
13 add r1, r1, r0, lsl #2 @ Get word offset variable
16 ALT_SMP(W(pldw) [r1])
20 1: ldrex r2, [r1]
22 strex r0, r2, [r1]
33 ands ip, r1, #3 variable
34 strneb r1, [ip] @ assert word-aligned variable
38 add r1, r1, r0, lsl #2 @ Get word offset variable
43 ALT_SMP(W(pldw) [r1])
46 1: ldrex r2, [r1]
49 strex ip, r2, [r1]
63 ands ip, r1, #3
64 strneb r1, [ip] @ assert word-aligned
70 ldr r2, [r1, r0, lsl #2]
72 str r2, [r1, r0, lsl #2]
90 ands ip, r1, #3
91 strneb r1, [ip] @ assert word-aligned
95 ldr r2, [r1, r0, lsl #2]!
99 \store r2, [r1]
|
| H A D | io-writesw-armv4.S | 25 .Loutsw_align: movs ip, r1, lsl #31
28 ldrh r3, [r1], #2
35 ands r3, r1, #3
43 .Loutsw_8_lp: ldmia r1!, {r3, r4, r5, ip}
54 ldmia r1!, {r3, ip}
61 ldr r3, [r1], #4
64 .Lno_outsw_2: ldrneh r3, [r1]
78 ARM( ldr r3, [r1, -r3]! )
80 THUMB( ldr r3, [r1, r3] )
81 THUMB( sub r1, r3 )
90 ldr r3, [r1, #4]!
|
| H A D | copy_page.S | 29 PLD( pld [r1, #0] )
30 PLD( pld [r1, #L1_CACHE_BYTES] )
32 ldmia r1!, {r3, r4, ip, lr} @ 4+1
33 1: PLD( pld [r1, #2 * L1_CACHE_BYTES])
34 PLD( pld [r1, #3 * L1_CACHE_BYTES])
38 ldmia r1!, {r3, r4, ip, lr} @ 4
42 ldmgtia r1!, {r3, r4, ip, lr} @ 4
44 PLD( ldmeqia r1!, {r3, r4, ip, lr} )
|
| H A D | io-readsw-armv4.S | 21 .Linsw_align: movs ip, r1, lsl #31
25 strh ip, [r1], #2
30 tst r1, #3
55 stmia r1!, {r3 - r5, ip}
69 stmia r1!, {r3, r4}
77 str r3, [r1], #4
80 strneh r3, [r1]
97 ldrccb ip, [r1, #-1]!
103 strb ip, [r1], #1
116 str ip, [r1], #4
123 strb ip, [r1], #1
126 strneb ip, [r1], #1
129 strneb ip, [r1]
|
| H A D | csumpartialcopyuser.S | 21 stmfd sp!, {r1, r2, r4 - r8, lr}
25 ldmfd sp!, {r1, r2, r4 - r8, pc}
56 * r0 = src, r1 = dst, r2 = len, r3 = sum, [sp] = *err_ptr
76 ldmia sp, {r1, r2} @ retrieve dst, len
77 add r2, r2, r1
79 9002: teq r2, r1
80 strneb r0, [r1], #1
|
| H A D | lib1funcs.S | 212 subs r2, r1, #1
215 cmp r0, r1
217 tst r1, r2
220 ARM_DIV_BODY r0, r1, r2, r3
229 12: ARM_DIV2_ORDER r1, r2
241 subs r2, r1, #1 @ compare divisor with 1
243 cmpne r0, r1 @ compare dividend with divisor
245 tsthi r1, r2 @ see if divisor is power of 2
249 ARM_MOD_BODY r0, r1, r2, r3
260 cmp r1, #0
261 eor ip, r0, r1 @ save the sign of the result.
263 rsbmi r1, r1, #0 @ loops below use unsigned.
264 subs r2, r1, #1 @ division by 1 or -1 ?
268 cmp r3, r1
270 tst r1, r2 @ divisor is power of 2 ?
273 ARM_DIV_BODY r3, r1, r0, r2
288 12: ARM_DIV2_ORDER r1, r2
302 cmp r1, #0
304 rsbmi r1, r1, #0 @ loops below use unsigned.
307 subs r2, r1, #1 @ compare divisor with 1
308 cmpne r0, r1 @ compare dividend with divisor
310 tsthi r1, r2 @ see if divisor is power of 2
314 ARM_MOD_BODY r0, r1, r2, r3
327 UNWIND(.save {r0, r1, ip, lr} )
329 stmfd sp!, {r0, r1, ip, lr}
331 ldmfd sp!, {r1, r2, ip, lr}
333 sub r1, r1, r3
341 UNWIND(.save {r0, r1, ip, lr} )
342 stmfd sp!, {r0, r1, ip, lr}
344 ldmfd sp!, {r1, r2, ip, lr}
346 sub r1, r1, r3
|
| H A D | backtrace.S | 35 tst r1, #0x10 @ 26 or 32-bit mode?
43 adr r1, 1b
44 sub offset, r0, r1
76 ldr r1, [frame, #-4] @ get saved lr
78 bic r1, r1, mask @ mask PC/LR for the mode
81 ldr r1, [sv_pc, #-4] @ if stmfd sp!, {args} exists,
83 teq r3, r1, lsr #11
88 1004: ldr r1, [sv_pc, #0] @ if stmfd sp!, {..., fp, ip, lr, pc}
90 teq r3, r1, lsr #11
102 mov r1, frame
121 mov instr, r1
135 mov r1, reg
|
| H A D | getuser.S | 19 * r1 contains the address limit, which must be preserved
36 check_uaccess r0, 1, r1, r2, __get_user_bad
43 check_uaccess r0, 2, r1, r2, __get_user_bad
63 check_uaccess r0, 4, r1, r2, __get_user_bad
70 check_uaccess r0, 8, r1, r2, __get_user_bad
84 check_uaccess r0, 8, r1, r2, __get_user_bad
96 check_uaccess r0, 1, r1, r2, __get_user_bad8
103 check_uaccess r0, 2, r1, r2, __get_user_bad8
119 check_uaccess r0, 4, r1, r2, __get_user_bad8
|
| H A D | csumpartialcopy.S | 16 * Params : r0 = src, r1 = dst, r2 = len, r3 = checksum
21 stmfd sp!, {r1, r4 - r8, lr}
25 ldmfd sp!, {r1, r4 - r8, pc}
|
| H A D | ecard.S | 26 mov r11, r1
27 mov r1, r0
42 add pc, r1, #8
|
| /linux-4.1.27/arch/sh/include/asm/ |
| H A D | atomic-grb.h | 12 " mov r15, r1 \n\t" /* r1 = saved sp */ \
17 "1: mov r1, r15 \n\t" /* LOGOUT */ \
21 : "memory" , "r0", "r1"); \
32 " mov r15, r1 \n\t" /* r1 = saved sp */ \
37 "1: mov r1, r15 \n\t" /* LOGOUT */ \
41 : "memory" , "r0", "r1"); \
63 " mov r15, r1 \n\t" /* r1 = saved sp */ atomic_clear_mask()
68 "1: mov r1, r15 \n\t" /* LOGOUT */ atomic_clear_mask()
72 : "memory" , "r0", "r1"); atomic_clear_mask()
82 " mov r15, r1 \n\t" /* r1 = saved sp */ atomic_set_mask()
87 "1: mov r1, r15 \n\t" /* LOGOUT */ atomic_set_mask()
91 : "memory" , "r0", "r1"); atomic_set_mask()
|
| H A D | bitops-grb.h | 16 " mov r15, r1 \n\t" /* r1 = saved sp */ set_bit()
21 "1: mov r1, r15 \n\t" /* LOGOUT */ set_bit()
25 : "memory" , "r0", "r1"); set_bit()
39 " mov r15, r1 \n\t" /* r1 = saved sp */ clear_bit()
44 "1: mov r1, r15 \n\t" /* LOGOUT */ clear_bit()
48 : "memory" , "r0", "r1"); clear_bit()
62 " mov r15, r1 \n\t" /* r1 = saved sp */ change_bit()
67 "1: mov r1, r15 \n\t" /* LOGOUT */ change_bit()
71 : "memory" , "r0", "r1"); change_bit()
86 " mov r15, r1 \n\t" /* r1 = saved sp */ test_and_set_bit()
95 "1: mov r1, r15 \n\t" /* LOGOUT */ test_and_set_bit()
100 : "memory" , "r0", "r1" ,"t"); test_and_set_bit()
119 " mov r15, r1 \n\t" /* r1 = saved sp */ test_and_clear_bit()
128 "1: mov r1, r15 \n\t" /* LOGOUT */ test_and_clear_bit()
134 : "memory" , "r0", "r1", "t"); test_and_clear_bit()
151 " mov r15, r1 \n\t" /* r1 = saved sp */ test_and_change_bit()
160 "1: mov r1, r15 \n\t" /* LOGOUT */ test_and_change_bit()
165 : "memory" , "r0", "r1", "t"); test_and_change_bit()
|
| H A D | romimage-macros.h | 10 mov.l 1f, r1
12 mov.l r0, @r1
23 mov.l 1f, r1
25 mov.w r0, @r1
36 mov.l 1f, r1
38 mov.b r0, @r1
64 mov.l 1f, r1
65 mov.l @r1, r0
|
| H A D | cmpxchg-grb.h | 12 " mov r15, r1 \n\t" /* r1 = saved sp */ xchg_u32()
16 "1: mov r1, r15 \n\t" /* LOGOUT */ xchg_u32()
21 : "memory", "r0", "r1"); xchg_u32()
33 " mov r15, r1 \n\t" /* r1 = saved sp */ xchg_u8()
38 "1: mov r1, r15 \n\t" /* LOGOUT */ xchg_u8()
43 : "memory" , "r0", "r1"); xchg_u8()
57 " mov r15, r1 \n\t" /* r1 = saved sp */ __cmpxchg_u32()
63 "1: mov r1, r15 \n\t" /* LOGOUT */ __cmpxchg_u32()
67 : "memory" , "r0", "r1", "t"); __cmpxchg_u32()
|
| /linux-4.1.27/arch/arm/mach-tegra/ |
| H A D | sleep-tegra30.S | 169 cpu_to_csr_reg r1, r3
170 add r1, r1, r12 @ virtual CSR address for this CPU
187 str r12, [r1]
195 ldr r3, [r1] @ read CSR
196 str r3, [r1] @ clear CSR
265 mov32 r1, tegra30_iram_start
266 sub r0, r0, r1
267 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
268 add r0, r0, r1
329 mov r1, #(1 << 28)
330 str r1, [r0, #CLK_RESET_SCLK_BURST]
331 str r1, [r0, #CLK_RESET_CCLK_BURST]
332 mov r1, #0
333 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
334 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
340 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
341 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
342 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
345 ldr r1, [r7]
346 add r1, r1, #2
347 wait_until r1, r7, r3
351 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
352 orr r1, r1, #(1 << 12)
353 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
355 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
356 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
357 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
364 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
365 orr r1, r1, #(1 << 12)
366 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
368 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
369 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
370 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
373 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
374 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
376 pll_locked r1, r0, CLK_RESET_PLLM_BASE
377 pll_locked r1, r0, CLK_RESET_PLLP_BASE
378 pll_locked r1, r0, CLK_RESET_PLLA_BASE
379 pll_locked r1, r0, CLK_RESET_PLLC_BASE
380 pll_locked r1, r0, CLK_RESET_PLLX_BASE
383 ldr r1, [r7]
384 add r1, r1, #LOCK_DELAY
385 wait_until r1, r7, r3
403 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
404 mvn r1, r1
405 bic r1, r1, #(1 << 31)
406 orr r1, r1, #(1 << 30)
407 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
420 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
421 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
422 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
423 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
424 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
425 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
428 ldr r1, [r0, #EMC_CFG_DIG_DLL]
429 orr r1, r1, #(1 << 30) @ set DLL_RESET
430 str r1, [r0, #EMC_CFG_DIG_DLL]
432 emc_timing_update r1, r0
435 movweq r1, #:lower16:TEGRA_EMC1_BASE
436 movteq r1, #:upper16:TEGRA_EMC1_BASE
437 cmpeq r0, r1
439 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
440 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
441 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
442 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
445 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
446 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
449 ldr r1, [r0, #EMC_CFG]
450 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
451 str r1, [r0, #EMC_CFG]
453 mov r1, #0
454 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
455 mov r1, #1
457 streq r1, [r0, #EMC_NOP]
458 streq r1, [r0, #EMC_NOP]
459 streq r1, [r0, #EMC_REFRESH]
461 emc_device_mask r1, r0
465 ands r2, r2, r1
468 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
484 tst r1, #2
503 tst r1, #2
514 mov r1, #0 @ unstall all transactions
515 str r1, [r0, #EMC_REQ_CTRL]
516 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
517 str r1, [r0, #EMC_ZCAL_INTERVAL]
518 ldr r1, [r5, #0x0] @ restore EMC_CFG
519 str r1, [r0, #EMC_CFG]
524 mov32 r1, TEGRA_EMC1_BASE
525 cmp r0, r1
526 movne r0, r1
617 ldr r1, [r7]
618 add r1, r1, #2
619 wait_until r1, r7, r9
631 ldr r1, [r7]
632 add r1, r1, #2
633 wait_until r1, r7, r9
656 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
674 cpu_id r1
676 cpu_to_csr_reg r2, r1
688 cpu_to_halt_reg r2, r1
731 ldr r1, [r0]
732 str r1, [r8, r9] @ save the content of the addr
750 mov r1, #0
751 str r1, [r0, #EMC_ZCAL_INTERVAL]
752 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
753 ldr r1, [r0, #EMC_CFG]
754 bic r1, r1, #(1 << 28)
755 bicne r1, r1, #(1 << 29)
756 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
758 emc_timing_update r1, r0
760 ldr r1, [r7]
761 add r1, r1, #5
762 wait_until r1, r7, r2
765 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
766 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
769 mov r1, #3
770 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
773 ldr r1, [r0, #EMC_EMC_STATUS]
774 tst r1, #4
777 mov r1, #1
778 str r1, [r0, #EMC_SELF_REF]
780 emc_device_mask r1, r0
784 and r2, r2, r1
785 cmp r2, r1
789 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
791 and r1, r1, r2
792 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
793 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
795 orreq r1, r1, #7 @ set E_NO_VTTGEN
796 orrne r1, r1, #0x3f
797 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
799 emc_timing_update r1, r0
804 mov32 r1, TEGRA_EMC1_BASE
805 cmp r0, r1
806 movne r0, r1
810 ldr r1, [r4, #PMC_CTRL]
811 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
817 mov32 r1, 0x8EC00000
818 str r1, [r4, #PMC_IO_DPD_REQ]
|
| H A D | sleep-tegra20.S | 100 mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
103 strb r12, [r1, r2]
105 cpu_to_halt_reg r1, r0
108 str r2, [r3, r1] @ put flow controller in wait event mode
109 ldr r2, [r3, r1]
112 movw r1, 0x1011
113 mov r1, r1, lsl r0
115 str r1, [r3, #0x340] @ put slave CPU in reset
136 * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
150 add r1, r3, #PMC_SCRATCH37
160 str r12, [r1] @ !turn = cpu
164 ldreq r12, [r1]
190 mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
193 strb r12, [r1, r2]
204 mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
207 strb r12, [r1, r2]
218 mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
220 ldrb r12, [r1, r2]
241 mov32 r1, tegra20_iram_start
242 sub r0, r0, r1
243 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
244 add r0, r0, r1
298 mov r1, #0
299 mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs
300 mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
347 mov r1, #(1 << 28)
348 str r1, [r0, #CLK_RESET_SCLK_BURST]
349 str r1, [r0, #CLK_RESET_CCLK_BURST]
350 mov r1, #0
351 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
352 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
354 pll_enable r1, r0, CLK_RESET_PLLM_BASE
355 pll_enable r1, r0, CLK_RESET_PLLP_BASE
356 pll_enable r1, r0, CLK_RESET_PLLC_BASE
366 ldr r1, [r4, r5]
367 str r1, [r7] @ restore the value in pad_save
376 ldr r1, [r7]
377 add r1, r1, #0xff
378 wait_until r1, r7, r9
387 ldr r1, [r0, #EMC_CFG]
388 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP
389 str r1, [r0, #EMC_CFG]
391 mov r1, #0
392 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
393 mov r1, #1
394 str r1, [r0, #EMC_NOP]
395 str r1, [r0, #EMC_NOP]
396 str r1, [r0, #EMC_REFRESH]
398 emc_device_mask r1, r0
402 ands r2, r2, r1
405 mov r1, #0 @ unstall all transactions
406 str r1, [r0, #EMC_REQ_CTRL]
444 ldr r1, [r7]
445 add r1, r1, #2
446 wait_until r1, r7, r9
477 cpu_id r1
478 cpu_to_halt_reg r1, r1
479 str r0, [r6, r1]
481 ldr r0, [r6, r1] /* memory barrier */
497 mov32 r1, TEGRA_EMC_BASE @ r1 reserved for emc base addr
500 str r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests
503 ldr r2, [r1, #EMC_EMC_STATUS]
508 str r2, [r1, #EMC_SELF_REF]
510 emc_device_mask r2, r1
513 ldr r3, [r1, #EMC_EMC_STATUS]
527 ldr r1, [r0]
528 str r1, [r4, r5] @ save the content of the addr
530 ldr r1, [r3, r5]
531 str r1, [r0] @ set the save val to the addr
|
| H A D | reset-handler.S | 59 cpu_to_csr_reg r1, r0
61 ldr r1, [r2, r1]
63 orr r1, r1, \
67 bic r1, r1, r0
68 str r1, [r2]
77 ldr r1, [r0]
78 orr r1, r1, #1
79 str r1, [r0]
237 mov r1, r0, lsl r10
238 str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
245 moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
247 movne r1, r10, lsl #3
248 addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
249 addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
260 str r0, [r6, +r1]
261 ldr r0, [r6, +r1] @ memory barrier
|
| /linux-4.1.27/arch/powerpc/platforms/pseries/ |
| H A D | hvCall.S | 37 std r3,STK_PARAM(R3)(r1); \
38 std r4,STK_PARAM(R4)(r1); \
39 std r5,STK_PARAM(R5)(r1); \
40 std r6,STK_PARAM(R6)(r1); \
41 std r7,STK_PARAM(R7)(r1); \
42 std r8,STK_PARAM(R8)(r1); \
43 std r9,STK_PARAM(R9)(r1); \
44 std r10,STK_PARAM(R10)(r1); \
45 std r0,16(r1); \
46 addi r4,r1,STK_PARAM(FIRST_REG); \
47 stdu r1,-STACK_FRAME_OVERHEAD(r1); \
49 ld r3,STACK_FRAME_OVERHEAD+STK_PARAM(R3)(r1); \
50 ld r4,STACK_FRAME_OVERHEAD+STK_PARAM(R4)(r1); \
51 ld r5,STACK_FRAME_OVERHEAD+STK_PARAM(R5)(r1); \
52 ld r6,STACK_FRAME_OVERHEAD+STK_PARAM(R6)(r1); \
53 ld r7,STACK_FRAME_OVERHEAD+STK_PARAM(R7)(r1); \
54 ld r8,STACK_FRAME_OVERHEAD+STK_PARAM(R8)(r1); \
55 ld r9,STACK_FRAME_OVERHEAD+STK_PARAM(R9)(r1); \
56 ld r10,STACK_FRAME_OVERHEAD+STK_PARAM(R10)(r1)
63 ld r0,STACK_FRAME_OVERHEAD+STK_PARAM(R3)(r1); \
64 std r3,STACK_FRAME_OVERHEAD+STK_PARAM(R3)(r1); \
68 ld r0,STACK_FRAME_OVERHEAD+16(r1); \
69 addi r1,r1,STACK_FRAME_OVERHEAD; \
70 ld r3,STK_PARAM(R3)(r1); \
95 std r12,32(r1); \
112 stw r0,8(r1)
116 lwz r0,8(r1)
125 lwz r0,8(r1)
134 stw r0,8(r1)
138 std r4,STK_PARAM(R4)(r1) /* Save ret buffer */
149 ld r12,STK_PARAM(R4)(r1)
155 lwz r0,8(r1)
164 std r4,STK_PARAM(R4)(r1)
176 ld r12,STK_PARAM(R4)(r1)
184 lwz r0,8(r1)
200 stw r0,8(r1)
202 std r4,STK_PARAM(R4)(r1) /* Save ret buffer */
213 ld r12,STK_PARAM(R4)(r1)
219 lwz r0,8(r1)
228 stw r0,8(r1)
232 std r4,STK_PARAM(R4)(r1) /* Save ret buffer */
240 ld r10,STK_PARAM(R11)(r1) /* put arg7 in R10 */
241 ld r11,STK_PARAM(R12)(r1) /* put arg8 in R11 */
242 ld r12,STK_PARAM(R13)(r1) /* put arg9 in R12 */
247 ld r12,STK_PARAM(R4)(r1)
258 lwz r0,8(r1)
267 std r4,STK_PARAM(R4)(r1)
276 ld r10,STACK_FRAME_OVERHEAD+STK_PARAM(R11)(r1)
277 ld r11,STACK_FRAME_OVERHEAD+STK_PARAM(R12)(r1)
278 ld r12,STACK_FRAME_OVERHEAD+STK_PARAM(R13)(r1)
283 ld r12,STACK_FRAME_OVERHEAD+STK_PARAM(R4)(r1)
296 lwz r0,8(r1)
307 stw r0,8(r1)
309 std r4,STK_PARAM(R4)(r1) /* Save ret buffer */
317 ld r10,STK_PARAM(R11)(r1) /* put arg7 in R10 */
318 ld r11,STK_PARAM(R12)(r1) /* put arg8 in R11 */
319 ld r12,STK_PARAM(R13)(r1) /* put arg9 in R12 */
324 ld r12,STK_PARAM(R4)(r1)
335 lwz r0,8(r1)
|
| /linux-4.1.27/arch/sh/lib64/ |
| H A D | udivdi3.S | 10 sub r21,r5,r1
11 mmulfx.w r1,r1,r4
12 mshflo.w r1,r63,r1
17 msub.w r1,r4,r1
18 madd.w r1,r1,r1
19 mmulfx.w r1,r1,r4
25 msub.w r1,r4,r1
27 mulu.l r1,r7,r4
28 addi r1,-3,r5
30 sub r63,r4,r4 // Negate to make sure r1 ends up <= 1/r2
33 muls.l r1,r4,r4 /* leaving at least one sign bit. */
35 mshalds.l r1,r21,r1
38 add r1,r4,r1 // 31 bit unsigned reciprocal now in r1 (msb equiv. 0.5)
40 /* Can do second step of 64 : 32 div now, using r1 and the rest in r2. */
43 mulu.l r21,r1,r21
56 mulu.l r2,r1,r7
72 msub.w r1,r4,r1
74 mulu.l r1,r7,r4
75 addi r1,-3,r5
77 sub r63,r4,r4 // Negate to make sure r1 ends up <= 1/r2
80 muls.l r1,r4,r4 /* leaving at least one sign bit. */
83 mshalds.l r1,r21,r1
85 add r1,r4,r1 // 31 bit unsigned reciprocal now in r1 (msb equiv. 0.5)
87 /* Can do second step of 64 : 32 div now, using r1 and the rest in r25. */
90 mulu.l r21,r1,r21
|
| H A D | sdivsi3.S | 8 /* clobbered: r1,r18,r19,r20,r21,r25,tr0 */
16 nsb r5, r1
17 shlld r5, r1, r25 /* normalize; [-2 ..1, 1..2) in s2.62 */
29 sub r63, r1, r1
30 addi r1, 92, r1
48 shard r21, r1, r21
|
| H A D | strlen.S | 25 ld.b r2, 0, r1
28 bnei/l r1, 0, tr0
|
| /linux-4.1.27/arch/powerpc/lib/ |
| H A D | ldstfp.S | 80 PPC_STLU r1,-STKFRM(r1)
82 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
89 stfd fr0,STKFRM-16(r1)
95 lfd fr0,STKFRM-16(r1)
96 4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
101 addi r1,r1,STKFRM
107 PPC_STLU r1,-STKFRM(r1)
109 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
116 stfd fr0,STKFRM-16(r1)
122 lfd fr0,STKFRM-16(r1)
123 4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
128 addi r1,r1,STKFRM
134 PPC_STLU r1,-STKFRM(r1)
136 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
143 stfd fr0,STKFRM-16(r1)
149 lfd fr0,STKFRM-16(r1)
150 4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
155 addi r1,r1,STKFRM
161 PPC_STLU r1,-STKFRM(r1)
163 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
170 stfd fr0,STKFRM-16(r1)
176 lfd fr0,STKFRM-16(r1)
177 4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
182 addi r1,r1,STKFRM
227 PPC_STLU r1,-STKFRM(r1)
229 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
237 stvx v0,r1,r8
243 lvx v0,r1,r8
244 4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
249 addi r1,r1,STKFRM
255 PPC_STLU r1,-STKFRM(r1)
257 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
265 stvx v0,r1,r8
271 lvx v0,r1,r8
272 4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
277 addi r1,r1,STKFRM
323 PPC_STLU r1,-STKFRM(r1)
325 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
340 4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
345 addi r1,r1,STKFRM
351 PPC_STLU r1,-STKFRM(r1)
353 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
368 4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
373 addi r1,r1,STKFRM
|
| H A D | copyuser_power7.S | 65 ld r16,STK_REG(R16)(r1)
66 ld r15,STK_REG(R15)(r1)
67 ld r14,STK_REG(R14)(r1)
70 ld r0,STACKFRAMESIZE+16(r1)
76 ld r22,STK_REG(R22)(r1)
77 ld r21,STK_REG(R21)(r1)
78 ld r20,STK_REG(R20)(r1)
79 ld r19,STK_REG(R19)(r1)
80 ld r18,STK_REG(R18)(r1)
81 ld r17,STK_REG(R17)(r1)
82 ld r16,STK_REG(R16)(r1)
83 ld r15,STK_REG(R15)(r1)
84 ld r14,STK_REG(R14)(r1)
86 addi r1,r1,STACKFRAMESIZE
88 ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
89 ld r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
90 ld r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
99 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
100 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
101 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
108 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
109 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
110 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
144 stdu r1,-STACKFRAMESIZE(r1)
145 std r14,STK_REG(R14)(r1)
146 std r15,STK_REG(R15)(r1)
147 std r16,STK_REG(R16)(r1)
148 std r17,STK_REG(R17)(r1)
149 std r18,STK_REG(R18)(r1)
150 std r19,STK_REG(R19)(r1)
151 std r20,STK_REG(R20)(r1)
152 std r21,STK_REG(R21)(r1)
153 std r22,STK_REG(R22)(r1)
154 std r0,STACKFRAMESIZE+16(r1)
200 ld r14,STK_REG(R14)(r1)
201 ld r15,STK_REG(R15)(r1)
202 ld r16,STK_REG(R16)(r1)
203 ld r17,STK_REG(R17)(r1)
204 ld r18,STK_REG(R18)(r1)
205 ld r19,STK_REG(R19)(r1)
206 ld r20,STK_REG(R20)(r1)
207 ld r21,STK_REG(R21)(r1)
208 ld r22,STK_REG(R22)(r1)
209 addi r1,r1,STACKFRAMESIZE
290 addi r1,r1,STACKFRAMESIZE
296 std r0,16(r1)
297 stdu r1,-STACKFRAMESIZE(r1)
300 ld r0,STACKFRAMESIZE+16(r1)
301 ld r3,STK_REG(R31)(r1)
302 ld r4,STK_REG(R30)(r1)
303 ld r5,STK_REG(R29)(r1)
419 std r14,STK_REG(R14)(r1)
420 std r15,STK_REG(R15)(r1)
421 std r16,STK_REG(R16)(r1)
456 ld r14,STK_REG(R14)(r1)
457 ld r15,STK_REG(R15)(r1)
458 ld r16,STK_REG(R16)(r1)
516 15: addi r1,r1,STACKFRAMESIZE
604 std r14,STK_REG(R14)(r1)
605 std r15,STK_REG(R15)(r1)
606 std r16,STK_REG(R16)(r1)
649 ld r14,STK_REG(R14)(r1)
650 ld r15,STK_REG(R15)(r1)
651 ld r16,STK_REG(R16)(r1)
719 15: addi r1,r1,STACKFRAMESIZE
|
| H A D | memcmp_64.S | 89 std r31,-8(r1)
90 std r30,-16(r1)
91 std r29,-24(r1)
92 std r28,-32(r1)
93 std r27,-40(r1)
182 ld r31,-8(r1)
183 ld r30,-16(r1)
184 ld r29,-24(r1)
185 ld r28,-32(r1)
186 ld r27,-40(r1)
228 ld r31,-8(r1)
229 ld r30,-16(r1)
230 ld r29,-24(r1)
231 ld r28,-32(r1)
232 ld r27,-40(r1)
|
| H A D | crtsavres.S | 321 std r14,-144(r1)
324 std r15,-136(r1)
327 std r16,-128(r1)
330 std r17,-120(r1)
333 std r18,-112(r1)
336 std r19,-104(r1)
339 std r20,-96(r1)
342 std r21,-88(r1)
345 std r22,-80(r1)
348 std r23,-72(r1)
351 std r24,-64(r1)
354 std r25,-56(r1)
357 std r26,-48(r1)
360 std r27,-40(r1)
363 std r28,-32(r1)
366 std r29,-24(r1)
369 std r30,-16(r1)
372 std r31,-8(r1)
373 std r0,16(r1)
378 ld r14,-144(r1)
381 ld r15,-136(r1)
384 ld r16,-128(r1)
387 ld r17,-120(r1)
390 ld r18,-112(r1)
393 ld r19,-104(r1)
396 ld r20,-96(r1)
399 ld r21,-88(r1)
402 ld r22,-80(r1)
405 ld r23,-72(r1)
408 ld r24,-64(r1)
411 ld r25,-56(r1)
414 ld r26,-48(r1)
417 ld r27,-40(r1)
420 ld r28,-32(r1)
423 ld r0,16(r1)
424 ld r29,-24(r1)
426 ld r30,-16(r1)
427 ld r31,-8(r1)
432 ld r30,-16(r1)
435 ld r0,16(r1)
436 ld r31,-8(r1)
|
| H A D | memcpy_power7.S | 36 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
43 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
77 stdu r1,-STACKFRAMESIZE(r1)
78 std r14,STK_REG(R14)(r1)
79 std r15,STK_REG(R15)(r1)
80 std r16,STK_REG(R16)(r1)
81 std r17,STK_REG(R17)(r1)
82 std r18,STK_REG(R18)(r1)
83 std r19,STK_REG(R19)(r1)
84 std r20,STK_REG(R20)(r1)
85 std r21,STK_REG(R21)(r1)
86 std r22,STK_REG(R22)(r1)
87 std r0,STACKFRAMESIZE+16(r1)
133 ld r14,STK_REG(R14)(r1)
134 ld r15,STK_REG(R15)(r1)
135 ld r16,STK_REG(R16)(r1)
136 ld r17,STK_REG(R17)(r1)
137 ld r18,STK_REG(R18)(r1)
138 ld r19,STK_REG(R19)(r1)
139 ld r20,STK_REG(R20)(r1)
140 ld r21,STK_REG(R21)(r1)
141 ld r22,STK_REG(R22)(r1)
142 addi r1,r1,STACKFRAMESIZE
219 15: ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
223 addi r1,r1,STACKFRAMESIZE
229 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
230 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
231 std r0,16(r1)
232 stdu r1,-STACKFRAMESIZE(r1)
235 ld r0,STACKFRAMESIZE+16(r1)
236 ld r3,STK_REG(R31)(r1)
237 ld r4,STK_REG(R30)(r1)
238 ld r5,STK_REG(R29)(r1)
352 std r14,STK_REG(R14)(r1)
353 std r15,STK_REG(R15)(r1)
354 std r16,STK_REG(R16)(r1)
389 ld r14,STK_REG(R14)(r1)
390 ld r15,STK_REG(R15)(r1)
391 ld r16,STK_REG(R16)(r1)
449 15: addi r1,r1,STACKFRAMESIZE
450 ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
538 std r14,STK_REG(R14)(r1)
539 std r15,STK_REG(R15)(r1)
540 std r16,STK_REG(R16)(r1)
583 ld r14,STK_REG(R14)(r1)
584 ld r15,STK_REG(R15)(r1)
585 ld r16,STK_REG(R16)(r1)
653 15: addi r1,r1,STACKFRAMESIZE
654 ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
|
| /linux-4.1.27/arch/openrisc/kernel/ |
| H A D | entry.S | 54 l.lwz r3,PT_PC(r1) ;\
56 l.lwz r3,PT_SR(r1) ;\
58 l.lwz r2,PT_GPR2(r1) ;\
59 l.lwz r3,PT_GPR3(r1) ;\
60 l.lwz r4,PT_GPR4(r1) ;\
61 l.lwz r5,PT_GPR5(r1) ;\
62 l.lwz r6,PT_GPR6(r1) ;\
63 l.lwz r7,PT_GPR7(r1) ;\
64 l.lwz r8,PT_GPR8(r1) ;\
65 l.lwz r9,PT_GPR9(r1) ;\
66 l.lwz r10,PT_GPR10(r1) ;\
67 l.lwz r11,PT_GPR11(r1) ;\
68 l.lwz r12,PT_GPR12(r1) ;\
69 l.lwz r13,PT_GPR13(r1) ;\
70 l.lwz r14,PT_GPR14(r1) ;\
71 l.lwz r15,PT_GPR15(r1) ;\
72 l.lwz r16,PT_GPR16(r1) ;\
73 l.lwz r17,PT_GPR17(r1) ;\
74 l.lwz r18,PT_GPR18(r1) ;\
75 l.lwz r19,PT_GPR19(r1) ;\
76 l.lwz r20,PT_GPR20(r1) ;\
77 l.lwz r21,PT_GPR21(r1) ;\
78 l.lwz r22,PT_GPR22(r1) ;\
79 l.lwz r23,PT_GPR23(r1) ;\
80 l.lwz r24,PT_GPR24(r1) ;\
81 l.lwz r25,PT_GPR25(r1) ;\
82 l.lwz r26,PT_GPR26(r1) ;\
83 l.lwz r27,PT_GPR27(r1) ;\
84 l.lwz r28,PT_GPR28(r1) ;\
85 l.lwz r29,PT_GPR29(r1) ;\
86 l.lwz r30,PT_GPR30(r1) ;\
87 l.lwz r31,PT_GPR31(r1) ;\
88 l.lwz r1,PT_SP(r1) ;\
95 /* r1, EPCR, ESR a already saved */ ;\
96 l.sw PT_GPR2(r1),r2 ;\
97 l.sw PT_GPR3(r1),r3 ;\
99 l.sw PT_GPR5(r1),r5 ;\
100 l.sw PT_GPR6(r1),r6 ;\
101 l.sw PT_GPR7(r1),r7 ;\
102 l.sw PT_GPR8(r1),r8 ;\
103 l.sw PT_GPR9(r1),r9 ;\
105 l.sw PT_GPR11(r1),r11 ;\
107 l.sw PT_GPR13(r1),r13 ;\
108 l.sw PT_GPR14(r1),r14 ;\
109 l.sw PT_GPR15(r1),r15 ;\
110 l.sw PT_GPR16(r1),r16 ;\
111 l.sw PT_GPR17(r1),r17 ;\
112 l.sw PT_GPR18(r1),r18 ;\
113 l.sw PT_GPR19(r1),r19 ;\
114 l.sw PT_GPR20(r1),r20 ;\
115 l.sw PT_GPR21(r1),r21 ;\
116 l.sw PT_GPR22(r1),r22 ;\
117 l.sw PT_GPR23(r1),r23 ;\
118 l.sw PT_GPR24(r1),r24 ;\
119 l.sw PT_GPR25(r1),r25 ;\
120 l.sw PT_GPR26(r1),r26 ;\
121 l.sw PT_GPR27(r1),r27 ;\
122 l.sw PT_GPR28(r1),r28 ;\
123 l.sw PT_GPR29(r1),r29 ;\
125 /* l.sw PT_GPR30(r1),r30*/ ;\
126 l.sw PT_GPR31(r1),r31 ;\
129 l.sw PT_ORIG_GPR11(r1),r30
134 /* r1, EPCR, ESR already saved */ ;\
135 l.sw PT_GPR2(r1),r2 ;\
136 l.sw PT_GPR3(r1),r3 ;\
137 l.sw PT_GPR5(r1),r5 ;\
138 l.sw PT_GPR6(r1),r6 ;\
139 l.sw PT_GPR7(r1),r7 ;\
140 l.sw PT_GPR8(r1),r8 ;\
141 l.sw PT_GPR9(r1),r9 ;\
143 l.sw PT_GPR11(r1),r11 ;\
145 l.sw PT_GPR13(r1),r13 ;\
146 l.sw PT_GPR14(r1),r14 ;\
147 l.sw PT_GPR15(r1),r15 ;\
148 l.sw PT_GPR16(r1),r16 ;\
149 l.sw PT_GPR17(r1),r17 ;\
150 l.sw PT_GPR18(r1),r18 ;\
151 l.sw PT_GPR19(r1),r19 ;\
152 l.sw PT_GPR20(r1),r20 ;\
153 l.sw PT_GPR21(r1),r21 ;\
154 l.sw PT_GPR22(r1),r22 ;\
155 l.sw PT_GPR23(r1),r23 ;\
156 l.sw PT_GPR24(r1),r24 ;\
157 l.sw PT_GPR25(r1),r25 ;\
158 l.sw PT_GPR26(r1),r26 ;\
159 l.sw PT_GPR27(r1),r27 ;\
160 l.sw PT_GPR28(r1),r28 ;\
161 l.sw PT_GPR29(r1),r29 ;\
163 l.sw PT_GPR30(r1),r30 ;\
164 /* l.sw PT_GPR31(r1),r31 */ ;\
167 l.sw PT_ORIG_GPR11(r1),r30 ;\
168 l.addi r3,r1,0 ;\
198 l.addi r3,r1,0 /* pt_regs */
213 l.addi r3,r1,0 // pt_regs
293 l.addi r3,r1,0 // pt_regs
308 l.addi r3,r1,0 /* pt_regs */
318 l.addi r3,r1,0 /* pt_regs */
328 l.lwz r5,PT_PC(r1)
366 l.add r4,r4,r1 /* Load the jump register value from the stack */
374 l.sw PT_PC(r1),r5
399 l.add r4,r4,r1
409 l.add r4,r4,r1
425 l.add r4,r4,r1
441 l.add r4,r4,r1
448 l.add r4,r4,r1
458 l.add r4,r4,r1
479 l.addi r3,r1,0 /* pt_regs */
488 l.lwz r4,PT_SR(r1) // were interrupts enabled ?
494 l.addi r1,r1,-0x8
497 l.sw 0x0(r1),r3
499 l.sw 0x4(r1),r4
500 l.addi r1,r1,0x8
509 // l.sw PT_SR(r1),r4
512 l.addi r3,r1,0
552 /* r1, EPCR, ESR a already saved */
553 l.sw PT_GPR2(r1),r2
558 l.sw PT_GPR3(r1),r3
561 l.lwz r4,PT_GPR4(r1)
562 l.sw PT_GPR5(r1),r5
563 l.sw PT_GPR6(r1),r6
564 l.sw PT_GPR7(r1),r7
565 l.sw PT_GPR8(r1),r8
566 l.sw PT_GPR9(r1),r9
568 l.sw PT_GPR11(r1),r11
570 l.sw PT_ORIG_GPR11(r1),r11
582 /* l.sw PT_GPR30(r1),r30 */
612 l.sw PT_GPR11(r1),r11 // save return value
619 l.sw -4(r1),r27
620 l.sw -8(r1),r11
621 l.addi r1,r1,-8
626 l.addi r1,r1,8
656 l.sw PT_GPR14(r1),r14
657 l.sw PT_GPR16(r1),r16
658 l.sw PT_GPR18(r1),r18
659 l.sw PT_GPR20(r1),r20
660 l.sw PT_GPR22(r1),r22
661 l.sw PT_GPR24(r1),r24
662 l.sw PT_GPR26(r1),r26
663 l.sw PT_GPR28(r1),r28
693 l.lwz r2,PT_GPR2(r1)
699 l.lwz r3,PT_GPR3(r1)
700 l.lwz r4,PT_GPR4(r1)
701 l.lwz r5,PT_GPR5(r1)
702 l.lwz r6,PT_GPR6(r1)
703 l.lwz r7,PT_GPR7(r1)
704 l.lwz r8,PT_GPR8(r1)
706 l.lwz r9,PT_GPR9(r1)
707 l.lwz r10,PT_GPR10(r1)
708 l.lwz r11,PT_GPR11(r1)
711 l.lwz r30,PT_GPR30(r1)
714 l.lwz r13,PT_PC(r1)
715 l.lwz r15,PT_SR(r1)
716 l.lwz r1,PT_SP(r1)
738 l.addi r3,r1,0
744 l.lwz r11,PT_GPR11(r1)
745 l.lwz r3,PT_GPR3(r1)
746 l.lwz r4,PT_GPR4(r1)
747 l.lwz r5,PT_GPR5(r1)
748 l.lwz r6,PT_GPR6(r1)
749 l.lwz r7,PT_GPR7(r1)
752 l.lwz r8,PT_GPR8(r1)
756 l.addi r3,r1,0
781 l.addi r3,r1,0 /* pt_regs */
865 l.lwz r5,PT_ORIG_GPR11(r1)
872 l.ori r3,r1,0 /* pt_regs */
885 l.lwz r11,PT_ORIG_GPR11(r1)
887 l.lwz r3,PT_GPR3(r1)
888 l.lwz r4,PT_GPR4(r1)
889 l.lwz r5,PT_GPR5(r1)
890 l.lwz r6,PT_GPR6(r1)
891 l.lwz r7,PT_GPR7(r1)
893 l.lwz r8,PT_GPR8(r1)
902 l.lwz r4,PT_SR(r1)
925 l.lwz r11,PT_GPR11(r1)
932 l.lwz r12,PT_GPR12(r1)
933 l.lwz r14,PT_GPR14(r1)
934 l.lwz r16,PT_GPR16(r1)
935 l.lwz r18,PT_GPR18(r1)
936 l.lwz r20,PT_GPR20(r1)
937 l.lwz r22,PT_GPR22(r1)
938 l.lwz r24,PT_GPR24(r1)
939 l.lwz r26,PT_GPR26(r1)
940 l.lwz r28,PT_GPR28(r1)
990 l.addi r1,r1,-(INT_FRAME_SIZE)
992 /* No need to store r1/PT_SP as it goes into KSP below */
993 l.sw PT_GPR2(r1),r2
994 l.sw PT_GPR9(r1),r9
997 l.sw PT_GPR12(r1),r12
998 l.sw PT_GPR14(r1),r14
999 l.sw PT_GPR16(r1),r16
1000 l.sw PT_GPR18(r1),r18
1001 l.sw PT_GPR20(r1),r20
1002 l.sw PT_GPR22(r1),r22
1003 l.sw PT_GPR24(r1),r24
1004 l.sw PT_GPR26(r1),r26
1005 l.sw PT_GPR28(r1),r28
1006 l.sw PT_GPR30(r1),r30
1019 l.sw PT_SP(r1),r29
1022 l.sw TI_KSP(r10),r1 /* Save old stack pointer */
1024 l.lwz r1,TI_KSP(r10) /* Load new stack pointer */
1027 l.lwz r29,PT_SP(r1)
1033 l.lwz r2,PT_GPR2(r1)
1034 l.lwz r9,PT_GPR9(r1)
1040 l.lwz r12,PT_GPR12(r1)
1041 l.lwz r14,PT_GPR14(r1)
1042 l.lwz r16,PT_GPR16(r1)
1043 l.lwz r18,PT_GPR18(r1)
1044 l.lwz r20,PT_GPR20(r1)
1045 l.lwz r22,PT_GPR22(r1)
1046 l.lwz r24,PT_GPR24(r1)
1047 l.lwz r26,PT_GPR26(r1)
1048 l.lwz r28,PT_GPR28(r1)
1049 l.lwz r30,PT_GPR30(r1)
1052 l.addi r1,r1,(INT_FRAME_SIZE)
1081 l.sw PT_GPR14(r1),r14
1082 l.sw PT_GPR16(r1),r16
1083 l.sw PT_GPR18(r1),r18
1084 l.sw PT_GPR20(r1),r20
1085 l.sw PT_GPR22(r1),r22
1086 l.sw PT_GPR24(r1),r24
1087 l.sw PT_GPR26(r1),r26
1089 l.sw PT_GPR28(r1),r28
1095 l.addi r7,r1,0
1101 l.addi r3,r1,0
1105 l.addi r3,r1,0
|
| /linux-4.1.27/arch/s390/kernel/ |
| H A D | swsusp.S | 29 lgr %r1,%r15
31 stg %r1,__SF_BACKCHAIN(%r15)
43 lghi %r1,0x1000
49 mvc 0x318(4,%r1),__SF_EMPTY(%r15) /* move prefix to lowcore */
50 stfpc 0x31c(%r1) /* store fpu control */
51 std 0,0x200(%r1) /* store f0 */
52 std 1,0x208(%r1) /* store f1 */
53 std 2,0x210(%r1) /* store f2 */
54 std 3,0x218(%r1) /* store f3 */
55 std 4,0x220(%r1) /* store f4 */
56 std 5,0x228(%r1) /* store f5 */
57 std 6,0x230(%r1) /* store f6 */
58 std 7,0x238(%r1) /* store f7 */
59 std 8,0x240(%r1) /* store f8 */
60 std 9,0x248(%r1) /* store f9 */
61 std 10,0x250(%r1) /* store f10 */
62 std 11,0x258(%r1) /* store f11 */
63 std 12,0x260(%r1) /* store f12 */
64 std 13,0x268(%r1) /* store f13 */
65 std 14,0x270(%r1) /* store f14 */
66 std 15,0x278(%r1) /* store f15 */
67 stam %a0,%a15,0x340(%r1) /* store access registers */
68 stctg %c0,%c15,0x380(%r1) /* store control registers */
69 stmg %r0,%r15,0x280(%r1) /* store general registers */
71 stpt 0x328(%r1) /* store timer */
73 stckc 0x330(%r1) /* store clock comparator */
77 slg %r0,0x328(%r1)
80 mvc __LC_LAST_UPDATE_TIMER(8),0x328(%r1)
115 lghi %r1,0x1000
116 spx 0x318(%r1)
128 lgr %r1,%r15
130 stg %r1,__SF_BACKCHAIN(%r15)
144 larl %r1,restore_pblist
145 lg %r1,0(%r1)
146 ltgr %r1,%r1
149 lg %r2,8(%r1)
150 lg %r4,0(%r1)
157 lg %r2,8(%r1)
159 lg %r1,16(%r1)
160 ltgr %r1,%r1
166 larl %r1,restart_entry
168 og %r1,0(%r2)
169 stg %r1,0(%r0)
170 larl %r1,.Lnew_pgm_check_psw
172 stm %r2,%r3,0(%r1)
173 mvc __LC_PGM_NEW_PSW(16,%r0),0(%r1)
177 lhi %r1,1
178 sigp %r1,%r0,SIGP_SET_ARCHITECTURE
181 larl %r1,smp_cpu_mt_shift
182 icm %r1,15,0(%r1)
184 llgfr %r1,%r1
186 sigp %r1,%r0,SIGP_SET_MULTI_THREADING
191 larl %r1,.Lnew_pgm_check_psw
192 lpswe 0(%r1)
196 larl %r1,.Lresume_cpu /* Resume CPU address: r2 */
197 stap 0(%r1)
198 llgh %r2,0(%r1)
199 llgh %r1,__LC_EXT_CPU_ADDR(%r0) /* Suspend CPU address: r1 */
200 cgr %r1,%r2
201 je restore_registers /* r1 = r2 -> nothing to do */
205 sigp %r9,%r1,SIGP_INITIAL_CPU_RESET /* sigp initial cpu reset */
214 lghi %r1,0
216 sigp %r1,%r0,SIGP_SET_ARCHITECTURE
222 sigp %r9,%r1,SIGP_RESTART /* sigp restart to suspend CPU */
230 larl %r1,.Lresume_cpu
231 llgh %r2,0(%r1)
241 lghi %r13,0x1000 /* %r1 = pointer to save area */
244 llgf %r1,0x318(%r13)
245 stck __LC_LAST_UPDATE_CLOCK(%r1)
|
| H A D | base.S | 18 larl %r1,s390_base_mcck_handler_fn
19 lg %r1,0(%r1)
20 ltgr %r1,%r1
22 basr %r14,%r1
23 1: la %r1,4095
24 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)
38 larl %r1,s390_base_ext_handler_fn
39 lg %r1,0(%r1)
40 ltgr %r1,%r1
42 basr %r14,%r1
58 larl %r1,s390_base_pgm_handler_fn
59 lg %r1,0(%r1)
60 ltgr %r1,%r1
62 basr %r14,%r1
97 lghi %r1,1
99 diag %r0,%r1,0x308
102 lhi %r1,2 # Use mode 2 = ESAME (dump)
103 sigp %r1,%r0,SIGP_SET_ARCHITECTURE # Switch to ESAME mode
|
| H A D | mcount.S | 29 lgr %r1,%r15
34 stg %r1,__SF_BACKCHAIN(%r15)
35 stg %r1,(STACK_PTREGS_GPRS+15*8)(%r15)
41 lgrl %r1,ftrace_trace_function
47 larl %r1,ftrace_trace_function
48 lg %r1,0(%r1)
52 basr %r14,%r1
65 lg %r1,(STACK_PTREGS_PSW+8)(%r15)
67 br %r1
73 lgr %r1,%r15
75 stg %r1,__SF_BACKCHAIN(%r15)
|
| H A D | relocate_kernel.S | 38 la %r1,load_psw-.base(%r13)
39 mvc 0(8,%r0),0(%r1)
46 lhi %r1,1 # mode 1 = esame
47 sigp %r1,%r0,SIGP_SET_ARCHITECTURE # switch to esame mode
96 sr %r1,%r1 # erase register r1
98 sigp %r1,%r2,SIGP_SET_ARCHITECTURE # set cpuid to zero
|
| /linux-4.1.27/arch/unicore32/mm/ |
| H A D | cache-ucv2.S | 58 sub r1, r1, r0
59 csub.a r1, #MAX_AREA_SIZE
62 andn r1, r1, #CACHE_LINESIZE - 1
63 add r1, r1, #CACHE_LINESIZE
68 sub.a r1, r1, #CACHE_LINESIZE
98 sub r1, r1, r0
99 csub.a r1, #MAX_AREA_SIZE
102 andn r1, r1, #CACHE_LINESIZE - 1
103 add r1, r1, #CACHE_LINESIZE
118 sub.a r1, r1, #CACHE_LINESIZE
152 sub r1, r1, r0
153 andn r1, r1, #CACHE_LINESIZE - 1
154 add r1, r1, #CACHE_LINESIZE
156 csub.a r1, #MAX_AREA_SIZE
171 sub.a r1, r1, #CACHE_LINESIZE
192 sub r1, r1, r0
193 andn r1, r1, #CACHE_LINESIZE - 1
194 add r1, r1, #CACHE_LINESIZE
196 csub.a r1, #MAX_AREA_SIZE
203 sub.a r1, r1, #CACHE_LINESIZE
|
| /linux-4.1.27/arch/sh/boot/compressed/ |
| H A D | head_32.S | 15 mov.l init_sr, r1
16 ldc r1, sr
25 mov #0xffffffe0, r1
26 and r1, r0 ! align cache line
28 mov r0, r1
29 sub r2, r1
31 mov.l @r1, r4
32 mov.l @(4,r1), r5
33 mov.l @(8,r1), r6
34 mov.l @(12,r1), r7
35 mov.l @(16,r1), r8
36 mov.l @(20,r1), r9
37 mov.l @(24,r1), r10
38 mov.l @(28,r1), r11
53 add #-32, r1
66 mov.l end_addr, r1
70 mov.l r0, @-r1
71 cmp/eq r1,r2
|
| /linux-4.1.27/arch/openrisc/lib/ |
| H A D | string.S | 37 l.addi r1,r1,-12
38 l.sw 0(r1),r6
39 l.sw 4(r1),r4
40 l.sw 8(r1),r3
54 l.lwz r6,0(r1)
55 l.lwz r4,4(r1)
56 l.lwz r3,8(r1)
58 l.addi r1,r1,12
78 l.addi r1,r1,-8
79 l.sw 0(r1),r4
80 l.sw 4(r1),r3
92 l.lwz r4,0(r1)
93 l.lwz r3,4(r1)
95 l.addi r1,r1,8
|
| /linux-4.1.27/arch/arm/mm/ |
| H A D | copypage-xsc3.c | 25 * r1 = source
39 pld [r1, #0] \n\ xsc3_mc_copy_user_page()
40 pld [r1, #32] \n\ xsc3_mc_copy_user_page()
41 1: pld [r1, #64] \n\ xsc3_mc_copy_user_page()
42 pld [r1, #96] \n\ xsc3_mc_copy_user_page()
44 2: ldrd r2, [r1], #8 \n\ xsc3_mc_copy_user_page()
46 ldrd r4, [r1], #8 \n\ xsc3_mc_copy_user_page()
49 ldrd r2, [r1], #8 \n\ xsc3_mc_copy_user_page()
51 ldrd r4, [r1], #8 \n\ xsc3_mc_copy_user_page()
54 ldrd r2, [r1], #8 \n\ xsc3_mc_copy_user_page()
56 ldrd r4, [r1], #8 \n\ xsc3_mc_copy_user_page()
59 ldrd r2, [r1], #8 \n\ xsc3_mc_copy_user_page()
62 ldrd r4, [r1], #8 \n\ xsc3_mc_copy_user_page()
89 * r1 = virtual user address of ultimate destination page
95 mov r1, %2 \n\ xsc3_mc_clear_user_highpage()
103 subs r1, r1, #1 \n\ xsc3_mc_clear_user_highpage()
107 : "r1", "r2", "r3"); xsc3_mc_clear_user_highpage()
|
| H A D | copypage-xscale.c | 51 pld [r1, #0] \n\ mc_copy_user_page()
52 pld [r1, #32] \n\ mc_copy_user_page()
55 pld [r1, #64] \n\ mc_copy_user_page()
56 pld [r1, #96] \n\ mc_copy_user_page()
59 mov ip, r1 \n\ mc_copy_user_page()
60 strd r2, [r1], #8 \n\ mc_copy_user_page()
62 strd r4, [r1], #8 \n\ mc_copy_user_page()
64 strd r2, [r1], #8 \n\ mc_copy_user_page()
65 strd r4, [r1], #8 \n\ mc_copy_user_page()
70 mov ip, r1 \n\ mc_copy_user_page()
71 strd r2, [r1], #8 \n\ mc_copy_user_page()
73 strd r4, [r1], #8 \n\ mc_copy_user_page()
75 strd r2, [r1], #8 \n\ mc_copy_user_page()
76 strd r4, [r1], #8 \n\ mc_copy_user_page()
114 "mov r1, %2 \n\ xscale_mc_clear_user_highpage()
123 subs r1, r1, #1 \n\ xscale_mc_clear_user_highpage()
128 : "r1", "r2", "r3", "ip"); xscale_mc_clear_user_highpage()
|
| H A D | copypage-feroceon.c | 22 1: mov lr, r1 \n\ feroceon_copy_user_page()
23 ldmia r1!, {r2 - r9} \n\ feroceon_copy_user_page()
32 ldmia r1!, {r2 - r9} \n\ feroceon_copy_user_page()
36 ldmia r1!, {r2 - r9} \n\ feroceon_copy_user_page()
40 ldmia r1!, {r2 - r9} \n\ feroceon_copy_user_page()
44 ldmia r1!, {r2 - r9} \n\ feroceon_copy_user_page()
48 ldmia r1!, {r2 - r9} \n\ feroceon_copy_user_page()
52 ldmia r1!, {r2 - r9} \n\ feroceon_copy_user_page()
56 ldmia r1!, {r2 - r9} \n\ feroceon_copy_user_page()
87 mov r1, %2 \n\ feroceon_clear_user_highpage()
97 subs r1, r1, #1 \n\ feroceon_clear_user_highpage()
101 mcr p15, 0, r1, c7, c10, 4 @ drain WB" feroceon_clear_user_highpage()
104 : "r1", "r2", "r3", "r4", "r5", "r6", "r7", "ip", "lr"); feroceon_clear_user_highpage()
|
| H A D | copypage-v4wt.c | 29 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ v4wt_copy_user_page()
31 ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\ v4wt_copy_user_page()
33 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ v4wt_copy_user_page()
35 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ v4wt_copy_user_page()
38 ldmneia r1!, {r3, r4, ip, lr} @ 4\n\ v4wt_copy_user_page()
67 mov r1, %2 @ 1\n\ v4wt_clear_user_highpage()
76 subs r1, r1, #1 @ 1\n\ v4wt_clear_user_highpage()
81 : "r1", "r2", "r3", "ip", "lr"); v4wt_clear_user_highpage()
|
| H A D | proc-v7-2level.S | 49 mmid r1, r1 @ get mm->context.id
55 bfi r1, r2, #8, #24 @ insert into new context ID
60 mcr p15, 0, r1, c13, c0, 1 @ set context ID
81 str r1, [r0] @ linux version
83 bic r3, r1, #0x000003f0
88 tst r1, #1 << 4
91 eor r1, r1, #L_PTE_DIRTY
92 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
95 tst r1, #L_PTE_USER
98 tst r1, #L_PTE_XN
101 tst r1, #L_PTE_YOUNG
102 tstne r1, #L_PTE_VALID
103 eorne r1, r1, #L_PTE_NONE
104 tstne r1, #L_PTE_NONE
|
| H A D | copypage-v4wb.c | 31 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ v4wb_copy_user_page()
34 ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\ v4wb_copy_user_page()
36 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ v4wb_copy_user_page()
39 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ v4wb_copy_user_page()
42 ldmneia r1!, {r3, r4, ip, lr} @ 4\n\ v4wb_copy_user_page()
44 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\ v4wb_copy_user_page()
72 mov r1, %2 @ 1\n\ v4wb_clear_user_highpage()
83 subs r1, r1, #1 @ 1\n\ v4wb_clear_user_highpage()
85 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB" v4wb_clear_user_highpage()
88 : "r1", "r2", "r3", "ip", "lr"); v4wb_clear_user_highpage()
|
| H A D | tlb-v6.S | 42 mov r1, r1, lsr #PAGE_SHIFT
45 mov r1, r1, lsl #PAGE_SHIFT
56 cmp r0, r1
73 mov r1, r1, lsr #PAGE_SHIFT
75 mov r1, r1, lsl #PAGE_SHIFT
84 cmp r0, r1
|
| H A D | copypage-fa.c | 26 1: ldmia r1!, {r3, r4, ip, lr} @ 4\n\ fa_copy_user_page()
30 ldmia r1!, {r3, r4, ip, lr} @ 4\n\ fa_copy_user_page()
63 mov r1, %2 @ 1\n\ fa_clear_user_highpage()
74 subs r1, r1, #1 @ 1\n\ fa_clear_user_highpage()
76 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB" fa_clear_user_highpage()
79 : "r1", "r2", "r3", "ip", "lr"); fa_clear_user_highpage()
|
| H A D | cache-v4wb.S | 83 ldr r1, [r3, #0]
84 eor r1, r1, #CACHE_DSIZE
85 str r1, [r3, #0]
86 add r2, r1, #CACHE_DSIZE
87 1: ldr r3, [r1], #32
88 cmp r1, r2
92 sub r1, r2, #512 @ only 512 bytes
93 1: ldr r3, [r1], #32
94 cmp r1, r2
112 sub r3, r1, r0 @ calculate total size
122 cmp r0, r1
138 add r1, r0, r1
169 cmp r0, r1
192 tst r1, #CACHE_DLINESIZE - 1
193 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
196 cmp r0, r1
213 cmp r0, r1
238 add r1, r1, r0
|
| H A D | cache-v6.S | 36 * r1 - corrupted
41 mrs r1, cpsr
47 msr cpsr_cx, r1 @ restore interrupts
139 cmp r0, r1
176 add r1, r0, r1
185 cmp r0, r1
216 tst r1, #D_CACHE_LINE_SIZE - 1
218 ldrneb r2, [r1, #-1] @ read for ownership
219 strneb r2, [r1, #-1] @ write for ownership
221 bic r1, r1, #D_CACHE_LINE_SIZE - 1
223 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
225 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
234 cmp r0, r1
261 cmp r0, r1
285 cmp r0, r1
302 add r1, r1, r0
322 add r1, r1, r0
|
| H A D | proc-arm1022.S | 146 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
147 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
151 subs r1, r1, #1 << 5
173 sub r3, r1, r0 @ calculate total size
180 cmp r0, r1
224 cmp r0, r1
242 add r1, r0, r1
245 cmp r0, r1
270 tst r1, #CACHE_DLINESIZE - 1
271 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
274 cmp r0, r1
296 cmp r0, r1
316 cmp r0, r1
329 add r1, r1, r0
358 subs r1, r1, #CACHE_DLINESIZE
376 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
377 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
381 subs r1, r1, #1 << 5
384 mov r1, #0
386 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
388 mcr p15, 0, r1, c7, c10, 4 @ drain WB
390 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
|
| H A D | cache-v7.S | 39 movw r1, #0x7fff
40 and r2, r1, r0, lsr #13
42 movw r1, #0x3ff
44 and r3, r1, r0, lsr #3 @ NumWays - 1
50 clz r1, r3 @ WayShift
55 mov r5, r3, lsl r1
100 movw r1, #:lower16:(0x410fc090 >> 4) @ ID of ARM Cortex A9 r0p?
101 movt r1, #:upper16:(0x410fc090 >> 4)
102 teq r1, r2, lsr #4 @ test for errata affected core and if so...
128 mov r1, r0, lsr r2 @ extract cache type bits from clidr
129 and r1, r1, #7 @ mask of the bits for current cache only
130 cmp r1, #2 @ see what cache we have at this level
137 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
141 and r2, r1, #7 @ extract the length of the cache lines
144 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
147 ands r7, r7, r1, lsr #13 @ extract max number of the index size
283 cmp r12, r1
292 cmp r12, r1
326 add r1, r0, r1
336 cmp r0, r1
363 tst r1, r3
364 bic r1, r1, r3
365 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
369 cmp r0, r1
391 cmp r0, r1
413 cmp r0, r1
426 add r1, r1, r0
439 add r1, r1, r0
|
| H A D | proc-v6.S | 60 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
61 bic r1, r1, #0x1 @ ...............m
62 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
63 mov r1, #0
64 mcr p15, 0, r1, c7, c5, 4 @ ISB
77 mov r1, #0
78 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
79 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
85 subs r1, r1, #D_CACHE_LINE_SIZE
102 mmid r1, r1 @ get mm->context.id
111 and r1, r1, #0xff
112 orr r1, r1, r2 @ insert into new context ID
114 mcr p15, 0, r1, c13, c0, 1 @ set context ID
165 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
166 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
167 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
|
| H A D | proc-arm940.S | 114 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
115 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
119 subs r1, r1, #1 << 4
164 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
165 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
169 subs r1, r1, #1 << 4
186 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
187 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
191 subs r1, r1, #1 << 4
209 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
210 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
214 subs r1, r1, #1 << 4
231 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
232 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
241 subs r1, r1, #1 << 4
253 add r1, r1, r0
|
| H A D | proc-feroceon.S | 61 ldr r1, __cache_params
71 stmia r1, {r2, r3}
159 ldr r1, __cache_params
160 ldmia r1, {r1, r3}
161 1: orr ip, r1, r3
165 subs r1, r1, #(1 << 5) @ next set
186 sub r3, r1, r0 @ calculate total size
196 cmp r0, r1
232 cmp r0, r1
249 add r1, r0, r1
252 cmp r0, r1
262 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
266 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
291 tst r1, #CACHE_DLINESIZE - 1
292 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
295 cmp r0, r1
305 tst r1, #CACHE_DLINESIZE - 1
306 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
307 cmp r1, r0
308 subne r1, r1, #1 @ top address is inclusive
312 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
331 cmp r0, r1
339 cmp r1, r0
340 subne r1, r1, #1 @ top address is inclusive
344 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
362 cmp r0, r1
370 cmp r1, r0
371 subne r1, r1, #1 @ top address is inclusive
375 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
387 add r1, r1, r0
401 add r1, r1, r0
450 mov r3, r1
454 subs r1, r1, #CACHE_DLINESIZE
537 mcr p15, 0, r1, c2, c0, 0 @ TTB address
|
| H A D | proc-xscale.S | 118 mrc p15, 0, r1, c1, c0, 1
119 bic r1, r1, #1
120 mcr p15, 0, r1, c1, c0, 1
147 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
148 msr cpsr_c, r1 @ reset CPSR
149 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
150 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
151 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
152 bic r1, r1, #0x0086 @ ........B....CA.
153 bic r1, r1, #0x3900 @ ..VIZ..S........
156 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
157 bic r1, r1, #0x0001 @ ...............M
159 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
215 clean_d_cache r0, r1
234 sub r3, r1, r0 @ calculate total size
243 cmp r0, r1
267 cmp r0, r1
289 cmp r0, r1
306 add r1, r0, r1
310 cmp r0, r1
332 tst r1, #CACHELINESIZE - 1
333 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
336 cmp r0, r1
353 cmp r0, r1
371 cmp r0, r1
383 add r1, r1, r0
397 add r1, r1, r0
459 subs r1, r1, #CACHELINESIZE
474 clean_d_cache r1, r2
513 and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_RDONLY) & ~(4 << 2)
516 moveq r1, #L_PTE_MT_WRITETHROUGH
517 and r1, r1, #L_PTE_MT_MASK
519 ldr ip, [ip, r1]
554 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
|
| H A D | proc-arm1020.S | 156 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
157 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
162 subs r1, r1, #1 << 5
184 sub r3, r1, r0 @ calculate total size
193 cmp r0, r1
239 cmp r0, r1
257 add r1, r0, r1
261 cmp r0, r1
288 tst r1, #CACHE_DLINESIZE - 1
290 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
294 cmp r0, r1
317 cmp r0, r1
339 cmp r0, r1
352 add r1, r1, r0
382 subs r1, r1, #CACHE_DLINESIZE
401 mov r1, #0xF @ 16 segments
404 orr ip, ip, r1, LSL #5 @ shift in/up index
411 subs r1, r1, #1
412 cmp r1, #0
416 mov r1, #0
418 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
420 mcr p15, 0, r1, c7, c10, 4 @ drain WB
422 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
|
| H A D | proc-arm1020e.S | 156 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
157 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
161 subs r1, r1, #1 << 5
183 sub r3, r1, r0 @ calculate total size
190 cmp r0, r1
233 cmp r0, r1
251 add r1, r0, r1
254 cmp r0, r1
279 tst r1, #CACHE_DLINESIZE - 1
280 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
283 cmp r0, r1
305 cmp r0, r1
325 cmp r0, r1
338 add r1, r1, r0
367 subs r1, r1, #CACHE_DLINESIZE
386 mov r1, #0xF @ 16 segments
389 orr ip, ip, r1, LSL #5 @ shift in/up index
395 subs r1, r1, #1
396 cmp r1, #0
400 mov r1, #0
402 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
404 mcr p15, 0, r1, c7, c10, 4 @ drain WB
406 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
|
| /linux-4.1.27/arch/sh/kernel/cpu/sh2/ |
| H A D | ex.S | 21 mov.l r1,@-sp
23 mov #no,r1
29 extu.b r1,r1
31 extu.w r1,r1
|
| H A D | entry.S | 41 ! r1
45 ! r1 = vector (pseudo EXPEVT / INTEVT / TRA)
66 mov.l r1,@-r15 ! TRA
89 mov r1,r9 ! save TRA
95 mov.l @(12,r8),r1
96 mov.l r1,@-r15
117 mov.l r1,@-r2 ! TRA
138 mov r1,r9
140 mov.l @(OFF_R1,r15),r1
198 mov.l @(OFF_SP,r0),r1
201 mov.l r3,@-r1
204 mov.l r3,@-r1
212 mov.l r1,@(8,r0)
214 mov.l @r15+, r1
264 mov.l @(r0,r3),r1
266 and r1,r3 ! copy MD bit
268 shll2 r1 ! clear MD bit
269 shlr2 r1
273 mov.l r1,@(4,r2) ! set sr
275 mov.l @(r0,r3),r1
276 mov.l r1,@r2 ! set pc
277 get_current_thread_info r0, r1
278 mov.l $current_thread_info,r1
279 mov.l r0,@r1
281 mov.l @r15+,r1
|
| /linux-4.1.27/arch/arm/mach-pxa/ |
| H A D | standby.S | 23 mov r1, #(PSSR_PH | PSSR_STS)
31 str r1, [r0] @ make sure PSSR_PH/STS are clear
51 mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG)
52 add r1, r1, #0x00100000
62 ldr r2, [r1] @ Dummy read PXA3_MDCNFG
69 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
71 str r0, [r1, #PXA3_DDR_HCAL]
72 1: ldr r0, [r1, #PXA3_DDR_HCAL]
76 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
78 str r0, [r1, #PXA3_RCOMP]
81 str r0, [r1, #PXA3_DMCISR]
83 ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
85 str r0, [r1, #PXA3_DMCIER]
87 ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
90 str r0, [r1, #PXA3_DDR_HCAL]
92 1: ldr r0, [r1, #PXA3_DMCISR]
96 ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
98 str r0, [r1, #PXA3_MDCNFG]
99 1: ldr r0, [r1, #PXA3_MDCNFG]
103 ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
105 str r0, [r1, #PXA3_DDR_HCAL]
107 ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
109 str r0, [r1, #PXA3_DMCIER]
|
| /linux-4.1.27/arch/powerpc/platforms/powermac/ |
| H A D | sleep.S | 62 stw r0,4(r1)
63 stwu r1,-SL_SIZE(r1)
65 stw r0,SL_CR(r1)
66 stw r2,SL_R2(r1)
67 stmw r12,SL_R12(r1)
71 stw r4,SL_MSR(r1)
73 stw r4,SL_SDR1(r1)
77 stw r4,SL_TB(r1)
79 stw r5,SL_TB+4(r1)
86 stw r4,SL_SPRG0(r1)
88 stw r4,SL_SPRG0+4(r1)
90 stw r4,SL_SPRG0+8(r1)
92 stw r4,SL_SPRG0+12(r1)
96 stw r4,SL_DBAT0(r1)
98 stw r4,SL_DBAT0+4(r1)
100 stw r4,SL_DBAT1(r1)
102 stw r4,SL_DBAT1+4(r1)
104 stw r4,SL_DBAT2(r1)
106 stw r4,SL_DBAT2+4(r1)
108 stw r4,SL_DBAT3(r1)
110 stw r4,SL_DBAT3+4(r1)
112 stw r4,SL_IBAT0(r1)
114 stw r4,SL_IBAT0+4(r1)
116 stw r4,SL_IBAT1(r1)
118 stw r4,SL_IBAT1+4(r1)
120 stw r4,SL_IBAT2(r1)
122 stw r4,SL_IBAT2+4(r1)
124 stw r4,SL_IBAT3(r1)
126 stw r4,SL_IBAT3+4(r1)
144 stw r5,SL_PC(r1)
146 tophys(r5,r1)
243 lwz r1,0(r3)
248 * r1 has the physical address of SL_PC(sp).
254 * we do any r1 memory access as we are not sure they
268 subi r1,r1,SL_PC
283 lwz r4,SL_SDR1(r1)
285 lwz r4,SL_SPRG0(r1)
287 lwz r4,SL_SPRG0+4(r1)
289 lwz r4,SL_SPRG0+8(r1)
291 lwz r4,SL_SPRG0+12(r1)
294 lwz r4,SL_DBAT0(r1)
296 lwz r4,SL_DBAT0+4(r1)
298 lwz r4,SL_DBAT1(r1)
300 lwz r4,SL_DBAT1+4(r1)
302 lwz r4,SL_DBAT2(r1)
304 lwz r4,SL_DBAT2+4(r1)
306 lwz r4,SL_DBAT3(r1)
308 lwz r4,SL_DBAT3+4(r1)
310 lwz r4,SL_IBAT0(r1)
312 lwz r4,SL_IBAT0+4(r1)
314 lwz r4,SL_IBAT1(r1)
316 lwz r4,SL_IBAT1+4(r1)
318 lwz r4,SL_IBAT2(r1)
320 lwz r4,SL_IBAT2+4(r1)
322 lwz r4,SL_IBAT3(r1)
324 lwz r4,SL_IBAT3+4(r1)
355 lwz r3,SL_MSR(r1)
359 tovirt(r1,r1)
364 lwz r3,SL_TB(r1)
365 lwz r4,SL_TB+4(r1)
370 lwz r0,SL_CR(r1)
372 lwz r2,SL_R2(r1)
373 lmw r12,SL_R12(r1)
374 addi r1,r1,SL_SIZE
375 lwz r0,4(r1)
|
| /linux-4.1.27/arch/sh/boot/romimage/ |
| H A D | head.S | 47 mov.l extra_data_size, r1
48 add r1, r0
49 mov.l empty_zero_page_dst, r1
60 mov.l r4, @r1
61 mov.l r5, @(4, r1)
62 mov.l r6, @(8, r1)
63 mov.l r7, @(12, r1)
65 add #16,r1
70 mov #1, r1
71 shld r4, r1
73 add r1, r0
74 mov.l extra_data_size, r1
75 add r1, r0
|
| /linux-4.1.27/arch/arm/mach-shmobile/ |
| H A D | headsmp.S | 28 ldr r1, 1f
29 bx r1
50 mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR
51 and r0, r1, r0 @ r0 = cpu_logical_map() value
52 mov r1, #0 @ r1 = CPU index
58 ldr r8, [r5, r1, lsl #2]
62 ldr r9, [r6, r1, lsl #2]
67 add r1, r1, #1
68 cmp r1, #NR_CPUS
74 ldr r0, [r7, r1, lsl #2]
|
| H A D | headsmp-scu.S | 30 mrc p15, 0, r1, c0, c0, 5 @ read MIPDR
31 and r1, r1, #3 @ mask out cpu ID
32 lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
35 lsl r3, r3, r1
|
| /linux-4.1.27/arch/blackfin/mach-bf561/ |
| H A D | atomic.S | 41 r1 = -L1_CACHE_BYTES; define
42 r1 = r0 & r1; define
51 p0 = r1;
87 * r1 = address of atomic data to flush and invalidate (32bit).
95 r1 = 0; define
96 [p0] = r1;
194 * r1 = address of atomic data
203 p1 = r1;
210 r1 = 1; define
211 r1 <<= r2;
212 r2 = ~r1;
214 r1 = [p1]; define
215 r1 >>= 28; /* CPU fingerprints are stored in the high nibble. */
216 r6 = r1 & r2;
217 r1 = [p1]; define
218 r1 <<= 4;
219 r1 >>= 4;
220 [p1] = r1;
227 r1 = 0; define
228 [p0] = r1;
254 * r1 = address of atomic data
260 p1 = r1;
263 r1 = 1; define
264 r1 <<= r2;
266 r2 = r1 | r2;
268 r1 = p1; define
285 r1 = p1; define
302 r1 = p1; define
337 r1 = p1; define
372 r1 = p1; define
392 r1 = [p1]; define
393 r1 += -1;
394 [p1] = r1;
395 cc = r1 < 0;
397 r1 = p1; define
407 r1 += 1;
408 [p1] = r1;
410 r1 = p1; define
415 r1 = [p1]; define
416 cc = r1 < 2;
430 r1 = [p1]; define
431 cc = r1 <= 0;
433 r1 += -1;
434 [p1] = r1;
435 r1 = p1; define
445 r1 = p1; define
465 r1 = [p1]; define
466 r1 += 1;
467 [p1] = r1;
468 r1 = p1; define
486 r1 = [p1]; define
487 r1 = r1 - r3; define
489 r2 = r1;
494 cc = r1 == 0;
497 [p1] = r1;
498 r1 = p1; define
508 r1 = p1; define
513 r1 = [p1]; define
515 r1 <<= 4;
516 r1 >>= 4;
518 cc = r1 == r3;
532 r1 = [p1]; define
535 cc = r1 == r2;
538 r1 >>= 28;
539 r1 <<= 28;
541 r1 = 0; define
543 [p1] = r1;
544 r1 = p1; define
555 r1 = p1; define
573 r1 = [p1]; define
574 r1 = r1 + r3; define
575 [p1] = r1;
576 r1 = p1; define
588 * r1 = value
595 r3 = r1;
601 r1 = p1; define
610 * r1 = mask
618 r3 = ~r1;
625 r1 = p1; define
634 * r1 = mask
642 r3 = r1;
649 r1 = p1; define
658 * r1 = mask
666 r3 = r1;
673 r1 = p1; define
682 * r1 = mask
692 r3 = r1;
693 r1 = -L1_CACHE_BYTES; define
694 r1 = r0 & r1; define
695 p0 = r1;
707 * r1 = value
714 r3 = r1; \
720 r1 = p1; \ define
740 * r1 = new
752 r3 = r1; \
760 r1 = p1; \ define
781 * r1 = bitnr
787 r2 = r1;
788 r1 = 1; define
789 r1 <<= r2;
795 * r1 = bitnr
801 r2 = r1;
802 r1 = 1; define
803 r1 <<= r2;
809 * r1 = bitnr
815 r2 = r1;
816 r1 = 1; define
817 r1 <<= r2;
823 * r1 = bitnr
830 [--sp] = r1;
832 r1 = [sp++]; define
834 r2 <<= r1;
846 * r1 = bitnr
853 [--sp] = r1;
855 r1 = [sp++]; define
857 r2 <<= r1;
869 * r1 = bitnr
877 [--sp] = r1;
879 r1 = [sp++]; define
881 r2 <<= r1;
893 * r1 = bitnr
902 r2 = r1;
903 r1 = 1; define
904 r1 <<= r2;
917 r1 = -L1_CACHE_BYTES; define
918 r1 = r0 & r1; define
919 p0 = r1;
|
| /linux-4.1.27/arch/m32r/boot/compressed/ |
| H A D | head.S | 34 seth r1, #high(CONFIG_MEMORY_START + 0x00400000) /* Start address */
36 sub r12, r1 /* difference */
44 ldi r1, #low(got_len)
45 srli r1, #2
46 beqz r1, 2f
53 addi r1, #-1
54 bnez r1, 1b
72 mv r4, r3 || ldi r1, #0
80 st r1, @+r2 || addi r4, #-1
81 st r1, @+r2
82 st r1, @+r2
83 st r1, @+r2 || cmpeq r1, r4 ; R4 = 0?
90 stb r1, @r2 || addi r4, #-1
105 ldi r1, #0 ; clear R1 for longwords store
109 st r1, @+r2 ; yep, zero out another longword
116 seth r1, #high(end)
117 or3 r1, r1, #low(end)
118 add r1, r12
119 mv sp, r1
126 seth r1, #high(zimage_data)
127 or3 r1, r1, #low(zimage_data)
128 add r1, r12
138 ldi r1, 0xd0 ; invalidate i-cache, copy back d-cache
139 stb r1, @r0
143 ldi r1, 0x0100 ; invalidate
144 stb r1, @r0
148 ldi r1, 0x0700 ; invalidate i-cache, copy back d-cache
149 sth r1, @r0
158 seth r1, #high(CONFIG_MEMORY_START)
159 or r0, r1
|
| /linux-4.1.27/arch/cris/arch-v32/mach-a3/ |
| H A D | dram_init.S | 34 move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1
35 move.d $r1, [$r0]
45 REG_STATE(ddr2, rw_phy_ctrl, cal_rst, yes), $r1
46 move.d $r1, [$r0]
47 move.d REG_STATE(ddr2, rw_phy_ctrl, cal_start, yes), $r1
48 move.d $r1, [$r0]
59 movu.b [$r2+], $r1
62 lslq 16, $r1
63 or.d $r3, $r1
64 move.d $r1, [$r0]
75 move.d CONFIG_ETRAX_DDR2_TIMING, $r1
76 move.d $r1, [$r0]
80 move.d CONFIG_ETRAX_DDR2_LATENCY, $r1
81 move.d $r1, [$r0]
85 move.d CONFIG_ETRAX_DDR2_CONFIG, $r1
86 move.d $r1, [$r0]
|
| /linux-4.1.27/arch/arm/mach-shmobile/include/mach/ |
| H A D | zboot_macros.h | 11 LDR r1, 2f variable
12 STR r1, [r0] variable
22 LDR r1, 2f variable
23 STRH r1, [r0] variable
33 LDR r1, 2f variable
34 STRB r1, [r0] variable
43 LDR r1, 1f variable
45 STR r0, [r1]
47 LDR r0, [r1]
59 LDR r1, 1f variable
68 LDR r1, 3f variable
72 AND r3, r1, r3 variable
|
| /linux-4.1.27/arch/arc/include/asm/ |
| H A D | tlb-mmu1.h | 27 ; r1 = TLBPD0 from TLB_RELOAD above
34 ; as r0/r1 saves above
40 asr r0,r1,12 ; get set # <<1, note bit 12=R=0 variable
52 /* r1 = data TLBPD0 at this point */
54 xor r0,r0,r1 /* compare set # */
60 ; lr r1,[ARC_REG_TLBPD0] /* Data VPN+ASID - already in r1 from TLB_RELOAD*/ variable
61 and r1,r1,0xff /* Data ASID */ variable
62 or r0,r0,r1 /* Instruction address + Data ASID */
64 lr r1,[ARC_REG_TLBPD0] /* save TLBPD0 containing data TLB*/ variable
68 sr r1,[ARC_REG_TLBPD0] /* restore TLBPD0 */ variable
82 mov_s r3, r1 ; save PD0 prepared by TLB_RELOAD in r3 variable
85 bmsk r1,r3,7 /* Data ASID, bits 7-0 */ variable
86 or_s r0,r0,r1 /* Instruction address + Data ASID */
94 lr r1,[ARC_REG_TLBINDEX] /* r1 = index where MMU wants to put data */ variable
95 cmp r0,r1 /* if no match on indices, go around */
96 xor.eq r1,r1,1 /* flip bottom bit of data index */ variable
97 sr r1,[ARC_REG_TLBINDEX] /* and put it back */ variable
|
| /linux-4.1.27/arch/s390/kernel/vdso64/ |
| H A D | clock_gettime.S | 42 lg %r1,1(%r15)
43 sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */
44 msgf %r1,__VDSO_TK_MULT(%r5) /* * tk->mult */
45 alg %r1,__VDSO_WTOM_NSEC(%r5)
46 srlg %r1,%r1,0(%r2) /* >> tk->shift */
50 1: clg %r1,0(%r5)
52 slg %r1,0(%r5)
56 stg %r1,8(%r3) /* store tp->tv_nsec */
66 lg %r1,__VDSO_WTOM_CRS_NSEC(%r5)
76 lg %r1,__VDSO_XTIME_CRS_NSEC(%r5)
87 lg %r1,1(%r15)
88 sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */
89 msgf %r1,__VDSO_TK_MULT(%r5) /* * tk->mult */
90 alg %r1,__VDSO_XTIME_NSEC(%r5) /* + tk->xtime_nsec */
91 srlg %r1,%r1,0(%r2) /* >> tk->shift */
96 6: clg %r1,0(%r5)
98 slg %r1,0(%r5)
102 stg %r1,8(%r3) /* store tp->tv_nsec */
125 algr %r1,%r0 /* r1 = cputime as TOD value */
126 mghi %r1,1000 /* convert to nanoseconds */
127 srlg %r1,%r1,12 /* r1 = cputime in nanosec */
128 lgr %r4,%r1
130 srlg %r1,%r1,9 /* divide by 1000000000 */
142 12: lghi %r1,__NR_clock_gettime
|
| H A D | gettimeofday.S | 33 lg %r1,1(%r15)
34 sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */
35 msgf %r1,__VDSO_TK_MULT(%r5) /* * tk->mult */
36 alg %r1,__VDSO_XTIME_NSEC(%r5) /* + tk->xtime_nsec */
41 srlg %r1,%r1,0(%r5) /* >> tk->shift */
43 2: clg %r1,0(%r5)
45 slg %r1,0(%r5)
|
| H A D | clock_getres.S | 22 larl %r1,4f
27 larl %r1,3f
41 lg %r0,0(%r1)
46 2: lghi %r1,__NR_clock_getres /* fallback to svc */
|
| /linux-4.1.27/arch/nios2/kernel/ |
| H A D | head.S | 68 movia r1, NIOS2_ICACHE_SIZE
72 initi r1
73 sub r1, r1, r2
74 bgt r1, r0, icache_init
118 movia r1, NIOS2_DCACHE_SIZE
122 initd 0(r1)
123 sub r1, r1, r2
124 bgt r1, r0, dcache_init
126 nextpc r1 /* Find out where we are */
129 beq r1, r2,finish_move /* We are running in RAM done */
130 addi r1, r1,(_start - chkadr) /* Source */
134 loop_move: /* r1: src, r2: dest, r3: last dest */
135 ldw r8, 0(r1) /* load a word from [r1] */
138 addi r1, r1, 4 /* inc the src addr */
142 movia r1, finish_move /* VMA(_start)->l1 */
143 jmp r1 /* jmp to _start */
152 movia r1, __bss_stop
156 bne r1, r2, 1b
158 movia r1, init_thread_union /* set stack at top of the task union */
159 addi sp, r1, THREAD_SIZE
161 stw r1, 0(r2)
163 movia r1, nios2_boot_init /* save args r4-r7 passed from u-boot */
164 callr r1
166 movia r1, start_kernel /* call start_kernel as a subroutine */
167 callr r1
|
| H A D | entry.S | 189 movui r1, __NR_syscalls
190 bgeu r2, r1, ret_invsyscall
191 slli r1, r2, 2
193 add r1, r1, r11
194 ldw r1, %lo(sys_call_table)(r1)
195 beq r1, r0, ret_invsyscall
203 callr r1
214 movi r1, 0
217 movi r1, 1
220 stw r1, PT_R7(sp)
224 ldw r1, PT_ESTATUS(sp)
226 TSTBNZ r1, r1, ESTATUS_EU, Luser_return
261 slli r1, r2, 2
263 add r1, r1, r11
264 ldw r1, %lo(sys_call_table)(r1)
266 callr r1
277 movi r1, 0
280 movi r1, 1
283 stw r1, PT_R7(sp)
295 BTBZ r1, r10, TIF_NEED_RESCHED, Lsignal_return
302 ANDI32 r1, r10, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME
303 beq r1, r0, restore_all
365 ldw r1, PT_ESTATUS(sp) /* check if returning to kernel */
366 TSTBNZ r1, r1, ESTATUS_EU, Luser_return
369 GET_THREAD_INFO r1
370 ldw r4, TI_PREEMPT_COUNT(r1)
372 ldw r4, TI_FLAGS(r1) /* ? Need resched set */
488 GET_THREAD_INFO r1
489 stw r1, 0(r24)
|
| /linux-4.1.27/arch/arm/mach-imx/ |
| H A D | headsmp.S | 21 ldr r1, [r0]
22 add r1, r1, r0 @ r1 = physical &g_diag_reg
23 ldr r0, [r1]
|
| /linux-4.1.27/arch/powerpc/kernel/ |
| H A D | entry_32.S | 96 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
120 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
151 addi r11,r1,STACK_FRAME_OVERHEAD
166 CURRENT_THREAD_INFO(r9, r1)
183 cmplw r1,r9 /* if r1 <= ksp_limit */
187 CURRENT_THREAD_INFO(r9, r1)
209 lwz r12,_MSR(r1)
221 * r3 can be different from GPR3(r1) at this point, r9 and r11
228 stwu r1,-32(r1)
229 stw r9,8(r1)
230 stw r11,12(r1)
231 stw r3,16(r1)
232 stw r4,20(r1)
233 stw r5,24(r1)
235 lwz r5,24(r1)
236 lwz r4,20(r1)
237 lwz r3,16(r1)
238 lwz r11,12(r1)
239 lwz r9,8(r1)
240 addi r1,r1,32
241 lwz r0,GPR0(r1)
242 lwz r6,GPR6(r1)
243 lwz r7,GPR7(r1)
244 lwz r8,GPR8(r1)
277 cmplw r1,r12
278 ble 5b /* r1 <= &_end is OK */
280 addi r3,r1,STACK_FRAME_OVERHEAD
281 lis r1,init_thread_union@ha
282 addi r1,r1,init_thread_union@l
283 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
301 stw r3,ORIG_GPR3(r1)
303 stw r12,RESULT(r1)
304 lwz r11,_CCR(r1) /* Clear SO bit in CR */
306 stw r11,_CCR(r1)
321 lwz r0,GPR0(r1)
322 lwz r3,GPR3(r1)
323 lwz r4,GPR4(r1)
325 lwz r5,GPR5(r1)
326 lwz r6,GPR6(r1)
327 lwz r7,GPR7(r1)
328 lwz r8,GPR8(r1)
332 CURRENT_THREAD_INFO(r10, r1)
344 addi r9,r1,STACK_FRAME_OVERHEAD
350 CURRENT_THREAD_INFO(r12, r1)
362 lwz r11,_CCR(r1) /* Load CR */
365 stw r11,_CCR(r1)
367 lwz r8,_MSR(r1)
375 stw r3,GPR3(r1)
377 lwz r3,GPR3(r1)
397 lwarx r7,0,r1
399 stwcx. r0,0,r1 /* to clear the reservation */
400 lwz r4,_LINK(r1)
401 lwz r5,_CCR(r1)
404 lwz r7,_NIP(r1)
406 lwz r2,GPR2(r1)
407 lwz r1,GPR1(r1)
424 REST_NVGPRS(r1)
431 REST_NVGPRS(r1)
442 SAVE_NVGPRS(r1)
444 stw r0,_TRAP(r1)
445 addi r3,r1,STACK_FRAME_OVERHEAD
453 lwz r3,GPR3(r1)
454 lwz r4,GPR4(r1)
455 lwz r5,GPR5(r1)
456 lwz r6,GPR6(r1)
457 lwz r7,GPR7(r1)
458 lwz r8,GPR8(r1)
459 REST_NVGPRS(r1)
465 REST_NVGPRS(r1)
471 lwz r11,_CCR(r1) /* Load CR */
474 stw r11,_CCR(r1)
476 1: stw r6,RESULT(r1) /* Save result */
477 stw r3,GPR3(r1) /* Update return value */
506 lwz r4,_TRAP(r1)
509 SAVE_NVGPRS(r1)
511 stw r4,_TRAP(r1)
513 addi r3,r1,STACK_FRAME_OVERHEAD
524 SAVE_NVGPRS(r1)
525 lwz r0,_TRAP(r1)
527 stw r0,_TRAP(r1) /* register set saved */
532 SAVE_NVGPRS(r1)
533 lwz r0,_TRAP(r1)
535 stw r0,_TRAP(r1) /* register set saved */
540 SAVE_NVGPRS(r1)
541 lwz r0,_TRAP(r1)
543 stw r0,_TRAP(r1) /* register set saved */
548 SAVE_NVGPRS(r1)
549 lwz r0,_TRAP(r1)
551 stw r0,_TRAP(r1) /* register set saved */
562 stw r4,_DAR(r1)
563 addi r3,r1,STACK_FRAME_OVERHEAD
567 SAVE_NVGPRS(r1)
568 lwz r0,_TRAP(r1)
570 stw r0,_TRAP(r1)
572 addi r3,r1,STACK_FRAME_OVERHEAD
573 lwz r4,_DAR(r1)
598 stwu r1,-INT_FRAME_SIZE(r1)
600 stw r0,INT_FRAME_SIZE+4(r1)
602 SAVE_NVGPRS(r1)
603 stw r0,_NIP(r1) /* Return to switch caller */
625 1: stw r11,_MSR(r1)
627 stw r10,_CCR(r1)
628 stw r1,KSP(r3) /* Set old stack pointer */
641 lwz r1,KSP(r4) /* Load new stack pointer */
660 lwz r0,_CCR(r1)
663 REST_NVGPRS(r1)
665 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
667 addi r1,r1,INT_FRAME_SIZE
725 addi r3,r1,STACK_FRAME_OVERHEAD
735 REST_NVGPRS(r1)
748 lwz r3,_MSR(r1) /* Returning to user mode? */
754 CURRENT_THREAD_INFO(r9, r1)
773 CURRENT_THREAD_INFO(r9, r1)
778 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
780 lwz r3,GPR1(r1)
782 mr r4,r1 /* src: current exception frame */
783 mr r1,r3 /* Reroute the trampoline frame to r1 */
795 lwz r5,GPR1(r1)
817 lwz r3,_MSR(r1)
828 CURRENT_THREAD_INFO(r9, r1)
856 lwz r9,_MSR(r1)
877 stwu r1,-32(r1)
879 stw r0,4(r1)
880 stwu r1,-32(r1)
882 lwz r1,0(r1)
883 lwz r1,0(r1)
884 lwz r9,_MSR(r1)
888 lwz r0,GPR0(r1)
889 lwz r2,GPR2(r1)
890 REST_4GPRS(3, r1)
891 REST_2GPRS(7, r1)
893 lwz r10,_XER(r1)
894 lwz r11,_CTR(r1)
898 PPC405_ERR77(0,r1)
900 lwarx r11,0,r1
902 stwcx. r0,0,r1 /* to clear the reservation */
908 lwz r10,_CCR(r1)
909 lwz r11,_LINK(r1)
927 lwz r12,_NIP(r1)
931 REST_4GPRS(9, r1)
932 lwz r1,GPR1(r1)
946 lwz r11,_LINK(r1)
948 lwz r10,_CCR(r1)
950 REST_2GPRS(9, r1)
953 lwz r11,_NIP(r1)
954 lwz r12,_MSR(r1)
958 REST_2GPRS(11, r1)
959 lwz r1,GPR1(r1)
972 * running with r1 pointing into critical_stack, not the current
986 tophys(r1, r1);
992 REST_NVGPRS(r1); \
993 lwz r3,_MSR(r1); \
997 lwz r0,GPR0(r1); \
998 lwz r2,GPR2(r1); \
999 REST_4GPRS(3, r1); \
1000 REST_2GPRS(7, r1); \
1001 lwz r10,_XER(r1); \
1002 lwz r11,_CTR(r1); \
1005 PPC405_ERR77(0,r1); \
1006 stwcx. r0,0,r1; /* to clear the reservation */ \
1007 lwz r11,_LINK(r1); \
1009 lwz r10,_CCR(r1); \
1012 lwz r9,_DEAR(r1); \
1013 lwz r10,_ESR(r1); \
1016 lwz r11,_NIP(r1); \
1017 lwz r12,_MSR(r1); \
1020 lwz r9,GPR9(r1); \
1021 lwz r12,GPR12(r1); \
1022 lwz r10,GPR10(r1); \
1023 lwz r11,GPR11(r1); \
1024 lwz r1,GPR1(r1); \
1030 lwz r9,_##exc_lvl_srr0(r1); \
1031 lwz r10,_##exc_lvl_srr1(r1); \
1038 lwz r11,MAS7(r1); \
1044 lwz r9,MAS0(r1); \
1045 lwz r10,MAS1(r1); \
1046 lwz r11,MAS2(r1); \
1048 lwz r9,MAS3(r1); \
1050 lwz r10,MAS6(r1); \
1057 lwz r9,MMUCR(r1); \
1084 lwz r10,SAVED_KSP_LIMIT(r1)
1093 lwz r10,SAVED_KSP_LIMIT(r1)
1096 CURRENT_THREAD_INFO(r10, r1)
1107 lwz r10,SAVED_KSP_LIMIT(r1)
1130 CURRENT_THREAD_INFO(r9, r1)
1171 CURRENT_THREAD_INFO(r9, r1)
1182 lwz r3,_TRAP(r1)
1185 SAVE_NVGPRS(r1)
1187 stw r3,_TRAP(r1)
1188 2: addi r3,r1,STACK_FRAME_OVERHEAD
1191 REST_NVGPRS(r1)
1219 lwz r3,_TRAP(r1)
1222 SAVE_NVGPRS(r1)
1224 stw r3,_TRAP(r1)
1225 4: addi r3,r1,STACK_FRAME_OVERHEAD
1247 stwu r1,-INT_FRAME_SIZE(r1)
1249 stw r0,INT_FRAME_SIZE+4(r1)
1254 tophys(r7,r1)
1258 stw r9,8(r1)
1268 1: tophys(r9,r1)
1272 addi r1,r1,INT_FRAME_SIZE
1299 lwz r0, 4(r1)
1347 lwz r4, 44(r1)
1351 lwz r3,52(r1)
1360 stw r3,52(r1)
1368 stwu r1, -32(r1)
1369 stw r3, 20(r1)
1370 stw r4, 16(r1)
1371 stw r31, 12(r1)
1372 mr r31, r1
1380 lwz r3, 20(r1)
1381 lwz r4, 16(r1)
1382 lwz r31,12(r1)
1383 lwz r1, 0(r1)
|
| H A D | entry_64.S | 55 mr r10,r1
56 addi r1,r1,-INT_FRAME_SIZE
58 ld r1,PACAKSAVE(r13)
59 1: std r10,0(r1)
60 std r11,_NIP(r1)
61 std r12,_MSR(r1)
62 std r0,GPR0(r1)
63 std r10,GPR1(r1)
66 2: std r2,GPR2(r1)
67 std r3,GPR3(r1)
69 std r4,GPR4(r1)
70 std r5,GPR5(r1)
71 std r6,GPR6(r1)
72 std r7,GPR7(r1)
73 std r8,GPR8(r1)
75 std r11,GPR9(r1)
76 std r11,GPR10(r1)
77 std r11,GPR11(r1)
78 std r11,GPR12(r1)
79 std r11,_XER(r1)
80 std r11,_CTR(r1)
81 std r9,GPR13(r1)
89 std r10,_LINK(r1)
90 std r11,_TRAP(r1)
91 std r3,ORIG_GPR3(r1)
92 std r2,_CCR(r1)
94 addi r9,r1,STACK_FRAME_OVERHEAD
108 REST_GPR(0,r1)
109 REST_4GPRS(3,r1)
110 REST_2GPRS(7,r1)
111 addi r9,r1,STACK_FRAME_OVERHEAD
141 std r10,SOFTE(r1)
143 CURRENT_THREAD_INFO(r11, r1)
173 std r3,RESULT(r1)
174 CURRENT_THREAD_INFO(r12, r1)
176 ld r8,_MSR(r1)
207 ld r5,_CCR(r1)
210 ld r7,_NIP(r1)
212 stdcx. r0,0,r1 /* to clear the reservation */
215 ld r4,_LINK(r1)
220 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
221 1: ld r2,GPR2(r1)
222 ld r1,GPR1(r1)
233 std r5,_CCR(r1)
239 addi r3,r1,STACK_FRAME_OVERHEAD
247 ld r3,GPR3(r1)
248 ld r4,GPR4(r1)
249 ld r5,GPR5(r1)
250 ld r6,GPR6(r1)
251 ld r7,GPR7(r1)
252 ld r8,GPR8(r1)
253 addi r9,r1,STACK_FRAME_OVERHEAD
254 CURRENT_THREAD_INFO(r10, r1)
271 REST_NVGPRS(r1)
277 ld r5,_CCR(r1)
280 std r5,_CCR(r1)
281 1: std r3,GPR3(r1)
310 addi r3,r1,STACK_FRAME_OVERHEAD
316 ld r11,_TRAP(r1)
319 SAVE_NVGPRS(r1)
321 std r0,_TRAP(r1)
366 REST_NVGPRS(r1)
372 REST_NVGPRS(r1)
403 std r0,16(r1)
404 stdu r1,-SWITCH_FRAME_SIZE(r1)
406 SAVE_8GPRS(14, r1)
407 SAVE_10GPRS(22, r1)
428 1: std r20,_NIP(r1)
430 std r23,_CCR(r1)
431 std r1,KSP(r3) /* Set old stack pointer */
461 ldarx r6,0,r1
478 clrrdi r9,r1,28 /* get current sp ESID */
481 clrrdi r9,r1,40 /* get current sp 1T ESID */
529 mr r1,r8 /* start using new stack pointer */
573 ld r6,_CCR(r1)
577 REST_8GPRS(14, r1)
578 REST_10GPRS(22, r1)
582 ld r7,_NIP(r1) /* Return to _switch caller in new task */
584 addi r1,r1,SWITCH_FRAME_SIZE
589 ld r11,_TRAP(r1)
592 REST_NVGPRS(r1)
607 CURRENT_THREAD_INFO(r9, r1)
608 ld r3,_MSR(r1)
648 addi r3,r1,STACK_FRAME_OVERHEAD
661 addi r3,r1,STACK_FRAME_OVERHEAD
670 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
672 lwz r3,GPR1(r1)
674 mr r4,r1 /* src: current exception frame */
675 mr r1,r3 /* Reroute the trampoline frame to r1 */
687 lwz r5,GPR1(r1)
706 ld r0,SOFTE(r1)
719 CURRENT_THREAD_INFO(r9, r1)
745 ld r5,SOFTE(r1)
786 stdcx. r0,0,r1 /* to clear the reservation */
788 ldarx r4,0,r1
799 ld r3,_MSR(r1)
800 ld r4,_CTR(r1)
801 ld r0,_LINK(r1)
804 ld r4,_XER(r1)
807 REST_8GPRS(5, r1)
842 REST_GPR(13, r1)
846 ld r2,_CCR(r1)
848 ld r2,_NIP(r1)
851 ld r0,GPR0(r1)
852 ld r2,GPR2(r1)
853 ld r3,GPR3(r1)
854 ld r4,GPR4(r1)
855 ld r1,GPR1(r1)
870 ld r3,_MSR(r1)
902 ld r4,_TRAP(r1)
905 std r4,_TRAP(r1)
913 addi r3,r1,STACK_FRAME_OVERHEAD;
918 addi r3,r1,STACK_FRAME_OVERHEAD;
923 addi r3,r1,STACK_FRAME_OVERHEAD;
938 addi r3,r1,STACK_FRAME_OVERHEAD;
945 addi r3,r1,STACK_FRAME_OVERHEAD
960 std r0,16(r1)
961 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
967 SAVE_GPR(2, r1) /* Save the TOC */
968 SAVE_GPR(13, r1) /* Save paca */
969 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
970 SAVE_10GPRS(22, r1) /* ditto */
973 std r4,_CCR(r1)
975 std r5,_CTR(r1)
977 std r6,_XER(r1)
979 std r7,_DAR(r1)
981 std r8,_DSISR(r1)
1008 std r1,PACAR1(r13)
1053 ld r1,PACAR1(r4) /* Restore our SP */
1066 REST_GPR(2, r1) /* Restore the TOC */
1067 REST_GPR(13, r1) /* Restore paca */
1068 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1069 REST_10GPRS(22, r1) /* ditto */
1073 ld r4,_CCR(r1)
1075 ld r5,_CTR(r1)
1077 ld r6,_XER(r1)
1079 ld r7,_DAR(r1)
1081 ld r8,_DSISR(r1)
1084 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
1085 ld r0,16(r1) /* get return address */
1094 std r0,16(r1)
1095 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
1101 SAVE_GPR(2, r1)
1102 SAVE_GPR(13, r1)
1103 SAVE_8GPRS(14, r1)
1104 SAVE_10GPRS(22, r1)
1107 std r10,_CCR(r1)
1108 std r11,_MSR(r1)
1135 /* Just make sure that r1 top 32 bits didn't get
1138 rldicl r1,r1,0,32
1141 ld r0,_MSR(r1)
1146 REST_GPR(2, r1)
1147 REST_GPR(13, r1)
1148 REST_8GPRS(14, r1)
1149 REST_10GPRS(22, r1)
1150 ld r4,_CCR(r1)
1153 addi r1,r1,PROM_FRAME_SIZE
1154 ld r0,16(r1)
1167 ld r11, 0(r1)
1168 stdu r1, -112(r1)
1169 std r3, 128(r1)
1182 ld r0, 128(r1)
1184 addi r1, r1, 112
1191 ld r11, 0(r1)
1192 stdu r1, -112(r1)
1193 std r3, 128(r1)
1208 ld r0, 128(r1)
1210 addi r1, r1, 112
1219 ld r4, 128(r1)
1223 ld r11, 112(r1)
1233 ld r11, 112(r1)
1236 ld r0, 128(r1)
1238 addi r1, r1, 112
1243 std r4, -32(r1)
1244 std r3, -24(r1)
1246 std r2, -16(r1)
1247 std r31, -8(r1)
1248 mr r31, r1
1249 stdu r1, -112(r1)
1263 ld r1, 0(r1)
1264 ld r4, -32(r1)
1265 ld r3, -24(r1)
1266 ld r2, -16(r1)
1267 ld r31, -8(r1)
|
| H A D | idle_power7.S | 44 std r0,0(r1); \
46 ld r0,0(r1); \
87 std r0,16(r1)
88 stdu r1,-INT_FRAME_SIZE(r1)
89 std r0,_LINK(r1)
90 std r0,_NIP(r1)
111 addi r1,r1,INT_FRAME_SIZE
112 ld r0,16(r1)
129 SAVE_GPR(2, r1)
130 SAVE_NVGPRS(r1)
132 std r4,_CCR(r1)
133 std r9,_MSR(r1)
134 std r1,PACAR1(r13)
221 std r3,_SDR1(r1)
223 std r3,_RPR(r1)
225 std r3,_SPURR(r1)
227 std r3,_PURR(r1)
229 std r3,_TSCR(r1)
231 std r3,_DSCR(r1)
233 std r3,_AMOR(r1)
235 std r3,_WORT(r1)
237 std r3,_WORC(r1)
278 ld r1,PACAR1(r13); \
279 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
282 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
288 ld r1,PACAR1(r13)
356 ld r4,_SDR1(r1)
358 ld r4,_RPR(r1)
360 ld r4,_AMOR(r1)
399 ld r4,_TSCR(r1)
401 ld r4,_WORC(r1)
437 ld r4,_SPURR(r1)
439 ld r4,_PURR(r1)
441 ld r4,_DSCR(r1)
443 ld r4,_WORT(r1)
464 REST_NVGPRS(r1)
465 REST_GPR(2, r1)
466 ld r3,_CCR(r1)
467 ld r4,_MSR(r1)
468 ld r5,_NIP(r1)
469 addi r1,r1,INT_FRAME_SIZE
488 ld r1,PACAR1(r13)
492 REST_NVGPRS(r1)
493 REST_GPR(2, r1)
494 ld r6,_CCR(r1)
495 ld r4,_MSR(r1)
496 ld r5,_NIP(r1)
497 addi r1,r1,INT_FRAME_SIZE
514 ld r1,PACAR1(r13)
515 ld r6,_CCR(r1)
516 ld r4,_MSR(r1)
517 ld r5,_NIP(r1)
518 addi r1,r1,INT_FRAME_SIZE
|
| H A D | idle_power4.S | 47 std r0,16(r1)
48 stdu r1,-128(r1)
50 addi r1,r1,128
51 ld r0,16(r1)
62 CURRENT_THREAD_INFO(r9, r1)
|
| H A D | tm.S | 103 stw r6, 8(r1)
104 std r0, 16(r1)
105 std r2, STK_GOT(r1)
106 stdu r1, -TM_FRAME_SIZE(r1)
108 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
110 std r3, STK_PARAM(R3)(r1)
111 SAVE_NVGPRS(r1)
133 std r14, TM_FRAME_L0(r1)
136 std r1, PACAR1(r13)
192 /* Stash the checkpointed r1 away in paca tm_scratch and get the real
195 std r1, PACATMSCRATCH(r13)
196 ld r1, PACAR1(r13)
199 std r11, GPR11(r1) /* Temporary stash */
204 std r7, GPR7(r1) /* Temporary stash */
205 std r12, GPR12(r1) /* '' '' '' */
206 ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
224 ld r3, PACATMSCRATCH(r13) /* user r1 */
225 ld r4, GPR7(r1) /* user r7 */
226 ld r5, GPR11(r1) /* user r11 */
227 ld r6, GPR12(r1) /* user r12 */
281 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
286 REST_NVGPRS(r1)
288 addi r1, r1, TM_FRAME_SIZE
289 lwz r4, 8(r1)
290 ld r0, 16(r1)
293 ld r2, STK_GOT(r1)
313 stw r5, 8(r1)
314 std r0, 16(r1)
315 std r2, STK_GOT(r1)
316 stdu r1, -TM_FRAME_SIZE(r1)
318 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
321 SAVE_NVGPRS(r1)
332 SET_SCRATCH0(r1)
419 * here before we load up the userspace r1 so any bugs we hit will get
460 GET_SCRATCH0(r1)
466 REST_NVGPRS(r1)
468 addi r1, r1, TM_FRAME_SIZE
469 lwz r4, 8(r1)
470 ld r0, 16(r1)
473 ld r2, STK_GOT(r1)
|
| H A D | idle_e500.S | 24 CURRENT_THREAD_INFO(r3, r1)
52 stwu r1,-16(r1)
54 stw r0,20(r1)
56 lwz r0,20(r1)
57 addi r1,r1,16
99 CURRENT_THREAD_INFO(r12, r1)
|
| H A D | idle_book3e.S | 28 std r0,16(r1)
45 stdu r1,-128(r1)
47 addi r1,r1,128
58 ld r0,16(r1)
65 CURRENT_THREAD_INFO(r11, r1)
|
| H A D | exceptions-64e.S | 62 std reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
65 ld reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
75 ld r3,_MSR(r1)
82 CURRENT_THREAD_INFO(r12, r1)
144 ld r10,_NIP(r1)
146 ld r10,_MSR(r1)
152 ld r3,_MSR(r1)
180 REST_NVGPRS(r1)
210 ld r5,SOFTE(r1)
235 stdcx. r0,0,r1 /* to clear the reservation */
237 REST_4GPRS(2, r1)
238 REST_4GPRS(6, r1)
240 ld r10,_CTR(r1)
241 ld r11,_XER(r1)
250 ld r10,_LINK(r1)
251 ld r11,_CCR(r1)
252 ld r0,GPR13(r1)
256 ld r10,GPR10(r1)
257 ld r11,GPR11(r1)
258 ld r12,GPR12(r1)
263 ld r10,_NIP(r1)
264 ld r11,_MSR(r1)
265 ld r0,GPR0(r1)
266 ld r1,GPR1(r1)
293 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
297 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
298 1: cmpdi cr1,r1,0; /* check if SP makes sense */ \
304 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
313 ld r1,PACA_CRIT_STACK(r13); \
314 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
319 ld r1,PACA_DBG_STACK(r13); \
320 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
325 ld r1,PACA_MC_STACK(r13); \
326 subi r1,r1,SPECIAL_EXC_FRAME_SIZE
381 std r0,GPR0(r1); /* save r0 in stackframe */ \
382 std r2,GPR2(r1); /* save r2 in stackframe */ \
383 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
384 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
385 std r9,GPR9(r1); /* save r9 in stackframe */ \
386 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
387 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
393 std r12,GPR12(r1); /* save r12 in stackframe */ \
398 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
403 std r3,GPR10(r1); /* save r10 to stackframe */ \
404 std r4,GPR11(r1); /* save r11 to stackframe */ \
405 std r5,GPR13(r1); /* save it to stackframe */ \
406 std r6,_LINK(r1); \
407 std r7,_CTR(r1); \
408 std r8,_XER(r1); \
410 std r9,0(r1); /* store stack frame back link */ \
411 std r10,_CCR(r1); /* store orig CR in stackframe */ \
412 std r9,GPR1(r1); /* store stack frame back link */ \
413 std r11,SOFTE(r1); /* and save it to stackframe */ \
414 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
415 std r3,_TRAP(r1); /* set trap number */ \
416 std r0,RESULT(r1); /* clear regs->result */
446 ld r11,_MSR(r1); \
452 li r1,(n); /* get exception number */ \
453 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
482 CURRENT_THREAD_INFO(r11, r1); \
486 ld r8,_LINK(r1); \
488 std r8,_NIP(r1); \
500 addi r3,r1,STACK_FRAME_OVERHEAD; \
556 addi r3,r1,STACK_FRAME_OVERHEAD
568 addi r3,r1,STACK_FRAME_OVERHEAD
612 std r14,_DSISR(r1)
613 addi r3,r1,STACK_FRAME_OVERHEAD
625 ld r12,_MSR(r1)
632 addi r3,r1,STACK_FRAME_OVERHEAD
644 ld r12,_MSR(r1)
654 addi r3,r1,STACK_FRAME_OVERHEAD
666 addi r3,r1,STACK_FRAME_OVERHEAD
693 addi r3,r1,STACK_FRAME_OVERHEAD
716 addi r3,r1,STACK_FRAME_OVERHEAD
751 ld r1,PACA_EXCRIT+EX_R1(r13)
772 std r14,_DSISR(r1)
773 addi r3,r1,STACK_FRAME_OVERHEAD
815 ld r1,PACA_EXDBG+EX_R1(r13)
837 std r14,_DSISR(r1)
838 addi r3,r1,STACK_FRAME_OVERHEAD
852 addi r3,r1,STACK_FRAME_OVERHEAD
868 addi r3,r1,STACK_FRAME_OVERHEAD
880 addi r3,r1,STACK_FRAME_OVERHEAD
894 addi r3,r1,STACK_FRAME_OVERHEAD
903 addi r3,r1,STACK_FRAME_OVERHEAD
914 addi r3,r1,STACK_FRAME_OVERHEAD
925 addi r3,r1,STACK_FRAME_OVERHEAD
991 std r1,PACA_EXGEN+EX_R1(r13);
994 subi r1,r1,INT_FRAME_SIZE;
1010 std r14,_DAR(r1)
1011 std r15,_DSISR(r1)
1012 addi r3,r1,STACK_FRAME_OVERHEAD
1023 addi r3,r1,STACK_FRAME_OVERHEAD
1024 ld r4,_DAR(r1)
1033 std r14,_DAR(r1)
1034 std r15,_DSISR(r1)
1035 addi r3,r1,STACK_FRAME_OVERHEAD
1057 ld r10,_MSR(r1)
1058 REST_4GPRS(2, r1)
1060 REST_2GPRS(6, r1)
1063 ld r0,GPR13(r1)
1065 1: stdcx. r0,0,r1 /* to clear the reservation */
1067 ld r8,_CCR(r1)
1068 ld r9,_LINK(r1)
1069 ld r10,_CTR(r1)
1070 ld r11,_XER(r1)
1075 REST_2GPRS(8, r1)
1076 ld r10,GPR10(r1)
1077 ld r11,GPR11(r1)
1078 ld r12,GPR12(r1)
1083 ld r10,_NIP(r1)
1084 ld r11,_MSR(r1)
1085 ld r0,GPR0(r1)
1086 ld r1,GPR1(r1)
1135 ld r1,PACAEMERGSP(r13)
1136 subi r1,r1,64+INT_FRAME_SIZE
1137 std r10,_NIP(r1)
1138 std r11,_MSR(r1)
1141 std r10,GPR1(r1)
1142 std r11,_CCR(r1)
1145 std r10,_DAR(r1)
1146 std r11,_DSISR(r1)
1147 std r0,GPR0(r1); /* save r0 in stackframe */ \
1148 std r2,GPR2(r1); /* save r2 in stackframe */ \
1149 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
1150 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
1151 std r9,GPR9(r1); /* save r9 in stackframe */ \
1155 std r3,GPR10(r1); /* save r10 to stackframe */ \
1156 std r4,GPR11(r1); /* save r11 to stackframe */ \
1157 std r12,GPR12(r1); /* save r12 in stackframe */ \
1158 std r5,GPR13(r1); /* save it to stackframe */ \
1162 std r10,_LINK(r1)
1163 std r11,_CTR(r1)
1164 std r12,_XER(r1)
1165 SAVE_10GPRS(14,r1)
1166 SAVE_8GPRS(24,r1)
1168 std r12,_TRAP(r1)
1169 addi r11,r1,INT_FRAME_SIZE
1170 std r11,0(r1)
1174 1: addi r3,r1,STACK_FRAME_OVERHEAD
|
| H A D | swsusp_asm64.S | 90 SAVE_REGISTER(r1)
129 addi r1,r1,-128
137 addi r1,r1,128
197 ld r1, SL_TB(r11)
199 srdi r2, r1, 32
206 mttbl r1
209 RESTORE_REGISTER(r1)
262 addi r1,r1,-128
267 addi r1,r1,128
|
| H A D | head_32.S | 82 * pointer (r1) points to just below the end of the half-meg region
259 tophys(r11,r1); /* use tophys(r1) if kernel */ \
281 stw r1,GPR1(r11); \
282 stw r1,0(r11); \
283 tovirt(r1,r11); /* set new kernel sp */ \
297 * Note2: once we have set r1 we are in a position to take exceptions
309 addi r3,r1,STACK_FRAME_OVERHEAD; \
357 * (Other exception handlers assume that r1 is a valid kernel stack
373 addi r3,r1,STACK_FRAME_OVERHEAD
427 addi r3,r1,STACK_FRAME_OVERHEAD
448 1: addi r3,r1,STACK_FRAME_OVERHEAD
492 * r1: linux style pte ( later becomes ppc hardware pte )
498 lis r1,PAGE_OFFSET@h /* check if kernel address */
499 cmplw 0,r1,r3
501 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
505 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
515 andc. r1,r1,r0 /* check access & ~permission */
524 rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
526 and r1,r1,r2 /* writable if _RW and _DIRTY */
529 ori r1,r1,0xe04 /* clear out reserved bits */
530 andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
532 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
534 mtspr SPRN_RPA,r1
541 rlwinm r1,r3,9,6,6 /* Get load/store bit */
543 addis r1,r1,0x2000
544 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
546 or r2,r2,r1
548 mfspr r1,SPRN_IMISS /* Get failing address */
551 xor r1,r1,r2
552 mtspr SPRN_DAR,r1 /* Set fault address */
566 * r1: linux style pte ( later becomes ppc hardware pte )
572 lis r1,PAGE_OFFSET@h /* check if kernel address */
573 cmplw 0,r1,r3
575 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
579 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
589 andc. r1,r1,r0 /* check access & ~permission */
598 rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
600 and r1,r1,r2 /* writable if _RW and _DIRTY */
603 ori r1,r1,0xe04 /* clear out reserved bits */
604 andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
606 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
608 mtspr SPRN_RPA,r1
613 mfspr r1,SPRN_SPRG_603_LRU
616 xor r1,r0,r1
617 srw r0,r1,r2
618 mtspr SPRN_SPRG_603_LRU,r1
627 rlwinm r1,r3,9,6,6 /* Get load/store bit */
628 addis r1,r1,0x2000
629 mtspr SPRN_DSISR,r1
632 mfspr r1,SPRN_DMISS /* Get failing address */
635 xori r1,r1,3
636 20: mtspr SPRN_DAR,r1 /* Set fault address */
650 * r1: linux style pte ( later becomes ppc hardware pte )
656 lis r1,PAGE_OFFSET@h /* check if kernel address */
657 cmplw 0,r1,r3
659 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
663 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
673 andc. r1,r1,r0 /* check access & ~permission */
683 li r1,0xe05 /* clear out reserved bits & PP lsb */
684 andc r1,r0,r1 /* PP = user? 2: 0 */
686 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
688 mtspr SPRN_RPA,r1
693 mfspr r1,SPRN_SPRG_603_LRU
696 xor r1,r0,r1
697 srw r0,r1,r2
698 mtspr SPRN_SPRG_603_LRU,r1
752 1: addi r3,r1,STACK_FRAME_OVERHEAD
757 addi r3,r1,STACK_FRAME_OVERHEAD
847 lis r1,secondary_ti@ha
848 tophys(r1,r1)
849 lwz r1,secondary_ti@l(r1)
850 tophys(r2,r1)
854 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
856 tophys(r3,r1)
958 lis r1,init_thread_union@ha
959 addi r1,r1,init_thread_union@l
961 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
|
| H A D | exceptions-64s.S | 472 * paca->mc_emergency_sp, otherwise r1 is already pointing to
479 mr r11,r1 /* Save r1 */
484 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
485 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
491 std r11,GPR1(r1) /* Save r1 on the stack. */
492 std r11,0(r1) /* make stack chain pointer */
494 std r11,_NIP(r1)
496 std r11,_MSR(r1)
498 std r11,_DAR(r1)
500 std r11,_DSISR(r1)
501 std r9,_CCR(r1) /* Save CR in stackframe */
518 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
994 ld r12,_MSR(r1)
1010 addi r3,r1,STACK_FRAME_OVERHEAD
1019 ld r12,_MSR(r1)
1020 ld r3,_NIP(r1)
1076 std r4,_DAR(r1)
1077 std r5,_DSISR(r1)
1084 1: addi r3,r1,STACK_FRAME_OVERHEAD
1108 std r3,_DAR(r1)
1109 std r4,_DSISR(r1)
1111 addi r3,r1,STACK_FRAME_OVERHEAD
1125 std r3,_DAR(r1)
1126 std r4,_DSISR(r1)
1129 addi r3,r1,STACK_FRAME_OVERHEAD
1139 addi r3,r1,STACK_FRAME_OVERHEAD
1150 addi r3,r1,STACK_FRAME_OVERHEAD
1169 addi r3,r1,STACK_FRAME_OVERHEAD
1195 addi r3,r1,STACK_FRAME_OVERHEAD
1204 addi r3,r1,STACK_FRAME_OVERHEAD
1229 addi r3,r1,STACK_FRAME_OVERHEAD
1238 addi r3,r1,STACK_FRAME_OVERHEAD
1288 mr r10,r1 /* Save r1 */
1289 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
1290 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1291 std r9,_CCR(r1) /* save CR in stackframe */
1293 std r11,_NIP(r1) /* save HSRR0 in stackframe */
1295 std r12,_MSR(r1) /* save SRR1 in stackframe */
1296 std r10,0(r1) /* make stack chain pointer */
1297 std r0,GPR0(r1) /* save r0 in stackframe */
1298 std r10,GPR1(r1) /* save r1 in stackframe */
1301 addi r3,r1,STACK_FRAME_OVERHEAD
1305 ld r9,_MSR(r1)
1307 ld r3,_NIP(r1)
1309 ld r9,_CTR(r1)
1311 ld r9,_XER(r1)
1313 ld r9,_LINK(r1)
1315 REST_GPR(0, r1)
1316 REST_8GPRS(2, r1)
1317 REST_GPR(10, r1)
1318 ld r11,_CCR(r1)
1320 REST_GPR(11, r1)
1321 REST_2GPRS(12, r1)
1322 /* restore original r1. */
1323 ld r1,GPR1(r1)
1343 ld r9,_MSR(r1); \
1345 ld r3,_NIP(r1); \
1347 ld r9,_CTR(r1); \
1349 ld r9,_XER(r1); \
1351 ld r9,_LINK(r1); \
1353 REST_GPR(0, r1); \
1354 REST_8GPRS(2, r1); \
1355 REST_GPR(10, r1); \
1356 ld r11,_CCR(r1); \
1362 REST_GPR(11, r1); \
1363 REST_2GPRS(12, r1); \
1364 /* restore original r1. */ \
1365 ld r1,GPR1(r1)
1374 std r0,GPR0(r1) /* Save r0 */
1377 addi r3,r1,STACK_FRAME_OVERHEAD
1379 std r3,RESULT(r1) /* Save result */
1380 ld r12,_MSR(r1)
1402 ld r1,PACAR1(r13)
1457 ld r3,RESULT(r1) /* Load result */
1476 addi r3,r1,STACK_FRAME_OVERHEAD
1482 1: addi r3,r1,STACK_FRAME_OVERHEAD
1543 1: addi r3,r1,STACK_FRAME_OVERHEAD
1552 ld r10,_LINK(r1) /* make idle task do the */
1553 std r10,_NIP(r1) /* equivalent of a blr */
1562 std r3,_DAR(r1)
1563 std r4,_DSISR(r1)
1569 CURRENT_THREAD_INFO(r11, r1)
1593 ld r6,_DSISR(r1)
1605 11: ld r4,_DAR(r1)
1606 ld r5,_DSISR(r1)
1607 addi r3,r1,STACK_FRAME_OVERHEAD
1613 addi r3,r1,STACK_FRAME_OVERHEAD
1614 lwz r4,_DAR(r1)
1621 ld r4,_DAR(r1)
1622 ld r5,_DSISR(r1)
1623 addi r3,r1,STACK_FRAME_OVERHEAD
1633 addi r3,r1,STACK_FRAME_OVERHEAD
1634 ld r4,_DAR(r1)
1647 addi r3,r1,STACK_FRAME_OVERHEAD
1661 ld r1,PACAEMERGSP(r13)
1662 subi r1,r1,64+INT_FRAME_SIZE
1663 std r9,_CCR(r1)
1664 std r10,GPR1(r1)
1665 std r11,_NIP(r1)
1666 std r12,_MSR(r1)
1669 std r11,_DAR(r1)
1670 std r12,_DSISR(r1)
1674 std r10,_LINK(r1)
1675 std r11,_CTR(r1)
1676 std r12,_XER(r1)
1677 SAVE_GPR(0,r1)
1678 SAVE_GPR(2,r1)
1680 std r10,GPR3(r1)
1681 SAVE_GPR(4,r1)
1682 SAVE_4GPRS(5,r1)
1685 SAVE_2GPRS(9,r1)
1689 std r9,GPR11(r1)
1690 std r10,GPR12(r1)
1691 std r11,GPR13(r1)
1694 std r10,ORIG_GPR3(r1)
1696 SAVE_8GPRS(14,r1)
1697 SAVE_10GPRS(22,r1)
1699 std r12,_TRAP(r1)
1700 addi r11,r1,INT_FRAME_SIZE
1701 std r11,0(r1)
1706 std r12,RESULT(r1)
1707 std r11,STACK_FRAME_OVERHEAD-16(r1)
1708 1: addi r3,r1,STACK_FRAME_OVERHEAD
|
| /linux-4.1.27/arch/s390/kernel/vdso32/ |
| H A D | clock_getres.S | 22 basr %r1,0
23 la %r1,4f-.(%r1)
28 la %r1,5f-4f(%r1)
35 1: l %r0,0(%r1)
40 3: lhi %r1,__NR_clock_getres /* fallback to svc */
|
| H A D | clock_gettime.S | 39 lm %r0,%r1,1(%r15)
41 sl %r1,__VDSO_XTIME_STAMP+4(%r5)
47 ltr %r1,%r1
53 al %r1,__VDSO_WTOM_NSEC+4(%r5)
64 cl %r1,20f-6b(%r5)
67 sl %r1,20f-6b(%r5)
72 st %r1,4(%r3) /* store tp->tv_nsec */
82 l %r1,__VDSO_WTOM_CRS_NSEC+4(%r5)
92 l %r1,__VDSO_XTIME_CRS_NSEC+4(%r5)
102 lm %r0,%r1,1(%r15)
104 sl %r1,__VDSO_XTIME_STAMP+4(%r5)
110 ltr %r1,%r1
116 al %r1,__VDSO_XTIME_NSEC+4(%r5)
127 cl %r1,20f-15b(%r5)
130 sl %r1,20f-15b(%r5)
135 st %r1,4(%r3) /* store tp->tv_nsec */
141 19: lhi %r1,__NR_clock_gettime
|
| H A D | gettimeofday.S | 34 lm %r0,%r1,1(%r15)
36 sl %r1,__VDSO_XTIME_STAMP+4(%r5)
42 ltr %r1,%r1
48 al %r1,__VDSO_XTIME_NSEC+4(%r5)
60 cl %r1,11f-6b(%r5)
63 sl %r1,11f-6b(%r5)
68 ltr %r1,%r1
|
| /linux-4.1.27/arch/m32r/boot/ |
| H A D | setup.S | 67 ldi r1, #0x0101 ; cache on (with invalidation)
68 ; ldi r1, #0x00 ; cache off
69 sth r1, @r0
73 ldi r1, #0x73 ; cache on (with invalidation)
74 ; ldi r1, #0x00 ; cache off
75 st r1, @r0
78 ldi r1, #0x101 ; cache on (with invalidation)
79 ; ldi r1, #0x00 ; cache off
80 st r1, @r0
83 seth r1, #0x0060 ; from 0x00600000
84 or3 r1, r1, #0x0005 ; size 2MB
85 st r1, @r0
86 seth r1, #0x0100 ; from 0x01000000
87 or3 r1, r1, #0x0003 ; size 16MB
88 st r1, @+r0
89 seth r1, #0x0200 ; from 0x02000000
90 or3 r1, r1, #0x0002 ; size 32MB
91 st r1, @+r0
93 ldi r1, #0x703 ; cache on (with invalidation)
94 st r1, @r0
126 ldi r1, #0x01
127 st r1, @(MATM_offset,r0) ; Set MATM (T bit ON)
133 ld24 r1,#0x8080
134 st r1,@r0
|
| /linux-4.1.27/arch/sh/kernel/cpu/sh3/ |
| H A D | swsusp.S | 17 #define k1 r1
44 mov.l @r2+,r1 /* 16n+0 */
45 mov.l r1,@r5
47 mov.l @r2+,r1 /* 16n+4 */
48 mov.l r1,@r5
50 mov.l @r2+,r1 /* 16n+8 */
51 mov.l r1,@r5
53 mov.l @r2+,r1 /* 16n+12 */
54 mov.l r1,@r5
73 mov.l @r15+, r1
100 stc sr, r1
101 ldc r1, ssr ! save sr in ssr
102 mov.l 1f, r1
103 ldc r1, spc ! setup pc value for resuming
111 mov.l 7f, r1
112 jsr @r1 ! switch to bank1 and save bank1 r7->r0
125 stc ssr, r1
126 ldc r1, sr ! restore old sr
|
| /linux-4.1.27/arch/hexagon/kernel/ |
| H A D | head.S | 53 r1.h = #HI(PAGE_OFFSET);
54 r1.l = #LO(PAGE_OFFSET);
55 r24 = sub(r24,r1); /* swapper_pg_dir - PAGE_OFFSET */
75 r1.l = #LO(_end);
80 r1.h = #HI(_end);
85 r1 = sub(r1, r2); define
87 } /* r1 = _end - stext */
88 r1 = add(r1, r3); /* + (4M-1) */ define
89 r26 = lsr(r1, #22); /* / 4M = # of entries */
91 r1 = r25; define
94 r1 = and(r1,r2); define
95 r2 = lsr(r1, #22) /* 4MB page number */
99 r1 = add(r1,r2) /* r1 = 4MB PTE for the first entry */ define
104 memw(r0 ++ #4) = r1
105 { r1 = add(r1, r2); } :endloop0
112 r0 = add(r1, r24); /* advance to 0xc0000000 entry */
113 r1 = r25; define
116 r1 = and(r1,r2); /* for huge page */ define
118 r1 = add(r1,r2); define
124 memw(r0 ++ #4) = r1;
125 { r1 = add(r1,r2); } :endloop0
135 r1 = #VM_TRANS_TYPE_TABLE define
153 r1.h = #0xffc0;
154 r1.l = #0x0000;
156 r2 = and(r1,r2);
158 r1.l = #lo(swapper_pg_dir)
159 r1.h = #hi(swapper_pg_dir)
162 r1 = add(r1,r2); define
171 r1 = #VM_TRANS_TYPE_TABLE define
208 { r0.L = #LO(__bss_start); r1 = #0; r2.l = #LO(__bss_stop); }
|
| /linux-4.1.27/arch/microblaze/lib/ |
| H A D | divsi3.S | 14 .frame r1, 0, r15
16 addik r1, r1, -16
17 swi r28, r1, 0
18 swi r29, r1, 4
19 swi r30, r1, 8
20 swi r31, r1, 12
65 lwi r28, r1, 0
66 lwi r29, r1, 4
67 lwi r30, r1, 8
68 lwi r31, r1, 12
70 addik r1, r1, 16
|
| H A D | modsi3.S | 16 .frame r1, 0, r15
18 addik r1, r1, -16
19 swi r28, r1, 0
20 swi r29, r1, 4
21 swi r30, r1, 8
22 swi r31, r1, 12
65 lwi r28, r1, 0
66 lwi r29, r1, 4
67 lwi r30, r1, 8
68 lwi r31, r1, 12
70 addik r1, r1, 16
|
| H A D | uaccess_old.S | 192 addik r1, r1, -40
193 swi r5, r1, 0
194 swi r6, r1, 4
195 swi r7, r1, 8
196 swi r19, r1, 12
197 swi r20, r1, 16
198 swi r21, r1, 20
199 swi r22, r1, 24
200 swi r23, r1, 28
201 swi r24, r1, 32
202 swi r25, r1, 36
216 lwi r5, r1, 0
217 lwi r6, r1, 4
218 lwi r7, r1, 8
219 lwi r19, r1, 12
220 lwi r20, r1, 16
221 lwi r21, r1, 20
222 lwi r22, r1, 24
223 lwi r23, r1, 28
224 lwi r24, r1, 32
225 lwi r25, r1, 36
226 addik r1, r1, 40
236 lwi r5, r1, 0
237 lwi r6, r1, 4
238 lwi r7, r1, 8
239 lwi r19, r1, 12
240 lwi r20, r1, 16
241 lwi r21, r1, 20
242 lwi r22, r1, 24
243 lwi r23, r1, 28
244 lwi r24, r1, 32
245 lwi r25, r1, 36
246 addik r1, r1, 40
|
| H A D | udivsi3.S | 17 .frame r1, 0, r15
19 addik r1, r1, -12
20 swi r29, r1, 0
21 swi r30, r1, 4
22 swi r31, r1, 8
77 lwi r29, r1, 0
78 lwi r30, r1, 4
79 lwi r31, r1, 8
81 addik r1, r1, 12
|
| H A D | umodsi3.S | 16 .frame r1, 0, r15
18 addik r1, r1, -12
19 swi r29, r1, 0
20 swi r30, r1, 4
21 swi r31, r1, 8
79 lwi r29, r1, 0
80 lwi r30, r1, 4
81 lwi r31, r1, 8
83 addik r1, r1, 12
|
| /linux-4.1.27/arch/powerpc/boot/ |
| H A D | ps3-hvcall.S | 37 * 5: 8(r1),12(r1) <-> r7
38 * 6: 16(r1),20(r1) <-> r8
39 * 7: 24(r1),28(r1) <-> r9
40 * 8: 32(r1),36(r1) <-> r10
64 stw r0, \offset(r1)
68 lwz r0, \offset(r1)
78 ld \target, \offset(r1)
138 lwz r11, 8(r1)
142 addi r1,r1,16
146 lwz r11, 16(r1)
148 lwz r11, 20(r1)
153 lwz r11, 24(r1)
|
| H A D | crt0.S | 136 lwz r1,0(r8)
138 stwu r0,-16(r1) /* establish a stack frame */
219 ld r1,0(r8)
221 stdu r0,-112(r1) /* establish a stack frame */
249 std r0,16(r1)
250 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
252 SAVE_GPR(2, r1)
253 SAVE_GPR(13, r1)
254 SAVE_8GPRS(14, r1)
255 SAVE_10GPRS(22, r1)
257 std r10,8*32(r1)
259 std r10,8*33(r1)
281 rldicl r1,r1,0,32
284 ld r10,8*(33)(r1)
289 REST_GPR(2, r1)
290 REST_GPR(13, r1)
291 REST_8GPRS(14, r1)
292 REST_10GPRS(22, r1)
293 ld r10,8*32(r1)
296 addi r1,r1,PROM_FRAME_SIZE
297 ld r0,16(r1)
|
| /linux-4.1.27/arch/arm/mach-exynos/ |
| H A D | sleep.S | 46 ldr r1, =CPU_MASK
47 and r0, r0, r1
48 ldr r1, =CPU_CORTEX_A9
49 cmp r0, r1
59 ldr r1, =CPU_MASK
60 and r0, r0, r1
61 ldr r1, =CPU_CORTEX_A9
62 cmp r0, r1
66 ldr r1, [r0]
67 ldr r1, [r0, r1]
80 ldr r1, [r0, #L2X0_R_PHY_BASE]
81 teq r1, #0
85 ldr r2, [r1, #L2X0_CTRL]
89 ldr r1, [r0, #L2X0_R_TAG_LATENCY]
100 ldr r1, [r0, #L2X0_R_PWR_CTRL]
108 mov r1, #1
|
| /linux-4.1.27/arch/powerpc/platforms/powernv/ |
| H A D | opal-wrappers.S | 62 std r0,16(r1); \
66 stw r12,8(r1); \
67 std r1,PACAR1(r13); \
94 lwz r4,8(r1);
95 ld r5,16(r1);
104 stdu r1,-STACKFRAMESIZE(r1)
105 std r0,STK_REG(R23)(r1)
106 std r3,STK_REG(R24)(r1)
107 std r4,STK_REG(R25)(r1)
108 std r5,STK_REG(R26)(r1)
109 std r6,STK_REG(R27)(r1)
110 std r7,STK_REG(R28)(r1)
111 std r8,STK_REG(R29)(r1)
112 std r9,STK_REG(R30)(r1)
113 std r10,STK_REG(R31)(r1)
115 addi r4,r1,STK_REG(R24)
117 ld r0,STK_REG(R23)(r1)
118 ld r3,STK_REG(R24)(r1)
119 ld r4,STK_REG(R25)(r1)
120 ld r5,STK_REG(R26)(r1)
121 ld r6,STK_REG(R27)(r1)
122 ld r7,STK_REG(R28)(r1)
123 ld r8,STK_REG(R29)(r1)
124 ld r9,STK_REG(R30)(r1)
125 ld r10,STK_REG(R31)(r1)
128 std r11,16(r1)
129 stw r12,8(r1)
130 std r1,PACAR1(r13)
149 std r3,STK_REG(R31)(r1)
151 ld r0,STK_REG(R23)(r1)
153 ld r3,STK_REG(R31)(r1)
154 addi r1,r1,STACKFRAMESIZE
155 ld r0,16(r1)
165 * r1 - stack pointer
170 std r12,PPC_LR_STKOFF(r1)
193 ld r12,PPC_LR_STKOFF(r1)
|
| /linux-4.1.27/arch/x86/crypto/ |
| H A D | aes-x86_64-asm_64.S | 52 #define prologue(FUNC,KEY,B128,B192,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11) \
54 movq r1,r2; \
59 movl 4(r7),r1 ## E; \
64 xorl -44(r9),r1 ## E; \
73 #define epilogue(FUNC,r1,r2,r3,r4,r5,r6,r7,r8,r9) \
74 movq r1,r2; \
83 #define round(TAB,OFFSET,r1,r2,r3,r4,r5,r6,r7,r8,ra,rb,rc,rd) \
97 movzbl r1 ## L,r7 ## E; \
98 movzbl r1 ## H,r4 ## E; \
100 movw r3 ## X,r1 ## X; \
101 roll $16,r1 ## E; \
108 movzbl r1 ## H,r7 ## E; \
109 movzbl r1 ## L,r3 ## E; \
110 shrl $16,r1 ## E; \
113 movzbl r1 ## H,r7 ## E; \
114 movzbl r1 ## L,r1 ## E; \
116 xorl TAB(,r1,4),r3 ## E; \
117 movzbl r2 ## H,r1 ## E; \
120 xorl TAB+3072(,r1,4),r3 ## E;\
122 movzbl r2 ## H,r1 ## E; \
126 xorl TAB+1024(,r1,4),r3 ## E;\
129 #define move_regs(r1,r2,r3,r4) \
130 movl r3 ## E,r1 ## E; \
|
| H A D | aes-i586-asm_32.S | 57 #define r1 ebx define
81 // output registers r0, r1, r4 or r5.
151 // the first previous round column values in r0,r1,r4,r5 and
156 // on entry: r0,r1,r4,r5
157 // on exit: r2,r1,r4,r5
159 save (0,r1); \
163 do_fcol(table, r2,r5,r4,r1, r0,r3, arg); /* idx=r0 */ \
164 do_col (table, r4,r1,r2,r5, r0,r3); /* idx=r4 */ \
166 do_col (table, r1,r2,r5,r4, r0,r3); /* idx=r1 */ \
168 do_col (table, r5,r4,r1,r2, r0,r3); /* idx=r5 */
171 // on entry: r2,r1,r4,r5
172 // on exit: r0,r1,r4,r5
174 save (0,r1); \
178 do_fcol(table, r0,r5,r4,r1, r2,r3, arg); /* idx=r2 */ \
179 do_col (table, r4,r1,r0,r5, r2,r3); /* idx=r4 */ \
181 do_col (table, r1,r0,r5,r4, r2,r3); /* idx=r1 */ \
183 do_col (table, r5,r4,r1,r0, r2,r3); /* idx=r5 */
186 // the first previous round column values in r0,r1,r4,r5 and
191 // on entry: r0,r1,r4,r5
192 // on exit: r2,r1,r4,r5
194 save (0,r1); \
198 do_icol(table, r2,r1,r4,r5, r0,r3, arg); /* idx=r0 */ \
199 do_col (table, r4,r5,r2,r1, r0,r3); /* idx=r4 */ \
201 do_col (table, r1,r4,r5,r2, r0,r3); /* idx=r1 */ \
203 do_col (table, r5,r2,r1,r4, r0,r3); /* idx=r5 */
206 // on entry: r2,r1,r4,r5
207 // on exit: r0,r1,r4,r5
209 save (0,r1); \
213 do_icol(table, r0,r1,r4,r5, r2,r3, arg); /* idx=r2 */ \
214 do_col (table, r4,r5,r0,r1, r2,r3); /* idx=r4 */ \
216 do_col (table, r1,r4,r5,r0, r2,r3); /* idx=r1 */ \
218 do_col (table, r5,r0,r1,r4, r2,r3); /* idx=r5 */
245 mov 4(%r2),%r1
249 xor 4(%ebp),%r1
285 mov %r1,4(%ebp)
317 mov 4(%r2),%r1
321 xor 4(%ebp),%r1
357 mov %r1,4(%ebp)
|
| /linux-4.1.27/arch/arm/kvm/ |
| H A D | init.S | 31 * r1 = pointer to hyp vectors
48 * - Phase 1: r0 = 0, r1 = 0, r2,r3 contain the boot PGD.
50 * - Phase 2: r0 = ToS, r1 = vectors, r2,r3 contain the runtime PGD.
82 mrc p15, 0, r1, c2, c0, 2 @ TTBCR
83 and r1, r1, #(HTCR_MASK & ~TTBCR_T0SZ)
84 orr r0, r0, r1
87 mrc p15, 4, r1, c2, c1, 2 @ VTCR
89 bic r1, r1, r2
91 orr r1, r0, r1
92 orr r1, r1, #(KVM_VTCR_SL0 | KVM_VTCR_T0SZ | KVM_VTCR_S)
93 mcr p15, 4, r1, c2, c1, 2 @ VTCR
118 mrc p15, 0, r1, c1, c0, 0 @ SCTLR
120 and r1, r1, r2
123 orr r1, r1, r2
124 orr r0, r0, r1
136 mcr p15, 4, r1, c12, c0, 0 @ HVBAR
140 adr r1, target
141 bfi r0, r1, #0, #PAGE_SHIFT
|
| H A D | interrupts.S | 138 ldr r1, [vcpu, #VCPU_MIDR]
139 mcr p15, 4, r1, c0, c0, 0
142 ldr r1, [vcpu, #CP15_OFFSET(c0_MPIDR)]
143 mcr p15, 4, r1, c0, c0, 5
146 ldr r1, [vcpu, #VCPU_KVM]
147 add r1, r1, #KVM_VTTBR
148 ldrd r2, r3, [r1]
159 * guest r0, r1, r2 saved on the stack
161 * r1: exception code
212 mov r0, r1 @ Return the return code
213 mov r1, #0 @ Clear upper bits in return value
215 @ r1 already has return code
232 * passed as r0, r1, and r2 (a maximum of 3 arguments in addition to the
235 * passed in r0 and r1.
270 * - r1, r2, and r3 contain arguments to the above function.
271 * - The HYP function will be called with its arguments in r0, r1 and r2.
282 mrrc p15, 6, r0, r1, c2 @ Read VTTBR
283 lsr r1, r1, #16
284 ands r1, r1, #0xff
290 mrc p15, 4, r1, c6, c0, 0 @ HDFAR
292 str r1, [vcpu, #VCPU_HxFAR]
296 mrc p15, 4, r1, c6, c0, 2 @ HIFAR
298 str r1, [vcpu, #VCPU_HxFAR]
300 mov r1, #\exception_code
309 mrs r1, ELR_hyp
359 push {r0, r1, r2}
362 mrc p15, 4, r1, c5, c2, 0 @ HSR
363 lsr r0, r1, #HSR_EC_SHIFT
382 pop {r0, r1, r2}
394 mov r0, r1
395 mov r1, r2
408 str r1, [vcpu, #VCPU_HSR]
411 lsr r1, r1, #HSR_EC_SHIFT
412 cmp r1, #HSR_EC_IABT
415 cmp r1, #HSR_EC_DABT
435 mrc p15, 4, r1, c5, c2, 0 @ HSR
436 and r0, r1, #HSR_FSC_TYPE
438 tsteq r1, #(1 << 7) @ S1PTW
443 mrrc p15, 0, r0, r1, c7 @ PAR
444 push {r0, r1}
449 mrrc p15, 0, r0, r1, c7 @ PAR
454 orr r2, r2, r1, lsl #24
457 pop {r0, r1}
458 mcrr p15, 0, r0, r1, c7 @ PAR
463 1: mov r1, #ARM_EXCEPTION_HVC
466 4: pop {r0, r1} @ Failed translation, return to guest
467 mcrr p15, 0, r0, r1, c7 @ PAR
469 pop {r0, r1, r2}
501 push {r0, r1, r2}
502 mov r1, #ARM_EXCEPTION_IRQ
|
| /linux-4.1.27/arch/arm/mach-mvebu/ |
| H A D | coherency_ll.S | 28 * Returns the coherency base address in r1 (r0 is untouched), or 0 if
32 mrc p15, 0, r1, c1, c0, 0
33 tst r1, #CR_M @ Check MMU bit enabled
42 ldr r1, =coherency_base
43 cmp r1, #0
45 adr r1, 3f
46 ldr r3, [r1]
47 ldr r1, [r1, r3]
54 ldr r1, =coherency_base
55 ldr r1, [r1]
97 cmp r1, #0
101 add r0, r1, #ARMADA_XP_CFB_CFG_REG_OFFSET
105 strex r1, r2, [r0]
106 cmp r1, #0
122 cmp r1, #0
126 add r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
130 strex r1, r2, [r0]
131 cmp r1, #0
149 cmp r1, #0
153 add r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
157 strex r1, r2, [r0]
158 cmp r1, #0
|
| H A D | pmsu_ll.S | 17 mrc p15, 4, r1, c15, c0 @ get SCU base address
18 orr r1, r1, #0x8 @ SCU CPU Power Status Register
21 add r1, r1, r0
23 strb r0, [r1] @ switch SCU power state to Normal mode
38 mrc p15, 0, r1, c1, c0, 0
39 bic r1, #1
40 mcr p15, 0, r1, c1, c0, 0
|
| /linux-4.1.27/arch/cris/arch-v32/mach-fs/ |
| H A D | dram_init.S | 29 move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
30 move.d $r1, [$r0]
32 move.d CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1
33 move.d $r1, [$r0]
47 move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
48 and.d 0x07, $r1 ; Get CAS latency
49 cmpq 2, $r1 ; CL = 2 ?
58 move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
59 and.d 0x200, $r1 ; DRAM width is bit 9
66 move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
67 and.d ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1
69 move.d $r1, [$r0]
73 moveq regk_bif_core_nop, $r1
74 move.d $r1, [$r5]
97 move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
99 move.d $r1, [$r0]
|
| /linux-4.1.27/arch/arm/mach-ep93xx/ |
| H A D | crunch-bits.S | 73 ldr r1, [r8, #0x80]
74 tst r1, #0x00800000 @ access to crunch enabled?
78 orr r1, r1, #0x00800000 @ enable access to crunch
79 str r1, [r8, #0x80]
84 ldr r1, [r3] @ get current crunch owner
92 teq r1, #0 @ test for last ownership
97 cfstr64 mvdx0, [r1, #CRUNCH_MVDX0] @ save 64b registers
98 cfstr64 mvdx1, [r1, #CRUNCH_MVDX1]
99 cfstr64 mvdx2, [r1, #CRUNCH_MVDX2]
100 cfstr64 mvdx3, [r1, #CRUNCH_MVDX3]
101 cfstr64 mvdx4, [r1, #CRUNCH_MVDX4]
102 cfstr64 mvdx5, [r1, #CRUNCH_MVDX5]
103 cfstr64 mvdx6, [r1, #CRUNCH_MVDX6]
104 cfstr64 mvdx7, [r1, #CRUNCH_MVDX7]
105 cfstr64 mvdx8, [r1, #CRUNCH_MVDX8]
106 cfstr64 mvdx9, [r1, #CRUNCH_MVDX9]
107 cfstr64 mvdx10, [r1, #CRUNCH_MVDX10]
108 cfstr64 mvdx11, [r1, #CRUNCH_MVDX11]
109 cfstr64 mvdx12, [r1, #CRUNCH_MVDX12]
110 cfstr64 mvdx13, [r1, #CRUNCH_MVDX13]
111 cfstr64 mvdx14, [r1, #CRUNCH_MVDX14]
112 cfstr64 mvdx15, [r1, #CRUNCH_MVDX15]
119 cfstr32 mvfx0, [r1, #CRUNCH_MVAX0L]
121 cfstr32 mvfx0, [r1, #CRUNCH_MVAX0M]
123 cfstr32 mvfx0, [r1, #CRUNCH_MVAX0H]
125 cfstr32 mvfx0, [r1, #CRUNCH_MVAX1L]
127 cfstr32 mvfx0, [r1, #CRUNCH_MVAX1M]
129 cfstr32 mvfx0, [r1, #CRUNCH_MVAX1H]
131 cfstr32 mvfx0, [r1, #CRUNCH_MVAX2L]
133 cfstr32 mvfx0, [r1, #CRUNCH_MVAX2M]
135 cfstr32 mvfx0, [r1, #CRUNCH_MVAX2H]
137 cfstr32 mvfx0, [r1, #CRUNCH_MVAX3L]
139 cfstr32 mvfx0, [r1, #CRUNCH_MVAX3M]
141 cfstr32 mvfx0, [r1, #CRUNCH_MVAX3H]
144 cfstr64 mvdx0, [r1, #CRUNCH_DSPSC]
147 cfldr64eq mvdx0, [r1, #CRUNCH_MVDX0] @ mvdx0 was clobbered
220 ldr r1, [r3] @ get current crunch owner
221 teq r1, #0 @ any current owner?
224 teqne r1, r2 @ or specified one?
253 * r1 = memory address where to store crunch state
270 mov r0, r1
271 mov r1, r2
286 * r1 = memory address where to get crunch state from
308 mov r0, r1
309 mov r1, #0 @ nothing to save
|
| /linux-4.1.27/sound/oss/ |
| H A D | vidc_fill.S | 21 1: cmp r0, r1
34 1: cmp r0, r1
48 1: cmp r0, r1
60 1: cmp r0, r1
75 1: cmp r0, r1
81 cmp r0, r1
93 1: cmp r0, r1
97 cmp r0, r1
106 mov r1, #0
110 stmltia r2!, {r0, r1, r4, r5}
116 mov r1, #0
120 stmia r2!, {r0, r1}
126 * r1 = phys end
139 ldmia r8, {r0, r1, r2, r3, r4, r5}
140 teq r1, #0
152 add r1, r1, r0 @ End of virtual DMA buffer
155 sub r1, r1, r0 @ Remaining length
156 stmia r8, {r0, r1}
189 teq r1, #0 @ If we have no more
208 .long 0 @ r1
|
| /linux-4.1.27/arch/cris/arch-v10/lib/ |
| H A D | dram_init.S | 58 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
59 move.d $r1, $r3
60 and.d 0x03, $r1 ; Get CAS latency
65 cmp.d 0x00, $r1 ; CAS latency = 2?
72 cmp.d 0x01, $r1 ; CAS latency = 2?
77 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
78 and.d 0x800000, $r1 ; DRAM width is bit 23
85 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
86 and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
87 or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
88 move.d $r1, $r5
89 or.d 0x0000c000, $r1 ; ref = disable
91 or.d $r2, $r1
92 move.d $r1, [R_SDRAM_TIMING]
107 or.d $r1, $r4
|
| /linux-4.1.27/arch/powerpc/net/ |
| H A D | bpf_jit_asm.S | 98 * local variable space at r1+(BPF_PPC_STACK_BASIC).
104 PPC_STL r0, PPC_LR_STKOFF(r1); \
106 PPC_STL r_skb, (BPF_PPC_STACKFRAME+BPF_PPC_STACK_R3_OFF)(r1); \
107 PPC_STL r_A, (BPF_PPC_STACK_BASIC+(0*REG_SZ))(r1); \
108 PPC_STL r_X, (BPF_PPC_STACK_BASIC+(1*REG_SZ))(r1); \
109 addi r5, r1, BPF_PPC_STACK_BASIC+(2*REG_SZ); \
110 PPC_STLU r1, -BPF_PPC_SLOWPATH_FRAME(r1); \
117 addi r1, r1, BPF_PPC_SLOWPATH_FRAME; \
118 PPC_LL r0, PPC_LR_STKOFF(r1); \
119 PPC_LL r_A, (BPF_PPC_STACK_BASIC+(0*REG_SZ))(r1); \
120 PPC_LL r_X, (BPF_PPC_STACK_BASIC+(1*REG_SZ))(r1); \
124 PPC_LL r_skb, (BPF_PPC_STACKFRAME+BPF_PPC_STACK_R3_OFF)(r1); \
130 lwz r_A, BPF_PPC_STACK_BASIC+(2*REG_SZ)(r1)
135 lhz r_A, BPF_PPC_STACK_BASIC+(2*8)(r1)
140 lbz r_A, BPF_PPC_STACK_BASIC+(2*8)(r1)
145 lbz r_X, BPF_PPC_STACK_BASIC+(2*8)(r1)
151 * local variable space at r1+(BPF_PPC_STACK_BASIC).
157 PPC_STL r0, PPC_LR_STKOFF(r1); \
159 PPC_STL r_skb, (BPF_PPC_STACKFRAME+BPF_PPC_STACK_R3_OFF)(r1); \
160 PPC_STL r_A, (BPF_PPC_STACK_BASIC+(0*REG_SZ))(r1); \
161 PPC_STL r_X, (BPF_PPC_STACK_BASIC+(1*REG_SZ))(r1); \
162 PPC_STLU r1, -BPF_PPC_SLOWPATH_FRAME(r1); \
169 addi r1, r1, BPF_PPC_SLOWPATH_FRAME; \
170 PPC_LL r0, PPC_LR_STKOFF(r1); \
171 PPC_LL r_A, (BPF_PPC_STACK_BASIC+(0*REG_SZ))(r1); \
172 PPC_LL r_X, (BPF_PPC_STACK_BASIC+(1*REG_SZ))(r1); \
177 PPC_LL r_skb, (BPF_PPC_STACKFRAME+BPF_PPC_STACK_R3_OFF)(r1); \
|
| /linux-4.1.27/arch/powerpc/platforms/pasemi/ |
| H A D | powersave.S | 40 std r3,8(r1); \
42 ld r3,8(r1); \
63 std r0, 16(r1)
64 stdu r1,-64(r1)
66 std r3, 48(r1)
73 ld r3, 48(r1)
85 1: addi r1,r1,64
86 ld r0,16(r1)
|
| /linux-4.1.27/arch/blackfin/mach-common/ |
| H A D | head.S | 19 r2 = r2 - r1;
23 p1 = r1;
76 r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)]; define
77 BITCLR (r1, ENICPLB_P);
78 [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
82 r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)]; define
83 BITCLR (r1, ENDCPLB_P);
84 [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
98 r1 = [p0 + PDA_DF_DCPLB]; define
102 [p1 + PDA_INIT_DF_DCPLB] = r1;
123 r1.l = __sbss_l1;
124 r1.h = __sbss_l1;
130 r1.l = __sbss_b_l1;
131 r1.h = __sbss_b_l1;
137 r1.l = __sbss_l2;
138 r1.h = __sbss_l2;
143 r1.l = ___bss_start;
144 r1.h = ___bss_start;
|
| /linux-4.1.27/tools/testing/selftests/powerpc/copyloops/ |
| H A D | copyuser_power7.S | 65 ld r16,STK_REG(R16)(r1)
66 ld r15,STK_REG(R15)(r1)
67 ld r14,STK_REG(R14)(r1)
70 ld r0,STACKFRAMESIZE+16(r1)
76 ld r22,STK_REG(R22)(r1)
77 ld r21,STK_REG(R21)(r1)
78 ld r20,STK_REG(R20)(r1)
79 ld r19,STK_REG(R19)(r1)
80 ld r18,STK_REG(R18)(r1)
81 ld r17,STK_REG(R17)(r1)
82 ld r16,STK_REG(R16)(r1)
83 ld r15,STK_REG(R15)(r1)
84 ld r14,STK_REG(R14)(r1)
86 addi r1,r1,STACKFRAMESIZE
88 ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
89 ld r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
90 ld r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
99 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
100 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
101 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
108 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
109 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
110 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
144 stdu r1,-STACKFRAMESIZE(r1)
145 std r14,STK_REG(R14)(r1)
146 std r15,STK_REG(R15)(r1)
147 std r16,STK_REG(R16)(r1)
148 std r17,STK_REG(R17)(r1)
149 std r18,STK_REG(R18)(r1)
150 std r19,STK_REG(R19)(r1)
151 std r20,STK_REG(R20)(r1)
152 std r21,STK_REG(R21)(r1)
153 std r22,STK_REG(R22)(r1)
154 std r0,STACKFRAMESIZE+16(r1)
200 ld r14,STK_REG(R14)(r1)
201 ld r15,STK_REG(R15)(r1)
202 ld r16,STK_REG(R16)(r1)
203 ld r17,STK_REG(R17)(r1)
204 ld r18,STK_REG(R18)(r1)
205 ld r19,STK_REG(R19)(r1)
206 ld r20,STK_REG(R20)(r1)
207 ld r21,STK_REG(R21)(r1)
208 ld r22,STK_REG(R22)(r1)
209 addi r1,r1,STACKFRAMESIZE
290 addi r1,r1,STACKFRAMESIZE
296 std r0,16(r1)
297 stdu r1,-STACKFRAMESIZE(r1)
300 ld r0,STACKFRAMESIZE+16(r1)
301 ld r3,STK_REG(R31)(r1)
302 ld r4,STK_REG(R30)(r1)
303 ld r5,STK_REG(R29)(r1)
419 std r14,STK_REG(R14)(r1)
420 std r15,STK_REG(R15)(r1)
421 std r16,STK_REG(R16)(r1)
456 ld r14,STK_REG(R14)(r1)
457 ld r15,STK_REG(R15)(r1)
458 ld r16,STK_REG(R16)(r1)
516 15: addi r1,r1,STACKFRAMESIZE
604 std r14,STK_REG(R14)(r1)
605 std r15,STK_REG(R15)(r1)
606 std r16,STK_REG(R16)(r1)
649 ld r14,STK_REG(R14)(r1)
650 ld r15,STK_REG(R15)(r1)
651 ld r16,STK_REG(R16)(r1)
719 15: addi r1,r1,STACKFRAMESIZE
|
| H A D | memcpy_power7.S | 36 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
43 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
77 stdu r1,-STACKFRAMESIZE(r1)
78 std r14,STK_REG(R14)(r1)
79 std r15,STK_REG(R15)(r1)
80 std r16,STK_REG(R16)(r1)
81 std r17,STK_REG(R17)(r1)
82 std r18,STK_REG(R18)(r1)
83 std r19,STK_REG(R19)(r1)
84 std r20,STK_REG(R20)(r1)
85 std r21,STK_REG(R21)(r1)
86 std r22,STK_REG(R22)(r1)
87 std r0,STACKFRAMESIZE+16(r1)
133 ld r14,STK_REG(R14)(r1)
134 ld r15,STK_REG(R15)(r1)
135 ld r16,STK_REG(R16)(r1)
136 ld r17,STK_REG(R17)(r1)
137 ld r18,STK_REG(R18)(r1)
138 ld r19,STK_REG(R19)(r1)
139 ld r20,STK_REG(R20)(r1)
140 ld r21,STK_REG(R21)(r1)
141 ld r22,STK_REG(R22)(r1)
142 addi r1,r1,STACKFRAMESIZE
219 15: ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
223 addi r1,r1,STACKFRAMESIZE
229 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
230 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
231 std r0,16(r1)
232 stdu r1,-STACKFRAMESIZE(r1)
235 ld r0,STACKFRAMESIZE+16(r1)
236 ld r3,STK_REG(R31)(r1)
237 ld r4,STK_REG(R30)(r1)
238 ld r5,STK_REG(R29)(r1)
352 std r14,STK_REG(R14)(r1)
353 std r15,STK_REG(R15)(r1)
354 std r16,STK_REG(R16)(r1)
389 ld r14,STK_REG(R14)(r1)
390 ld r15,STK_REG(R15)(r1)
391 ld r16,STK_REG(R16)(r1)
449 15: addi r1,r1,STACKFRAMESIZE
450 ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
538 std r14,STK_REG(R14)(r1)
539 std r15,STK_REG(R15)(r1)
540 std r16,STK_REG(R16)(r1)
583 ld r14,STK_REG(R14)(r1)
584 ld r15,STK_REG(R15)(r1)
585 ld r16,STK_REG(R16)(r1)
653 15: addi r1,r1,STACKFRAMESIZE
654 ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
|
| /linux-4.1.27/arch/arm/mach-rockchip/ |
| H A D | sleep.S | 29 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off
30 mrc p15, 0, r1, c0, c0, 5
31 and r1, r1, #0xf
32 cmp r1, #0
46 ldr r1, rkpm_bootdata_cpu_code
47 bx r1
|
| /linux-4.1.27/arch/parisc/kernel/ |
| H A D | syscall.S | 109 mfsp %sr7,%r1 /* save user sr7 */
110 mtsp %r1,%sr3 /* and store it in sr3 */
119 ssm PSW_SM_W, %r1
120 extrd,u %r1,PSW_W_BIT,1,%r1
123 or,ev %r1,%r30,%r30
136 mfctl %cr30,%r1
137 xor %r1,%r30,%r30 /* ye olde xor trick */
138 xor %r1,%r30,%r1
139 xor %r1,%r30,%r30
150 STREGM %r1,FRAME_SIZE(%r30) /* save r1 (usp) here for now */
151 mfctl %cr30,%r1 /* get task ptr in %r1 */
152 LDREG TI_TASK(%r1),%r1
159 STREG %r0, TASK_PT_PSW(%r1)
160 STREG %r2, TASK_PT_GR2(%r1) /* preserve rp */
161 STREG %r19, TASK_PT_GR19(%r1)
169 std %r19,TASK_PT_PSW(%r1)
172 STREG %r2, TASK_PT_GR30(%r1) /* ... and save it */
174 STREG %r20, TASK_PT_GR20(%r1) /* Syscall number */
175 STREG %r21, TASK_PT_GR21(%r1)
176 STREG %r22, TASK_PT_GR22(%r1)
177 STREG %r23, TASK_PT_GR23(%r1) /* 4th argument */
178 STREG %r24, TASK_PT_GR24(%r1) /* 3rd argument */
179 STREG %r25, TASK_PT_GR25(%r1) /* 2nd argument */
180 STREG %r26, TASK_PT_GR26(%r1) /* 1st argument */
181 STREG %r27, TASK_PT_GR27(%r1) /* user dp */
182 STREG %r28, TASK_PT_GR28(%r1) /* return value 0 */
183 STREG %r0, TASK_PT_ORIG_R28(%r1) /* don't prohibit restarts */
184 STREG %r29, TASK_PT_GR29(%r1) /* return value 1 */
185 STREG %r31, TASK_PT_GR31(%r1) /* preserve syscall return ptr */
187 ldo TASK_PT_FR0(%r1), %r27 /* save fpregs from the kernel */
191 STREG %r27, TASK_PT_SAR(%r1)
206 mfctl %cr30, %r1
207 LDREG TI_FLAGS(%r1),%r1
209 and,COND(=) %r1, %r19, %r0
216 ldil L%sys_call_table, %r1
218 addil L%(sys_call_table64-sys_call_table), %r1
219 ldo R%sys_call_table(%r1), %r19
221 ldo R%sys_call_table64(%r1), %r19
223 ldil L%sys_call_table, %r1
224 ldo R%sys_call_table(%r1), %r19
255 ldil L%syscall_exit,%r1
256 be R%syscall_exit(%sr7,%r1)
273 ldo -THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1 /* get task ptr */
274 LDREG TI_TASK(%r1), %r1
276 STREG %r2,TASK_PT_PSW(%r1) /* Lower 8 bits only!! */
278 STREG %r2,TASK_PT_SR0(%r1)
280 STREG %r2,TASK_PT_SR1(%r1)
282 STREG %r2,TASK_PT_SR2(%r1)
284 STREG %r2,TASK_PT_SR3(%r1)
285 STREG %r2,TASK_PT_SR4(%r1)
286 STREG %r2,TASK_PT_SR5(%r1)
287 STREG %r2,TASK_PT_SR6(%r1)
288 STREG %r2,TASK_PT_SR7(%r1)
289 STREG %r2,TASK_PT_IASQ0(%r1)
290 STREG %r2,TASK_PT_IASQ1(%r1)
291 LDREG TASK_PT_GR31(%r1),%r2
292 STREG %r2,TASK_PT_IAOQ0(%r1)
294 STREG %r2,TASK_PT_IAOQ1(%r1)
295 ldo TASK_REGS(%r1),%r2
316 ldil L%do_syscall_trace_enter,%r1
318 be R%do_syscall_trace_enter(%sr7,%r1)
327 ldil L%sys_call_table,%r1
328 ldo R%sys_call_table(%r1), %r19
330 ldo -THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1 /* get task ptr */
331 LDREG TI_TASK(%r1), %r1
332 LDREG TASK_PT_GR26(%r1), %r26 /* Restore the users args */
333 LDREG TASK_PT_GR25(%r1), %r25
334 LDREG TASK_PT_GR24(%r1), %r24
335 LDREG TASK_PT_GR23(%r1), %r23
336 LDREG TASK_PT_GR22(%r1), %r22
337 LDREG TASK_PT_GR21(%r1), %r21
369 ldo -THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1 /* get task ptr */
370 LDREG TI_TASK(%r1), %r1
374 ldo TASK_REGS(%r1),%r26
376 STREG %r28,TASK_PT_GR28(%r1) /* save return value now */
377 ldo -THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1 /* get task ptr */
378 LDREG TI_TASK(%r1), %r1
379 LDREG TASK_PT_GR28(%r1), %r28 /* Restore return val. */
381 ldil L%syscall_exit,%r1
382 be,n R%syscall_exit(%sr7,%r1)
391 ldo -THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1 /* get task ptr */
392 LDREG TI_TASK(%r1), %r1
397 ldo TASK_REGS(%r1),%r26
399 ldil L%syscall_exit_rfi,%r1
400 be,n R%syscall_exit_rfi(%sr7,%r1)
422 - %r1, %r27, %r29
461 ssm PSW_SM_W, %r1
462 extrd,u %r1,PSW_W_BIT,1,%r1
465 or,ev %r1,%r30,%r30
476 mfsp %sr7,%r1 /* get userspace into sr3 */
477 mtsp %r1,%sr3
481 ldil L%lws_table, %r1
482 ldo R%lws_table(%r1), %r28 /* Scratch use of r28 */
498 extrd,u,*<> %r30,63,1,%r1
501 xor %r30,%r1,%r30
530 Scratch: r20, r28, r1
624 mfctl %cr27, %r1
625 stw %r1, 4(%sr2,%r20)
682 Scratch: r20, r22, r28, r29, r1, fr4 (32bit for 64bit CAS only)
|
| H A D | entry.S | 62 /* Switch to virtual mapping, trashing only %r1 */
70 load32 KERNEL_PSW, %r1
75 mtctl %r1, %ipsw
76 load32 4f, %r1
77 mtctl %r1, %cr18 /* Set IIAOQ tail */
78 ldo 4(%r1), %r1
79 mtctl %r1, %cr18 /* Set IIAOQ head */
119 mfctl %cr30, %r1
120 ldo THREAD_SZ_ALGN(%r1), %r30
123 tophys %r1,%r9
124 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
125 tophys %r1,%r9
139 copy %r30,%r1
141 STREG %r1,PT_GR30(%r9)
149 LDREG PT_GR1(%r29), %r1
763 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
764 LDREG TASK_PT_GR25(%r1), %r26
766 LDREG TASK_PT_GR27(%r1), %r27
768 LDREG TASK_PT_GR26(%r1), %r1
769 ble 0(%sr7, %r1)
838 load32 USER_PSW_MASK,%r1
841 depd %r20,31,32,%r1
843 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
844 load32 USER_PSW,%r1
845 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
870 mfctl %cr30,%r1
871 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
877 mfctl %cr30,%r1
878 LDREG TI_FLAGS(%r1),%r19
912 ldo PT_FR31(%r29),%r1
913 rest_fp %r1
927 * It also restores r1 and r30.
979 mfctl %cr30, %r1
980 LDREG TI_PRE_COUNT(%r1), %r19
1081 extrd,u %r16,63,SPACEID_SHIFT,%r1 /* get high bits from isr for ior */
1082 depd %r1,31,SPACEID_SHIFT,%r17 /* deposit them into ior */
1130 t0 = r1 /* temporary register 0 */
1347 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1348 copy %r1,%r24
1351 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1353 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1383 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1385 copy %r0,%r1 /* Write zero to target register */
1652 %r1 clobbered by system call macro in userspace
1712 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1713 ldo TASK_REGS(%r1),%r1
1714 reg_save %r1
1718 STREG %r28, PT_CR27(%r1)
1731 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1732 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1734 LDREG PT_CR27(%r1), %r3
1736 reg_restore %r1
1759 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1760 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1761 reg_restore %r1
1768 LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
1779 mfctl %cr30, %r1
1780 LDREG TI_TASK(%r1),%r1
1781 STREG %r28,TASK_PT_GR28(%r1)
1808 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1809 ldo TASK_REGS(%r1), %r26 /* struct pt_regs *regs */
1819 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1820 ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
1826 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1829 ldw TASK_FLAGS(%r1),%r19
1834 ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
1837 LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
1840 LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
1841 LDREG TASK_PT_GR19(%r1),%r19
1842 LDREG TASK_PT_GR20(%r1),%r20
1843 LDREG TASK_PT_GR21(%r1),%r21
1844 LDREG TASK_PT_GR22(%r1),%r22
1845 LDREG TASK_PT_GR23(%r1),%r23
1846 LDREG TASK_PT_GR24(%r1),%r24
1847 LDREG TASK_PT_GR25(%r1),%r25
1848 LDREG TASK_PT_GR26(%r1),%r26
1849 LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
1850 LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
1851 LDREG TASK_PT_GR29(%r1),%r29
1852 LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
1855 LDREG TASK_PT_GR30(%r1),%r1 /* Get user sp */
1857 copy %r1,%r30 /* Restore user sp */
1858 mfsp %sr3,%r1 /* Get user space id */
1859 mtsp %r1,%sr7 /* Restore sr7 */
1864 mtsp %r1,%sr4 /* Restore sr4 */
1865 mtsp %r1,%sr5 /* Restore sr5 */
1866 mtsp %r1,%sr6 /* Restore sr6 */
1875 extrd,u,*<> %r30,63,1,%r1
1878 xor %r30,%r1,%r30
1890 LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
1906 STREG %r20,TASK_PT_PSW(%r1)
1911 STREG %r25,TASK_PT_SR3(%r1)
1912 STREG %r25,TASK_PT_SR4(%r1)
1913 STREG %r25,TASK_PT_SR5(%r1)
1914 STREG %r25,TASK_PT_SR6(%r1)
1915 STREG %r25,TASK_PT_SR7(%r1)
1916 STREG %r25,TASK_PT_IASQ0(%r1)
1917 STREG %r25,TASK_PT_IASQ1(%r1)
1929 ldo TASK_REGS(%r1),%r25
1934 STREG %r2,TASK_PT_SR0(%r1)
1938 STREG %r2,TASK_PT_SR1(%r1)
1941 STREG %r0,TASK_PT_SR2(%r1)
1943 LDREG TASK_PT_GR31(%r1),%r2
1945 STREG %r2,TASK_PT_IAOQ0(%r1)
1947 STREG %r2,TASK_PT_IAOQ1(%r1)
1952 LDREG TASK_PT_IAOQ0(%r1),%r2
1954 STREG %r2,TASK_PT_IAOQ0(%r1)
1955 LDREG TASK_PT_IAOQ1(%r1),%r2
1957 STREG %r2,TASK_PT_IAOQ1(%r1)
2004 copy %sp, %r1
2018 STREG %r1, -136(%sp)
2026 STREG %r1, -68(%sp)
2046 * r1. This routine can't be used for shadowed registers, since
2048 * registers we put a -1 into r1 to indicate that the register
2056 copy %r0,%r1
2057 bv %r0(%r25) /* r1 - shadowed */
2058 ldi -1,%r1
2060 copy %r2,%r1
2062 copy %r3,%r1
2064 copy %r4,%r1
2066 copy %r5,%r1
2068 copy %r6,%r1
2070 copy %r7,%r1
2072 ldi -1,%r1
2074 ldi -1,%r1
2076 copy %r10,%r1
2078 copy %r11,%r1
2080 copy %r12,%r1
2082 copy %r13,%r1
2084 copy %r14,%r1
2086 copy %r15,%r1
2088 ldi -1,%r1
2090 ldi -1,%r1
2092 copy %r18,%r1
2094 copy %r19,%r1
2096 copy %r20,%r1
2098 copy %r21,%r1
2100 copy %r22,%r1
2102 copy %r23,%r1
2104 ldi -1,%r1
2106 ldi -1,%r1
2108 copy %r26,%r1
2110 copy %r27,%r1
2112 copy %r28,%r1
2114 copy %r29,%r1
2116 copy %r30,%r1
2118 copy %r31,%r1
2124 * copy the value of r1 into the general register specified in
2130 copy %r1,%r0
2131 bv %r0(%r25) /* r1 */
2132 copy %r1,%r1
2134 copy %r1,%r2
2136 copy %r1,%r3
2138 copy %r1,%r4
2140 copy %r1,%r5
2142 copy %r1,%r6
2144 copy %r1,%r7
2146 copy %r1,%r8
2148 copy %r1,%r9
2150 copy %r1,%r10
2152 copy %r1,%r11
2154 copy %r1,%r12
2156 copy %r1,%r13
2158 copy %r1,%r14
2160 copy %r1,%r15
2162 copy %r1,%r16
2164 copy %r1,%r17
2166 copy %r1,%r18
2168 copy %r1,%r19
2170 copy %r1,%r20
2172 copy %r1,%r21
2174 copy %r1,%r22
2176 copy %r1,%r23
2178 copy %r1,%r24
2180 copy %r1,%r25
2182 copy %r1,%r26
2184 copy %r1,%r27
2186 copy %r1,%r28
2188 copy %r1,%r29
2190 copy %r1,%r30
2192 copy %r1,%r31
|
| H A D | pacache.S | 58 load32 PA(1f), %r1
68 mtctl %r1, %cr18 /* IIAOQ head */
69 ldo 4(%r1), %r1
70 mtctl %r1, %cr18 /* IIAOQ tail */
71 load32 REAL_MODE_PSW, %r1
72 mtctl %r1, %ipsw
76 1: load32 PA(cache_info), %r1
80 LDREG ITLB_SID_BASE(%r1), %r20
81 LDREG ITLB_SID_STRIDE(%r1), %r21
82 LDREG ITLB_SID_COUNT(%r1), %r22
83 LDREG ITLB_OFF_BASE(%r1), %arg0
84 LDREG ITLB_OFF_STRIDE(%r1), %arg1
85 LDREG ITLB_OFF_COUNT(%r1), %arg2
86 LDREG ITLB_LOOP(%r1), %arg3
123 LDREG DTLB_SID_BASE(%r1), %r20
124 LDREG DTLB_SID_STRIDE(%r1), %r21
125 LDREG DTLB_SID_COUNT(%r1), %r22
126 LDREG DTLB_OFF_BASE(%r1), %arg0
127 LDREG DTLB_OFF_STRIDE(%r1), %arg1
128 LDREG DTLB_OFF_COUNT(%r1), %arg2
129 LDREG DTLB_LOOP(%r1), %arg3
169 load32 2f, %r1
179 mtctl %r1, %cr18 /* IIAOQ head */
180 ldo 4(%r1), %r1
181 mtctl %r1, %cr18 /* IIAOQ tail */
182 load32 KERNEL_PSW, %r1
183 or %r1, %r19, %r1 /* I-bit to state on entry */
184 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
202 load32 cache_info, %r1
206 LDREG ICACHE_BASE(%r1), %arg0
207 LDREG ICACHE_STRIDE(%r1), %arg1
208 LDREG ICACHE_COUNT(%r1), %arg2
209 LDREG ICACHE_LOOP(%r1), %arg3
269 load32 cache_info, %r1
273 LDREG DCACHE_BASE(%r1), %arg0
274 LDREG DCACHE_STRIDE(%r1), %arg1
275 LDREG DCACHE_COUNT(%r1), %arg2
276 LDREG DCACHE_LOOP(%r1), %arg3
336 ldil L%pa_tlb_lock,%r1
337 ldo R%pa_tlb_lock(%r1),\la
367 ldi (PAGE_SIZE / 128), %r1
388 addib,COND(>),n -1, %r1, 1b
397 ldi (PAGE_SIZE / 64), %r1
417 addib,COND(>),n -1, %r1, 1b
441 ldi (PAGE_SIZE / 128), %r1
486 addib,COND(>),n -1, %r1, 1b
499 ldi (PAGE_SIZE / 64), %r1
535 addib,COND(>),n -1, %r1, 1b
596 ldil L%(__PAGE_OFFSET), %r1
597 sub %r26, %r1, %r26
598 sub %r25, %r1, %r23
639 ldi (PAGE_SIZE / 128), %r1
687 addib,COND(>),n -1, %r1, 1b /* bundle 10 */
691 ldi (PAGE_SIZE / 64), %r1
736 addib,COND(>) -1, %r1,1b
779 ldi (PAGE_SIZE / 128), %r1
800 addib,COND(>) -1, %r1, 1b
804 ldi (PAGE_SIZE / 64), %r1
822 addib,COND(>) -1, %r1, 1b
862 ldil L%dcache_stride, %r1
863 ldw R%dcache_stride(%r1), r31
938 ldil L%icache_stride, %r1
939 ldw R%icache_stride(%r1), %r31
992 ldil L%dcache_stride, %r1
993 ldw R%dcache_stride(%r1), %r23
1035 ldil L%dcache_stride, %r1
1036 ldw R%dcache_stride(%r1), %r23
1077 ldil L%dcache_stride, %r1
1078 ldw R%dcache_stride(%r1), %r23
1098 ldil L%dcache_stride, %r1
1099 ldw R%dcache_stride(%r1), %r23
1120 ldil L%icache_stride, %r1
1121 ldw R%icache_stride(%r1), %r23
1141 ldil L%icache_stride, %r1
1142 ldw R%icache_stride(%r1), %r23
1184 ldil L%icache_stride, %r1
1185 ldw R%icache_stride(%r1), %r23
1213 load32 PA(1f), %r1
1223 mtctl %r1, %cr18 /* IIAOQ head */
1224 ldo 4(%r1), %r1
1225 mtctl %r1, %cr18 /* IIAOQ tail */
1226 load32 REAL_MODE_PSW, %r1
1227 mtctl %r1, %ipsw
1269 load32 2f, %r1
1279 mtctl %r1, %cr18 /* IIAOQ head */
1280 ldo 4(%r1), %r1
1281 mtctl %r1, %cr18 /* IIAOQ tail */
1282 load32 KERNEL_PSW, %r1
1283 mtctl %r1, %ipsw
|
| H A D | real2.S | 90 b,l save_control_regs,%r2 /* modifies r1, r2, r28 */
105 b,l restore_control_regs, %r2 /* modifies r1, r2, r26 */
125 # define PUSH_CR(r, where) mfctl r, %r1 ! STREG,ma %r1, REG_SZ(where)
126 # define POP_CR(r, where) LDREG,mb -REG_SZ(where), %r1 ! mtctl %r1, r
165 load32 PA(rfi_v2r_1), %r1
175 mtctl %r1, %cr18 /* IIAOQ head */
176 ldo 4(%r1), %r1
177 mtctl %r1, %cr18 /* IIAOQ tail */
178 load32 REAL_MODE_PSW, %r1
179 mtctl %r1, %cr22
199 load32 (rfi_r2v_1), %r1
209 mtctl %r1, %cr18 /* IIAOQ head */
210 ldo 4(%r1), %r1
211 mtctl %r1, %cr18 /* IIAOQ tail */
212 load32 KERNEL_PSW, %r1
213 mtctl %r1, %cr22
268 b,l save_control_regs,%r2 /* modifies r1, r2, r28 */
276 b,l restore_control_regs, %r2 /* modifies r1, r2, r26 */
|
| H A D | perf_asm.S | 114 ;* %r1 - scratch
150 extrd,u arg1,63,6,%r1 ; setup shift amount by bits to move
152 mtsar %r1
153 shladd arg0,2,%r0,%r1 ; %r1 = 4 * RDR number
154 blr %r1,%r0 ; branch to 8-instruction sequence
167 shrpd ret0,%r0,%sar,%r1
168 MTDIAG_1 (1) ; mtdiag %dr1, %r1
191 shrpd ret0,%r0,%sar,%r1
287 shrpd ret0,%r0,%sar,%r1
299 shrpd ret0,%r0,%sar,%r1
335 shrpd ret0,%r0,%sar,%r1
371 shrpd ret0,%r0,%sar,%r1
383 shrpd ret0,%r0,%sar,%r1
479 shrpd ret0,%r0,%sar,%r1
491 shrpd ret0,%r0,%sar,%r1
527 shrpd ret0,%r0,%sar,%r1
594 shladd arg0,2,%r0,%r1 ; %r1 = 4 * RDR number
595 blr %r1,%r0 ; branch to 8-instruction sequence
1013 ;* %r1 - scratch
1043 extrd,u arg1,63,6,%r1
1045 mtsar %r1
1046 shladd arg0,2,%r0,%r1 ; %r1 = 4 * RDR number
1047 blr %r1,%r0 ; branch to 8-instruction sequence
1056 shrpd ret0,%r0,%sar,%r1
1065 shrpd ret0,%r0,%sar,%r1
1137 shrpd ret0,%r0,%sar,%r1
1146 shrpd ret0,%r0,%sar,%r1
1155 shrpd ret0,%r0,%sar,%r1
1164 shrpd ret0,%r0,%sar,%r1
1173 shrpd ret0,%r0,%sar,%r1
1182 shrpd ret0,%r0,%sar,%r1
1191 shrpd ret0,%r0,%sar,%r1
1209 shrpd ret0,%r0,%sar,%r1
1218 shrpd ret0,%r0,%sar,%r1
1290 shrpd ret0,%r0,%sar,%r1
1299 shrpd ret0,%r0,%sar,%r1
1326 shrpd ret0,%r0,%sar,%r1
1335 shrpd ret0,%r0,%sar,%r1
1390 shladd arg0,2,%r0,%r1 ; %r1 = 4 * RDR number
1391 blr %r1,%r0 ; branch to 8-instruction sequence
|
| /linux-4.1.27/arch/parisc/lib/ |
| H A D | lusercopy.S | 49 mfctl %cr30,%r1
50 ldw TI_SEGMENT(%r1),%r22
51 mfsp %sr3,%r1
53 copy %r0,%r1
54 mtsp %r1,%sr1
58 ldil L%\lbl, %r1
59 ldo R%\lbl(%r1), %r1
60 bv %r0(%r1)
110 1: ldbs,ma 1(%sr1,%r26),%r1
112 comib,=,n 0,%r1,$lslen_done
114 2: ldbs,ma 1(%sr1,%r26),%r1
|
| /linux-4.1.27/arch/arm/crypto/ |
| H A D | aes-armv4.S | 153 stmdb sp!,{r1,r4-r12,lr}
163 ldrb r1,[r12,#7]
169 orr r1,r1,r4,lsl#8
171 orr r1,r1,r5,lsl#16
173 orr r1,r1,r6,lsl#24
188 ldr r1,[r12,#4]
193 rev r1,r1
204 rev r1,r1
209 str r1,[r12,#4]
218 mov r4,r1,lsr#24
220 mov r5,r1,lsr#16
222 mov r6,r1,lsr#8
228 strb r1,[r12,#7]
252 eor r1,r1,r5
264 and r7,lr,r1,lsr#16 @ i0
266 and r8,lr,r1
268 and r9,lr,r1,lsr#8
270 mov r1,r1,lsr#24
276 ldr r1,[r10,r1,lsl#2] @ Te0[s1>>24]
283 eor r1,r1,r4,ror#24
291 eor r1,r1,r8,ror#8
303 eor r1,r1,r8,ror#16
313 eor r1,r1,r4
326 and r7,lr,r1,lsr#16 @ i0
328 and r8,lr,r1
330 and r9,lr,r1,lsr#8
332 mov r1,r1,lsr#24
338 ldrb r1,[r10,r1,lsl#2] @ Te4[s1>>24]
345 eor r1,r4,r1,lsl#24
353 eor r1,r1,r8,lsl#16
366 eor r1,r1,r8,lsl#8
374 eor r1,r1,r4
393 teq r1,#128
395 teq r1,#192
397 teq r1,#256
405 mov lr,r1 @ bits
414 ldrb r1,[r12,#7]
420 orr r1,r1,r4,lsl#8
422 orr r1,r1,r5,lsl#16
424 orr r1,r1,r6,lsl#24
437 str r1,[r11,#-12]
443 ldr r1,[r12,#4]
448 rev r1,r1
453 str r1,[r11,#-12]
480 eor r1,r1,r0 @ rk[5]=rk[1]^rk[4]
482 eor r2,r2,r1 @ rk[6]=rk[2]^rk[5]
483 str r1,[r11,#-12]
544 eor r1,r1,r0 @ rk[7]=rk[1]^rk[6]
546 eor r2,r2,r1 @ rk[8]=rk[2]^rk[7]
547 str r1,[r11,#-20]
613 eor r1,r1,r0 @ rk[9]=rk[1]^rk[8]
615 eor r2,r2,r1 @ rk[10]=rk[2]^rk[9]
616 str r1,[r11,#-28]
677 ldr r1,[r7,#4]
685 str r1,[r8,#16+4]
706 and r1,r0,r9
709 eor r1,r4,r1,lsl#1 @ tp2
711 and r4,r1,r7
712 and r2,r1,r9
723 eor r4,r1,r2
726 eor r4,r4,r1,ror#24
848 stmdb sp!,{r1,r4-r12,lr}
858 ldrb r1,[r12,#7]
864 orr r1,r1,r4,lsl#8
866 orr r1,r1,r5,lsl#16
868 orr r1,r1,r6,lsl#24
883 ldr r1,[r12,#4]
888 rev r1,r1
899 rev r1,r1
904 str r1,[r12,#4]
913 mov r4,r1,lsr#24
915 mov r5,r1,lsr#16
917 mov r6,r1,lsr#8
923 strb r1,[r12,#7]
947 eor r1,r1,r5
959 and r7,lr,r1 @ i0
961 and r8,lr,r1,lsr#16
963 and r9,lr,r1,lsr#8
965 mov r1,r1,lsr#24
971 ldr r1,[r10,r1,lsl#2] @ Td0[s1>>24]
978 eor r1,r1,r4,ror#8
986 eor r1,r1,r8,ror#24
998 eor r1,r1,r8,ror#16
1008 eor r1,r1,r4
1031 and r7,lr,r1 @ i0
1033 and r8,lr,r1,lsr#16
1035 and r9,lr,r1,lsr#8
1038 ARM( ldrb r1,[r10,r1,lsr#24] ) @ Td4[s1>>24]
1039 THUMB( add r1,r10,r1,lsr#24 ) @ Td4[s1>>24]
1040 THUMB( ldrb r1,[r1] )
1044 eor r1,r4,r1,lsl#8
1058 eor r1,r8,r1,lsl#16
1073 eor r1,r1,r8,lsl#8
1081 eor r1,r1,r4
|
| /linux-4.1.27/arch/powerpc/crypto/ |
| H A D | sha1-spe-asm.S | 62 stwu r1,-128(r1); /* create stack frame */ \
63 evstdw r14,8(r1); /* We must save non volatile */ \
64 evstdw r15,16(r1); /* registers. Take the chance */ \
65 evstdw r16,24(r1); /* and save the SPE part too */ \
66 evstdw r17,32(r1); \
67 evstdw r18,40(r1); \
68 evstdw r19,48(r1); \
69 evstdw r20,56(r1); \
70 evstdw r21,64(r1); \
71 evstdw r22,72(r1); \
72 evstdw r23,80(r1);
76 evldw r14,8(r1); /* restore SPE registers */ \
77 evldw r15,16(r1); \
78 evldw r16,24(r1); \
79 evldw r17,32(r1); \
80 evldw r18,40(r1); \
81 evldw r19,48(r1); \
82 evldw r20,56(r1); \
83 evldw r21,64(r1); \
84 evldw r22,72(r1); \
85 evldw r23,80(r1); \
87 stw r0,8(r1); /* Delete sensitive data */ \
88 stw r0,16(r1); /* that we might have pushed */ \
89 stw r0,24(r1); /* from other context that runs */ \
90 stw r0,32(r1); /* the same code. Assume that */ \
91 stw r0,40(r1); /* the lower part of the GPRs */ \
92 stw r0,48(r1); /* were already overwritten on */ \
93 stw r0,56(r1); /* the way down to here */ \
94 stw r0,64(r1); \
95 stw r0,72(r1); \
96 stw r0,80(r1); \
97 addi r1,r1,128; /* cleanup stack frame */
|
| H A D | sha256-spe-asm.S | 53 stwu r1,-128(r1); /* create stack frame */ \
54 evstdw r14,8(r1); /* We must save non volatile */ \
55 evstdw r15,16(r1); /* registers. Take the chance */ \
56 evstdw r16,24(r1); /* and save the SPE part too */ \
57 evstdw r17,32(r1); \
58 evstdw r18,40(r1); \
59 evstdw r19,48(r1); \
60 evstdw r20,56(r1); \
61 evstdw r21,64(r1); \
62 evstdw r22,72(r1); \
63 evstdw r23,80(r1); \
64 stw r24,88(r1); /* save normal registers */ \
65 stw r25,92(r1);
69 evldw r14,8(r1); /* restore SPE registers */ \
70 evldw r15,16(r1); \
71 evldw r16,24(r1); \
72 evldw r17,32(r1); \
73 evldw r18,40(r1); \
74 evldw r19,48(r1); \
75 evldw r20,56(r1); \
76 evldw r21,64(r1); \
77 evldw r22,72(r1); \
78 evldw r23,80(r1); \
79 lwz r24,88(r1); /* restore normal registers */ \
80 lwz r25,92(r1); \
82 stw r0,8(r1); /* Delete sensitive data */ \
83 stw r0,16(r1); /* that we might have pushed */ \
84 stw r0,24(r1); /* from other context that runs */ \
85 stw r0,32(r1); /* the same code. Assume that */ \
86 stw r0,40(r1); /* the lower part of the GPRs */ \
87 stw r0,48(r1); /* was already overwritten on */ \
88 stw r0,56(r1); /* the way down to here */ \
89 stw r0,64(r1); \
90 stw r0,72(r1); \
91 stw r0,80(r1); \
92 addi r1,r1,128; /* cleanup stack frame */
|
| H A D | aes-spe-modes.S | 59 stw rI0,96(r1); /* save 32 bit registers */ \
60 stw rI1,100(r1); \
61 stw rI2,104(r1); \
62 stw rI3,108(r1);
65 lwz rI0,96(r1); /* restore 32 bit registers */ \
66 lwz rI1,100(r1); \
67 lwz rI2,104(r1); \
68 lwz rI3,108(r1);
72 stw rG0,112(r1); /* save 32 bit registers */ \
73 stw rG1,116(r1); \
74 stw rG2,120(r1); \
75 stw rG3,124(r1);
79 lwz rG0,112(r1); /* restore 32 bit registers */ \
80 lwz rG1,116(r1); \
81 lwz rG2,120(r1); \
82 lwz rG3,124(r1);
86 stwu r1,-160(r1); /* create stack frame */ \
88 stw r0,8(r1); /* save link register */ \
90 evstdw r14,16(r1); \
92 evstdw r15,24(r1); /* We must save non volatile */ \
93 evstdw r16,32(r1); /* registers. Take the chance */ \
94 evstdw r17,40(r1); /* and save the SPE part too */ \
95 evstdw r18,48(r1); \
96 evstdw r19,56(r1); \
97 evstdw r20,64(r1); \
98 evstdw r21,72(r1); \
99 evstdw r22,80(r1); \
100 evstdw r23,88(r1); \
104 lwz r0,8(r1); \
105 evldw r14,16(r1); /* restore SPE registers */ \
106 evldw r15,24(r1); \
107 evldw r16,32(r1); \
108 evldw r17,40(r1); \
109 evldw r18,48(r1); \
110 evldw r19,56(r1); \
111 evldw r20,64(r1); \
112 evldw r21,72(r1); \
113 evldw r22,80(r1); \
114 evldw r23,88(r1); \
118 stw r0,16(r1); /* delete sensitive data */ \
119 stw r0,24(r1); /* that we might have pushed */ \
120 stw r0,32(r1); /* from other context that runs */ \
121 stw r0,40(r1); /* the same code */ \
122 stw r0,48(r1); \
123 stw r0,56(r1); \
124 stw r0,64(r1); \
125 stw r0,72(r1); \
126 stw r0,80(r1); \
127 stw r0,88(r1); \
128 addi r1,r1,160; /* cleanup stack frame */
|
| H A D | sha1-powerpc-asm.S | 116 PPC_STLU r1,-INT_FRAME_SIZE(r1)
117 SAVE_8GPRS(14, r1)
118 SAVE_10GPRS(22, r1)
176 REST_8GPRS(14, r1)
177 REST_10GPRS(22, r1)
178 addi r1,r1,INT_FRAME_SIZE
|
| /linux-4.1.27/arch/cris/arch-v32/kernel/ |
| H A D | head.S | 74 | REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0), $r1
139 move $r1, $s1 ; kbase_lo.
148 move $r1, $s1 ; kbase_lo
204 move.d text_start, $r1 ; Destination.
207 sub.d $r1, $r4
209 move.w $r3, [$r1+]
210 cmp.d $r2, $r1
216 move.d romfs_length, $r1
217 move.d $r0, [$r1]
226 move.d romfs_length, $r1
227 move.d $r0, [$r1]
229 move.d romfs_start, $r1
230 move.d $r4, [$r1]
232 move.d romfs_in_flash, $r1
233 move.d $r0, [$r1]
244 move.d nand_boot, $r1 ; tell axisflashmap we're booting from NAND
245 move.d $r0, [$r1]
247 move.d romfs_in_flash, $r1 ; (directly accessed) flash
248 move.d $r0, [$r1]
257 move.d romfs_length, $r1
258 move.d $r0, [$r1]
277 move.d romfs_length, $r1
278 move.d $r0, [$r1]
280 move.d romfs_start, $r1
281 move.d $r9, [$r1]
283 move.d romfs_in_flash, $r1
284 move.d $r0, [$r1]
300 move.d [$r0], $r1
301 cmp.d CRAMFS_MAGIC, $r1 ; cramfs magic?
304 cmp.d JHEAD_MAGIC, $r1 ; jffs2 (jhead) magic?
319 move.d _end, $r1 ; start of cramfs -> r1
321 move.d $r1, [$r3] ; store at romfs_start (for axisflashmap)
326 add.d $r2, $r1
332 move.w $r3, [$r1]
334 subq 2, $r1
345 move.d romfs_in_flash, $r1
346 move.d $r0, [$r1]
348 move.d nand_boot, $r1
349 move.d $r0, [$r1]
365 move.b [$r11+], $r1
366 move.b $r1, [$r10+]
379 move.d etrax_irv, $r1 ; Set the exception base register and pointer.
380 move.d $r0, [$r1]
384 move.d _end, $r1
386 cmp.d $r1, $r0
|
| /linux-4.1.27/arch/arm/include/uapi/asm/ |
| H A D | swab.h | 41 t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */ __arch_swab32()
44 t &= ~0x00FF0000; /* bic r1,r1,#0x00FF0000 */ __arch_swab32()
45 x ^= (t >> 8); /* eor r0,r0,r1,lsr #8 */ __arch_swab32()
|
| /linux-4.1.27/arch/tile/kernel/ |
| H A D | entry.S | 31 { move r2, lr; lnk r1 }
32 { move r4, r52; addli r1, r1, dump_stack - . }
38 { move r2, lr; lnk r1 }
39 { move r4, r52; addli r1, r1, KBacktraceIterator_init_current - . }
61 movei r1, 1
63 mtspr INTERRUPT_CRITICAL_SECTION, r1
|
| H A D | regs_32.S | 66 addli r4, r1, TASK_STRUCT_THREAD_KSP_OFFSET
79 addli r4, r1, TASK_STRUCT_THREAD_PC_OFFSET
108 .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, \
124 lnk r1
126 sw r0, r1
129 mfspr r1, INTERRUPT_CRITICAL_SECTION
130 shli r1, r1, SPR_EX_CONTEXT_1_1__ICS_SHIFT
131 ori r1, r1, KERNEL_PL
133 sw r0, r1
|
| H A D | regs_64.S | 65 addli r4, r1, TASK_STRUCT_THREAD_KSP_OFFSET
79 addli r4, r1, TASK_STRUCT_THREAD_PC_OFFSET
108 .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, \
124 lnk r1
126 st r0, r1
129 mfspr r1, INTERRUPT_CRITICAL_SECTION
130 shli r1, r1, SPR_EX_CONTEXT_1_1__ICS_SHIFT
131 ori r1, r1, KERNEL_PL
133 st r0, r1
|
| /linux-4.1.27/arch/arm/vfp/ |
| H A D | vfphw.S | 42 mov r1, \arg
59 mov r1, \arg1
89 VFPFMRX r1, FPEXC @ Is the VFP enabled?
90 DBGSTR1 "fpexc %08x", r1
91 tst r1, #FPEXC_EN
96 orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set
98 bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled
119 tst r1, #FPEXC_EX @ is there additional state to save?
122 tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
127 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
160 ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
162 tst r1, #FPEXC_EX @ is there additional state to restore?
165 tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
174 tst r1, #FPEXC_EX
179 VFPFMXR FPEXC, r1 @ Restore FPEXC last
191 tst r1, #FPEXC_EX | FPEXC_DEX
202 orr r1, r1, #FPEXC_DEX
220 @ r1 holds the FPEXC value
231 @ r1 - FPEXC
235 tst r1, #FPEXC_EX @ is there additional state to save?
238 tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
242 stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
275 tbl_branch r1, r3, #3
289 1: fmrrd r0, r1, d\dr
296 1: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
304 mov r1, #0
311 1: fmdrr d\dr, r0, r1
318 1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr
|
| /linux-4.1.27/arch/parisc/math-emu/ |
| H A D | fpudispatch.c | 290 u_int r1,r2,t; /* operand register offsets */ decode_0c() local
303 r1 = extru(ir,fpr1pos,5) * sizeof(double)/sizeof(u_int); decode_0c()
304 if (r1 == 0) /* map fr0 source to constant zero */ decode_0c()
305 r1 = fpzeroreg; decode_0c()
323 r1 &= ~3; decode_0c()
324 fpregs[t+3] = fpregs[r1+3]; decode_0c()
325 fpregs[t+2] = fpregs[r1+2]; decode_0c()
327 fpregs[t+1] = fpregs[r1+1]; decode_0c()
329 fpregs[t] = fpregs[r1]; decode_0c()
338 r1 &= ~3; decode_0c()
339 fpregs[t+3] = fpregs[r1+3]; decode_0c()
340 fpregs[t+2] = fpregs[r1+2]; decode_0c()
342 fpregs[t+1] = fpregs[r1+1]; decode_0c()
345 fpregs[t] = fpregs[r1] & 0x7fffffff; decode_0c()
354 r1 &= ~3; decode_0c()
355 fpregs[t+3] = fpregs[r1+3]; decode_0c()
356 fpregs[t+2] = fpregs[r1+2]; decode_0c()
358 fpregs[t+1] = fpregs[r1+1]; decode_0c()
361 fpregs[t] = fpregs[r1] ^ 0x80000000; decode_0c()
370 r1 &= ~3; decode_0c()
371 fpregs[t+3] = fpregs[r1+3]; decode_0c()
372 fpregs[t+2] = fpregs[r1+2]; decode_0c()
374 fpregs[t+1] = fpregs[r1+1]; decode_0c()
377 fpregs[t] = fpregs[r1] | 0x80000000; decode_0c()
383 return(sgl_fsqrt(&fpregs[r1],0, decode_0c()
386 return(dbl_fsqrt(&fpregs[r1],0, decode_0c()
395 return(sgl_frnd(&fpregs[r1],0, decode_0c()
398 return(dbl_frnd(&fpregs[r1],0, decode_0c()
427 return(sgl_to_dbl_fcnvff(&fpregs[r1],0, decode_0c()
430 return(dbl_to_sgl_fcnvff(&fpregs[r1],0, decode_0c()
438 return(sgl_to_sgl_fcnvxf(&fpregs[r1],0, decode_0c()
441 return(sgl_to_dbl_fcnvxf(&fpregs[r1],0, decode_0c()
444 return(dbl_to_sgl_fcnvxf(&fpregs[r1],0, decode_0c()
447 return(dbl_to_dbl_fcnvxf(&fpregs[r1],0, decode_0c()
453 return(sgl_to_sgl_fcnvfx(&fpregs[r1],0, decode_0c()
456 return(sgl_to_dbl_fcnvfx(&fpregs[r1],0, decode_0c()
459 return(dbl_to_sgl_fcnvfx(&fpregs[r1],0, decode_0c()
462 return(dbl_to_dbl_fcnvfx(&fpregs[r1],0, decode_0c()
468 return(sgl_to_sgl_fcnvfxt(&fpregs[r1],0, decode_0c()
471 return(sgl_to_dbl_fcnvfxt(&fpregs[r1],0, decode_0c()
474 return(dbl_to_sgl_fcnvfxt(&fpregs[r1],0, decode_0c()
477 return(dbl_to_dbl_fcnvfxt(&fpregs[r1],0, decode_0c()
483 return(sgl_to_sgl_fcnvuf(&fpregs[r1],0, decode_0c()
486 return(sgl_to_dbl_fcnvuf(&fpregs[r1],0, decode_0c()
489 return(dbl_to_sgl_fcnvuf(&fpregs[r1],0, decode_0c()
492 return(dbl_to_dbl_fcnvuf(&fpregs[r1],0, decode_0c()
498 return(sgl_to_sgl_fcnvfu(&fpregs[r1],0, decode_0c()
501 return(sgl_to_dbl_fcnvfu(&fpregs[r1],0, decode_0c()
504 return(dbl_to_sgl_fcnvfu(&fpregs[r1],0, decode_0c()
507 return(dbl_to_dbl_fcnvfu(&fpregs[r1],0, decode_0c()
513 return(sgl_to_sgl_fcnvfut(&fpregs[r1],0, decode_0c()
516 return(sgl_to_dbl_fcnvfut(&fpregs[r1],0, decode_0c()
519 return(dbl_to_sgl_fcnvfut(&fpregs[r1],0, decode_0c()
522 return(dbl_to_dbl_fcnvfut(&fpregs[r1],0, decode_0c()
558 retval = sgl_fcmp(&fpregs[r1], decode_0c()
565 retval = dbl_fcmp(&fpregs[r1], decode_0c()
589 retval = sgl_fcmp(&fpregs[r1], decode_0c()
596 retval = dbl_fcmp(&fpregs[r1], decode_0c()
640 return(sgl_fadd(&fpregs[r1],&fpregs[r2], decode_0c()
643 return(dbl_fadd(&fpregs[r1],&fpregs[r2], decode_0c()
652 return(sgl_fsub(&fpregs[r1],&fpregs[r2], decode_0c()
655 return(dbl_fsub(&fpregs[r1],&fpregs[r2], decode_0c()
664 return(sgl_fmpy(&fpregs[r1],&fpregs[r2], decode_0c()
667 return(dbl_fmpy(&fpregs[r1],&fpregs[r2], decode_0c()
676 return(sgl_fdiv(&fpregs[r1],&fpregs[r2], decode_0c()
679 return(dbl_fdiv(&fpregs[r1],&fpregs[r2], decode_0c()
688 return(sgl_frem(&fpregs[r1],&fpregs[r2], decode_0c()
691 return(dbl_frem(&fpregs[r1],&fpregs[r2], decode_0c()
709 u_int r1,r2,t; /* operand register offsets */ decode_0e() local
718 r1 = ((extru(ir,fpr1pos,5)<<1)|(extru(ir,fpxr1pos,1))); decode_0e()
719 if (r1 == 0) decode_0e()
720 r1 = fpzeroreg; decode_0e()
734 r1 &= ~1; decode_0e()
751 fpregs[t+1] = fpregs[r1+1]; decode_0e()
753 fpregs[t] = fpregs[r1]; decode_0e()
762 fpregs[t+1] = fpregs[r1+1]; decode_0e()
764 fpregs[t] = fpregs[r1] & 0x7fffffff; decode_0e()
773 fpregs[t+1] = fpregs[r1+1]; decode_0e()
775 fpregs[t] = fpregs[r1] ^ 0x80000000; decode_0e()
784 fpregs[t+1] = fpregs[r1+1]; decode_0e()
786 fpregs[t] = fpregs[r1] | 0x80000000; decode_0e()
792 return(sgl_fsqrt(&fpregs[r1],0, decode_0e()
795 return(dbl_fsqrt(&fpregs[r1],0, decode_0e()
804 return(sgl_frnd(&fpregs[r1],0, decode_0e()
807 return(dbl_frnd(&fpregs[r1],0, decode_0e()
834 return(sgl_to_dbl_fcnvff(&fpregs[r1],0, decode_0e()
837 return(dbl_to_sgl_fcnvff(&fpregs[r1],0, decode_0e()
845 return(sgl_to_sgl_fcnvxf(&fpregs[r1],0, decode_0e()
848 return(sgl_to_dbl_fcnvxf(&fpregs[r1],0, decode_0e()
851 return(dbl_to_sgl_fcnvxf(&fpregs[r1],0, decode_0e()
854 return(dbl_to_dbl_fcnvxf(&fpregs[r1],0, decode_0e()
860 return(sgl_to_sgl_fcnvfx(&fpregs[r1],0, decode_0e()
863 return(sgl_to_dbl_fcnvfx(&fpregs[r1],0, decode_0e()
866 return(dbl_to_sgl_fcnvfx(&fpregs[r1],0, decode_0e()
869 return(dbl_to_dbl_fcnvfx(&fpregs[r1],0, decode_0e()
875 return(sgl_to_sgl_fcnvfxt(&fpregs[r1],0, decode_0e()
878 return(sgl_to_dbl_fcnvfxt(&fpregs[r1],0, decode_0e()
881 return(dbl_to_sgl_fcnvfxt(&fpregs[r1],0, decode_0e()
884 return(dbl_to_dbl_fcnvfxt(&fpregs[r1],0, decode_0e()
890 return(sgl_to_sgl_fcnvuf(&fpregs[r1],0, decode_0e()
893 return(sgl_to_dbl_fcnvuf(&fpregs[r1],0, decode_0e()
896 return(dbl_to_sgl_fcnvuf(&fpregs[r1],0, decode_0e()
899 return(dbl_to_dbl_fcnvuf(&fpregs[r1],0, decode_0e()
905 return(sgl_to_sgl_fcnvfu(&fpregs[r1],0, decode_0e()
908 return(sgl_to_dbl_fcnvfu(&fpregs[r1],0, decode_0e()
911 return(dbl_to_sgl_fcnvfu(&fpregs[r1],0, decode_0e()
914 return(dbl_to_dbl_fcnvfu(&fpregs[r1],0, decode_0e()
920 return(sgl_to_sgl_fcnvfut(&fpregs[r1],0, decode_0e()
923 return(sgl_to_dbl_fcnvfut(&fpregs[r1],0, decode_0e()
926 return(dbl_to_sgl_fcnvfut(&fpregs[r1],0, decode_0e()
929 return(dbl_to_dbl_fcnvfut(&fpregs[r1],0, decode_0e()
962 retval = sgl_fcmp(&fpregs[r1], decode_0e()
969 retval = dbl_fcmp(&fpregs[r1], decode_0e()
994 retval = sgl_fcmp(&fpregs[r1], decode_0e()
1001 retval = dbl_fcmp(&fpregs[r1], decode_0e()
1036 return(sgl_fadd(&fpregs[r1],&fpregs[r2], decode_0e()
1039 return(dbl_fadd(&fpregs[r1],&fpregs[r2], decode_0e()
1045 return(sgl_fsub(&fpregs[r1],&fpregs[r2], decode_0e()
1048 return(dbl_fsub(&fpregs[r1],&fpregs[r2], decode_0e()
1069 * impyu(&fpregs[r1],&fpregs[r2], decode_0e()
1080 return(sgl_fmpy(&fpregs[r1], decode_0e()
1083 return(dbl_fmpy(&fpregs[r1], decode_0e()
1090 return(sgl_fdiv(&fpregs[r1],&fpregs[r2], decode_0e()
1093 return(dbl_fdiv(&fpregs[r1],&fpregs[r2], decode_0e()
1099 return(sgl_frem(&fpregs[r1],&fpregs[r2], decode_0e()
1102 return(dbl_frem(&fpregs[r1],&fpregs[r2], decode_0e()
|
| /linux-4.1.27/arch/arc/kernel/ |
| H A D | fpu.c | 20 * dexcl1 0, r1, r0 ; where r1:r0 is the 64 bit val
24 * daddh11 r1, r3, r3 ; get "hi" into r1 (dpfp1 unchanged)
25 * dexcl1 r0, r1, r3 ; get "low" into r0 (dpfp1 low clobbered)
26 * dexcl1 0, r1, r0 ; restore dpfp1 to orig value
|
| /linux-4.1.27/tools/testing/selftests/powerpc/pmu/ebb/ |
| H A D | ebb_handler.S | 10 /* ppc-asm.h defines most of the reg aliases, but not r1/r2. */
11 #define r1 1 define
20 * Back chain ------+ <- r1 <-------+
37 * Back chain <+ <- updated r1 --------+
65 #define SAVE_GPR(n) std n,GPR_SAVE(n)(r1)
66 #define REST_GPR(n) ld n,GPR_SAVE(n)(r1)
69 #define SAVE_VSR(n, b) li b, VSR_SAVE(n); stxvd2x n,b,r1
70 #define LOAD_VSR(n, b) li b, VSR_SAVE(n); lxvd2x n,b,r1
103 stdu r1,-STACK_FRAME(r1)
106 std r0,LR_SAVE(r1)
108 std r0,CCR_SAVE(r1)
110 std r0,CTR_SAVE(r1)
112 std r0,XER_SAVE(r1)
145 stfd f0, FSCR_SAVE(r1)
147 stfd f0, VSCR_SAVE(r1)
255 lfd f0, FSCR_SAVE(r1)
257 lfd f0, VSCR_SAVE(r1)
324 ld r0,XER_SAVE(r1)
326 ld r0,CTR_SAVE(r1)
328 ld r0,LR_SAVE(r1)
330 ld r0,CCR_SAVE(r1)
363 addi r1,r1,STACK_FRAME
|
| /linux-4.1.27/tools/testing/selftests/powerpc/stringloops/ |
| H A D | memcmp_64.S | 89 std r31,-8(r1)
90 std r30,-16(r1)
91 std r29,-24(r1)
92 std r28,-32(r1)
93 std r27,-40(r1)
182 ld r31,-8(r1)
183 ld r30,-16(r1)
184 ld r29,-24(r1)
185 ld r28,-32(r1)
186 ld r27,-40(r1)
228 ld r31,-8(r1)
229 ld r30,-16(r1)
230 ld r29,-24(r1)
231 ld r28,-32(r1)
232 ld r27,-40(r1)
|
| /linux-4.1.27/arch/avr32/kernel/ |
| H A D | entry-avr32b.S | 99 mfsr r1, SYSREG_PTBR
108 ld.w r3, r1[r2 << 2]
109 bfextu r1, r0, PAGE_SHIFT, PGDIR_SHIFT - PAGE_SHIFT
114 ld.w r2, r3[r1 << 2]
121 st.w r3[r1 << 2], r2
128 mfsr r1, SYSREG_MMUCR
135 1: bfins r1, r2, SYSREG_DRP_OFFSET, SYSREG_DRP_SIZE
136 mtsr SYSREG_MMUCR, r1
171 mov r1, lo(swapper_pg_dir)
172 orh r1, hi(swapper_pg_dir)
173 ld.w r3, r1[r2 << 2]
176 mfsr r1, SYSREG_PTBR
177 st.w r1[r2 << 2], r3
199 mfsr r1, SYSREG_RSR_SUP
204 stm --sp, r0-r1
208 ld.w r1, r0[TI_flags]
209 bld r1, TIF_SYSCALL_TRACE
231 ld.w r1, r0[TI_flags]
232 andl r1, _TIF_ALLWORK_MASK, COH
262 mov pc, r1
271 bld r1, TIF_SYSCALL_TRACE
276 ld.w r1, r0[TI_flags]
278 1: bld r1, TIF_NEED_RESCHED
283 ld.w r1, r0[TI_flags]
287 tst r1, r2
294 ld.w r1, r0[TI_flags]
297 3: bld r1, TIF_BREAKPOINT
383 ld.w r1, r0[TI_task]
384 ld.w r2, r1[TSK_active_mm]
392 mov r1, lr
490 mfsr r1, SYSREG_TLBEAR
492 lsr r2, r1, PGDIR_SHIFT
494 lsl r1, (32 - PGDIR_SHIFT)
495 lsr r1, (32 - PGDIR_SHIFT) + PAGE_SHIFT
500 add r2, r0, r1 << 2
534 ld.w r1, r0[TI_flags]
535 andl r1, _TIF_WORK_MASK, COH
553 ld.w r1, r0[TI_flags]
554 bld r1, TIF_NEED_RESCHED
565 mfsr r1, SYSREG_SR
582 ld.w r1, r0[TI_flags]
585 bld r1, TIF_NEED_RESCHED
590 ld.w r1, r0[TI_flags]
594 tst r1, r2
601 ld.w r1, r0[TI_flags]
604 2: bld r1, TIF_BREAKPOINT
633 ld.w r1, r0[TI_flags]
635 tst r1, r2
638 bld r1, TIF_SINGLE_STEP
686 mov r1, r2
691 mtsr SYSREG_SR, r1
767 ld.w r1, r0[TI_flags]
768 andl r1, _TIF_WORK_MASK, COH
793 ld.w r1, r0[TI_flags]
794 bld r1, TIF_CPU_GOING_TO_SLEEP
800 sub r1, pc, . - cpu_idle_skip_sleep
801 stdsp sp[REG_PC], r1
807 ld.w r1, r0[TI_flags]
808 bld r1, TIF_NEED_RESCHED
|
| /linux-4.1.27/arch/powerpc/mm/ |
| H A D | hash_low_64.S | 57 std r0,16(r1)
58 stdu r1,-STACKFRAMESIZE(r1)
60 std r6,STK_PARAM(R6)(r1)
61 std r8,STK_PARAM(R8)(r1)
62 std r9,STK_PARAM(R9)(r1)
71 std r27,STK_REG(R27)(r1)
72 std r28,STK_REG(R28)(r1)
73 std r29,STK_REG(R29)(r1)
74 std r30,STK_REG(R30)(r1)
75 std r31,STK_REG(R31)(r1)
169 std r3,STK_PARAM(R4)(r1)
199 ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
204 ld r10,STK_PARAM(R9)(r1) /* segment size */
224 ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
229 ld r10,STK_PARAM(R9)(r1) /* segment size */
267 ld r6,STK_PARAM(R6)(r1)
271 ld r27,STK_REG(R27)(r1)
272 ld r28,STK_REG(R28)(r1)
273 ld r29,STK_REG(R29)(r1)
274 ld r30,STK_REG(R30)(r1)
275 ld r31,STK_REG(R31)(r1)
276 addi r1,r1,STACKFRAMESIZE
277 ld r0,16(r1)
301 ld r8,STK_PARAM(R9)(r1) /* segment size */
302 ld r9,STK_PARAM(R8)(r1) /* get "flags" param */
326 ld r6,STK_PARAM(R6)(r1)
351 std r0,16(r1)
352 stdu r1,-STACKFRAMESIZE(r1)
354 std r6,STK_PARAM(R6)(r1)
355 std r8,STK_PARAM(R8)(r1)
356 std r9,STK_PARAM(R9)(r1)
367 std r25,STK_REG(R25)(r1)
368 std r26,STK_REG(R26)(r1)
369 std r27,STK_REG(R27)(r1)
370 std r28,STK_REG(R28)(r1)
371 std r29,STK_REG(R29)(r1)
372 std r30,STK_REG(R30)(r1)
373 std r31,STK_REG(R31)(r1)
485 std r3,STK_PARAM(R4)(r1)
506 ld r6,STK_PARAM(R6)(r1)
528 ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
533 ld r10,STK_PARAM(R9)(r1) /* segment size */
557 ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
562 ld r10,STK_PARAM(R9)(r1) /* segment size */
597 ld r7,STK_PARAM(R9)(r1) /* ssize */
598 ld r8,STK_PARAM(R8)(r1) /* flags */
614 ld r6,STK_PARAM(R6)(r1)
635 ld r25,STK_REG(R25)(r1)
636 ld r26,STK_REG(R26)(r1)
637 ld r27,STK_REG(R27)(r1)
638 ld r28,STK_REG(R28)(r1)
639 ld r29,STK_REG(R29)(r1)
640 ld r30,STK_REG(R30)(r1)
641 ld r31,STK_REG(R31)(r1)
642 addi r1,r1,STACKFRAMESIZE
643 ld r0,16(r1)
669 ld r8,STK_PARAM(R9)(r1) /* segment size */
670 ld r9,STK_PARAM(R8)(r1) /* get "flags" param */
684 ld r6,STK_PARAM(R6)(r1)
697 ld r6,STK_PARAM(R6)(r1)
714 std r0,16(r1)
715 stdu r1,-STACKFRAMESIZE(r1)
717 std r6,STK_PARAM(R6)(r1)
718 std r8,STK_PARAM(R8)(r1)
719 std r9,STK_PARAM(R9)(r1)
728 std r27,STK_REG(R27)(r1)
729 std r28,STK_REG(R28)(r1)
730 std r29,STK_REG(R29)(r1)
731 std r30,STK_REG(R30)(r1)
732 std r31,STK_REG(R31)(r1)
830 std r3,STK_PARAM(R4)(r1)
863 ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
868 ld r10,STK_PARAM(R9)(r1) /* segment size */
888 ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
893 ld r10,STK_PARAM(R9)(r1) /* segment size */
931 ld r6,STK_PARAM(R6)(r1)
935 ld r27,STK_REG(R27)(r1)
936 ld r28,STK_REG(R28)(r1)
937 ld r29,STK_REG(R29)(r1)
938 ld r30,STK_REG(R30)(r1)
939 ld r31,STK_REG(R31)(r1)
940 addi r1,r1,STACKFRAMESIZE
941 ld r0,16(r1)
965 ld r8,STK_PARAM(R9)(r1) /* segment size */
966 ld r9,STK_PARAM(R8)(r1) /* get "flags" param */
990 ld r6,STK_PARAM(R6)(r1)
|
| /linux-4.1.27/drivers/block/paride/ |
| H A D | fit2.c | 56 w0(0); a = r1(); fit2_read_regr()
57 w0(1); b = r1(); fit2_read_regr()
73 w0(0); a = r1(); w0(1); b = r1(); fit2_read_block()
74 w0(3); c = r1(); w0(2); d = r1(); fit2_read_block()
79 a = r1(); w0(3); b = r1(); fit2_read_block()
80 w0(1); c = r1(); w0(0); d = r1(); fit2_read_block()
|
| H A D | comm.c | 54 w2(6); l = r1(); w0(0x80); h = r1(); w2(4); comm_read_regr()
63 case 4: w3(r+0x20); (void)r1(); comm_read_regr()
85 case 4: w3(r); (void)r1(); w4(val); comm_write_regr()
116 w0(0); w2(6); l = r1(); comm_read_block()
117 w0(0x80); h = r1(); w2(4); comm_read_block()
129 case 2: w3(0x68); (void)r1(); w2(0x24); comm_read_block()
134 case 3: w3(0x68); (void)r1(); w2(0x24); comm_read_block()
139 case 4: w3(0x68); (void)r1(); w2(0x24); comm_read_block()
163 case 2: w3(0x48); (void)r1(); comm_write_block()
167 case 3: w3(0x48); (void)r1(); comm_write_block()
171 case 4: w3(0x48); (void)r1(); comm_write_block()
|
| H A D | ktti.c | 49 a = r1(); w2(0xc); b = r1(); w2(9); w2(0xc); w2(9); ktti_read_regr()
60 a = r1(); w2(0xc); b = r1(); w2(9); ktti_read_block()
62 a = r1(); w2(0xc); b = r1(); w2(9); ktti_read_block()
|
| /linux-4.1.27/arch/score/include/asm/ |
| H A D | asmmacro.h | 22 .set r1
23 sw r1, [r0, PT_R1]
92 .set r1
93 ldis r1, 0x00ff
94 and r30, r30, r1
95 not r1, r1 variable
97 and r31, r31, r1
119 .set r1
120 lw r1, [r0, PT_R1]
|
| /linux-4.1.27/arch/arm/common/ |
| H A D | vlock.S | 58 @ r1: CPU ID (0-based index within cluster)
60 add r1, r1, #VLOCK_VOTING_OFFSET
62 voting_begin r0, r1, r2
70 strb r1, [r0, #VLOCK_OWNER_OFFSET] @ submit my vote
72 voting_end r0, r1, r2 @ implies DMB
91 eor r0, r1, r2 @ zero if I won, else nonzero
95 voting_end r0, r1, r2
103 mov r1, #VLOCK_OWNER_NONE
104 strb r1, [r0, #VLOCK_OWNER_OFFSET]
|
| /linux-4.1.27/arch/sh/kernel/ |
| H A D | relocate_kernel.S | 56 mov.l r1, @-r15
71 mov.l r1, @-r15
98 mov.l @r15+, r1
112 mov.l @r15+, r1
156 mov #-16,r1
157 and r1,r2
194 mov.l @(0, r5), r1
196 mov.l r1, @(0, r2)
199 mov.l @(4, r5), r1
201 mov.l r1, @(4, r2)
204 mov.l @(8, r5), r1
206 mov.l r1, @(8, r2)
209 mov.l @(12, r5), r1
211 mov.l r1, @(12, r2)
|
| /linux-4.1.27/arch/unicore32/boot/compressed/ |
| H A D | head.S | 29 ldm (r1, r2, r3, r5, r6, r7, r8), [r0]+
31 sub.a r0, r0, r1 @ calculate the delta offset
66 1001: ldw r1, [r7+], #0
67 add r1, r1, r0
68 stw.w r1, [r7]+, #4
100 mov r1, sp @ malloc space above stack
133 * r1: free_mem_ptr_p
162 LC0: .word LC0 @ r1
174 2001: ldb.w r1, [r0]+, #1
175 csub.a r1, #0
182 movc p1.c1, r1, #1
183 csub.a r1, #'\n'
184 cmoveq r1, #'\r'
|
| /linux-4.1.27/arch/powerpc/kvm/ |
| H A D | booke_interrupts.S | 219 stw r1, VCPU_GPR(R1)(r4)
233 lwz r1, VCPU_HOST_STACK(r4)
251 lwz r3, HOST_RUN(r1)
252 lwz r2, HOST_R2(r1)
321 lwz r14, HOST_NV_GPR(R14)(r1)
322 lwz r15, HOST_NV_GPR(R15)(r1)
323 lwz r16, HOST_NV_GPR(R16)(r1)
324 lwz r17, HOST_NV_GPR(R17)(r1)
325 lwz r18, HOST_NV_GPR(R18)(r1)
326 lwz r19, HOST_NV_GPR(R19)(r1)
327 lwz r20, HOST_NV_GPR(R20)(r1)
328 lwz r21, HOST_NV_GPR(R21)(r1)
329 lwz r22, HOST_NV_GPR(R22)(r1)
330 lwz r23, HOST_NV_GPR(R23)(r1)
331 lwz r24, HOST_NV_GPR(R24)(r1)
332 lwz r25, HOST_NV_GPR(R25)(r1)
333 lwz r26, HOST_NV_GPR(R26)(r1)
334 lwz r27, HOST_NV_GPR(R27)(r1)
335 lwz r28, HOST_NV_GPR(R28)(r1)
336 lwz r29, HOST_NV_GPR(R29)(r1)
337 lwz r30, HOST_NV_GPR(R30)(r1)
338 lwz r31, HOST_NV_GPR(R31)(r1)
341 lwz r4, HOST_STACK_LR(r1)
342 lwz r5, HOST_CR(r1)
343 addi r1, r1, HOST_STACK_SIZE
355 stwu r1, -HOST_STACK_SIZE(r1)
356 stw r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
359 stw r3, HOST_RUN(r1)
361 stw r3, HOST_STACK_LR(r1)
363 stw r5, HOST_CR(r1)
366 stw r14, HOST_NV_GPR(R14)(r1)
367 stw r15, HOST_NV_GPR(R15)(r1)
368 stw r16, HOST_NV_GPR(R16)(r1)
369 stw r17, HOST_NV_GPR(R17)(r1)
370 stw r18, HOST_NV_GPR(R18)(r1)
371 stw r19, HOST_NV_GPR(R19)(r1)
372 stw r20, HOST_NV_GPR(R20)(r1)
373 stw r21, HOST_NV_GPR(R21)(r1)
374 stw r22, HOST_NV_GPR(R22)(r1)
375 stw r23, HOST_NV_GPR(R23)(r1)
376 stw r24, HOST_NV_GPR(R24)(r1)
377 stw r25, HOST_NV_GPR(R25)(r1)
378 stw r26, HOST_NV_GPR(R26)(r1)
379 stw r27, HOST_NV_GPR(R27)(r1)
380 stw r28, HOST_NV_GPR(R28)(r1)
381 stw r29, HOST_NV_GPR(R29)(r1)
382 stw r30, HOST_NV_GPR(R30)(r1)
383 stw r31, HOST_NV_GPR(R31)(r1)
414 stw r2, HOST_R2(r1)
449 lwz r1, VCPU_GPR(R1)(r4)
|
| H A D | bookehv_interrupts.S | 73 PPC_STL r1, VCPU_GPR(R1)(r4)
75 PPC_LL r1, VCPU_HOST_STACK(r4)
76 PPC_LL r2, HOST_R2(r1)
444 PPC_LL r3, HOST_RUN(r1)
481 PPC_LL r5, HOST_STACK_LR(r1)
482 lwz r6, HOST_CR(r1)
508 PPC_LL r14, HOST_NV_GPR(R14)(r1)
509 PPC_LL r15, HOST_NV_GPR(R15)(r1)
510 PPC_LL r16, HOST_NV_GPR(R16)(r1)
511 PPC_LL r17, HOST_NV_GPR(R17)(r1)
512 PPC_LL r18, HOST_NV_GPR(R18)(r1)
513 PPC_LL r19, HOST_NV_GPR(R19)(r1)
514 PPC_LL r20, HOST_NV_GPR(R20)(r1)
515 PPC_LL r21, HOST_NV_GPR(R21)(r1)
516 PPC_LL r22, HOST_NV_GPR(R22)(r1)
517 PPC_LL r23, HOST_NV_GPR(R23)(r1)
518 PPC_LL r24, HOST_NV_GPR(R24)(r1)
519 PPC_LL r25, HOST_NV_GPR(R25)(r1)
520 PPC_LL r26, HOST_NV_GPR(R26)(r1)
521 PPC_LL r27, HOST_NV_GPR(R27)(r1)
522 PPC_LL r28, HOST_NV_GPR(R28)(r1)
523 PPC_LL r29, HOST_NV_GPR(R29)(r1)
524 PPC_LL r30, HOST_NV_GPR(R30)(r1)
525 PPC_LL r31, HOST_NV_GPR(R31)(r1)
530 addi r1, r1, HOST_STACK_SIZE
539 stwu r1, -HOST_STACK_SIZE(r1)
540 PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
543 PPC_STL r3, HOST_RUN(r1)
546 PPC_STL r3, HOST_STACK_LR(r1)
548 stw r5, HOST_CR(r1)
551 PPC_STL r14, HOST_NV_GPR(R14)(r1)
552 PPC_STL r15, HOST_NV_GPR(R15)(r1)
553 PPC_STL r16, HOST_NV_GPR(R16)(r1)
554 PPC_STL r17, HOST_NV_GPR(R17)(r1)
555 PPC_STL r18, HOST_NV_GPR(R18)(r1)
556 PPC_STL r19, HOST_NV_GPR(R19)(r1)
557 PPC_STL r20, HOST_NV_GPR(R20)(r1)
558 PPC_STL r21, HOST_NV_GPR(R21)(r1)
559 PPC_STL r22, HOST_NV_GPR(R22)(r1)
560 PPC_STL r23, HOST_NV_GPR(R23)(r1)
561 PPC_STL r24, HOST_NV_GPR(R24)(r1)
562 PPC_STL r25, HOST_NV_GPR(R25)(r1)
563 PPC_STL r26, HOST_NV_GPR(R26)(r1)
564 PPC_STL r27, HOST_NV_GPR(R27)(r1)
565 PPC_STL r28, HOST_NV_GPR(R28)(r1)
566 PPC_STL r29, HOST_NV_GPR(R29)(r1)
567 PPC_STL r30, HOST_NV_GPR(R30)(r1)
568 PPC_STL r31, HOST_NV_GPR(R31)(r1)
592 PPC_STL r2, HOST_R2(r1)
650 PPC_LL r1, VCPU_GPR(R1)(r4)
|
| H A D | book3s_interrupts.S | 76 PPC_STL r0,PPC_LR_STKOFF(r1)
79 PPC_STLU r1, -SWITCH_FRAME_SIZE(r1)
82 SAVE_2GPRS(3, r1)
85 SAVE_NVGPRS(r1)
89 stw r14, _CCR(r1)
92 PPC_STL r0, _LINK(r1)
102 REST_GPR(4, r1)
159 PPC_LL r3, GPR4(r1) /* vcpu pointer */
184 PPC_LL r7, GPR4(r1)
209 REST_2GPRS(3, r1)
221 PPC_LL r4, _LINK(r1)
224 lwz r14, _CCR(r1)
228 REST_NVGPRS(r1)
230 addi r1, r1, SWITCH_FRAME_SIZE
235 PPC_LL r4, _LINK(r1)
236 PPC_STL r4, (PPC_LR_STKOFF + SWITCH_FRAME_SIZE)(r1)
239 REST_2GPRS(3, r1)
250 REST_GPR(4, r1)
|
| H A D | book3s_hv_interrupts.S | 44 std r0,PPC_LR_STKOFF(r1)
47 stdu r1, -SWITCH_FRAME_SIZE(r1)
50 SAVE_NVGPRS(r1)
52 std r3, _CCR(r1)
151 REST_NVGPRS(r1)
152 ld r4, _CCR(r1)
155 addi r1, r1, SWITCH_FRAME_SIZE
156 ld r0, PPC_LR_STKOFF(r1)
|
| /linux-4.1.27/arch/blackfin/lib/ |
| H A D | divsi3.S | 45 r1 = abs r1; /* now both positive, r3.30 means "negate result", define
48 cc = r0 < r1;
50 r2 = r1 >> 15;
53 r2 = r1 << 16;
76 r1 = r3 >> 31; /* add overflow issue back in */ define
77 r0 = r0 + r1;
78 r1 = -r0; define
80 if cc r0 = r1;
138 r1 = r3 >> 31; define
139 r2 = r2 + r1;
188 r1 = r3 >> 31; define
189 r0 = r0 + r1;
|
| /linux-4.1.27/arch/sh/kernel/cpu/shmobile/ |
| H A D | sleep.S | 25 #define k1 r1
131 mov #4, r1
132 mov.l r1, @r0
144 mov #0, r1
145 mov.l r1, @r0
165 mov #0x80, r1
174 mov.l @(SH_SLEEP_RESUME, r5), r1
175 mov.l r1, @r0
179 mov #0x20, r1
187 mov #0x10, r1
192 mov #0x00, r1
198 mov.l r1, @r0
206 mov.l @(r0, r5), r1
208 mov.l @r1, r1
210 mov.l r1, @(r0, r5)
236 mov.l r1, @-r15
375 mov.l @(r0, r5), r1
379 mov.l r1, @r0
393 mov.l @r15+, r1
|
| /linux-4.1.27/arch/s390/boot/compressed/ |
| H A D | head.S | 31 la %r1,0x200
32 mvc 0(mover_end-mover,%r1),mover-.LPG1(%r13)
35 br %r1
|
| /linux-4.1.27/arch/blackfin/kernel/ |
| H A D | ftrace-entry.S | 39 [--sp] = r1;
48 r1 = [sp + 16]; /* skip the 4 local regs on stack */ define
64 r1 = [sp++]; define
120 [--sp] = r1;
132 r1 = [sp + 16]; /* skip the 4 local regs on stack */ define
141 r1 = [sp++]; define
162 [--sp] = r1;
167 r1 = rets; /* unsigned long self_addr */ define
170 r1 = [sp]; /* unsigned long self_addr */ define
176 r1 += -MCOUNT_INSN_SIZE;
190 [--sp] = r1;
202 r1 = [sp++]; define
|
| /linux-4.1.27/security/selinux/ss/ |
| H A D | mls_types.h | 47 #define mls_range_contains(r1, r2) \
48 (mls_level_dom(&(r2).level[0], &(r1).level[0]) && \
49 mls_level_dom(&(r1).level[1], &(r2).level[1]))
|
| /linux-4.1.27/kernel/bpf/ |
| H A D | helpers.c | 26 static u64 bpf_map_lookup_elem(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5) bpf_map_lookup_elem() argument
32 struct bpf_map *map = (struct bpf_map *) (unsigned long) r1; bpf_map_lookup_elem()
54 static u64 bpf_map_update_elem(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5) bpf_map_update_elem() argument
56 struct bpf_map *map = (struct bpf_map *) (unsigned long) r1; bpf_map_update_elem()
75 static u64 bpf_map_delete_elem(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5) bpf_map_delete_elem() argument
77 struct bpf_map *map = (struct bpf_map *) (unsigned long) r1; bpf_map_delete_elem()
93 static u64 bpf_get_prandom_u32(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5) bpf_get_prandom_u32() argument
104 static u64 bpf_get_smp_processor_id(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5) bpf_get_smp_processor_id() argument
|
| /linux-4.1.27/firmware/av7110/ |
| H A D | Boot.S | 61 ldr r1, wait_address
66 ldmia r1!, {r5-r12}
68 cmp r1, r2
72 wait: ldrh r1, [r4] // wait for flag!=0
73 cmp r1, #0
76 mov r1, r13 // buffer address
87 ldmia r1!, {r5-r12}
89 ldmia r1!, {r5-r12}
|
| /linux-4.1.27/arch/unicore32/lib/ |
| H A D | backtrace.S | 40 adr r1, 1b
41 sub offset, r0, r1
74 ldw r1, [frame+], #-4 @ get saved lr
78 ldw r1, [sv_pc+], #-4 @ if stmfd sp, {args} exists,
80 cxor.a r3, r1 >> #14
86 1004: ldw r1, [sv_pc+], #0 @ if stmfd {, fp, ip, lr, pc}
88 cxor.a r3, r1 >> #14
101 mov r1, frame
121 mov instr, r1
134 cmoveq r1, #'\n'
135 cmovne r1, #' '
|
| /linux-4.1.27/arch/ia64/kernel/ |
| H A D | minstate.h | 50 mov r20=r1; /* A */ \
62 adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 \
72 (pUStk) addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \
73 (pKStk) mov r1=sp; /* get sp */ \
76 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
80 (pKStk) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \
84 adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \
85 adds r16=PT(CR_IPSR),r1; \
95 adds r16=PT(R8),r1; /* initialize first base pointer */ \
96 adds r17=PT(R9),r1; /* initialize second base pointer */ \
129 .mem.offset 0,0; st8.spill [r16]=r20,16; /* save original r1 */ \
131 adds r12=-16,r1; /* switch to kernel memory stack (with 16 bytes of scratch) */ \
143 adds r2=IA64_PT_REGS_R16_OFFSET,r1; \
146 movl r1=__gp; /* establish kernel global pointer */ \
|
| /linux-4.1.27/tools/perf/arch/s390/util/ |
| H A D | dwarf-regs.c | 15 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
|
| /linux-4.1.27/arch/powerpc/math-emu/ |
| H A D | udivmodti4.c | 13 _FP_W_TYPE q0, q1, r0, r1; _fp_udivmodti4() local
42 r1 = 0; _fp_udivmodti4()
112 r1 = 0; _fp_udivmodti4()
126 r1 = n1; _fp_udivmodti4()
154 r1 = n1; _fp_udivmodti4()
184 r1 = n1 >> bm; _fp_udivmodti4()
190 r[0] = r0, r[1] = r1; _fp_udivmodti4()
|
| /linux-4.1.27/arch/m32r/kernel/ |
| H A D | entry.S | 32 * @(0x14,sp) - r1
134 ld r1, R1(r8)
135 jl r1
242 mv r1, r9 ; arg2 : __u32 thread_info_flags
253 ld r1, R1(sp)
302 mv r1, sp ; arg1(regs)
336 mv r0, r1 ; arg0(regs)
404 push r1
409 mv r0, r1
416 pop r1
433 srl3 r1, r4, #4
435 and3 r1, r1, #0x0000ffff
438 beqz r1, inst
441 srli r1, #1
444 and3 r1, r4, #2
445 srli r1, #1
446 or3 r1, r1, #8
454 or r1, r3
458 * r1 : unsigned long error-code
479 ldi r1, #0x30 ; error_code
489 ldi r1, #0x20 ; error_code
498 ldi r1, #0 ; error_code ; FIXME
510 ldi r1, #0 ; error_code
519 ldi r1, #0 ; error_code ; FIXME
529 push r1
545 pop r1
|
| /linux-4.1.27/arch/arm/mach-sa1100/ |
| H A D | sleep.S | 34 mcr p15, 0, r1, c15, c2, 2
57 mov r1, #0
58 str r1, [r5]
66 * r1 = &MSC1
82 ldr r1, =MSC1
89 ldr r4, [r1]
121 str r4, [r1]
|