Lines Matching refs:r1
88 mov r1, #0x1
91 str r1, [r2, r3] @ write to l2dis_3630
112 mov r1, #0 @ set task id for ROM code in r1
192 ldr r1, kernel_flush
194 bx r1
211 ldr r1, kernel_flush
212 blx r1
387 ldr r1, sram_base
392 stmia r1!, {r3} @ *dst = val
395 ldr r1, sram_base
396 blx r1
401 ldr r1, pm_prepwstst_core_p
402 ldr r2, [r1]
407 ldr r1, control_mem_rta
409 str r2, [r1]
419 ldr r1, pm_pwstctrl_mpu
420 ldr r2, [r1]
425 adr r1, l2dis_3630_offset @ address for offset
426 ldr r0, [r1] @ value for offset
427 ldr r0, [r1, r0] @ value at l2dis_3630
435 ldr r1, [r0]
436 and r1, #0x700
437 cmp r1, #0x300
444 mov r1, #0 @ set task id for ROM code in r1
453 mov r1, #0 @ set task id for ROM code in r1
467 mov r1, #0 @ set task ID for ROM code in r1
499 ldr r1, [r0] @ value for offset
500 ldr r1, [r0, r1] @ value at l2dis_3630
501 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
503 mrc p15, 0, r1, c1, c0, 1
504 orr r1, r1, #2 @ re-enable L2 cache
505 mcr p15, 0, r1, c1, c0, 1