Searched refs:primary (Results 1 - 200 of 786) sorted by relevance

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/linux-4.1.27/drivers/mfd/
H A Dwm831x-irq.c31 int primary; member in struct:wm831x_irq_data
38 .primary = WM831X_TEMP_INT,
43 .primary = WM831X_GP_INT,
48 .primary = WM831X_GP_INT,
53 .primary = WM831X_GP_INT,
58 .primary = WM831X_GP_INT,
63 .primary = WM831X_GP_INT,
68 .primary = WM831X_GP_INT,
73 .primary = WM831X_GP_INT,
78 .primary = WM831X_GP_INT,
83 .primary = WM831X_GP_INT,
88 .primary = WM831X_GP_INT,
93 .primary = WM831X_GP_INT,
98 .primary = WM831X_GP_INT,
103 .primary = WM831X_GP_INT,
108 .primary = WM831X_GP_INT,
113 .primary = WM831X_GP_INT,
118 .primary = WM831X_GP_INT,
123 .primary = WM831X_ON_PIN_INT,
128 .primary = WM831X_PPM_INT,
133 .primary = WM831X_PPM_INT,
138 .primary = WM831X_PPM_INT,
143 .primary = WM831X_WDOG_INT,
148 .primary = WM831X_RTC_INT,
153 .primary = WM831X_RTC_INT,
158 .primary = WM831X_CHG_INT,
163 .primary = WM831X_CHG_INT,
168 .primary = WM831X_CHG_INT,
173 .primary = WM831X_CHG_INT,
178 .primary = WM831X_CHG_INT,
183 .primary = WM831X_CHG_INT,
188 .primary = WM831X_CHG_INT,
193 .primary = WM831X_CHG_INT,
198 .primary = WM831X_TCHDATA_INT,
203 .primary = WM831X_TCHPD_INT,
208 .primary = WM831X_AUXADC_INT,
213 .primary = WM831X_AUXADC_INT,
218 .primary = WM831X_AUXADC_INT,
223 .primary = WM831X_AUXADC_INT,
228 .primary = WM831X_AUXADC_INT,
233 .primary = WM831X_CS_INT,
238 .primary = WM831X_CS_INT,
243 .primary = WM831X_HC_INT,
248 .primary = WM831X_HC_INT,
253 .primary = WM831X_UV_INT,
258 .primary = WM831X_UV_INT,
263 .primary = WM831X_UV_INT,
268 .primary = WM831X_UV_INT,
273 .primary = WM831X_UV_INT,
278 .primary = WM831X_UV_INT,
283 .primary = WM831X_UV_INT,
288 .primary = WM831X_UV_INT,
293 .primary = WM831X_UV_INT,
298 .primary = WM831X_UV_INT,
303 .primary = WM831X_UV_INT,
308 .primary = WM831X_UV_INT,
313 .primary = WM831X_UV_INT,
318 .primary = WM831X_UV_INT,
452 /* The processing of the primary interrupt occurs in a thread so that
458 int primary, status_addr, ret; wm831x_irq_thread() local
463 primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS); wm831x_irq_thread()
464 if (primary < 0) { wm831x_irq_thread()
466 primary); wm831x_irq_thread()
470 /* The touch interrupts are visible in the primary register as wm831x_irq_thread()
475 if (primary & WM831X_TCHPD_INT) wm831x_irq_thread()
478 if (primary & WM831X_TCHDATA_INT) wm831x_irq_thread()
481 primary &= ~(WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT); wm831x_irq_thread()
486 if (!(primary & wm831x_irqs[i].primary)) wm831x_irq_thread()
522 if (primary == WM831X_GP_INT && wm831x_irq_thread()
533 if (primary == WM831X_GP_INT && wm831x_irq_thread()
H A Dwm8350-irq.c40 int primary; member in struct:wm8350_irq_data
48 .primary = WM8350_OC_INT,
54 .primary = WM8350_UV_INT,
59 .primary = WM8350_UV_INT,
64 .primary = WM8350_UV_INT,
69 .primary = WM8350_UV_INT,
74 .primary = WM8350_UV_INT,
79 .primary = WM8350_UV_INT,
84 .primary = WM8350_UV_INT,
89 .primary = WM8350_UV_INT,
94 .primary = WM8350_UV_INT,
99 .primary = WM8350_UV_INT,
104 .primary = WM8350_CHG_INT,
109 .primary = WM8350_CHG_INT,
114 .primary = WM8350_CHG_INT,
119 .primary = WM8350_CHG_INT,
124 .primary = WM8350_CHG_INT,
129 .primary = WM8350_CHG_INT,
134 .primary = WM8350_CHG_INT,
139 .primary = WM8350_CHG_INT,
144 .primary = WM8350_CHG_INT,
149 .primary = WM8350_CHG_INT,
154 .primary = WM8350_RTC_INT,
159 .primary = WM8350_RTC_INT,
164 .primary = WM8350_RTC_INT,
169 .primary = WM8350_CS_INT,
174 .primary = WM8350_CS_INT,
179 .primary = WM8350_SYS_INT,
184 .primary = WM8350_SYS_INT,
189 .primary = WM8350_SYS_INT,
194 .primary = WM8350_SYS_INT,
199 .primary = WM8350_AUXADC_INT,
204 .primary = WM8350_AUXADC_INT,
209 .primary = WM8350_AUXADC_INT,
214 .primary = WM8350_AUXADC_INT,
219 .primary = WM8350_AUXADC_INT,
224 .primary = WM8350_USB_INT,
230 .primary = WM8350_WKUP_INT,
235 .primary = WM8350_WKUP_INT,
240 .primary = WM8350_WKUP_INT,
245 .primary = WM8350_WKUP_INT,
250 .primary = WM8350_WKUP_INT,
255 .primary = WM8350_WKUP_INT,
260 .primary = WM8350_WKUP_INT,
265 .primary = WM8350_CODEC_INT,
270 .primary = WM8350_CODEC_INT,
275 .primary = WM8350_CODEC_INT,
280 .primary = WM8350_CODEC_INT,
285 .primary = WM8350_EXT_INT,
290 .primary = WM8350_EXT_INT,
295 .primary = WM8350_EXT_INT,
300 .primary = WM8350_GP_INT,
305 .primary = WM8350_GP_INT,
310 .primary = WM8350_GP_INT,
315 .primary = WM8350_GP_INT,
320 .primary = WM8350_GP_INT,
325 .primary = WM8350_GP_INT,
330 .primary = WM8350_GP_INT,
335 .primary = WM8350_GP_INT,
340 .primary = WM8350_GP_INT,
345 .primary = WM8350_GP_INT,
350 .primary = WM8350_GP_INT,
355 .primary = WM8350_GP_INT,
360 .primary = WM8350_GP_INT,
401 if (!(level_one & data->primary)) wm8350_irq()
H A Dbcm590xx.c63 dev_err(&i2c_pri->dev, "primary regmap init failed: %d\n", ret); bcm590xx_i2c_probe()
/linux-4.1.27/drivers/gpu/drm/mga/
H A Dmga_dma.c78 drm_mga_primary_buffer_t *primary = &dev_priv->prim; mga_do_dma_reset() local
82 /* The primary DMA stream should look like new right about now. mga_do_dma_reset()
84 primary->tail = 0; mga_do_dma_reset()
85 primary->space = primary->size; mga_do_dma_reset()
86 primary->last_flush = 0; mga_do_dma_reset()
105 drm_mga_primary_buffer_t *primary = &dev_priv->prim; mga_do_dma_flush() local
120 if (primary->tail == primary->last_flush) { mga_do_dma_flush()
125 tail = primary->tail + dev_priv->primary->offset; mga_do_dma_flush()
139 primary->last_flush = primary->tail; mga_do_dma_flush()
144 primary->space = primary->size - primary->tail; mga_do_dma_flush()
146 primary->space = head - tail; mga_do_dma_flush()
148 DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset)); mga_do_dma_flush()
149 DRM_DEBUG(" tail = 0x%06lx\n", (unsigned long)(tail - dev_priv->primary->offset)); mga_do_dma_flush()
150 DRM_DEBUG(" space = 0x%06x\n", primary->space); mga_do_dma_flush()
160 drm_mga_primary_buffer_t *primary = &dev_priv->prim; mga_do_dma_wrap_start() local
173 tail = primary->tail + dev_priv->primary->offset; mga_do_dma_wrap_start()
175 primary->tail = 0; mga_do_dma_wrap_start()
176 primary->last_flush = 0; mga_do_dma_wrap_start()
177 primary->last_wrap++; mga_do_dma_wrap_start()
181 if (head == dev_priv->primary->offset) mga_do_dma_wrap_start()
182 primary->space = primary->size; mga_do_dma_wrap_start()
184 primary->space = head - dev_priv->primary->offset; mga_do_dma_wrap_start()
186 DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset)); mga_do_dma_wrap_start()
187 DRM_DEBUG(" tail = 0x%06x\n", primary->tail); mga_do_dma_wrap_start()
188 DRM_DEBUG(" wrap = %d\n", primary->last_wrap); mga_do_dma_wrap_start()
189 DRM_DEBUG(" space = 0x%06x\n", primary->space); mga_do_dma_wrap_start()
194 set_bit(0, &primary->wrapped); mga_do_dma_wrap_start()
200 drm_mga_primary_buffer_t *primary = &dev_priv->prim; mga_do_dma_wrap_end() local
202 u32 head = dev_priv->primary->offset; mga_do_dma_wrap_end()
211 clear_bit(0, &primary->wrapped); mga_do_dma_wrap_end()
232 dev_priv->primary->offset)); mga_freelist_print()
238 (unsigned long)(entry->age.head - dev_priv->primary->offset)); mga_freelist_print()
336 (unsigned long)(tail->age.head - dev_priv->primary->offset) : 0, mga_freelist_get()
339 (unsigned long)(head - dev_priv->primary->offset), wrap); mga_freelist_get()
363 dev_priv->primary->offset), mga_freelist_put()
521 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary); mga_do_agp_dma_bootstrap()
523 DRM_ERROR("Unable to map primary DMA region: %d\n", err); mga_do_agp_dma_bootstrap()
570 drm_legacy_ioremap(dev_priv->primary, dev); mga_do_agp_dma_bootstrap()
574 !dev_priv->primary->handle || !dev->agp_buffer_map->handle) { mga_do_agp_dma_bootstrap()
576 dev_priv->warp->handle, dev_priv->primary->handle, mga_do_agp_dma_bootstrap()
599 * The algorithm for decreasing the size of the primary DMA buffer could be
642 * alignment of the primary or secondary DMA buffers. mga_do_pci_dma_bootstrap()
649 _DRM_READ_ONLY, &dev_priv->primary); mga_do_pci_dma_bootstrap()
655 DRM_ERROR("Unable to allocate primary DMA region: %d\n", err); mga_do_pci_dma_bootstrap()
659 if (dev_priv->primary->size != dma_bs->primary_size) { mga_do_pci_dma_bootstrap()
662 (unsigned)dev_priv->primary->size); mga_do_pci_dma_bootstrap()
663 dma_bs->primary_size = dev_priv->primary->size; mga_do_pci_dma_bootstrap()
839 dev_priv->primary = drm_legacy_findmap(dev, init->primary_offset); mga_do_init_dma()
840 if (!dev_priv->primary) { mga_do_init_dma()
841 DRM_ERROR("failed to find primary dma region!\n"); mga_do_init_dma()
853 drm_legacy_ioremap(dev_priv->primary, dev); mga_do_init_dma()
862 !dev_priv->primary->handle || mga_do_init_dma()
886 /* Init the primary DMA registers. mga_do_init_dma()
888 MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL); mga_do_init_dma()
894 dev_priv->prim.start = (u8 *) dev_priv->primary->handle; mga_do_init_dma()
895 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle mga_do_init_dma()
896 + dev_priv->primary->size); mga_do_init_dma()
897 dev_priv->prim.size = dev_priv->primary->size; mga_do_init_dma()
908 dev_priv->prim.status[0] = dev_priv->primary->offset; mga_do_init_dma()
942 if ((dev_priv->primary != NULL) mga_do_cleanup_dma()
943 && (dev_priv->primary->type != _DRM_CONSISTENT)) mga_do_cleanup_dma()
944 drm_legacy_ioremapfree(dev_priv->primary, dev); mga_do_cleanup_dma()
972 dev_priv->primary = NULL; mga_do_cleanup_dma()
H A Dmga_drv.h147 drm_local_map_t *primary; member in struct:drm_mga_private
301 dev_priv->primary->offset)); \
311 /* Never use this, always use DMA_BLOCK(...) for primary DMA output.
334 /* Buffer aging via primary DMA stream head pointer.
352 dev_priv->primary->offset); \
/linux-4.1.27/drivers/gpu/drm/
H A Ddrm_plane_helper.c40 * primary plane support on top of the normal CRTC configuration interface.
41 * Since the legacy ->set_config interface ties the primary plane together with
42 * the CRTC state this does not allow userspace to disable the primary plane
45 * restrictions as primary planes had thus. The default primary plane only
49 * Drivers are highly recommended to implement proper support for primary
66 * creating the primary plane. However drivers that still call
117 * only be false for primary planes.
174 * (including those that use the primary plane helper's drm_plane_helper_check_update()
190 * drm_primary_helper_update() - Helper for primary plane update
194 * @crtc_x: x offset of primary plane on crtc
195 * @crtc_y: y offset of primary plane on crtc
196 * @crtc_w: width of primary plane rectangle on crtc
197 * @crtc_h: height of primary plane rectangle on crtc
203 * Provides a default plane update handler for primary planes. This is handler
208 * SetPlane() on a primary plane of a disabled CRTC is not supported, and will
301 * drm_primary_helper_disable() - Helper for primary plane disable
304 * Provides a default plane disable handler for primary planes. This is handler
307 * -EINVAL the only way to disable the primary plane without driver support is
310 * Note that some hardware may be able to disable the primary plane without
312 * own disable handler that disables just the primary plane (and they'll likely
314 * disabled primary plane).
326 * drm_primary_helper_destroy() - Helper for primary plane destruction
329 * Provides a default plane destroy handler for primary planes. This handler
330 * is called during CRTC destruction. We disable the primary plane, remove
349 struct drm_plane *primary; create_primary_plane() local
352 primary = kzalloc(sizeof(*primary), GFP_KERNEL); create_primary_plane()
353 if (primary == NULL) { create_primary_plane()
354 DRM_DEBUG_KMS("Failed to allocate primary plane\n"); create_primary_plane()
362 primary->format_default = true; create_primary_plane()
365 ret = drm_universal_plane_init(dev, primary, 0, create_primary_plane()
371 kfree(primary); create_primary_plane()
372 primary = NULL; create_primary_plane()
375 return primary; create_primary_plane()
384 * Initialize a CRTC object with a default helper-provided primary plane and no
393 struct drm_plane *primary; drm_crtc_init() local
395 primary = create_primary_plane(dev); drm_crtc_init()
396 return drm_crtc_init_with_planes(dev, crtc, primary, NULL, funcs); drm_crtc_init()
499 * @crtc_x: x offset of primary plane on crtc
500 * @crtc_y: y offset of primary plane on crtc
501 * @crtc_w: width of primary plane rectangle on crtc
502 * @crtc_h: height of primary plane rectangle on crtc
H A Ddrm_crtc_helper.c55 * except for the handling of the primary plane: Atomic helpers require that the
56 * primary plane is implemented as a real standalone plane and not directly tied
201 crtc->primary->fb = NULL; __drm_helper_disable_unused_functions()
545 save_set.fb = set->crtc->primary->fb; drm_crtc_helper_set_config()
549 if (set->crtc->primary->fb != set->fb) { drm_crtc_helper_set_config()
551 if (set->crtc->primary->fb == NULL) { drm_crtc_helper_set_config()
557 set->crtc->primary->fb->pixel_format) { drm_crtc_helper_set_config()
659 set->crtc->primary->fb = set->fb; drm_crtc_helper_set_config()
665 set->crtc->primary->fb = save_set.fb; drm_crtc_helper_set_config()
680 set->crtc->primary->fb = set->fb; drm_crtc_helper_set_config()
686 set->crtc->primary->fb = save_set.fb; drm_crtc_helper_set_config()
885 crtc->x, crtc->y, crtc->primary->fb); drm_helper_resume_force_mode()
928 * the primary plane the driver must also provide the ->mode_set_nofb callback
992 * functions for the primary plane.
1001 struct drm_plane *plane = crtc->primary; drm_helper_crtc_mode_set_base()
1014 drm_atomic_set_fb_for_plane(plane_state, crtc->primary->fb); drm_helper_crtc_mode_set_base()
H A Ddrm_crtc.c617 if (crtc->primary->fb == fb) { drm_framebuffer_remove()
643 * specified primary and cursor planes.
646 * @primary: Primary plane for CRTC
656 struct drm_plane *primary, drm_crtc_init_with_planes()
663 WARN_ON(primary && primary->type != DRM_PLANE_TYPE_PRIMARY); drm_crtc_init_with_planes()
680 crtc->primary = primary; drm_crtc_init_with_planes()
682 if (primary) drm_crtc_init_with_planes()
683 primary->possible_crtcs = 1 << drm_crtc_index(crtc); drm_crtc_init_with_planes()
1141 * @type: type of plane (overlay, primary, cursor)
1213 * @is_primary: plane type (primary vs overlay)
1707 drm_mode_group_destroy(&dev->primary->mode_group); drm_reinit_primary_mode_group()
1708 drm_mode_group_init_legacy_group(dev, &dev->primary->mode_group); drm_reinit_primary_mode_group()
2004 drm_modeset_lock_crtc(crtc, crtc->primary); drm_mode_getcrtc()
2006 if (crtc->primary->fb) drm_mode_getcrtc()
2007 crtc_resp->fb_id = crtc->primary->fb->base.id; drm_mode_getcrtc()
2012 crtc_resp->x = crtc->primary->state->src_x >> 16; drm_mode_getcrtc()
2013 crtc_resp->y = crtc->primary->state->src_y >> 16; drm_mode_getcrtc()
2643 tmp->primary->old_fb = tmp->primary->fb; drm_mode_set_config_internal()
2649 crtc->primary->crtc = crtc; drm_mode_set_config_internal()
2650 crtc->primary->fb = fb; drm_mode_set_config_internal()
2654 if (tmp->primary->fb) drm_mode_set_config_internal()
2655 drm_framebuffer_reference(tmp->primary->fb); drm_mode_set_config_internal()
2656 if (tmp->primary->old_fb) drm_mode_set_config_internal()
2657 drm_framebuffer_unreference(tmp->primary->old_fb); drm_mode_set_config_internal()
2658 tmp->primary->old_fb = NULL; drm_mode_set_config_internal()
2772 if (!crtc->primary->fb) { drm_mode_setcrtc()
2777 fb = crtc->primary->fb; drm_mode_setcrtc()
2811 * Check whether the primary plane supports the fb pixel format. drm_mode_setcrtc()
2817 if (!crtc->primary->format_default) { drm_mode_setcrtc()
2818 ret = drm_plane_check_pixel_format(crtc->primary, drm_mode_setcrtc()
4937 drm_modeset_lock_crtc(crtc, crtc->primary); drm_mode_page_flip_ioctl()
4938 if (crtc->primary->fb == NULL) { drm_mode_page_flip_ioctl()
4960 if (crtc->primary->fb->pixel_format != fb->pixel_format) { drm_mode_page_flip_ioctl()
4993 crtc->primary->old_fb = crtc->primary->fb; drm_mode_page_flip_ioctl()
5003 crtc->primary->old_fb = NULL; drm_mode_page_flip_ioctl()
5011 WARN_ON(crtc->primary->fb != fb); drm_mode_page_flip_ioctl()
5019 if (crtc->primary->old_fb) drm_mode_page_flip_ioctl()
5020 drm_framebuffer_unreference(crtc->primary->old_fb); drm_mode_page_flip_ioctl()
5021 crtc->primary->old_fb = NULL; drm_mode_page_flip_ioctl()
655 drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc *crtc, struct drm_plane *primary, struct drm_plane *cursor, const struct drm_crtc_funcs *funcs) drm_crtc_init_with_planes() argument
H A Ddrm_platform.c62 driver->date, dev->primary->index); drm_get_platform_dev()
H A Ddrm_atomic_helper.c658 crtc->x = crtc->primary->state->src_x >> 16; for_each_crtc_in_state()
659 crtc->y = crtc->primary->state->src_y >> 16; for_each_crtc_in_state()
1257 * drm_atomic_helper_update_plane - Helper for primary plane update using atomic
1261 * @crtc_x: x offset of primary plane on crtc
1262 * @crtc_y: y offset of primary plane on crtc
1263 * @crtc_w: width of primary plane rectangle on crtc
1264 * @crtc_h: height of primary plane rectangle on crtc
1344 * drm_atomic_helper_disable_plane - Helper for primary plane disable using * atomic
1518 primary_state = drm_atomic_get_plane_state(state, crtc->primary); drm_atomic_helper_set_config()
1587 crtc->primary->old_fb = crtc->primary->fb; drm_atomic_helper_set_config()
1794 struct drm_plane *plane = crtc->primary; drm_atomic_helper_page_flip()
H A Ddrm_sysfs.c471 device_create_with_groups(drm_class, dev->primary->kdev, 0, drm_sysfs_connector_add()
473 "card%d-%s", dev->primary->index, drm_sysfs_connector_add()
528 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp); drm_sysfs_hotplug_event()
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dradeon_dp_mst.c25 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary, radeon_dp_mst_set_be_cntl() argument
29 struct drm_device *dev = primary->base.dev; radeon_dp_mst_set_be_cntl()
35 reg = RREG32(NI_DIG_BE_CNTL + primary->offset); radeon_dp_mst_set_be_cntl()
47 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg); radeon_dp_mst_set_be_cntl()
48 WREG32(NI_DIG_BE_CNTL + primary->offset, reg); radeon_dp_mst_set_be_cntl()
57 DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe); radeon_dp_mst_set_be_cntl()
62 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary, radeon_dp_mst_set_stream_attrib() argument
67 struct drm_device *dev = primary->base.dev; radeon_dp_mst_set_stream_attrib()
76 temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset); radeon_dp_mst_set_stream_attrib()
86 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp); radeon_dp_mst_set_stream_attrib()
87 WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp); radeon_dp_mst_set_stream_attrib()
89 WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1); radeon_dp_mst_set_stream_attrib()
92 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset); radeon_dp_mst_set_stream_attrib()
96 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset); radeon_dp_mst_set_stream_attrib()
103 struct radeon_encoder *primary) radeon_dp_mst_update_stream_attribs()
138 radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots); radeon_dp_mst_update_stream_attribs()
145 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0); radeon_dp_mst_update_stream_attribs()
385 struct radeon_encoder *radeon_encoder, *primary; radeon_mst_encoder_dpms() local
406 primary = mst_enc->primary; radeon_mst_encoder_dpms()
408 dig_enc = primary->enc_priv; radeon_mst_encoder_dpms()
424 atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0); radeon_mst_encoder_dpms()
425 atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE, radeon_mst_encoder_dpms()
430 radeon_dp_link_train(&primary->base, &mst_enc->connector->base); radeon_mst_encoder_dpms()
449 radeon_dp_mst_set_be_cntl(primary, mst_enc, radeon_mst_encoder_dpms()
453 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); radeon_mst_encoder_dpms()
456 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0, radeon_mst_encoder_dpms()
481 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); radeon_mst_encoder_dpms()
483 radeon_dp_mst_set_be_cntl(primary, mst_enc, radeon_mst_encoder_dpms()
485 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0, radeon_mst_encoder_dpms()
514 mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices; radeon_mst_mode_fixup()
516 mst_enc->primary->active_device, mst_enc->primary->devices, radeon_mst_mode_fixup()
517 mst_enc->connector->devices, mst_enc->primary->base.encoder_type); radeon_mst_mode_fixup()
543 struct radeon_encoder *radeon_encoder, *primary; radeon_mst_encoder_prepare() local
558 primary = mst_enc->primary; radeon_mst_encoder_prepare()
560 dig_enc = primary->enc_priv; radeon_mst_encoder_prepare()
565 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1); radeon_mst_encoder_prepare()
566 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder); radeon_mst_encoder_prepare()
571 DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset); radeon_mst_encoder_prepare()
650 mst_enc->primary = to_radeon_encoder(enc_master); radeon_dp_create_fake_mst_encoder()
102 radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn, struct radeon_encoder *primary) radeon_dp_mst_update_stream_attribs() argument
H A Dr100_track.h37 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
H A Dradeon_legacy_crtc.c312 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC. radeon_crtc_dpms()
314 * This is different for GPU's with a single CRTC but a primary and a radeon_crtc_dpms()
388 if (!atomic && !crtc->primary->fb) { radeon_crtc_do_set_base()
398 radeon_fb = to_radeon_framebuffer(crtc->primary->fb); radeon_crtc_do_set_base()
399 target_fb = crtc->primary->fb; radeon_crtc_do_set_base()
447 if (!atomic && fb && fb != crtc->primary->fb) { radeon_crtc_do_set_base()
558 if (!atomic && fb && fb != crtc->primary->fb) { radeon_crtc_do_set_base()
602 switch (crtc->primary->fb->bits_per_pixel) { radeon_set_crtc_timing()
1091 if (crtc->primary->fb) { radeon_crtc_disable()
1096 radeon_fb = to_radeon_framebuffer(crtc->primary->fb); radeon_crtc_disable()
/linux-4.1.27/drivers/ide/
H A Dide-generic.c53 static void ide_generic_check_pci_legacy_iobases(int *primary, int *secondary) ide_generic_check_pci_legacy_iobases() argument
61 *primary = 1; for_each_pci_dev()
69 *primary = *secondary = 1; for_each_pci_dev()
80 *primary = 1; for_each_pci_dev()
91 int i, rc = 0, primary = 0, secondary = 0; ide_generic_init() local
93 ide_generic_check_pci_legacy_iobases(&primary, &secondary); ide_generic_init()
99 if (primary == 0) ide_generic_init()
H A Dcy82c693.c92 /* select primary or secondary channel */ cy82c693_set_pio_mode()
150 static ide_hwif_t *primary; init_iops_cy82c693() local
154 primary = hwif; init_iops_cy82c693()
156 hwif->mate = primary; init_iops_cy82c693()
183 Function 1 is primary IDE channel, function 2 - secondary. */ cy82c693_init_one()
H A Dtrm290.c67 * bit3 0=primary IDE channel, 1=secondary IDE channel
76 * defaults: 0x1f0 for primary, 0x170 for secondary
101 * defaults: 0x3f6 for primary, 0x376 for secondary
118 * 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary
122 * 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary
126 * 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary
H A Drz1000.c13 * Dunno if this fixes both ports, or only the primary port (?).
H A Djmicron.c53 as the internal primary channel */ jmicron_cable_detect()
69 if (control & (1 << 3)) /* 40/80 pin primary */ jmicron_cable_detect()
H A Dopti621.c34 * is at reg_base (0x1f0 primary, 0x170 secondary,
48 * is at reg_base (0x1f0 primary, 0x170 secondary,
H A Dqd65xx.c72 * bit 0 : 1 = Only primary port enabled : channel 0 for hda, channel 1 for hdb
75 * bit 1 : 1 = only disks on primary port
76 * 0 = disks & ATAPI devices on primary port
80 * bit 7 : set 1 for non-ATAPI devices on primary port
H A Ddtc2278.c30 * the primary (EIDE). You may probably have to enable the 32-bit support to
/linux-4.1.27/fs/ext3/
H A Dresize.c382 * Check that all of the backup GDT blocks are held in the primary GDT block.
387 struct buffer_head *primary) verify_reserved_gdb()
389 const ext3_fsblk_t blk = primary->b_blocknr; verify_reserved_gdb()
395 __le32 *p = (__le32 *)primary->b_data; verify_reserved_gdb()
416 * use from the resize inode. The primary copy of the new GDT block currently
429 struct buffer_head **primary) add_new_gdb()
448 * If we are not using the primary superblock/GDT copy don't resize, add_new_gdb()
460 *primary = sb_bread(sb, gdblock); add_new_gdb()
461 if (!*primary) add_new_gdb()
464 if ((gdbackups = verify_reserved_gdb(sb, *primary)) < 0) { add_new_gdb()
488 if ((err = ext3_journal_get_write_access(handle, *primary))) add_new_gdb()
514 * reserved inode, and will become GDT blocks (primary and backup). add_new_gdb()
526 memset((*primary)->b_data, 0, sb->s_blocksize); add_new_gdb()
527 err = ext3_journal_dirty_metadata(handle, *primary); add_new_gdb()
534 n_group_desc[gdb_num] = *primary; add_new_gdb()
554 //ext3_journal_release_buffer(handle, *primary); add_new_gdb()
556 //ext3_journal_release_buffer(handle, *primary); add_new_gdb()
560 brelse(*primary); add_new_gdb()
573 * The indirect blocks are actually the primary reserved GDT blocks,
575 * double-indirect block to verify it is pointing to the primary reserved
577 * backup GDT blocks are stored in their reserved primary GDT block.
584 struct buffer_head **primary; reserve_backup_gdb() local
593 primary = kmalloc(reserved_gdb * sizeof(*primary), GFP_NOFS); reserve_backup_gdb()
594 if (!primary) reserve_backup_gdb()
609 /* Get each reserved primary GDT block and verify it holds backups */ reserve_backup_gdb()
620 primary[res] = sb_bread(sb, blk); reserve_backup_gdb()
621 if (!primary[res]) { reserve_backup_gdb()
625 if ((gdbackups = verify_reserved_gdb(sb, primary[res])) < 0) { reserve_backup_gdb()
626 brelse(primary[res]); reserve_backup_gdb()
635 if ((err = ext3_journal_get_write_access(handle, primary[i]))) { reserve_backup_gdb()
639 ext3_journal_release_buffer(handle, primary[j]); reserve_backup_gdb()
650 * the new group to its reserved primary GDT block. reserve_backup_gdb()
655 data = (__le32 *)primary[i]->b_data; reserve_backup_gdb()
657 primary[i]->b_blocknr, gdbackups, reserve_backup_gdb()
658 blk + primary[i]->b_blocknr); */ reserve_backup_gdb()
659 data[gdbackups] = cpu_to_le32(blk + primary[i]->b_blocknr); reserve_backup_gdb()
660 err2 = ext3_journal_dirty_metadata(handle, primary[i]); reserve_backup_gdb()
669 brelse(primary[res]); reserve_backup_gdb()
673 kfree(primary); reserve_backup_gdb()
682 * _should_ update the backups if possible, in case the primary gets trashed
789 struct buffer_head *primary = NULL; ext3_group_add() local
873 primary = sbi->s_group_desc[gdb_num]; ext3_group_add()
874 if ((err = ext3_journal_get_write_access(handle, primary))) ext3_group_add()
880 } else if ((err = add_new_gdb(handle, inode, input, &primary))) ext3_group_add()
903 gdp = (struct ext3_group_desc *)primary->b_data + gdb_off; ext3_group_add()
951 err = ext3_journal_dirty_metadata(handle, primary); ext3_group_add()
974 update_backups(sb, primary->b_blocknr, primary->b_data, ext3_group_add()
975 primary->b_size); ext3_group_add()
386 verify_reserved_gdb(struct super_block *sb, struct buffer_head *primary) verify_reserved_gdb() argument
427 add_new_gdb(handle_t *handle, struct inode *inode, struct ext3_new_group_data *input, struct buffer_head **primary) add_new_gdb() argument
/linux-4.1.27/drivers/staging/sm750fb/
H A Dsm750_hw.h26 sm750_simul_pri,/* primary => all head */
30 sm750_dual_normal,/* primary => panel head and secondary => crt */
32 sm750_dual_swap,/* primary => crt head and secondary => panel */
78 1: primary crtc hw cursor enabled,
H A Dddk750_display.h15 /* primary timing & plane enable bit
108 /* LCD1 show primary and DSUB show secondary */
112 /* LCD1 show secondary and DSUB show primary */
H A Dddk750_display.c17 /* Set the primary display control */ setDisplayControl()
136 /* primary controller */ waitNextVerticalSync()
254 /* set primary timing and plane en_bit */ ddk750_setLogicalDispOut()
H A Dsm750.h141 *channel=0 means primary channel
/linux-4.1.27/drivers/gpu/drm/sti/
H A Dsti_drm_crtc.h15 struct drm_plane *primary, struct drm_plane *cursor);
H A Dsti_compositor.c97 struct drm_plane *primary = NULL; sti_compositor_bind() local
118 primary = sti_drm_plane_init(drm_dev, sti_compositor_bind()
129 /* The first planes are reserved for primary planes*/ sti_compositor_bind()
130 if (crtc < compo->nb_mixers && primary) { sti_compositor_bind()
132 primary, cursor); sti_compositor_bind()
135 primary = NULL; sti_compositor_bind()
H A Dsti_drm_crtc.c60 layer = to_sti_layer(crtc->primary); sti_drm_crtc_commit()
304 struct drm_plane *primary, struct drm_plane *cursor) sti_drm_crtc_init()
309 res = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, sti_drm_crtc_init()
303 sti_drm_crtc_init(struct drm_device *drm_dev, struct sti_mixer *mixer, struct drm_plane *primary, struct drm_plane *cursor) sti_drm_crtc_init() argument
/linux-4.1.27/security/selinux/ss/
H A Dsymtab.h16 u32 nprim; /* number of primary names in table */
/linux-4.1.27/drivers/mtd/chips/
H A Dgen_probe.c35 mtd = check_cmd_set(map, 1); /* First the primary cmdset */ mtd_do_chip_probe()
200 int primary) cfi_cmdset_unknown()
203 __u16 type = primary?cfi->cfiq->P_ID:cfi->cfiq->A_ID; cfi_cmdset_unknown()
219 mtd = (*probe_function)(map, primary); cfi_cmdset_unknown()
230 static struct mtd_info *check_cmd_set(struct map_info *map, int primary) check_cmd_set() argument
233 __u16 type = primary?cfi->cfiq->P_ID:cfi->cfiq->A_ID; check_cmd_set()
245 return cfi_cmdset_0001(map, primary); check_cmd_set()
251 return cfi_cmdset_0002(map, primary); check_cmd_set()
255 return cfi_cmdset_0020(map, primary); check_cmd_set()
258 return cfi_cmdset_unknown(map, primary); check_cmd_set()
199 cfi_cmdset_unknown(struct map_info *map, int primary) cfi_cmdset_unknown() argument
/linux-4.1.27/drivers/gpu/drm/exynos/
H A Dexynos_drm_crtc.c59 struct exynos_drm_plane *exynos_plane = to_exynos_plane(crtc->primary); exynos_drm_crtc_commit()
89 struct drm_framebuffer *fb = crtc->primary->fb; exynos_drm_crtc_mode_set()
100 ret = exynos_check_plane(crtc->primary, fb); exynos_drm_crtc_mode_set()
106 exynos_plane_mode_set(crtc->primary, crtc, fb, 0, 0, exynos_drm_crtc_mode_set()
116 struct drm_framebuffer *fb = crtc->primary->fb; exynos_drm_crtc_mode_set_base()
129 return exynos_update_plane(crtc->primary, crtc, fb, 0, 0, exynos_drm_crtc_mode_set_base()
167 struct drm_framebuffer *old_fb = crtc->primary->fb; exynos_drm_crtc_page_flip()
201 crtc->primary->fb = fb; exynos_drm_crtc_page_flip()
204 ret = exynos_update_plane(crtc->primary, crtc, fb, 0, 0, exynos_drm_crtc_page_flip()
208 crtc->primary->fb = old_fb; exynos_drm_crtc_page_flip()
/linux-4.1.27/arch/alpha/boot/tools/
H A Dobjstrip.c45 "usage: %s [-v] -p file primary\n" usage()
55 int fd, ofd, i, j, verbose = 0, primary = 0; main() local
79 primary = 1; /* make primary bootblock */ main()
105 if (primary) { main()
106 /* generate bootblock for primary loader */ main()
/linux-4.1.27/drivers/gpu/drm/mgag200/
H A Dmgag200_drv.c46 bool primary = false; mgag200_kick_out_firmware_fb() local
56 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; mgag200_kick_out_firmware_fb()
58 remove_conflicting_framebuffers(ap, "mgag200drmfb", primary); mgag200_kick_out_firmware_fb()
H A Dmgag200_mode.c33 struct drm_framebuffer *fb = crtc->primary->fb; mga_crtc_load_lut()
746 mga_fb = to_mga_framebuffer(crtc->primary->fb); mga_crtc_do_set_base()
809 bppshift = mdev->bpp_shifts[(crtc->primary->fb->bits_per_pixel >> 3) - 1]; mga_crtc_mode_set()
847 switch (crtc->primary->fb->bits_per_pixel) { mga_crtc_mode_set()
852 if (crtc->primary->fb->depth == 15) mga_crtc_mode_set()
900 pitch = crtc->primary->fb->pitches[0] / (crtc->primary->fb->bits_per_pixel / 8); mga_crtc_mode_set()
901 if (crtc->primary->fb->bits_per_pixel == 24) mga_crtc_mode_set()
978 if (crtc->primary->fb->bits_per_pixel == 24) mga_crtc_mode_set()
1038 if (crtc->primary->fb->bits_per_pixel > 16) mga_crtc_mode_set()
1040 else if (crtc->primary->fb->bits_per_pixel > 8) mga_crtc_mode_set()
1281 if (crtc->primary->fb) { mga_crtc_disable()
1282 struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb); mga_crtc_disable()
1291 crtc->primary->fb = NULL; mga_crtc_disable()
/linux-4.1.27/arch/um/drivers/
H A Dnull.c20 static int null_open(int input, int output, int primary, void *d, null_open() argument
H A Dchan_kern.c22 static int not_configged_open(int input, int output, int primary, void *data, not_configged_open() argument
93 else fd = (*chan->ops->open)(chan->input, chan->output, chan->primary, open_one_chan()
119 if (chan->primary) list_for_each()
127 if (chan && chan->primary && chan->ops->winch) chan_enable_winch()
151 if (chan->primary) enable_chan()
266 if (chan->primary) { write_chan()
282 if (chan->primary) console_write_chan()
306 if (chan && chan->primary) { chan_window_size()
313 if (chan && chan->primary) { chan_window_size()
331 if (chan->primary && chan->output) free_one_chan()
398 if (in && !in->primary) chan_config_string()
400 if (out && !out->primary) chan_config_string()
486 .primary = 1, parse_chan()
570 if (chan->primary) { chan_interrupt()
576 if (chan->primary) chan_interrupt()
H A Dpty.c40 static int pts_open(int input, int output, int primary, void *d, pts_open() argument
113 static int pty_open(int input, int output, int primary, void *d, pty_open() argument
H A Dchan.h20 unsigned int primary:1; member in struct:chan
H A Dfd.c50 static int fd_open(int input, int output, int primary, void *d, char **dev_out) fd_open() argument
H A Dtty.c39 static int tty_open(int input, int output, int primary, void *d, tty_open() argument
H A Dport_user.c70 static int port_open(int input, int output, int primary, void *d, port_open() argument
/linux-4.1.27/arch/powerpc/platforms/44x/
H A Dvirtex_ml510.c12 /* Assign irq 14 to the primary ide channel */ ml510_ali_quirk()
/linux-4.1.27/arch/m68k/coldfire/
H A Dm5407.c46 /* Only support the external interrupts on their primary level */ config_BSP()
H A Dm5206.c52 /* Only support the external interrupts on their primary level */ config_BSP()
H A Dm5307.c62 /* Only support the external interrupts on their primary level */ config_BSP()
/linux-4.1.27/arch/alpha/kernel/
H A Dsys_sable.c257 *32 PCI 0 slot 4 A primary bus 32
258 *33 PCI 0 slot 4 B primary bus 33
259 *34 PCI 0 slot 4 C primary bus 34
260 *35 PCI 0 slot 4 D primary bus
261 *36 PCI 0 slot 5 A primary bus
262 *37 PCI 0 slot 5 B primary bus
263 *38 PCI 0 slot 5 C primary bus
264 *39 PCI 0 slot 5 D primary bus
265 *40 PCI 0 slot 6 A primary bus
266 *41 PCI 0 slot 6 B primary bus
267 *42 PCI 0 slot 6 C primary bus
268 *43 PCI 0 slot 6 D primary bus
269 *44 PCI 0 slot 7 A primary bus
270 *45 PCI 0 slot 7 B primary bus
271 *46 PCI 0 slot 7 C primary bus
272 *47 PCI 0 slot 7 D primary bus
/linux-4.1.27/drivers/sh/intc/
H A Dcore.c80 unsigned int data[2], primary; intc_register_irq() local
98 primary = 0; intc_register_irq()
100 primary = 1; intc_register_irq()
109 if (!data[primary]) intc_register_irq()
110 primary ^= 1; intc_register_irq()
112 BUG_ON(!data[primary]); /* must have primary masking method */ intc_register_irq()
119 irq_set_chip_data(irq, (void *)data[primary]); intc_register_irq()
127 if (data[!primary]) intc_register_irq()
128 _intc_enable(irq_data, data[!primary]); intc_register_irq()
136 if (primary) { intc_register_irq()
H A Dchip.c147 * primary masking method is using intc_prio_level[irq] intc_set_priority()
/linux-4.1.27/drivers/gpu/drm/rcar-du/
H A Drcar_du_plane.h23 /* The RCAR DU has 8 hardware planes, shared between primary and overlay planes.
25 * more than 7 overlay planes can be available. We thus create 1 primary plane
/linux-4.1.27/net/ceph/
H A Dosdmap.c376 * to a set of osds) and primary_temp (explicit primary setting)
1039 pr_info("osd%d primary-affinity 0x%x\n", osd, aff); decode_new_primary_affinity()
1526 * Given raw set, calculate up set and up primary.
1528 * Return up set length. *primary is set to up primary osd id, or -1
1533 int *osds, int len, int *primary) raw_to_up_osds()
1562 *primary = up_primary; raw_to_up_osds()
1568 int *osds, int len, int *primary) apply_primary_affinity()
1593 * Pick the primary. Feed both the seed (for the pg) and the apply_primary_affinity()
1595 * osd's pgs get rejected as primary. apply_primary_affinity()
1609 * We chose not to use this primary. Note it apply_primary_affinity()
1623 *primary = osds[pos]; apply_primary_affinity()
1626 /* move the new primary to the front */ apply_primary_affinity()
1629 osds[0] = *primary; apply_primary_affinity()
1636 * Return acting set length. *primary is set to acting primary osd id,
1641 int *osds, int len, int *primary) apply_temps()
1669 /* apply pg_temp's primary */ apply_temps()
1678 temp_primary = *primary; apply_temps()
1686 *primary = temp_primary; apply_temps()
1693 * Return acting set length, or error. *primary is set to acting
1694 * primary osd id, or -1 if acting set is empty or on error.
1697 int *osds, int *primary) ceph_calc_pg_acting()
1705 *primary = -1; ceph_calc_pg_acting()
1729 *primary = -1; ceph_calc_pg_acting()
1733 len = raw_to_up_osds(osdmap, pool, osds, len, primary); ceph_calc_pg_acting()
1735 apply_primary_affinity(osdmap, pps, pool, osds, len, primary); ceph_calc_pg_acting()
1737 len = apply_temps(osdmap, pool, pgid, osds, len, primary); ceph_calc_pg_acting()
1743 * Return primary osd for given pgid, or -1 if none.
1748 int primary; ceph_calc_pg_primary() local
1750 ceph_calc_pg_acting(osdmap, pgid, osds, &primary); ceph_calc_pg_primary()
1752 return primary; ceph_calc_pg_primary()
1531 raw_to_up_osds(struct ceph_osdmap *osdmap, struct ceph_pg_pool_info *pool, int *osds, int len, int *primary) raw_to_up_osds() argument
1566 apply_primary_affinity(struct ceph_osdmap *osdmap, u32 pps, struct ceph_pg_pool_info *pool, int *osds, int len, int *primary) apply_primary_affinity() argument
1639 apply_temps(struct ceph_osdmap *osdmap, struct ceph_pg_pool_info *pool, struct ceph_pg pgid, int *osds, int len, int *primary) apply_temps() argument
1696 ceph_calc_pg_acting(struct ceph_osdmap *osdmap, struct ceph_pg pgid, int *osds, int *primary) ceph_calc_pg_acting() argument
/linux-4.1.27/drivers/gpu/drm/cirrus/
H A Dcirrus_drv.c47 bool primary = false; cirrus_kick_out_firmware_fb() local
57 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; cirrus_kick_out_firmware_fb()
59 remove_conflicting_framebuffers(ap, "cirrusdrmfb", primary); cirrus_kick_out_firmware_fb()
H A Dcirrus_mode.c153 cirrus_fb = to_cirrus_framebuffer(crtc->primary->fb); cirrus_crtc_do_set_base()
272 switch (crtc->primary->fb->bits_per_pixel) { cirrus_crtc_mode_set()
295 tmp = crtc->primary->fb->pitches[0] / 8; cirrus_crtc_mode_set()
300 tmp |= (crtc->primary->fb->pitches[0] >> 7) & 0x10; cirrus_crtc_mode_set()
301 tmp |= (crtc->primary->fb->pitches[0] >> 6) & 0x40; cirrus_crtc_mode_set()
/linux-4.1.27/drivers/gpu/drm/qxl/
H A Dqxl_debugfs.c129 qdev->ddev->primary->debugfs_root, qxl_debugfs_add_files()
130 qdev->ddev->primary); qxl_debugfs_add_files()
146 qdev->ddev->primary); qxl_debugfs_remove_files()
H A Dqxl_display.c226 struct qxl_framebuffer *qfb_old = to_qxl_framebuffer(crtc->primary->fb); qxl_crtc_page_flip()
240 crtc->primary->fb = fb; qxl_crtc_page_flip()
486 /* if we aren't primary surface ignore this */ qxl_framebuffer_surface_dirty()
609 if (!crtc->primary->fb) { qxl_crtc_mode_set()
618 qfb = to_qxl_framebuffer(crtc->primary->fb); qxl_crtc_mode_set()
646 "recreate primary: %dx%d,%d,%d\n", qxl_crtc_mode_set()
654 DRM_DEBUG_KMS("setting surface_id to 0 for primary surface %d on crtc %d\n", bo->surface_id, qcrtc->index); qxl_crtc_mode_set()
690 if (crtc->primary->fb) { qxl_crtc_disable()
691 struct qxl_framebuffer *qfb = to_qxl_framebuffer(crtc->primary->fb); qxl_crtc_disable()
697 crtc->primary->fb = NULL; qxl_crtc_disable()
1119 /* primary surface must be created by this point, to allow qxl_modeset_init()
/linux-4.1.27/arch/powerpc/sysdev/
H A Dmv64x60_pci.c126 int primary; mv64x60_add_bridge() local
159 primary = (hose->first_busno == 0); mv64x60_add_bridge()
160 pci_process_bridge_OF_ranges(hose, dev, primary); mv64x60_add_bridge()
H A Dfsl_pci.c619 bus->primary == hose->first_busno) { mpc83xx_pcie_exclude_device()
732 int primary; mpc83xx_add_bridge() local
766 * Controller at offset 0x8500 is primary mpc83xx_add_bridge()
769 primary = 1; mpc83xx_add_bridge()
771 primary = 0; mpc83xx_add_bridge()
807 pci_process_bridge_OF_ranges(hose, dev, primary); mpc83xx_add_bridge()
1044 /* Callers can specify the primary bus using other means. */ fsl_pci_assign_primary()
1048 /* If a PCI host bridge contains an ISA node, it's primary. */ fsl_pci_assign_primary()
1060 * designate one as primary. This can go away once fsl_pci_assign_primary()
1061 * various bugs with primary-less systems are fixed. fsl_pci_assign_primary()
H A Dppc4xx_pci.c332 int primary = 0; ppc4xx_probe_pci_bridge() local
354 /* Check if primary bridge */ ppc4xx_probe_pci_bridge()
355 if (of_get_property(np, "primary", NULL)) ppc4xx_probe_pci_bridge()
356 primary = 1; ppc4xx_probe_pci_bridge()
387 pci_process_bridge_OF_ranges(hose, np, primary); ppc4xx_probe_pci_bridge()
538 int big_pim = 0, msi = 0, primary = 0; ppc4xx_probe_pcix_bridge() local
561 /* Check if primary bridge */ ppc4xx_probe_pcix_bridge()
562 if (of_get_property(np, "primary", NULL)) ppc4xx_probe_pcix_bridge()
563 primary = 1; ppc4xx_probe_pcix_bridge()
600 pci_process_bridge_OF_ranges(hose, np, primary); ppc4xx_probe_pcix_bridge()
1928 int primary = 0, busses; ppc4xx_pciex_port_setup_hose() local
1933 /* Check if primary bridge */ ppc4xx_pciex_port_setup_hose()
1934 if (of_get_property(port->node, "primary", NULL)) ppc4xx_pciex_port_setup_hose()
1935 primary = 1; ppc4xx_pciex_port_setup_hose()
2016 pci_process_bridge_OF_ranges(hose, port->node, primary); ppc4xx_pciex_port_setup_hose()
H A Dfsl_gtm.c181 /* CPM2 doesn't have primary prescaler */ gtm_set_ref_timer16()
187 * We have two 8 bit prescalers -- primary and secondary (psr, sps), gtm_set_ref_timer16()
370 /* CPM2 doesn't have primary prescaler */ gtm_set_shortcuts()
/linux-4.1.27/arch/s390/kernel/
H A Dhead64.S42 lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space,
48 .quad 0 # cr1: primary space segment table
52 .quad .Lduct # cr5: primary-aste origin
/linux-4.1.27/drivers/gpu/drm/omapdrm/
H A Domap_crtc.c514 * The primary plane CRTC can be reset if the plane is disabled directly omap_crtc_mode_set()
517 crtc->primary->crtc = crtc; omap_crtc_mode_set()
519 return omap_plane_mode_set(crtc->primary, crtc, crtc->primary->fb, omap_crtc_mode_set()
542 struct drm_plane *plane = crtc->primary; omap_crtc_mode_set_base()
545 return omap_plane_mode_set(plane, crtc, crtc->primary->fb, omap_crtc_mode_set_base()
585 omap_plane_mode_set(crtc->primary, crtc, crtc->primary->fb, page_flip_worker()
591 bo = omap_framebuffer_bo(crtc->primary->fb, 0); page_flip_worker()
612 struct drm_plane *primary = crtc->primary; omap_crtc_page_flip_locked() local
616 DBG("%d -> %d (event=%p)", primary->fb ? primary->fb->base.id : -1, omap_crtc_page_flip_locked()
628 omap_crtc->old_fb = primary->fb = fb; omap_crtc_page_flip_locked()
656 return omap_plane_set_property(crtc->primary, property, val); omap_crtc_set_property()
753 omap_plane_install_properties(crtc->primary, &crtc->base); omap_crtc_init()
/linux-4.1.27/include/linux/mfd/
H A Dsi476x-platform.h234 * @SI476X_PHDIV_PRIMARY_COMBINING: Tuner works as a primary tuner
237 * @SI476X_PHDIV_PRIMARY_ANTENNA: Tuner works as a primary tuner
239 * @SI476X_PHDIV_SECONDARY_ANTENNA: Tuner works as a primary tuner
243 * primary one.
/linux-4.1.27/drivers/net/wireless/ath/ath9k/
H A Ddfs_debug.h34 * @pri_phy_errors: pulses reported for primary channel
36 * @dc_phy_errors: pulses reported for primary + extension channel
/linux-4.1.27/arch/powerpc/include/asm/
H A Dppc-pci.h20 extern void pci_setup_phb_io(struct pci_controller *hose, int primary);
21 extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
H A Dtsi108_pci.h40 extern int tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary);
H A Dmpic.h394 /* Get the version of primary MPIC */
409 * used only on primary mpic
466 /* Request IPIs on primary mpic */
481 /* This one gets from the primary mpic */
483 /* This one gets from the primary mpic via CoreInt*/
485 /* Fetch Machine Check interrupt from primary mpic */
H A Ddelay.h49 * This primary purpose of this macro is to poll on a hardware register
/linux-4.1.27/fs/fscache/
H A Dnetfs.c31 /* allocate a cookie for the primary index */ __fscache_register_netfs()
40 /* initialise the primary index cookie */ __fscache_register_netfs()
/linux-4.1.27/sound/pci/hda/
H A Dhda_generic.h78 int no_primary_dac; /* no primary DAC */
80 int shared_primary; /* primary DAC is shared with main output */
81 int shared_surr; /* secondary DAC shared with main or primary */
82 int shared_clfe; /* third DAC shared with main or primary */
134 /* min_channel_count contains the minimum channel count for primary
138 * ext_channel_count contains the current channel count of the primary
145 int min_channel_count; /* min. channel count for primary out */
146 int ext_channel_count; /* current channel count for primary */
/linux-4.1.27/drivers/gpu/drm/i915/
H A Di915_sysfs.c619 ret = sysfs_merge_group(&dev->primary->kdev->kobj, i915_setup_sysfs()
625 ret = sysfs_merge_group(&dev->primary->kdev->kobj, i915_setup_sysfs()
631 ret = sysfs_merge_group(&dev->primary->kdev->kobj, i915_setup_sysfs()
638 ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs); i915_setup_sysfs()
643 ret = device_create_bin_file(dev->primary->kdev, i915_setup_sysfs()
652 ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs); i915_setup_sysfs()
654 ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs); i915_setup_sysfs()
658 ret = sysfs_create_bin_file(&dev->primary->kdev->kobj, i915_setup_sysfs()
666 sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr); i915_teardown_sysfs()
668 sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs); i915_teardown_sysfs()
670 sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs); i915_teardown_sysfs()
671 device_remove_bin_file(dev->primary->kdev, &dpf_attrs_1); i915_teardown_sysfs()
672 device_remove_bin_file(dev->primary->kdev, &dpf_attrs); i915_teardown_sysfs()
674 sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group); i915_teardown_sysfs()
675 sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6p_attr_group); i915_teardown_sysfs()
H A Di915_trace.h383 __entry->dev = dev->primary->index;
403 __entry->dev = dev->primary->index;
419 __entry->dev = vm->dev->primary->index;
440 __entry->dev = from->dev->primary->index;
466 __entry->dev = ring->dev->primary->index;
489 __entry->dev = ring->dev->primary->index;
514 __entry->dev = ring->dev->primary->index;
541 __entry->dev = ring->dev->primary->index;
581 __entry->dev = ring->dev->primary->index;
609 __entry->dev = ring->dev->primary->index;
726 __entry->dev = vm->dev->primary->index;
762 __entry->dev = ctx->file_priv->dev_priv->dev->primary->index;
802 __entry->dev = ring->dev->primary->index;
H A Dintel_sprite.c418 * Enable gamma to match primary/cursor plane behaviour. vlv_update_plane()
551 * Enable gamma to match primary/cursor plane behaviour. ivb_update_plane()
699 * Enable gamma to match primary/cursor plane behaviour. ilk_update_plane()
790 * intel_post_enable_primary - Perform operations after enabling primary plane
791 * @crtc: the CRTC whose primary plane was just enabled
793 * Performs potentially sleeping operations that must be done after the primary
795 * called due to an explicit primary plane update, or due to an implicit
797 * completely hide the primary plane.
816 * when going from primary only to sprite only and vice intel_post_enable_primary()
827 * intel_pre_disable_primary - Perform operations before disabling primary plane
828 * @crtc: the CRTC whose primary plane is to be disabled
831 * primary plane is enabled, such as updating FBC and IPS. Note that this may
832 * be called due to an explicit primary plane update, or due to an implicit
833 * disable that is caused when a sprite plane completely hides the primary
851 * when going from primary only to sprite only and vice intel_pre_disable_primary()
1022 * If the sprite is completely covering the primary plane, intel_check_sprite_plane()
1023 * we can disable the primary and save power. intel_check_sprite_plane()
H A Dintel_dp_mst.c37 struct intel_digital_port *intel_dig_port = intel_mst->primary; intel_dp_mst_compute_config()
106 struct intel_digital_port *intel_dig_port = intel_mst->primary; intel_mst_disable_dp()
123 struct intel_digital_port *intel_dig_port = intel_mst->primary; intel_mst_post_disable_dp()
146 struct intel_digital_port *intel_dig_port = intel_mst->primary; intel_mst_pre_enable_dp()
208 struct intel_digital_port *intel_dig_port = intel_mst->primary; intel_mst_enable_dp()
240 struct intel_digital_port *intel_dig_port = intel_mst->primary; intel_dp_mst_enc_get_config()
510 intel_mst->primary = intel_dig_port; intel_dp_create_fake_mst_encoder()
H A Dintel_fbc.c72 struct drm_framebuffer *fb = crtc->primary->fb; i8xx_fbc_enable()
131 struct drm_framebuffer *fb = crtc->primary->fb; g4x_fbc_enable()
187 struct drm_framebuffer *fb = crtc->primary->fb; ilk_fbc_enable()
258 struct drm_framebuffer *fb = crtc->primary->fb; gen7_fbc_enable()
338 if (work->crtc->primary->fb == work->fb) { intel_fbc_work_fn()
342 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id; intel_fbc_work_fn()
395 work->fb = crtc->primary->fb; intel_fbc_enable()
473 if (!crtc || crtc->primary->fb == NULL) {
544 fb = crtc->primary->fb; intel_fbc_update()
589 crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { intel_fbc_update()
H A Dintel_display.c966 * We can ditch the crtc->primary->fb check as soon as we can intel_crtc_active()
973 return intel_crtc->active && crtc->primary->state->fb && intel_crtc_active()
2199 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2233 * intel_disable_primary_hw_plane - disable the primary hardware plane
2614 struct drm_plane *primary = intel_crtc->base.primary; intel_find_initial_plane_obj() local
2640 fb = c->primary->fb; for_each_crtc()
2658 primary->fb = fb;
2659 primary->state->crtc = &intel_crtc->base;
2660 primary->crtc = &intel_crtc->base;
2661 update_state_fb(primary);
2768 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { i9xx_update_primary_plane()
2867 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { ironlake_update_primary_plane()
3012 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) skylake_update_primary_plane()
3018 surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj); skylake_update_primary_plane()
3071 * FIXME: Once we have proper support for primary planes (and for_each_crtc()
3073 * a NULL crtc->primary->fb. for_each_crtc()
3075 if (intel_crtc->active && crtc->primary->fb) for_each_crtc()
3077 crtc->primary->fb, for_each_crtc()
3128 * so update the base address of all primary intel_finish_reset()
3813 if (crtc->primary->fb) { intel_crtc_wait_for_pending_flips()
3815 intel_finish_fb(crtc->primary->fb); intel_crtc_wait_for_pending_flips()
4465 intel_enable_primary_hw_plane(crtc->primary, crtc); intel_crtc_enable_planes()
4501 intel_disable_primary_hw_plane(crtc->primary, crtc); intel_crtc_disable_planes()
4927 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; intel_display_port_power_domain()
5559 crtc->primary->funcs->disable_plane(crtc->primary); intel_crtc_disable()
9023 ret = drm_modeset_lock(&crtc->primary->mutex, ctx); intel_get_load_detect_pipe()
9063 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9119 crtc->primary->crtc = crtc;
9455 if (!crtc->primary->fb) for_each_crtc()
9505 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); intel_unpin_work_fn()
9915 struct drm_framebuffer *fb = intel_crtc->base.primary->fb; skl_do_mmio_flip()
9950 to_intel_framebuffer(intel_crtc->base.primary->fb); ilk_do_mmio_flip()
10109 struct drm_framebuffer *old_fb = crtc->primary->fb; intel_crtc_page_flip()
10112 struct drm_plane *primary = crtc->primary; intel_crtc_page_flip() local
10121 * a disabled primary plane. intel_crtc_page_flip()
10127 if (fb->pixel_format != crtc->primary->fb->pixel_format) intel_crtc_page_flip()
10135 (fb->offsets[0] != crtc->primary->fb->offsets[0] || intel_crtc_page_flip()
10136 fb->pitches[0] != crtc->primary->fb->pitches[0])) intel_crtc_page_flip()
10183 crtc->primary->fb = fb; intel_crtc_page_flip()
10184 update_state_fb(crtc->primary); intel_crtc_page_flip()
10213 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, intel_crtc_page_flip()
10214 crtc->primary->state, ring); intel_crtc_page_flip()
10218 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) intel_crtc_page_flip()
10254 intel_unpin_fb_obj(fb, crtc->primary->state); intel_crtc_page_flip()
10259 crtc->primary->fb = old_fb; intel_crtc_page_flip()
10260 update_state_fb(crtc->primary); intel_crtc_page_flip()
10275 ret = intel_plane_restore(primary); intel_crtc_page_flip()
11600 struct drm_plane *primary = intel_crtc->base.primary; for_each_intel_crtc_masked() local
11604 ret = primary->funcs->update_plane(primary, &intel_crtc->base, for_each_intel_crtc_masked()
11735 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
11862 } else if (set->crtc->primary->fb != set->fb) { intel_set_config_compute_mode_changes()
11866 * be active if we've only disabled the primary plane, or intel_set_config_compute_mode_changes()
11869 if (set->crtc->primary->fb == NULL) { intel_set_config_compute_mode_changes()
11883 set->crtc->primary->fb->pixel_format) { intel_set_config_compute_mode_changes()
12118 save_set.fb = set->crtc->primary->fb; intel_crtc_set_config()
12168 struct drm_plane *primary = set->crtc->primary; intel_crtc_set_config() local
12172 ret = primary->funcs->update_plane(primary, set->crtc, set->fb, intel_crtc_set_config()
12178 * We need to make sure the primary plane is re-enabled if it intel_crtc_set_config()
12183 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); intel_crtc_set_config()
12482 * the primary plane enable function except that that intel_check_primary_plane()
12506 * now lets consider that when we make primary invisible intel_check_primary_plane()
12554 * If clipping results in a non-visible primary plane, intel_commit_primary_plane()
12555 * we'll disable the primary plane. Note that this is intel_commit_primary_plane()
12661 * Common destruction function for all types of planes (primary, cursor,
12686 struct intel_plane *primary; intel_primary_plane_create() local
12691 primary = kzalloc(sizeof(*primary), GFP_KERNEL); intel_primary_plane_create()
12692 if (primary == NULL) intel_primary_plane_create()
12695 state = intel_create_plane_state(&primary->base); intel_primary_plane_create()
12697 kfree(primary); intel_primary_plane_create()
12700 primary->base.state = &state->base; intel_primary_plane_create()
12702 primary->can_scale = false; intel_primary_plane_create()
12703 primary->max_downscale = 1; intel_primary_plane_create()
12704 primary->pipe = pipe; intel_primary_plane_create()
12705 primary->plane = pipe; intel_primary_plane_create()
12706 primary->check_plane = intel_check_primary_plane; intel_primary_plane_create()
12707 primary->commit_plane = intel_commit_primary_plane; intel_primary_plane_create()
12709 primary->plane = !pipe; intel_primary_plane_create()
12719 drm_universal_plane_init(dev, &primary->base, 0, intel_primary_plane_create()
12731 drm_object_attach_property(&primary->base.base, intel_primary_plane_create()
12736 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); intel_primary_plane_create()
12738 return &primary->base; intel_primary_plane_create()
12889 struct drm_plane *primary = NULL; intel_crtc_init() local
12903 primary = intel_primary_plane_create(dev, pipe); intel_crtc_init()
12904 if (!primary) intel_crtc_init()
12911 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, intel_crtc_init()
12951 if (primary) intel_crtc_init()
12952 drm_plane_cleanup(primary); intel_crtc_init()
14311 obj = intel_fb_obj(c->primary->fb); for_each_crtc()
14316 ret = intel_pin_and_fence_fb_obj(c->primary, for_each_crtc()
14317 c->primary->fb, for_each_crtc()
14318 c->primary->state, for_each_crtc()
14324 drm_framebuffer_unreference(c->primary->fb); for_each_crtc()
14325 c->primary->fb = NULL; for_each_crtc()
14326 update_state_fb(c->primary); for_each_crtc()
H A Dintel_pm.c403 pipe_name(pipe), plane == 0 ? "primary" : "sprite", vlv_get_fifo_size()
655 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; pineview_update_wm()
731 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; g4x_compute_wm0()
818 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; g4x_compute_srwm()
824 /* Use the minimum of the small and large buffer method for primary */ g4x_compute_srwm()
854 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); vlv_write_wm_values()
859 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | vlv_write_wm_values()
860 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); vlv_write_wm_values()
876 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | vlv_write_wm_values()
882 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | vlv_write_wm_values()
885 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | vlv_write_wm_values()
888 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); vlv_write_wm_values()
897 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | vlv_write_wm_values()
900 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); vlv_write_wm_values()
997 num_planes = !!wm->pipe[pipe].primary + vlv_compute_sr_wm()
1034 wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary); valleyview_update_wm()
1035 wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc, valleyview_update_wm()
1036 to_intel_plane(crtc->primary), valleyview_update_wm()
1051 wm.pipe[pipe].primary, wm.pipe[pipe].cursor, valleyview_update_wm()
1201 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; i965_update_wm()
1280 int cpp = crtc->primary->state->fb->bits_per_pixel / 8; i9xx_update_wm()
1302 int cpp = crtc->primary->state->fb->bits_per_pixel / 8; i9xx_update_wm()
1325 obj = intel_fb_obj(enabled->primary->state->fb); i9xx_update_wm()
1349 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; i9xx_update_wm()
1608 /* BDW primary/sprite plane watermarks */ ilk_plane_wm_reg_max()
1611 /* IVB/HSW primary/sprite plane watermarks */ ilk_plane_wm_reg_max()
1614 /* ILK/SNB primary plane watermarks */ ilk_plane_wm_reg_max()
1638 /* Calculate the maximum primary/sprite plane watermark */ ilk_plane_wm_max()
1898 /* ILK primary LP0 latency is 700 ns */ intel_read_wm_latency()
2048 if (crtc->primary->state->fb) ilk_compute_wm_parameters()
2050 crtc->primary->state->fb->bits_per_pixel / 8; ilk_compute_wm_parameters()
2056 * TODO: for now, assume primary and cursor planes are always enabled. ilk_compute_wm_parameters()
2829 fb = crtc->primary->state->fb; skl_compute_wm_pipe_parameters()
2841 p->plane[0].rotation = crtc->primary->state->rotation; skl_compute_wm_pipe_parameters()
/linux-4.1.27/arch/powerpc/kvm/
H A Dbook3s_32_mmu.c112 bool primary) kvmppc_mmu_book3s_32_get_pteg()
122 if (!primary) kvmppc_mmu_book3s_32_get_pteg()
138 static u32 kvmppc_mmu_book3s_32_get_ptem(u32 sre, gva_t eaddr, bool primary) kvmppc_mmu_book3s_32_get_ptem() argument
141 (primary ? 0 : 0x40) | 0x80000000; kvmppc_mmu_book3s_32_get_ptem()
201 bool iswrite, bool primary) kvmppc_mmu_book3s_32_xlate_pte()
218 ptegp = kvmppc_mmu_book3s_32_get_pteg(vcpu, sre, eaddr, primary); kvmppc_mmu_book3s_32_xlate_pte()
224 ptem = kvmppc_mmu_book3s_32_get_ptem(sre, eaddr, primary); kvmppc_mmu_book3s_32_xlate_pte()
110 kvmppc_mmu_book3s_32_get_pteg(struct kvm_vcpu *vcpu, u32 sre, gva_t eaddr, bool primary) kvmppc_mmu_book3s_32_get_pteg() argument
199 kvmppc_mmu_book3s_32_xlate_pte(struct kvm_vcpu *vcpu, gva_t eaddr, struct kvmppc_pte *pte, bool data, bool iswrite, bool primary) kvmppc_mmu_book3s_32_xlate_pte() argument
H A Dbook3s_32_mmu_host.c118 bool primary) kvmppc_mmu_get_pteg()
126 if (!primary) kvmppc_mmu_get_pteg()
152 bool primary = false; kvmppc_mmu_map_page() local
182 primary = !primary; kvmppc_mmu_map_page()
187 pteg = kvmppc_mmu_get_pteg(vcpu, vsid, eaddr, primary); kvmppc_mmu_map_page()
206 (primary ? 0 : PTE_SEC); kvmppc_mmu_map_page()
117 kvmppc_mmu_get_pteg(struct kvm_vcpu *vcpu, u32 vsid, u32 eaddr, bool primary) kvmppc_mmu_get_pteg() argument
/linux-4.1.27/drivers/net/bonding/
H A Dbond_procfs.c60 struct slave *curr, *primary; bond_info_show_master() local
85 primary = rcu_dereference(bond->primary_slave); bond_info_show_master()
87 primary ? primary->dev->name : "None"); bond_info_show_master()
88 if (primary) { bond_info_show_master()
H A Dbond_options.c307 .name = "primary",
318 .desc = "Reselect primary slave once it comes up",
1059 char *p, *primary = newval->string; bond_option_primary_set() local
1065 p = strchr(primary, '\n'); bond_option_primary_set()
1068 /* check to see if we are clearing primary */ bond_option_primary_set()
1069 if (!strlen(primary)) { bond_option_primary_set()
1070 netdev_info(bond->dev, "Setting primary slave to None\n"); bond_option_primary_set()
1072 memset(bond->params.primary, 0, sizeof(bond->params.primary)); bond_option_primary_set()
1078 if (strncmp(slave->dev->name, primary, IFNAMSIZ) == 0) { bond_for_each_slave()
1079 netdev_info(bond->dev, "Setting %s as primary slave\n", bond_for_each_slave()
1082 strcpy(bond->params.primary, slave->dev->name); bond_for_each_slave()
1089 netdev_info(bond->dev, "Setting primary slave to None\n");
1093 strncpy(bond->params.primary, primary, IFNAMSIZ);
1094 bond->params.primary[IFNAMSIZ - 1] = 0;
1096 netdev_info(bond->dev, "Recording %s as primary, but it has not been enslaved to %s yet\n",
1097 primary, bond->dev->name);
H A Dbond_netlink.c272 char *primary = ""; local
276 primary = dev->name;
278 bond_opt_initstr(&newval, primary);
451 struct slave *primary; bond_fill_info() local
501 primary = rtnl_dereference(bond->primary_slave); bond_fill_info()
502 if (primary && bond_fill_info()
503 nla_put_u32(skb, IFLA_BOND_PRIMARY, primary->dev->ifindex)) bond_fill_info()
H A Dbond_main.c99 static char *primary; variable
141 module_param(primary, charp, 0);
142 MODULE_PARM_DESC(primary, "Primary network device to use");
144 MODULE_PARM_DESC(primary_reselect, "Reselect primary slave "
147 "1 for only if speed of primary is "
581 * old active slaves (if any). Modes that are not using primary keep all
582 * slaves up date at all times; only the modes that use primary need to call
740 struct slave *slave, *bestslave = NULL, *primary; bond_find_best_slave() local
744 primary = rtnl_dereference(bond->primary_slave); bond_find_best_slave()
745 if (primary && primary->link == BOND_LINK_UP && bond_find_best_slave()
747 return primary; bond_find_best_slave()
1479 /* If the mode uses primary, then the following is handled by bond_enslave()
1580 if (bond_uses_primary(bond) && bond->params.primary[0]) { bond_enslave()
1581 /* if there is a primary slave, remember it */ bond_enslave()
1582 if (strcmp(bond->params.primary, new_slave->dev->name) == 0) { bond_enslave()
1867 /* If the mode uses primary, then this case was handled above by __bond_release_one()
2064 struct slave *slave, *primary; bond_miimon_commit() local
2075 primary = rtnl_dereference(bond->primary_slave); bond_for_each_slave()
2082 } else if (slave != primary) { bond_for_each_slave()
2103 if (!bond->curr_active_slave || slave == primary) bond_for_each_slave()
2943 struct slave *slave = bond_slave_get_rtnl(slave_dev), *primary; bond_slave_netdev_event() local
2957 primary = rtnl_dereference(bond->primary_slave); bond_slave_netdev_event()
3006 /* we don't care if we don't have primary set */ bond_slave_netdev_event()
3008 !bond->params.primary[0]) bond_slave_netdev_event()
3011 if (slave == primary) { bond_slave_netdev_event()
3012 /* slave's name changed - he's no longer primary */ bond_slave_netdev_event()
3014 } else if (!strcmp(slave_dev->name, bond->params.primary)) { bond_slave_netdev_event()
3015 /* we have a new primary slave */ bond_slave_netdev_event()
3017 } else { /* we didn't change primary - exit */ bond_slave_netdev_event()
3022 primary ? slave_dev->name : "none"); bond_slave_netdev_event()
4439 if (primary && !bond_mode_uses_primary(bond_mode)) { bond_check_params()
4440 /* currently, using a primary only makes sense bond_check_params()
4443 pr_warn("Warning: %s primary device specified but has no effect in %s mode\n", bond_check_params()
4444 primary, bond_mode_name(bond_mode)); bond_check_params()
4445 primary = NULL; bond_check_params()
4448 if (primary && primary_reselect) { bond_check_params()
4496 params->primary[0] = 0; bond_check_params()
4517 if (primary) { bond_check_params()
4518 strncpy(params->primary, primary, IFNAMSIZ); bond_check_params()
4519 params->primary[IFNAMSIZ - 1] = 0; bond_check_params()
H A Dbond_sysfs.c422 /* Show the primary slave. */ bonding_show_primary()
428 struct slave *primary; bonding_show_primary() local
432 primary = rcu_dereference(bond->primary_slave); bonding_show_primary()
433 if (primary) bonding_show_primary()
434 count = sprintf(buf, "%s\n", primary->dev->name); bonding_show_primary()
439 static DEVICE_ATTR(primary, S_IRUGO | S_IWUSR,
/linux-4.1.27/drivers/media/rc/img-ir/
H A Dimg-ir-hw.h94 * @s00: Zero symbol timing data for primary decoder
95 * @s01: One symbol timing data for primary decoder
122 * @s00: Zero symbol timing register value for primary decoder
123 * @s01: One symbol timing register value for primary decoder
196 * @timings: Processed primary timings.
/linux-4.1.27/drivers/misc/cxl/
H A Dfault.c38 struct cxl_sste *primary, *sste, *ret = NULL; find_free_sste() local
48 primary = ctx->sstp + (hash << 3); find_free_sste()
50 for (entry = 0, sste = primary; entry < 8; entry++, sste++) { find_free_sste()
60 ret = primary + ctx->sst_lru; find_free_sste()
68 /* mask is the group index, we search primary and secondary here. */ cxl_load_segment()
/linux-4.1.27/drivers/iio/imu/inv_mpu6050/
H A Dinv_mpu_acpi.c80 break; /* Not a MPU6500 primary */ asus_acpi_get_sensor_info()
167 unsigned short primary, secondary; inv_mpu_acpi_create_mux_client() local
169 ret = inv_mpu_process_acpi_config(st->client, &primary, inv_mpu_acpi_create_mux_client()
/linux-4.1.27/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_dc.h109 * @primary: primary plane
115 struct atmel_hlcdc_plane *primary; member in struct:atmel_hlcdc_planes
H A Datmel_hlcdc_plane.c445 struct atmel_hlcdc_plane *primary; atmel_hlcdc_plane_prepare_disc_area() local
448 primary = drm_plane_to_atmel_hlcdc_plane(c_state->crtc->primary); atmel_hlcdc_plane_prepare_disc_area()
449 layout = &primary->layer.desc->layout; atmel_hlcdc_plane_prepare_disc_area()
454 &primary->base); atmel_hlcdc_plane_prepare_disc_area()
464 if (ovl == c_state->crtc->primary) drm_atomic_crtc_state_for_each_plane()
1027 if (planes->primary) atmel_hlcdc_create_planes()
1029 planes->primary = plane; atmel_hlcdc_create_planes()
/linux-4.1.27/drivers/ata/
H A Dpata_jmicron.c37 * either as primary or secondary (or neither). We don't do any policy
68 as the internal primary channel */ jmicron_pre_reset()
86 if (control & (1 << 3)) /* 40/80 pin primary */ jmicron_pre_reset()
H A Dpata_legacy.c135 static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
136 static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
137 static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
1033 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, legacy_check_special_cases() argument
1038 *primary = *secondary = 1; legacy_check_special_cases()
1043 *primary = *secondary = 1; legacy_check_special_cases()
1055 *primary = 1; legacy_check_special_cases()
1184 int primary = 0; legacy_init() local
1199 primary = 1; for_each_pci_dev()
1204 legacy_check_special_cases(p, &primary, &secondary); for_each_pci_dev()
1214 if (primary == 0 || all)
H A Dpata_cypress.c134 /* Devfn 1 is the ATA primary. The secondary is magic and on devfn2. cy82c693_init_one()
/linux-4.1.27/drivers/video/fbdev/matrox/
H A Di2c-matroxfb.c22 /* primary head DDC for Mystique(?), G100, G200, G400 */
25 /* primary head DDC for Millennium, Millennium II */
200 printk(KERN_ERR "i2c-matroxfb: Could not register primary adapter DDC bus.\n"); i2c_matroxfb_probe()
/linux-4.1.27/include/uapi/linux/
H A Dchio.h122 char cge_pvoltag[36]; /* primary volume tag */
131 #define CGE_PVOLTAG 0x10 /* primary volume tag available */
145 #define CSV_PVOLTAG 0x01 /* primary volume tag */
/linux-4.1.27/arch/arm/mach-omap2/
H A Domap-headsmp.S31 * The primary core will update this flag using a hardware
47 * omap5_secondary_startup if the primary CPU was put into HYP mode by
68 * The primary core will update this flag using a hardware
/linux-4.1.27/arch/arm/kernel/
H A Dreboot.c129 * while the primary CPU resets the system. Systems with a single CPU can
133 * This is required so that any code running after reset on the primary CPU
135 * executing pre-reset code, and using RAM that the primary CPU's code wishes
H A Dhyp-stub.S38 * Save the primary CPU boot mode. Requires 3 scratch registers.
49 * Compare the current mode with the one saved on the primary CPU.
58 cmp \mode, \reg1 @ matches primary CPU boot mode?
85 @ Call this from the primary CPU
/linux-4.1.27/fs/freevxfs/
H A Dvxfs_fshead.c66 * @which: 0 for the structural, 1 for the primary fsh.
69 * vxfs_getfsh reads either the structural or primary fileset header
148 printk(KERN_ERR "vxfs: unable to get primary fsh\n"); vxfs_read_fshead()
/linux-4.1.27/net/tipc/
H A Dbcast.h46 * @primary: pointer to primary bearer
54 struct tipc_bearer *primary; member in struct:tipc_bcbearer_pair
H A Dbcast.c624 struct tipc_bearer *p = bcbearer->bpairs[bp_index].primary; tipc_bcbearer_send()
690 if (!bp_temp[b->priority].primary) tipc_bcbearer_sort()
691 bp_temp[b->priority].primary = b; tipc_bcbearer_sort()
703 if (!bp_temp[pri].primary) tipc_bcbearer_sort()
706 bp_curr->primary = bp_temp[pri].primary; tipc_bcbearer_sort()
709 if (tipc_nmap_equal(&bp_temp[pri].primary->nodes, tipc_bcbearer_sort()
714 bp_curr->primary = bp_temp[pri].secondary; tipc_bcbearer_sort()
/linux-4.1.27/block/partitions/
H A Datari.c19 least one of the primary entries is ok this way */
56 * if there's no valid primary partition, assume that no Atari atari_partition()
/linux-4.1.27/arch/arm/mach-s3c24xx/
H A Dvr1000.h74 * 0x02000000 to 0x02100000 1MB IDE primary channel
75 * 0x02100000 to 0x02200000 1MB IDE primary channel aux
H A Dbast.h144 * 0x02000000 to 0x02100000 1MB IDE primary channel
145 * 0x02100000 to 0x02200000 1MB IDE primary channel aux
/linux-4.1.27/net/sctp/
H A Dproc.c126 union sctp_addr *addr, *primary = NULL; sctp_seq_dump_local_addrs() local
134 WARN(1, "Association %p with NULL primary path!\n", asoc); sctp_seq_dump_local_addrs()
138 primary = &peer->saddr; sctp_seq_dump_local_addrs()
148 if (primary && af->cmp_addr(addr, primary)) { sctp_seq_dump_local_addrs()
160 union sctp_addr *addr, *primary; sctp_seq_dump_remote_addrs() local
163 primary = &assoc->peer.primary_addr; sctp_seq_dump_remote_addrs()
172 if (af->cmp_addr(addr, primary)) { sctp_seq_dump_remote_addrs()
H A Doutqueue.c106 * and t was not sent to the current primary then the
109 static inline int sctp_cacc_skip_3_1_d(struct sctp_transport *primary, sctp_cacc_skip_3_1_d() argument
113 if (count_of_newacks >= 2 && transport != primary) sctp_cacc_skip_3_1_d()
141 static inline int sctp_cacc_skip_3_1(struct sctp_transport *primary, sctp_cacc_skip_3_1() argument
145 if (!primary->cacc.cycling_changeover) { sctp_cacc_skip_3_1()
146 if (sctp_cacc_skip_3_1_d(primary, transport, count_of_newacks)) sctp_cacc_skip_3_1()
158 * than next_tsn_at_change of the current primary, then
162 static inline int sctp_cacc_skip_3_2(struct sctp_transport *primary, __u32 tsn) sctp_cacc_skip_3_2() argument
164 if (primary->cacc.cycling_changeover && sctp_cacc_skip_3_2()
165 TSN_lt(tsn, primary->cacc.next_tsn_at_change)) sctp_cacc_skip_3_2()
184 static inline int sctp_cacc_skip(struct sctp_transport *primary, sctp_cacc_skip() argument
189 if (primary->cacc.changeover_active && sctp_cacc_skip()
190 (sctp_cacc_skip_3_1(primary, transport, count_of_newacks) || sctp_cacc_skip()
191 sctp_cacc_skip_3_2(primary, tsn))) sctp_cacc_skip()
1135 struct sctp_transport *primary = asoc->peer.primary_path; sctp_outq_sack() local
1152 * on the current primary, the CHANGEOVER_ACTIVE flag SHOULD be sctp_outq_sack()
1164 if (primary->cacc.changeover_active) { sctp_outq_sack()
1167 if (TSN_lte(primary->cacc.next_tsn_at_change, sack_ctsn)) { sctp_outq_sack()
1168 primary->cacc.changeover_active = 0; sctp_outq_sack()
1582 struct sctp_transport *primary = asoc->peer.primary_path; sctp_mark_missing() local
1602 if (!transport || !sctp_cacc_skip(primary, list_for_each_entry()
H A Dsm_statetable.c390 /* The primary index for this table is the chunk type.
451 /* The primary index for this table is the chunk type.
478 /* The primary index for this table is the chunk type.
504 /* The primary index for this table is the chunk type.
646 /* The primary index for this table is the primitive type.
H A Dassociola.c428 /* Change the primary destination address for the peer. */ sctp_assoc_set_primary()
434 /* it's a changeover only if we already have a primary path sctp_assoc_set_primary()
447 /* If the primary path is changing, assume that the sctp_assoc_set_primary()
456 * Upon the receipt of a request to change the primary sctp_assoc_set_primary()
458 * primary destination, the sender MUST do the following: sctp_assoc_set_primary()
703 /* If we do not yet have a primary path, set one. */ sctp_assoc_add_peer()
755 struct sctp_transport *primary) sctp_assoc_del_nonprimary_peers()
762 /* if the current transport is not the primary one, delete it */ sctp_assoc_del_nonprimary_peers()
763 if (t != primary) sctp_assoc_del_nonprimary_peers()
1190 * When there is outbound data to send and the primary path
1336 * By default, an endpoint should always transmit to the primary sctp_select_active_and_retran_path()
1339 * address) to use. [If the primary is active but not most recent, sctp_select_active_and_retran_path()
1350 * path; either primary path that we found is the the same as sctp_select_active_and_retran_path()
754 sctp_assoc_del_nonprimary_peers(struct sctp_association *asoc, struct sctp_transport *primary) sctp_assoc_del_nonprimary_peers() argument
/linux-4.1.27/drivers/hv/
H A Dchannel_mgmt.c781 * When a primary channel has multiple sub-channels, we try to
784 struct vmbus_channel *vmbus_get_outgoing_channel(struct vmbus_channel *primary) vmbus_get_outgoing_channel() argument
789 struct vmbus_channel *outgoing_channel = primary; vmbus_get_outgoing_channel()
793 if (list_empty(&primary->sc_list)) vmbus_get_outgoing_channel()
796 next_channel = primary->next_oc++; vmbus_get_outgoing_channel()
798 if (next_channel > (primary->num_sc)) { vmbus_get_outgoing_channel()
799 primary->next_oc = 0; vmbus_get_outgoing_channel()
805 list_for_each_safe(cur, tmp, &primary->sc_list) { vmbus_get_outgoing_channel()
845 bool vmbus_are_subchannels_present(struct vmbus_channel *primary) vmbus_are_subchannels_present() argument
849 ret = !list_empty(&primary->sc_list); vmbus_are_subchannels_present()
857 invoke_sc_cb(primary); vmbus_are_subchannels_present()
/linux-4.1.27/fs/ext4/
H A Dresize.c27 * If we are not using the primary superblock/GDT copy don't resize, ext4_resize_begin()
706 * Check that all of the backup GDT blocks are held in the primary GDT block.
712 struct buffer_head *primary) verify_reserved_gdb()
714 const ext4_fsblk_t blk = primary->b_blocknr; verify_reserved_gdb()
719 __le32 *p = (__le32 *)primary->b_data; verify_reserved_gdb()
742 * use from the resize inode. The primary copy of the new GDT block currently
835 * reserved inode, and will become GDT blocks (primary and backup). add_new_gdb()
927 * The indirect blocks are actually the primary reserved GDT blocks,
929 * double-indirect block to verify it is pointing to the primary reserved
931 * backup GDT blocks are stored in their reserved primary GDT block.
938 struct buffer_head **primary; reserve_backup_gdb() local
947 primary = kmalloc(reserved_gdb * sizeof(*primary), GFP_NOFS); reserve_backup_gdb()
948 if (!primary) reserve_backup_gdb()
963 /* Get each reserved primary GDT block and verify it holds backups */ reserve_backup_gdb()
973 primary[res] = sb_bread(sb, blk); reserve_backup_gdb()
974 if (!primary[res]) { reserve_backup_gdb()
978 gdbackups = verify_reserved_gdb(sb, group, primary[res]); reserve_backup_gdb()
980 brelse(primary[res]); reserve_backup_gdb()
989 BUFFER_TRACE(primary[i], "get_write_access"); reserve_backup_gdb()
990 if ((err = ext4_journal_get_write_access(handle, primary[i]))) reserve_backup_gdb()
999 * the new group to its reserved primary GDT block. reserve_backup_gdb()
1004 data = (__le32 *)primary[i]->b_data; reserve_backup_gdb()
1006 primary[i]->b_blocknr, gdbackups, reserve_backup_gdb()
1007 blk + primary[i]->b_blocknr); */ reserve_backup_gdb()
1008 data[gdbackups] = cpu_to_le32(blk + primary[i]->b_blocknr); reserve_backup_gdb()
1009 err2 = ext4_handle_dirty_metadata(handle, NULL, primary[i]); reserve_backup_gdb()
1018 brelse(primary[res]); reserve_backup_gdb()
1022 kfree(primary); reserve_backup_gdb()
1031 * _should_ update the backups if possible, in case the primary gets trashed
710 verify_reserved_gdb(struct super_block *sb, ext4_group_t end, struct buffer_head *primary) verify_reserved_gdb() argument
/linux-4.1.27/drivers/staging/lustre/lustre/ptlrpc/
H A Dnrs.c148 * Transitions the \a nrs NRS head's primary policy to
174 * If a primary policy different to the current one is specified, this function
178 * the old primary policy (if there is one) to
183 * to stop the current primary policy, without substituting it with another
184 * primary policy, so the primary policy (if any) is transitioned to
211 * primary policy, if any. nrs_policy_start_locked()
227 * Shouldn't start primary policy if w/o fallback policy. nrs_policy_start_locked()
279 * Try to stop the current primary policy if there is one. nrs_policy_start_locked()
284 * And set the newly-started policy as the primary one. nrs_policy_start_locked()
415 * the fallback and current primary policy (if any), that will later be used
435 struct ptlrpc_nrs_policy *primary = NULL; nrs_resource_get_safe() local
448 primary = nrs->nrs_policy_primary; nrs_resource_get_safe()
449 if (primary != NULL) nrs_resource_get_safe()
450 nrs_policy_get_locked(primary); nrs_resource_get_safe()
460 if (primary != NULL) { nrs_resource_get_safe()
461 resp[NRS_RES_PRIMARY] = nrs_resource_get(primary, nrq, nrs_resource_get_safe()
464 * A primary policy may exist which may not wish to serve a nrs_resource_get_safe()
470 nrs_policy_put(primary); nrs_resource_get_safe()
549 * function attempts to enqueue the request first on the primary policy
563 * Try in descending order, because the primary policy (if any) is nrs_request_enqueue()
581 * Should never get here, as at least the primary policy's nrs_request_enqueue()
/linux-4.1.27/drivers/net/wireless/iwlwifi/mvm/
H A Dcoex.c511 struct ieee80211_chanctx_conf *primary; member in struct:iwl_bt_iterator_data
595 /* low latency is always primary */ iwl_mvm_bt_notif_iterator()
599 data->secondary = data->primary; iwl_mvm_bt_notif_iterator()
600 data->primary = chanctx_conf; iwl_mvm_bt_notif_iterator()
607 if (chanctx_conf == data->primary) iwl_mvm_bt_notif_iterator()
612 * downgrade the current primary no matter what its iwl_mvm_bt_notif_iterator()
615 data->secondary = data->primary; iwl_mvm_bt_notif_iterator()
616 data->primary = chanctx_conf; iwl_mvm_bt_notif_iterator()
625 * STA / P2P Client, try to be primary if first vif. If we are in low iwl_mvm_bt_notif_iterator()
626 * latency mode, we are already in primary and just don't do much iwl_mvm_bt_notif_iterator()
628 if (!data->primary || data->primary == chanctx_conf) iwl_mvm_bt_notif_iterator()
629 data->primary = chanctx_conf; iwl_mvm_bt_notif_iterator()
685 if (data.primary) { iwl_mvm_bt_coex_notif_handle()
686 struct ieee80211_chanctx_conf *chan = data.primary; iwl_mvm_bt_coex_notif_handle()
705 cpu_to_le32(*((u16 *)data.primary->drv_priv)); iwl_mvm_bt_coex_notif_handle()
H A Dcoex_legacy.c820 struct ieee80211_chanctx_conf *primary; member in struct:iwl_bt_iterator_data
907 /* low latency is always primary */ iwl_mvm_bt_notif_iterator()
911 data->secondary = data->primary; iwl_mvm_bt_notif_iterator()
912 data->primary = chanctx_conf; iwl_mvm_bt_notif_iterator()
919 if (chanctx_conf == data->primary) iwl_mvm_bt_notif_iterator()
924 * downgrade the current primary no matter what its iwl_mvm_bt_notif_iterator()
927 data->secondary = data->primary; iwl_mvm_bt_notif_iterator()
928 data->primary = chanctx_conf; iwl_mvm_bt_notif_iterator()
937 * STA / P2P Client, try to be primary if first vif. If we are in low iwl_mvm_bt_notif_iterator()
938 * latency mode, we are already in primary and just don't do much iwl_mvm_bt_notif_iterator()
940 if (!data->primary || data->primary == chanctx_conf) iwl_mvm_bt_notif_iterator()
941 data->primary = chanctx_conf; iwl_mvm_bt_notif_iterator()
997 if (data.primary) { iwl_mvm_bt_coex_notif_handle()
998 struct ieee80211_chanctx_conf *chan = data.primary; iwl_mvm_bt_coex_notif_handle()
1019 cmd.primary_ch_phy_id = *((u16 *)data.primary->drv_priv); iwl_mvm_bt_coex_notif_handle()
/linux-4.1.27/drivers/pci/
H A Dirq.c29 * The primary function of this routine is to report a lost interrupt
H A Dsetup-irq.c32 /* If this device is not on the primary bus, we need to figure out pdev_fixup_irq()
/linux-4.1.27/drivers/gpu/drm/bochs/
H A Dbochs_kms.c62 if (WARN_ON(crtc->primary->fb == NULL)) bochs_crtc_mode_set_base()
65 bochs_fb = to_bochs_framebuffer(crtc->primary->fb); bochs_crtc_mode_set_base()
115 struct drm_framebuffer *old_fb = crtc->primary->fb; bochs_crtc_page_flip()
118 crtc->primary->fb = fb; bochs_crtc_page_flip()
/linux-4.1.27/arch/tile/include/asm/
H A Dtimex.h21 * frequency is highly tunable but also quite precise, so for the primary use
/linux-4.1.27/drivers/block/drbd/
H A Ddrbd_state.h82 unsigned role:2 ; /* 3/4 primary/secondary/unknown */
83 unsigned peer:2 ; /* 3/4 primary/secondary/unknown */
101 unsigned peer:2 ; /* 3/4 primary/secondary/unknown */
102 unsigned role:2 ; /* 3/4 primary/secondary/unknown */
H A Ddrbd_strings.c94 [-SS_O_VOL_PEER_PRI] = "Other vol primary on peer not allowed by config",
/linux-4.1.27/arch/powerpc/kernel/
H A Dcrash.c33 * The primary CPU waits a while for all secondary CPUs to enter. This is to
37 * The secondary timeout has to be longer than the primary. Both timeouts are
147 * The primary CPU returns here via setjmp, and the secondary crash_kexec_prepare_cpus()
187 /* Wait for the primary crash CPU to signal its progress */ crash_kexec_secondary()
/linux-4.1.27/arch/frv/mm/
H A Dhighmem.c51 * The first 4 primary maps are reserved for architecture code kmap_atomic()
/linux-4.1.27/arch/arm/kvm/
H A Dcoproc_a15.c28 * CRn denotes the primary register number, but is copied to the CRm in the
H A Dcoproc_a7.c31 * CRn denotes the primary register number, but is copied to the CRm in the
/linux-4.1.27/include/linux/
H A Ddrbd.h269 unsigned role:2 ; /* 3/4 primary/secondary/unknown */
270 unsigned peer:2 ; /* 3/4 primary/secondary/unknown */
292 unsigned peer:2 ; /* 3/4 primary/secondary/unknown */
293 unsigned role:2 ; /* 3/4 primary/secondary/unknown */
H A Ddio.h100 #define DIO_IDOFF 0x01 /* primary device ID */
137 /* The hardware has primary and secondary IDs; we encode these in a single
143 /* macro to determine whether a given primary ID requires a secondary ID byte */
H A Dhyperv.h721 * The initial offer is considered the primary channel and this
724 * open these sub-channels as a normal "primary" channel. However,
726 * primary channel. Requests sent on a given channel will result in a
744 * All Sub-channels of a primary channel are linked here.
748 * The primary channel this sub-channel belongs to.
749 * This will be NULL for the primary channel.
794 * When a primary channel has multiple sub-channels, we choose a
798 struct vmbus_channel *vmbus_get_outgoing_channel(struct vmbus_channel *primary);
811 bool vmbus_are_subchannels_present(struct vmbus_channel *primary);
H A Dmmu_notifier.h61 * at a smaller granularity than the primary MMU.
354 * This is safe to start by updating the secondary MMUs, because the primary MMU
360 * page is already writable by some CPU through the primary MMU.
/linux-4.1.27/include/linux/irqchip/
H A Dchained_irq.h24 * Entry/exit functions for chained handlers where the primary IRQ chip
/linux-4.1.27/drivers/gpu/drm/gma500/
H A Doaktrail_crtc.c602 struct psb_framebuffer *psbfb = to_psb_fb(crtc->primary->fb); oaktrail_pipe_set_base()
611 if (!crtc->primary->fb) { oaktrail_pipe_set_base()
620 offset = y * crtc->primary->fb->pitches[0] + x * (crtc->primary->fb->bits_per_pixel / 8); oaktrail_pipe_set_base()
622 REG_WRITE(map->stride, crtc->primary->fb->pitches[0]); oaktrail_pipe_set_base()
627 switch (crtc->primary->fb->bits_per_pixel) { oaktrail_pipe_set_base()
632 if (crtc->primary->fb->depth == 15) oaktrail_pipe_set_base()
H A Dgma_display.c62 struct psb_framebuffer *psbfb = to_psb_fb(crtc->primary->fb); gma_pipe_set_base()
73 if (!crtc->primary->fb) { gma_pipe_set_base()
84 offset = y * crtc->primary->fb->pitches[0] + x * (crtc->primary->fb->bits_per_pixel / 8); gma_pipe_set_base()
86 REG_WRITE(map->stride, crtc->primary->fb->pitches[0]); gma_pipe_set_base()
91 switch (crtc->primary->fb->bits_per_pixel) { gma_pipe_set_base()
96 if (crtc->primary->fb->depth == 15) gma_pipe_set_base()
521 if (crtc->primary->fb) { gma_crtc_disable()
522 gt = to_psb_fb(crtc->primary->fb)->gtt; gma_crtc_disable()
H A Dmdfld_intel_display.c169 struct psb_framebuffer *psbfb = to_psb_fb(crtc->primary->fb); mdfld__intel_pipe_set_base()
181 if (!crtc->primary->fb) { mdfld__intel_pipe_set_base()
186 ret = check_fb(crtc->primary->fb); mdfld__intel_pipe_set_base()
199 offset = y * crtc->primary->fb->pitches[0] + x * (crtc->primary->fb->bits_per_pixel / 8); mdfld__intel_pipe_set_base()
201 REG_WRITE(map->stride, crtc->primary->fb->pitches[0]); mdfld__intel_pipe_set_base()
205 switch (crtc->primary->fb->bits_per_pixel) { mdfld__intel_pipe_set_base()
210 if (crtc->primary->fb->depth == 15) mdfld__intel_pipe_set_base()
703 ret = check_fb(crtc->primary->fb); mdfld_crtc_mode_set()
/linux-4.1.27/drivers/net/wireless/orinoco/
H A Dfw.c50 __le32 pri_offset; /* Offset to primary plug data */
84 orinoco_cached_fw_get(struct orinoco_private *priv, bool primary) orinoco_cached_fw_get() argument
86 if (primary) orinoco_cached_fw_get()
92 #define orinoco_cached_fw_get(priv, primary) (NULL)
302 /* Load primary firmware */ symbol_dl_firmware()
/linux-4.1.27/drivers/clk/rockchip/
H A Dclk-cpu.c45 * of the primary parent clock.
48 * primary parent clock.
152 * dividing the primary parent by the extra dividers that were rockchip_cpuclk_pre_rate_change()
192 * post-rate change event, re-mux to primary parent and remove dividers. rockchip_cpuclk_post_rate_change()
195 * primary parent by the extra dividers that were needed for the alt. rockchip_cpuclk_post_rate_change()
/linux-4.1.27/arch/powerpc/platforms/85xx/
H A Dsmp.c208 int primary = cpu_first_thread_sibling(nr); smp_85xx_kick_cpu() local
219 if (!cpu_online(primary)) { smp_85xx_kick_cpu()
220 pr_err("%s: cpu %d: primary %d not online\n", smp_85xx_kick_cpu()
221 __func__, nr, primary); smp_85xx_kick_cpu()
225 smp_call_function_single(primary, wake_hw_thread, &nr, 0); smp_85xx_kick_cpu()
/linux-4.1.27/drivers/target/
H A Dtarget_core_alua.c45 int *primary);
296 int alua_access_state, primary = 0, valid_states; target_emulate_set_target_port_groups() local
347 * the state is a primary or secondary target port asymmetric target_emulate_set_target_port_groups()
351 valid_states, &primary); target_emulate_set_target_port_groups()
368 * specifies a primary target port asymmetric access state, target_emulate_set_target_port_groups()
370 * a primary target port group for which the primary target target_emulate_set_target_port_groups()
379 if (primary) { target_emulate_set_target_port_groups()
461 * by the ALUA primary or secondary access state.. set_ascq()
480 * temporarily delayed for the Active/NonOptimized primary access state. core_alua_state_nonoptimized()
784 core_alua_check_transition(int state, int valid, int *primary) core_alua_check_transition() argument
788 * defined as primary target port asymmetric access states. core_alua_check_transition()
794 *primary = 1; core_alua_check_transition()
799 *primary = 1; core_alua_check_transition()
804 *primary = 1; core_alua_check_transition()
809 *primary = 1; core_alua_check_transition()
814 *primary = 1; core_alua_check_transition()
823 *primary = 0; core_alua_check_transition()
1049 * Set the current primary ALUA access state to the requested new state core_alua_do_transition_tg_pt_work()
1055 " from primary access state %s to %s\n", (explicit) ? "explicit" : core_alua_do_transition_tg_pt_work()
1099 * Save the old primary ALUA access state, and set the current state core_alua_do_transition_tg_pt()
1113 * Check for the optional ALUA primary state transition delay core_alua_do_transition_tg_pt()
1155 int primary, valid_states, rc = 0; core_alua_do_port_transition() local
1158 if (core_alua_check_transition(new_state, valid_states, &primary) != 0) core_alua_do_port_transition()
1244 " Group IDs: %hu %s transition to primary state: %s\n", core_alua_do_port_transition()
/linux-4.1.27/arch/powerpc/mm/
H A Dhash_low_32.S339 /* Get the address of the primary PTE group in the hash table (r3) */
344 xor r3,r3,r0 /* make primary hash */
360 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
381 /* Search the primary PTEG for an empty slot */
383 addi r4,r3,-HPTE_SIZE /* search primary PTEG */
389 /* update counter of times that the primary PTEG is full */
409 * Choose an arbitrary slot in the primary PTEG to overwrite.
410 * Since both the primary and secondary PTEGs are full, and we
411 * have no information that the PTEs in the primary PTEG are
414 * advantage to putting the PTE in the primary PTEG, we always
415 * put the PTE in the primary PTEG.
579 /* Get the address of the primary PTE group in the hash table (r3) */
584 xor r8,r0,r8 /* make primary hash */
586 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
H A Dhash_low_64.S120 * Calculate hash value for primary slot and store it in r28
134 * calculate hash value for primary slot and
194 /* Calculate primary group hash */
425 * Calculate hash value for primary slot and store it in r28
443 * Calculate hash value for primary slot and
523 /* Calculate primary group hash */
782 /* Calculate hash value for primary slot and store it in r28
795 * calculate hash value for primary slot and
858 /* Calculate primary group hash */
/linux-4.1.27/drivers/s390/net/
H A Dqeth_l2_sys.c49 word = "primary"; break; qeth_bridge_port_role_state_show()
82 if (sysfs_streq(buf, "primary")) qeth_bridge_port_role_store()
/linux-4.1.27/drivers/clocksource/
H A Dtimer-integrator-ap.c182 "arm,timer-primary", &path); integrator_ap_timer_init_of()
193 /* The primary timer lacks IRQ, use as clocksource */ integrator_ap_timer_init_of()
/linux-4.1.27/sound/soc/txx9/
H A Dtxx9aclc-ac97.c108 /* wait for primary codec ready status */ txx9aclc_ac97_cold_reset()
113 dev_err(&ac97->dev, "primary codec is not ready " txx9aclc_ac97_cold_reset()
/linux-4.1.27/include/drm/
H A Ddrm_plane_helper.h31 * Drivers that don't allow primary plane scaling may pass this macro in place
42 * Helper functions to assist with creation and handling of CRTC primary
H A Ddrm_dp_mst_helper.h110 * primary branch device at the root, along with any other branches connected
406 * @lock: protects mst state, primary, dpcd.
408 * @mst_primary: pointer to the primary branch device.
409 * @dpcd: cache of DPCD for primary port.
430 struct mutex lock; /* protects mst_state + primary + dpcd */
/linux-4.1.27/include/linux/mfd/arizona/
H A Dpdata.h90 /** Mode for primary IRQ (defaults to active low) */
174 /** GPIO for primary IRQ (used for edge triggered emulation) */
/linux-4.1.27/drivers/isdn/hardware/eicon/
H A Dxdi_msg.h45 Reset of the board + activation of primary
/linux-4.1.27/arch/metag/tbx/
H A Dtbiroot.S38 * Register Usage: D1Ar1 is Id, D0Re0 is the primary result
/linux-4.1.27/drivers/gpu/drm/udl/
H A Dudl_drv.c83 DRM_INFO("Initialized udl on minor %d\n", dev->primary->index); udl_usb_probe()
H A Dudl_modeset.c314 struct udl_framebuffer *ufb = to_udl_fb(crtc->primary->fb); udl_crtc_mode_set()
376 struct drm_framebuffer *old_fb = crtc->primary->fb; udl_crtc_page_flip()
389 crtc->primary->fb = fb; udl_crtc_page_flip()
/linux-4.1.27/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_ldu.c97 fb = entry->base.crtc.primary->fb; vmw_ldu_commit_list()
105 fb = entry->base.crtc.primary->fb; vmw_ldu_commit_list()
263 crtc->primary->fb = NULL; vmw_ldu_crtc_set_config()
284 crtc->primary->fb = fb; vmw_ldu_crtc_set_config()
H A Dvmwgfx_scrn.c311 crtc->primary->fb = NULL; vmw_sou_crtc_set_config()
372 crtc->primary->fb = NULL; vmw_sou_crtc_set_config()
385 crtc->primary->fb = fb; vmw_sou_crtc_set_config()
576 vmw_framebuffer_to_vfb(sou->base.crtc.primary->fb); vmw_kms_screen_object_update_implicit_fb()
/linux-4.1.27/fs/jfs/
H A Djfs_filsys.h165 #define SUPER1_B 64 /* primary superblock */
194 #define SUPER1_OFF 0x8000 /* primary superblock */
216 * currently defined to be 32K. This turns out to be the same as the primary
224 * turns out to be the same as the primary superblock's byte offset, since it
/linux-4.1.27/include/net/irda/
H A Dirlap_event.h51 LAP_NRM_P, /* Normal response mode as primary */
/linux-4.1.27/arch/powerpc/platforms/powernv/
H A Dsubcore-asm.S53 /* Order reading the SPRs vs telling the primary we are ready to split */
H A Dpci-p5ioc2.c105 static int primary = 1; pnv_pci_init_p5ioc2_phb() local
162 pci_process_bridge_OF_ranges(phb->hose, np, primary); pnv_pci_init_p5ioc2_phb()
163 primary = 0; pnv_pci_init_p5ioc2_phb()
/linux-4.1.27/arch/ia64/pci/
H A Dfixup.c27 * already determined primary video card.
/linux-4.1.27/arch/arm/mach-prima2/
H A Dplatsmp.c30 * let the primary processor know we're out of the sirfsoc_secondary_init()
/linux-4.1.27/arch/arm/mach-sti/
H A Dplatsmp.c44 * let the primary processor know we're out of the sti_secondary_init()
/linux-4.1.27/arch/arm/plat-versatile/
H A Dplatsmp.c38 * let the primary processor know we're out of the versatile_secondary_init()
/linux-4.1.27/arch/arm/include/asm/mach/
H A Dpci.h49 int busnr; /* primary bus number */
/linux-4.1.27/arch/arm/include/asm/
H A Dvirt.h36 * __boot_cpu_mode records what mode the primary CPU was booted in.
/linux-4.1.27/drivers/gpu/drm/armada/
H A Darmada_crtc.c506 drm_framebuffer_reference(crtc->primary->fb); armada_drm_crtc_mode_set()
510 i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb, armada_drm_crtc_mode_set()
596 val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt); armada_drm_crtc_mode_set()
597 val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod); armada_drm_crtc_mode_set()
599 if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420) armada_drm_crtc_mode_set()
637 i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs, armada_drm_crtc_mode_set_base()
645 drm_framebuffer_reference(crtc->primary->fb); armada_drm_crtc_mode_set_base()
662 armada_drm_crtc_finish_fb(dcrtc, crtc->primary->fb, true); armada_drm_crtc_disable()
931 if (fb->pixel_format != crtc->primary->fb->pixel_format) armada_drm_crtc_page_flip()
939 work->old_fb = dcrtc->crtc.primary->fb; armada_drm_crtc_page_flip()
965 dcrtc->crtc.primary->fb = fb; armada_drm_crtc_page_flip()
/linux-4.1.27/drivers/gpu/drm/nouveau/dispnv04/
H A Dcrtc.c243 struct drm_framebuffer *fb = crtc->primary->fb; nv_crtc_mode_set_vga()
497 /* Except for rare conditions I2C is enabled on the primary crtc */ nv_crtc_mode_set_regs()
578 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->primary->fb->depth + 1) / 8; nv_crtc_mode_set_regs()
592 if (crtc->primary->fb->depth == 16) nv_crtc_mode_set_regs()
613 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); nv_crtc_swap_fbs()
812 if (!nv_crtc->base.primary->fb) { nv_crtc_gamma_set()
836 if (!atomic && !crtc->primary->fb) { nv04_crtc_do_mode_set_base()
848 drm_fb = crtc->primary->fb; nv04_crtc_do_mode_set_base()
849 fb = nouveau_framebuffer(crtc->primary->fb); nv04_crtc_do_mode_set_base()
861 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->primary->fb->depth + 1) / 8; nv04_crtc_do_mode_set_base()
863 if (crtc->primary->fb->depth == 16) nv04_crtc_do_mode_set_base()
/linux-4.1.27/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop.c729 crtc_w = crtc->primary->fb->width - crtc->x; vop_update_primary_plane()
730 crtc_h = crtc->primary->fb->height - crtc->y; vop_update_primary_plane()
732 return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb, vop_update_primary_plane()
989 struct drm_framebuffer *old_fb = crtc->primary->fb; vop_crtc_page_flip()
998 crtc->primary->fb = fb; vop_crtc_page_flip()
1002 crtc->primary->fb = old_fb; vop_crtc_page_flip()
1182 struct drm_plane *primary = NULL, *cursor = NULL, *plane; vop_create_crtc() local
1189 * Create drm_plane for primary and cursor planes first, since we need vop_create_crtc()
1213 primary = plane; vop_create_crtc()
1218 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, vop_create_crtc()
/linux-4.1.27/drivers/gpu/drm/shmobile/
H A Dshmob_drm_crtc.c177 format = shmob_drm_format_info(crtc->primary->fb->pixel_format); shmob_drm_crtc_start()
307 struct drm_framebuffer *fb = crtc->primary->fb; shmob_drm_crtc_compute_base()
386 format = shmob_drm_format_info(crtc->primary->fb->pixel_format); shmob_drm_crtc_mode_set()
389 crtc->primary->fb->pixel_format); shmob_drm_crtc_mode_set()
394 scrtc->line_size = crtc->primary->fb->pitches[0]; shmob_drm_crtc_mode_set()
406 crtc->primary->fb->pitches[0], shmob_drm_crtc_mode_set()
493 crtc->primary->fb = fb; shmob_drm_crtc_page_flip()
/linux-4.1.27/arch/ia64/sn/kernel/
H A Dsetup.c268 u8 primary; member in struct:pcdp_device_desc
297 /* from pcdp_device_desc.primary */
338 if (! (device.primary & PCDP_PRIMARY_CONSOLE)) sn_scan_pcdp()
339 continue; /* not primary console */ sn_scan_pcdp()
355 break; /* once we find the primary, we're done */ sn_scan_pcdp()
399 * on the PCDP table to identify the primary VGA console if one sn_setup()
407 * here so that the primary VGA console (as defined by PCDP) will sn_setup()
/linux-4.1.27/arch/sparc/kernel/
H A Dsbus.c285 /* Clear primary/secondary error status bits. */ sysio_ue_handler()
294 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n", sysio_ue_handler()
359 /* Clear primary/secondary error status bits. */ sysio_ce_handler()
367 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n", sysio_ce_handler()
437 /* Clear primary/secondary error status bits. */ sysio_sbus_error_handler()
446 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n", sysio_sbus_error_handler()
H A Dpci_sabre.c208 /* Clear the primary/secondary error status bits. */ sabre_ue_intr()
218 printk("%s: Uncorrectable Error, primary error type[%s%s]\n", sabre_ue_intr()
268 /* Clear primary/secondary error status bits. */ sabre_ce_intr()
277 printk("%s: Correctable Error, primary error type[%s]\n", sabre_ce_intr()
389 /* Use a primary/seconday latency timer value apb_init()
/linux-4.1.27/drivers/gpu/drm/imx/
H A Dipuv3-crtc.c126 crtc->primary->fb = fb; ipu_page_flip()
202 crtc->primary->fb, ipu_crtc_mode_set()
231 ipu_plane_set_base(plane, ipu_crtc->base.primary->fb, ipu_irq_handler()
/linux-4.1.27/arch/arm64/kernel/
H A Dprocess.c139 * while the primary CPU resets the system. Systems with a single CPU can
143 * This is required so that any code running after reset on the primary CPU
145 * executing pre-reset code, and using RAM that the primary CPU's code wishes
/linux-4.1.27/drivers/iommu/
H A Dfsl_pamu_domain.h62 * valid bit for the primary PAACE in the PAMU
/linux-4.1.27/drivers/net/ethernet/altera/
H A Daltera_tse.h182 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
186 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
/linux-4.1.27/arch/x86/boot/
H A Dpm.c42 outb(0xfb, 0x21); /* Mask all but cascade on the primary PIC */ mask_all_interrupts()
/linux-4.1.27/include/uapi/asm-generic/
H A Dioctls.h70 #define TIOCGDEV _IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */
/linux-4.1.27/arch/powerpc/platforms/cell/
H A Dsmp.c63 * At boot time, there is nothing to do for primary threads which were
/linux-4.1.27/arch/mn10300/boot/compressed/
H A Dhead.S28 # Must save primary CPU's D0-D2 registers as they hold boot parameters
/linux-4.1.27/arch/parisc/include/uapi/asm/
H A Dioctls.h57 #define TIOCGDEV _IOR('T',0x32, int) /* Get primary device node of /dev/console */
/linux-4.1.27/arch/powerpc/include/uapi/asm/
H A Dioctls.h97 #define TIOCGDEV _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */
/linux-4.1.27/arch/frv/include/asm/
H A Ddma.h111 #define DMAC_PIXx 0x28 /* primary index reg */
/linux-4.1.27/arch/arm/mach-realview/include/mach/
H A Dirqs-pb1176.h28 * ARM1176 DevChip interrupt sources (primary GIC)
H A Dirqs-pb11mp.h28 * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
/linux-4.1.27/arch/arm/mach-spear/
H A Dplatsmp.c42 * let the primary processor know we're out of the spear13xx_secondary_init()
/linux-4.1.27/arch/arm/mach-ixp4xx/include/mach/
H A Dplatform.h116 * Frequency of clock used for primary clocksource
/linux-4.1.27/tools/power/cpupower/utils/helpers/
H A Dtopology.c92 because the primary sort of the core_info struct was just get_cpu_topology()
/linux-4.1.27/drivers/media/platform/soc_camera/
H A Dsh_mobile_csi2.c69 /* All MIPI CSI-2 devices must support one of primary formats */ sh_csi2_try_fmt()
82 /* All MIPI CSI-2 devices must support one of primary formats */ sh_csi2_try_fmt()
/linux-4.1.27/drivers/net/wireless/brcm80211/brcmfmac/
H A Dp2p.h26 * @P2PAPI_BSSCFG_PRIMARY: maps to driver's primary bsscfg.
32 P2PAPI_BSSCFG_PRIMARY, /* maps to driver's primary bsscfg */
/linux-4.1.27/arch/x86/kernel/
H A Dkvmclock.c180 kvm_register_clock("primary cpu clock, resume"); kvm_restore_sched_clock_state()
243 if (kvm_register_clock("primary cpu clock")) { kvmclock_init()
/linux-4.1.27/arch/x86/tools/
H A Dgen-insn-attr-x86.awk144 if (aid == -1 && eid == -1) # primary opcode table
191 # print primary/escaped tables
/linux-4.1.27/include/net/sctp/
H A Dcommand.h97 SCTP_CMD_DEL_NON_PRIMARY, /* Removes non-primary peer transports. */
99 SCTP_CMD_FORCE_PRIM_RETRAN, /* Forces retrans. over primary path. */
/linux-4.1.27/include/uapi/linux/android/
H A Dbinder.h205 * Else the remote object has acquired a primary reference.
285 * Else you have acquired a primary reference on the object.
/linux-4.1.27/sound/arm/
H A Dpxa2xx-ac97-lib.c56 /* set up primary or secondary codec space */ pxa2xx_ac97_read()
96 /* set up primary or secondary codec space */ pxa2xx_ac97_write()
/linux-4.1.27/arch/powerpc/platforms/maple/
H A Dpci.c498 int primary = 1; maple_add_bridge() local
519 primary = 0; maple_add_bridge()
523 primary = 1; maple_add_bridge()
527 primary = 0; maple_add_bridge()
534 pci_process_bridge_OF_ranges(hose, dev, primary); maple_add_bridge()
/linux-4.1.27/drivers/gpu/drm/tegra/
H A Ddc.c960 bo = tegra_fb_get_plane(crtc->primary->fb, 0); tegra_dc_finish_page_flip()
972 if (base == bo->paddr + crtc->primary->fb->offsets[0]) { tegra_dc_finish_page_flip()
1639 struct drm_plane *primary = NULL; tegra_dc_init() local
1655 primary = tegra_dc_primary_plane_create(drm, dc); tegra_dc_init()
1656 if (IS_ERR(primary)) { tegra_dc_init()
1657 err = PTR_ERR(primary); tegra_dc_init()
1669 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, tegra_dc_init()
1695 err = tegra_dc_debugfs_init(dc, drm->primary); tegra_dc_init()
1750 if (primary) tegra_dc_init()
1751 drm_plane_cleanup(primary); tegra_dc_init()
/linux-4.1.27/drivers/media/radio/
H A Dradio-si476x.c222 * on, primary tuner's antenna is the main one.
224 * off, primary tuner's antenna is the main one.
405 .primary = false, si476x_radio_g_tuner()
432 strlcpy(tuner->name, "AM/FM (primary)", si476x_radio_g_tuner()
681 .primary = false, si476x_radio_g_frequency()
1304 .primary = false, si476x_radio_read_rsq_blob()
1339 .primary = true, si476x_radio_read_rsq_primary_blob()
/linux-4.1.27/arch/x86/mm/
H A Dpageattr.c662 * primary protection behavior: __split_large_page()
1091 int primary) __cpa_process_fault()
1097 * Ignore all non primary paths. __cpa_process_fault()
1099 if (!primary) __cpa_process_fault()
1123 static int __change_page_attr(struct cpa_data *cpa, int primary) __change_page_attr() argument
1142 return __cpa_process_fault(cpa, address, primary); __change_page_attr()
1146 return __cpa_process_fault(cpa, address, primary); __change_page_attr()
1244 * No need to redo, when the primary call touched the direct cpa_process_alias()
1271 * If the primary call didn't touch the high mapping already cpa_process_alias()
1090 __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, int primary) __cpa_process_fault() argument
/linux-4.1.27/arch/sparc/include/uapi/asm/
H A Dasi.h271 * primary, implicit
279 * Most-Recently-Used, primary,
289 * Most-Recently-Used, primary,
/linux-4.1.27/arch/mips/sgi-ip22/
H A Dip28-berr.c79 * Save all primary data cache (indexed by VA[13:5]) tags which save_cache_tags()
83 * matching primary tags here already. save_cache_tags()
98 * Save primary instruction cache (indexed by VA[13:6]) tags save_cache_tags()
/linux-4.1.27/kernel/irq/
H A Dspurious.c290 * (primary and threaded). Aside of that in the threaded note_interrupt()
310 * shared primary handlers returned IRQ_HANDLED. If note_interrupt()
367 * One of the primary handlers returned note_interrupt()
/linux-4.1.27/kernel/
H A Dprofile.c283 unsigned long primary, secondary, flags, pc = (unsigned long)__pc; do_profile_hits() local
288 i = primary = (pc & (NR_PROFILE_GRP - 1)) << PROFILE_GRPSHIFT; do_profile_hits()
314 } while (i != primary); do_profile_hits()
/linux-4.1.27/drivers/irqchip/
H A Dirq-versatile-fpga.c220 * pass-thru to the primary controller for IRQs 20 and 22-31 which need fpga_irq_of_init()
/linux-4.1.27/drivers/media/pci/saa7134/
H A Dsaa7134-tvaudio.c175 int primary, int secondary) tvaudio_setcarrier()
178 secondary = primary; tvaudio_setcarrier()
179 saa_writel(SAA7134_CARRIER1_FREQ0 >> 2, tvaudio_carr2reg(primary)); tvaudio_setcarrier()
579 /* Note: at least the primary carrier is right here */ tvaudio_thread()
174 tvaudio_setcarrier(struct saa7134_dev *dev, int primary, int secondary) tvaudio_setcarrier() argument
/linux-4.1.27/drivers/scsi/dpt/
H A Ddpti_ioctl.h98 uCHAR primary; /* 1 For Primary, 0 For Secondary */ member in struct:__anon8785
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Dssv_dnp.c152 * allocated for the primary 8259, so we don't need to allocate them dnp_attach()

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