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/linux-4.1.27/arch/sh/kernel/
Dtraps_32.c86 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, in handle_unaligned_ins() argument
94 index = (instruction>>8)&15; /* 0x0F00 */ in handle_unaligned_ins()
97 index = (instruction>>4)&15; /* 0x00F0 */ in handle_unaligned_ins()
100 count = 1<<(instruction&3); in handle_unaligned_ins()
110 switch (instruction>>12) { in handle_unaligned_ins()
112 if (instruction & 8) { in handle_unaligned_ins()
144 dstu += (instruction&0x000F)<<2; in handle_unaligned_ins()
152 if (instruction & 4) in handle_unaligned_ins()
166 srcu += (instruction & 0x000F) << 2; in handle_unaligned_ins()
177 if (instruction & 4) in handle_unaligned_ins()
[all …]
Dio_trapped.c274 insn_size_t instruction; in handle_trapped_io() local
286 if (copy_from_user(&instruction, (void *)(regs->pc), in handle_trapped_io()
287 sizeof(instruction))) { in handle_trapped_io()
292 tmp = handle_unaligned_access(instruction, regs, in handle_trapped_io()
/linux-4.1.27/drivers/media/usb/gspca/
Djl2005bcd.c121 static u8 instruction[2] = {0x95, 0x00}; in jl2005c_read_reg() local
123 instruction[1] = reg; in jl2005c_read_reg()
125 retval = jl2005c_write2(gspca_dev, instruction); in jl2005c_read_reg()
139 static u8 instruction[2] = {0x7f, 0x01}; in jl2005c_start_new_frame() local
141 retval = jl2005c_write2(gspca_dev, instruction); in jl2005c_start_new_frame()
165 u8 instruction[2]; in jl2005c_write_reg() local
167 instruction[0] = reg; in jl2005c_write_reg()
168 instruction[1] = value; in jl2005c_write_reg()
170 retval = jl2005c_write2(gspca_dev, instruction); in jl2005c_write_reg()
212 static u8 instruction[][2] = { in jl2005c_stream_start_vga_lg() local
[all …]
Dsn9c2028.c39 unsigned char instruction[6]; member
234 cam_commands[i].instruction); in run_start_commands()
238 cam_commands[i].instruction); in run_start_commands()
242 cam_commands[i].instruction); in run_start_commands()
Djeilinj.c74 unsigned char instruction[2]; member
259 jlj_write2(gspca_dev, start_commands[i].instruction); in jlj_start()
/linux-4.1.27/net/nfc/hci/
Dhcp.c34 u8 type, u8 instruction, in nfc_hci_hcp_message_tx() argument
87 packet->message.header = HCP_HEADER(type, instruction); in nfc_hci_hcp_message_tx()
132 u8 instruction, struct sk_buff *skb) in nfc_hci_hcp_message_rx() argument
136 nfc_hci_resp_received(hdev, instruction, skb); in nfc_hci_hcp_message_rx()
139 nfc_hci_cmd_received(hdev, pipe, instruction, skb); in nfc_hci_hcp_message_rx()
142 nfc_hci_event_received(hdev, pipe, instruction, skb); in nfc_hci_hcp_message_rx()
146 type, instruction); in nfc_hci_hcp_message_rx()
Dhci.h83 u8 type, u8 instruction,
89 u8 instruction, struct sk_buff *skb);
Dcore.c146 u8 instruction; in nfc_hci_msg_rx_work() local
153 instruction = HCP_MSG_GET_CMD(message->header); in nfc_hci_msg_rx_work()
156 nfc_hci_hcp_message_rx(hdev, pipe, type, instruction, skb); in nfc_hci_msg_rx_work()
846 u8 instruction; in nfc_hci_recv_from_llc() local
899 instruction = HCP_MSG_GET_CMD(packet->message.header); in nfc_hci_recv_from_llc()
902 nfc_hci_hcp_message_rx(hdev, pipe, type, instruction, hcp_skb); in nfc_hci_recv_from_llc()
/linux-4.1.27/arch/nios2/platform/
DKconfig.platform56 bool "Enable MUL instruction"
60 instruction. This will enable the -mhw-mul compiler flag.
63 bool "Enable MULX instruction"
67 instruction. Enables the -mhw-mulx compiler flag.
70 bool "Enable DIV instruction"
74 instruction. Enables the -mhw-div compiler flag.
83 bool "Byteswap custom instruction"
86 Use the byteswap (endian converter) Nios II custom instruction provided
91 int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT
94 Number of the instruction as configured in QSYS Builder.
[all …]
/linux-4.1.27/Documentation/
Dlzo.txt20 the operands for the instruction, whose size and position depend on the
21 opcode and on the number of literals copied by previous instruction. The
57 After any instruction except the large literal copy, 0, 1, 2 or 3 literals
58 are copied before starting the next instruction. The number of literals that
59 were copied may change the meaning and behaviour of the next instruction. In
60 practice, only one instruction needs to know whether 0, less than 4, or more
63 generally encoded in the last two bits of the instruction but may also be
67 instruction may encode this distance (0001HLLL), it takes one LE16 operand
80 0..17 : follow regular instruction encoding, see below. It is worth
97 Depends on the number of literals copied by the last instruction.
[all …]
Dkprobes.txt31 on virtually any instruction in the kernel. A jprobe is inserted at
59 instruction and replaces the first byte(s) of the probed instruction
60 with a breakpoint instruction (e.g., int3 on i386 and x86_64).
62 When a CPU hits the breakpoint instruction, a trap occurs, the CPU's
68 Next, Kprobes single-steps its copy of the probed instruction.
69 (It would be simpler to single-step the actual instruction in place,
71 instruction. This would open a small time window when another CPU
74 After the instruction is single-stepped, Kprobes executes the
76 Execution then continues with the instruction following the probepoint.
89 Kprobes then points the saved instruction pointer at the jprobe's
[all …]
Dstatic-keys.txt63 consist of a single atomic 'no-op' instruction (5 bytes on x86), in the
65 'no-op' in the straight-line codepath with a 'jump' instruction to the
230 Thus, the disable jump label case adds a 'mov', 'test' and 'jne' instruction
232 to a 5 byte atomic no-op instruction at boot-time.) Thus, the disabled jump
238 of instruction memory for this small function. In this case the non-jump label
239 function is 80 bytes long. Thus, we have saved 20% of the instruction
Dthis_cpu_ops.txt11 specific per cpu base and encode that operation in the instruction
68 instruction via a segment register prefix.
77 results in a single instruction
91 The above results in the following single instruction (no lock prefix!)
111 after the this_cpu instruction is executed. In general this means that
247 instruction.
Dpercpu-rw-semaphore.txt13 instruction in the lock and unlock path. On the other hand, locking for
Doops-tracing.txt93 of bytes that precede the current instruction pointer as well as bytes at and
94 following the current instruction pointer. In some cases, one instruction
96 <> or () markings indicate the current instruction pointer. Example from
Dintel_txt.txt94 processor instruction that initiates the dynamic root of trust.
102 o The GETSEC[SENTER] instruction will return control to tboot and
106 instruction had put them in and place them into a wait-for-SIPI
Dcircular-buffers.txt70 modulus (divide) instruction. However, if the buffer is of a power-of-2 size,
71 then a much quicker bitwise-AND instruction can be used instead.
Dcachetlb.txt79 executable (and thus could be in the 'instruction TLB' in
191 executable (and thus could be in the 'instruction cache' in
343 instruction cache does not snoop cpu stores, it is very
344 likely that you will need to flush the instruction cache
Dkmemcheck.txt261 bit) value. This will help us pinpoint exactly which instruction that caused
353 RIP value, they actually point to the _next_ instruction (they are return
516 As expected, it's the "rep movsl" instruction from the memcpy() that causes
725 But after the instruction has been executed, we should hide the page again, so
728 finished the one instruction that generated the memory access, a debug
Dpreempt-locking.txt44 if the kernel is executing a floating-point instruction and is then preempted.
Dmemory-barriers.txt486 instruction; the barrier can be considered to draw a line in that CPU's
1162 got to that point in the instruction execution flow yet. This permits the
1163 actual load instruction to potentially complete immediately because the CPU
1567 with a single memory-reference instruction, prevents "load tearing"
2354 instruction itself is complete.
2614 This means that it must be considered that the CPU will execute its instruction
2616 instruction in the stream depends on an earlier instruction, then that
2617 earlier instruction must be sufficiently complete[*] before the later
2618 instruction may proceed; in other words: provided that the appearance of
2625 A CPU may also discard any instruction sequence that winds up having no
[all …]
Dlocal_ops.txt15 a single instruction and yield more compact and faster executing code.
/linux-4.1.27/Documentation/arm64/
Dlegacy_instructions.txt3 the architecture. The infrastructure code uses undefined instruction
5 the instruction execution in hardware.
13 Generates undefined instruction abort. Default for instructions that
19 usage of emulated instruction is traced as well as rate limited
31 The default mode depends on the status of the instruction in the
36 individual instruction notes for further information.
Dbooting.txt186 - The primary CPU must jump directly to the first instruction of the
201 contained in the reserved region. A wfe instruction may be inserted
/linux-4.1.27/arch/openrisc/
DKconfig79 bool "Have instruction l.ff1"
82 Select this if your implementation has the Class II instruction l.ff1
85 bool "Have instruction l.fl1"
88 Select this if your implementation has the Class II instruction l.fl1
91 bool "Have instruction l.mul for hardware multiply"
94 Select this if your implementation has a hardware multiply instruction
97 bool "Have instruction l.div for hardware divide"
100 Select this if your implementation has a hardware divide instruction
/linux-4.1.27/arch/arm/probes/kprobes/
Dtest-core.h157 #define TEST_INSTRUCTION(instruction) \ argument
159 "1: "instruction" \n\t" \
162 #define TEST_BRANCH_F(instruction) \ argument
163 TEST_INSTRUCTION(instruction) \
167 #define TEST_BRANCH_B(instruction) \ argument
172 TEST_INSTRUCTION(instruction)
174 #define TEST_BRANCH_FX(instruction, codex) \ argument
175 TEST_INSTRUCTION(instruction) \
181 #define TEST_BRANCH_BX(instruction, codex) \ argument
187 TEST_INSTRUCTION(instruction)
/linux-4.1.27/arch/arm/nwfpe/
Dentry.S90 bne next @ get the next instruction;
93 bl EmulateAll @ emulate the instruction
98 .Lx1: ldrt r6, [r5], #4 @ get the next instruction and
115 @ plain LDR instruction. Weird, but it seems harmless.
Dfpmodule.inl24 /* Note: The CPU thinks it has dealt with the current instruction.
26 instruction, and points 4 bytes beyond the actual instruction
27 that caused the invalid instruction trap to occur. We adjust
/linux-4.1.27/arch/frv/kernel/
Dcmode.S88 # (4) Preload a series of following instructions to the instruction
111 # (5) Flush the content of all caches by the DCEF instruction.
123 # (8) Execute memory barrier instruction (MEMBAR).
132 # (10) Execute memory barrier instruction (MEMBAR).
144 # (13) Execute the instruction just after the memory barrier
145 # instruction that executes the self-loop 256 times. (Meanwhile,
Dsleep.S138 # Flush all data in the cache using the DCEF instruction.
332 # (3) Flush all data in the cache using the DCEF instruction.
335 # (4) Execute the memory barrier instruction
Dbreak.S123 # handle BREAK instruction in kernel-mode exception epilogue
337 # instruction after the broken-into exception returns
/linux-4.1.27/arch/m68k/fpsp040/
Dbugfix.S247 | dest and the dest of the xu. We must clear the instruction in
248 | the cu and restore the state, allowing the instruction in the
249 | xu to complete. Remember, the instruction in the nu
251 | If the result of the xu instruction is not exceptional, we can
252 | restore the instruction from the cu to the frame and continue
275 | Check if the instruction which just completed was exceptional.
280 | It is necessary to isolate the result of the instruction in the
369 | dest and the dest of the xu. We must clear the instruction in
370 | the cu and restore the state, allowing the instruction in the
371 | xu to complete. Remember, the instruction in the nu
[all …]
Dsmovecr.S5 | offset given in the instruction field.
7 | Input: An offset in the instruction word.
Dx_fline.S8 | Next, determine if the instruction is an fmovecr with a non-zero
50 moveal EXC_PC+4(%a6),%a0 |get address of fline instruction
65 | ;if an FMOVECR instruction, fix stack
Dx_unimp.S4 | fpsp_unimp --- FPSP handler for unimplemented instruction
19 | instruction.
Dx_ovfl.S14 | If the instruction is move_out, then garbage is stored in the
15 | destination. If the instruction is not move_out, then the
Dutil.S94 | instruction is fsgldiv or fsglmul or fsadd, fdadd, fsub, fdsub, fsmul,
96 | If the instruction is fsgldiv of fsglmul, the rounding precision must be
97 | extended. If the instruction is not fsgldiv or fsglmul but a force-
98 | precision instruction, the rounding precision is then set to the force
118 bra ovf_fpcr |instruction is none of the above
124 beql ovff_sgl |the instruction is force single
126 beql ovff_dbl |the instruction is force double
301 | get_fline --- get f-line opcode of interrupted instruction
Dget_op.S8 | instruction exception handler ('unimp' - vector 11). 'get_op'
40 | then an frestore is done to restore the instruction back into
42 | a normalized number in the source and the instruction is
50 | norm. The instruction is then restored back into the '040
Dsgetem.S39 | This entry point is used by the unimplemented instruction exception
65 | This entry point is used by the unimplemented instruction exception
Dgen_except.S221 | No exceptions are to be reported. If the instruction was
322 | are set by a previous instruction and not cleared by
324 | instruction in an emulation routine caused the exception
347 | instruction of an emulation routine.
Dscale.S10 | the fscale unimplemented instruction.
41 | This entry point is used by the unimplemented instruction exception
Dskeleton.S9 | before the jump instruction. If there no handling necessary, then
433 | The FPSP calls mem_read to read the original F-line instruction in order
Dres_func.S757 | This code handles the case of the instruction resulting in
802 | and complete the instruction.
977 | and complete the instruction.
1158 | and complete the instruction.
1196 | and complete the instruction.
1217 | This code handles the case of the instruction resulting in
Dx_snan.S18 | disabled with the exception posted. If the instruction is not move_
/linux-4.1.27/Documentation/arm/nwfpe/
DNOTES8 often uses an stfe instruction to save f4 on the stack upon entry to a
9 function, and an ldfe instruction to restore it before returning.
15 This is a side effect of the stfe instruction. The double in f4 had to be
29 in extended precision, due to the stfe instruction used to save f4 in log(y).
DREADME.FPE36 instruction. The format in memory is unlikely to be compatible with
57 presently check the CPU mode, and do an invalid instruction trap if not called
116 instruction. Since URD cannot return a unnormalized number, NRM becomes
DTODO42 the rounding mode one must specify it with each instruction.
48 the instruction, and use the mode specified in the bits in the FPCR.
DREADME43 which instruction contains the bug. Small programs illustrating a specific
/linux-4.1.27/arch/m68k/ifpsp060/src/
Disp.S1218 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1219 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1230 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1231 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1242 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1243 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1254 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1255 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1266 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1267 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
[all …]
Dpfpsp.S1228 # the FPIAR holds the "current PC" of the faulting instruction
1232 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1233 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
1234 bsr.l _imem_read_long # fetch the instruction words
1722 # three instruction exceptions don't update the stack pointer. so, if the
2038 # The opclass two PACKED instruction that took an "Unimplemented Data Type"
2371 # _imem_read_long() - read instruction longword #
2384 # fmovm_dynamic() - emulate dynamic fmovm instruction #
2385 # fmovm_ctrl() - emulate fmovm control instruction #
2404 # (2) The "fmovm.x" instruction w/ dynamic register specification. #
[all …]
Dfpsp.S1229 # the FPIAR holds the "current PC" of the faulting instruction
1233 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1234 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
1235 bsr.l _imem_read_long # fetch the instruction words
1723 # three instruction exceptions don't update the stack pointer. so, if the
2039 # The opclass two PACKED instruction that took an "Unimplemented Data Type"
2372 # _imem_read_long() - read instruction longword #
2385 # fmovm_dynamic() - emulate dynamic fmovm instruction #
2386 # fmovm_ctrl() - emulate fmovm control instruction #
2405 # (2) The "fmovm.x" instruction w/ dynamic register specification. #
[all …]
Dilsp.S63 # _060LSP__idivu64_(): Emulate 64-bit unsigned div instruction. #
64 # _060LSP__idivs64_(): Emulate 64-bit signed div instruction. #
68 # 64-bit divide instruction. #
88 # Restore sign info if signed instruction. Set the condition #
91 # divide instruction. This way, the operating system can record that #
480 # _060LSP__imulu64_(): Emulate 64-bit unsigned mul instruction #
481 # _060LSP__imuls64_(): Emulate 64-bit signed mul instruction. #
485 # 64-bit multiply instruction. #
/linux-4.1.27/arch/xtensa/
DKconfig.debug27 bool "Perform S32C1I instruction self-test at boot"
30 Enable this option to test S32C1I instruction behavior at boot.
31 Correct operation of this instruction requires some cooperation from hardware
/linux-4.1.27/arch/powerpc/kernel/
Dalign.c738 unsigned int instr, nb, flags, instruction = 0; in fix_alignment() local
790 instruction = instr; in fix_alignment()
812 if (IS_XFORM(instruction) && ((instruction >> 1) & 0x3ff) == 532) { in fix_alignment()
815 } else if (IS_XFORM(instruction) && in fix_alignment()
816 ((instruction >> 1) & 0x3ff) == 660) { in fix_alignment()
845 if ((instruction & 0xfc00003e) == 0x7c000018) { in fix_alignment()
849 reg |= (instruction & 0x1) << 5; in fix_alignment()
853 if (instruction & 0x200) in fix_alignment()
859 if (instruction & 0x80) in fix_alignment()
865 if (instruction & 0x100) in fix_alignment()
[all …]
Dmodule_64.c475 static int restore_r2(u32 *instruction, struct module *me) in restore_r2() argument
477 if (*instruction != PPC_INST_NOP) { in restore_r2()
479 me->name, *instruction); in restore_r2()
483 *instruction = 0xe8410000 | R2_STACK_OFFSET; in restore_r2()
/linux-4.1.27/arch/arm/kernel/
Dentry-armv.S235 @ Correct the PC such that it is pointing at the instruction
236 @ which caused the fault. If the faulting instruction was ARM
237 @ the PC will be pointing at the next instruction, and have to
239 @ pointing at the second half of the Thumb instruction. We
250 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
259 @ the instruction, or the more conventional lr if we are to treat
260 @ this as a real undefined instruction
262 @ r0 - instruction
268 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
269 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
[all …]
Dentry-common.S154 USER( ldreq r10, [lr, #-4] ) @ get SWI instruction
156 USER( ldr r10, [lr, #-4] ) @ get SWI instruction
158 ARM_BE8(rev r10, r10) @ little endian instruction
173 USER( ldr scno, [lr, #-4] ) @ get SWI instruction
Dswp_emulate.c67 #define EXTRACT_REG_NUM(instruction, offset) \ argument
68 (((instruction) & (0xf << (offset))) >> (offset))
/linux-4.1.27/drivers/gpu/drm/sti/
Dsti_awg_utils.c29 u32 instruction = 0; in awg_generate_instr() local
109 instruction = ((opcode) << AWG_OPCODE_OFFSET) | arg; in awg_generate_instr()
111 instruction & (0x3fff); in awg_generate_instr()
/linux-4.1.27/arch/powerpc/xmon/
Dppc.h179 (unsigned long instruction, long op, int dialect, const char **errmsg);
198 long (*extract) (unsigned long instruction, int dialect, int *invalid);
/linux-4.1.27/arch/m68k/ifpsp060/
DCHANGES41 3) For an opclass three FP instruction where the effective addressing
62 next instruction, and the result created in fp0 will be
78 For instruction read access errors, the info stacked is:
80 PC = PC of instruction being emulated
82 ADDRESS = PC of instruction being emulated
102 PC = PC of instruction being emulated
Dilsp.doc35 and the "cmp2" instruction. These instructions are not
71 function. A branch instruction located at the selected entry point
78 For example, to use a 64-bit multiply instruction,
115 An example of using the "cmp2" instruction is as follows:
128 If the instruction being emulated is a divide and the source
130 instruction, executes an implemented divide using a zero
133 point to the correct instruction, the user will at least be able
Dfskeleton.S111 | instruction.
130 | instruction.
149 | instruction.
168 | instruction.
189 | bit in the FPSR, and does an "rte". The instruction that caused the
227 | frame to the PC of the instruction causing the exception, and does an "rte".
228 | The execution of the instruction then proceeds with an enabled floating-point
245 | This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction
Dos.S107 | Reads from data/instruction memory while in supervisor mode.
174 | Read an instruction word from user memory.
180 | d0 - instruction word in d0
210 | Read an instruction longword from user memory.
216 | d0 - instruction longword in d0
Diskeleton.S63 | the PC pointing to the instruction following the instruction
65 | To simply continue execution at the next instruction, just
85 | Instruction exception handler. If the instruction was a "chk2"
120 | Instruction exception handler isp_unimp(). If the instruction is a 64-bit
Dfplsp.doc72 function. A branch instruction located at the selected entry point
79 There are 3 entry-points for each instruction type: single precision,
82 As an example, the "fsin" library instruction can be passed an
111 For example, if the instruction being emulated should cause a
127 the instruction but rather simply executes it.
Disp.doc179 After the 060ISP decodes the instruction type and fetches the appropriate
/linux-4.1.27/arch/powerpc/lib/
Dcode-patching.c38 unsigned int instruction; in create_branch() local
50 instruction = 0x48000000 | (flags & 0x3) | (offset & 0x03FFFFFC); in create_branch()
52 return instruction; in create_branch()
58 unsigned int instruction; in create_cond_branch() local
70 instruction = 0x40000000 | (flags & 0x3FF0003) | (offset & 0xFFFC); in create_cond_branch()
72 return instruction; in create_cond_branch()
/linux-4.1.27/drivers/scsi/aic7xxx/aicasm/
Daicasm.c100 static STAILQ_HEAD(,instruction) seq_program;
322 struct instruction *cur_instr; in back_patch()
351 struct instruction *cur_instr; in output_code()
524 struct instruction *cur_instr; in output_listing()
732 struct instruction *
735 struct instruction *new_instr; in seq_alloc()
737 new_instr = (struct instruction *)malloc(sizeof(struct instruction)); in seq_alloc()
Daicasm_insformat.h167 struct instruction { struct
171 STAILQ_ENTRY(instruction) links; argument
Daicasm.h92 struct instruction *seq_alloc(void);
Daicasm_gram.y1653 struct instruction *instr; in format_1_instr()
1730 struct instruction *instr; in format_2_instr()
1791 struct instruction *instr; in format_3_instr()
/linux-4.1.27/arch/arm/mm/
Dabort-lv4t.S28 ldr r8, [r4] @ read arm instruction
71 and r9, r8, #15 << 16 @ Extract 'n' from instruction
89 and r9, r8, #15 << 16 @ Extract 'n' from instruction
103 and r9, r8, #15 << 16 @ Extract 'n' from instruction
115 and r7, r8, #15 @ Extract 'm' from instruction
157 ldrh r8, [r4] @ read instruction
Dabort-ev4.S21 ldr r3, [r4] @ read aborted ARM instruction
Dabort-ev4t.S23 ldreq r3, [r4] @ read aborted ARM instruction
Dabort-ev5t.S23 ldreq r3, [r4] @ read aborted ARM instruction
Dabort-ev5tj.S26 ldreq r3, [r4] @ read aborted ARM instruction
Dabort-macro.S15 ldrh \tmp, [\pc] @ Read aborted Thumb instruction
Dabort-ev6.S34 ldr r3, [r4] @ read aborted ARM instruction
DKconfig4 # which CPUs we support in the kernel image, and the compiler instruction
103 instruction and data caches. It is used in Altera's
122 different instruction and data caches. It is used in TI's OMAP
140 instruction sequences for cache and TLB operations. Curiously,
176 instruction and 4KB data cases, each with a 4-word line
194 The TCM and ARMv5TE 32-bit instruction set is supported.
418 # This defines the compiler instruction set which depends on the machine type.
554 instruction cache entry.
565 and invalidate instruction cache entry. Branch target buffer is
645 The Thumb instruction set is a compressed form of the standard ARM
[all …]
Dproc-xscale.S74 sub pc, pc, #4 @ flush instruction pipeline
80 @ flush instruction pipeline
Dproc-arm940.S289 mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
/linux-4.1.27/arch/mips/bcm47xx/
DKconfig18 This will generate an image with support for SSB and MIPS32 R1 instruction set.
35 This will generate an image with support for BCMA and MIPS32 R2 instruction set.
/linux-4.1.27/Documentation/virtual/kvm/
Dhypercalls.txt5 instruction. The hypervisor can replace it with instructions that are
17 S390 uses diagnose instruction as hypercall (0x500) along with hypercall
78 execute HLT instruction once it has busy-waited for more than a threshold
79 time-interval. Execution of HLT instruction would cause the hypervisor to put
Dppc-pv.txt75 instruction reads the first field of the magic page:
137 guest. Implementing any of those mappings is optional, as the instruction traps
179 or store instruction can deliver. To enable patching of those, we keep some
184 2) patch that code to fit the emulated instruction
186 4) patch the original instruction to branch to the new code
189 instruction. This allows us to check for pending interrupts when setting EE=1
Ds390-diag.txt45 Upon completion of the DIAGNOSE instruction, general register 2 contains
Dtimekeeping.txt315 instruction cycles issued by the processor, which can be used as a measure of
331 Some vendors have implemented an additional instruction, RDTSCP, which returns
335 The presence of this instruction must be determined by consulting CPUID feature
452 X86_FEATURE_RDTSCP : The RDTSCP instruction is available
514 This is a consequence of the superscalar execution of the instruction stream,
517 measurement with the TSC, and requires a serializing instruction, such as CPUID
Dapi.txt78 Architectures: which instruction set architectures provide this ioctl.
511 Defines the vcpu responses to the cpuid instruction. Applications
1019 - KVM_MP_STATE_HALTED: the vcpu has executed a HLT instruction and
1213 The entries returned are the host cpuid as returned by the cpuid instruction,
1231 eax, ebx, ecx, edx: the values returned by the cpuid instruction for
2253 be OR'ed into the "vsid" argument of the slbmte instruction.
2735 which kvm emulates, as returned by the CPUID instruction, with unknown
2757 eax, ebx, ecx, edx: the values returned by the cpuid instruction for
3068 executed a port I/O instruction which could not be satisfied by kvm.
3088 executed a memory-mapped I/O instruction which could not be satisfied
[all …]
Dmmu.txt94 - invlpg/invlpga instruction execution
253 guest cr3. In this case, the guest is obliged to issue an invlpg instruction
305 - emulate the instruction
307 - update any translations that were modified by the instruction
/linux-4.1.27/arch/arm/vfp/
Dentry.S20 @ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
24 @ lr = unrecognised instruction return address
Dvfphw.S74 @ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
79 @ lr = unrecognised instruction return address
/linux-4.1.27/Documentation/devicetree/bindings/nios2/
Dnios2.txt18 - icache-line-size: Contains instruction line size.
20 - icache-size: Contains instruction cache size.
28 - altr,has-initda: Specifies CPU support initda instruction, should be 1.
/linux-4.1.27/drivers/acpi/apei/
Dapei-base.c183 if (entry->instruction >= ctx->instructions || in __apei_exec_run()
184 !ctx->ins_table[entry->instruction].run) { in __apei_exec_run()
187 entry->instruction); in __apei_exec_run()
190 run = ctx->ins_table[entry->instruction].run; in __apei_exec_run()
222 ins = entry->instruction; in apei_exec_for_each_entry()
243 u8 ins = entry->instruction; in pre_map_gar_callback()
276 u8 ins = entry->instruction; in post_unmap_gar_callback()
721 u8 ins = entry->instruction; in collect_res_callback()
Deinj.c225 entry->instruction == ACPI_EINJ_WRITE_REGISTER && in einj_get_parameter_address()
230 entry->instruction == ACPI_EINJ_WRITE_REGISTER && in einj_get_parameter_address()
288 entry->instruction == ACPI_EINJ_WRITE_REGISTER_VALUE && in einj_get_trigger_parameter_region()
/linux-4.1.27/net/nfc/nci/
Dhci.c374 u8 type, u8 instruction, struct sk_buff *skb) in nci_hci_hcp_message_rx() argument
378 nci_hci_resp_received(ndev, pipe, instruction, skb); in nci_hci_hcp_message_rx()
381 nci_hci_cmd_received(ndev, pipe, instruction, skb); in nci_hci_hcp_message_rx()
384 nci_hci_event_received(ndev, pipe, instruction, skb); in nci_hci_hcp_message_rx()
388 type, instruction); in nci_hci_hcp_message_rx()
402 u8 pipe, type, instruction; in nci_hci_msg_rx_work() local
409 instruction = NCI_HCP_MSG_GET_CMD(message->header); in nci_hci_msg_rx_work()
413 type, instruction, skb); in nci_hci_msg_rx_work()
/linux-4.1.27/Documentation/parisc/
Dregisters58 N (Nullify next instruction) used by C code
83 Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce
99 r1: The addil instruction is hardwired to place its result in r1,
100 so if you use that instruction be aware of that.
122 r31: the ble instruction puts the return pointer in here.
Ddebugging34 was interrupted - so if you get an interruption between the instruction
37 instruction that cleared the Q bit, if you're not it points anywhere
/linux-4.1.27/Documentation/arm/
Dswp_emulation1 Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE)
8 instructions, triggering an undefined instruction exception when executed.
Dkernel_mode_neon.txt35 instruction is issued, allowing the kernel to step in and perform the restore if
69 software assistance, it signals the kernel by raising an undefined instruction
71 current instruction and arguments, and emulates the instruction in software.
DBooting212 directly to the first instruction of the kernel image.
214 On CPUs supporting the ARM instruction set, the entry must be
217 On CPUs supporting only the Thumb instruction set such as
Dmem_alignment34 process name, pid, pc, instruction, address, and the
Dtcm.txt10 Harvard-architecture, so there is an ITCM (instruction TCM)
Dkernel_user_helpers.txt11 the available instruction set, or whether it is a SMP systems. In other
/linux-4.1.27/arch/xtensa/kernel/
Dalign.S212 __src_b a4, a4, a5 # a4 has the instruction
347 1: # a7: instruction pointer, a4: instruction, a3: value
352 addi a7, a7, 2 # incr. PC,assume 16-bit instruction
358 addi a7, a7, 1 # increment PC, 32-bit instruction
360 addi a7, a7, 3 # increment PC, 32-bit instruction
422 1: wsr a7, epc1 # skip emulated instruction
Dsignal.c297 # error Generating the MOVI instruction below breaks! in gen_return_code()
/linux-4.1.27/arch/unicore32/mm/
DKconfig4 # which CPUs we support in the kernel image, and the compiler instruction
15 Say Y here to disable the processor instruction cache. Unless
/linux-4.1.27/arch/s390/kernel/
Dmcount.S54 # The j instruction gets runtime patched to a nop instruction.
Dhead64.S50 .quad 0 # cr3: instruction authorization
51 .quad 0 # cr4: instruction authorization
/linux-4.1.27/arch/unicore32/kernel/
Dentry.S290 @ restore BSR and restart the instruction
338 @ r0 - address of faulting instruction
341 mov r0, r2 @ pass address of aborted instruction
353 @ restore BSR and restart the instruction
377 @ it has emulated the instruction, or the more conventional lr
378 @ if we are to treat this as a real extended instruction
380 @ r0 - instruction
410 @ r0 = faulted instruction
422 @ r0 holds the trigger instruction
476 mov r0, r2 @ pass address of aborted instruction.
[all …]
/linux-4.1.27/arch/s390/kvm/
Dtrace.h156 __field(__u64, instruction)
161 __entry->instruction = ((__u64)ipa << 48) |
166 __entry->instruction,
167 __print_symbolic(icpt_insn_decoder(__entry->instruction),
/linux-4.1.27/Documentation/mn10300/
DABI.txt39 it inserts a CALL instruction. The CALL instruction will write into the TOS
41 instruction reads from the TOS word of the stack, but doesn't move the stack
149 instruction stores registers onto the stack.
/linux-4.1.27/drivers/scsi/
Dscript_asm.pl709 $instruction = $1;
711 if ($instruction =~ /JUMP/i) {
713 } elsif ($instruction =~ /CALL/i) {
752 $instruction = $1;
754 print STDERR "Parsing $instruction\n" if ($debug);
755 $code[$address] = ($instruction =~ /RETURN/i) ? 0x90_00_00_00 :
/linux-4.1.27/arch/ia64/scripts/
Dcheck-serialize.S2 .serialize.instruction
/linux-4.1.27/Documentation/networking/
Dfilter.txt169 BPF engine and instruction set
193 The element op is a 16 bit wide opcode that has a particular instruction
197 ways depending on the given instruction in op.
199 The instruction set consists of load, store, branch, alu, miscellaneous
429 code: [40] jt[0] jf[0] k[12] <-- plain BPF code of current instruction
430 curr: l0: ldh [12] <-- disassembly of current instruction
450 on the next BPF instruction, thus +1. (No `run` needs to be issued here.)
565 Internally, for the kernel interpreter, a different instruction set
567 paragraphs is being used. However, the instruction set format is modelled
568 closer to the underlying architecture to mimic native instruction sets, so
[all …]
/linux-4.1.27/arch/mips/dec/prom/
Dlocore.S26 addiu k0, 4 # skip the causing instruction
/linux-4.1.27/arch/s390/include/asm/
Ddis.h45 int insn_to_mnemonic(unsigned char *instruction, char *buf, unsigned int len);
/linux-4.1.27/drivers/media/usb/gspca/m5602/
Dm5602_sensor.h38 enum instruction { enum
/linux-4.1.27/Documentation/x86/
Dtlb.txt3 1. Flush the entire TLB with a two-instruction sequence. This is
7 2. Use the invlpg instruction to invalidate a single page at a
34 invlpg instruction (or instructions _near_ it) show up high in
Dentry_64.txt19 - system_call: syscall instruction from 64-bit code.
47 Dealing with the swapgs instruction is especially tricky. Swapgs
49 instruction is rather fragile: it must nest perfectly and only in
Dintel_mpx.txt35 starts. New instruction prefixes are noops for old CPUs.
52 issues a bndstx instruction. Since the bounds directory is empty at
194 When a BNDSTX instruction attempts to save bounds to a bounds directory
217 directory. So kernel have to use XSAVE instruction to get the base
233 directory at them through XSAVE instruction, and then set valid bit
Dexception-tables.txt45 There it uses the address of the instruction that caused the exception
239 backward) is the address of the instruction that might fault, i.e.
277 instruction immediately after the faulting user access).
279 The steps 8a to 8c in a certain way emulate the faulting instruction.
Dusb-legacy-support.txt43 on the HLT instruction as well.
/linux-4.1.27/arch/x86/kernel/kprobes/
Dcommon.h70 extern int can_boost(kprobe_opcode_t *instruction);
/linux-4.1.27/arch/cris/arch-v32/kernel/
Dhead.S56 ;; and the instruction MMU.
59 ;; bank 1 is the instruction MMU, bank 2 is the data MMU.
133 ;; Update instruction MMU.
151 ;; Enable data and instruction MMU.
/linux-4.1.27/arch/x86/math-emu/
DREADME82 emulate each FPU instruction to completion without interruption.
134 The FPU instruction may be (usually will be) loaded into the pre-fetch
135 queue of the CPU before the mov instruction is executed. If the
136 destination of the 'movl' overlaps the FPU instruction then the bytes
138 instruction is executed. The emulator will be invoked but will not be
139 able to find the instruction which caused the device-not-present
165 upon instruction mix. Relative performance is best for the instructions
167 affected by the FPU instruction trap overhead.
343 the same). The total number of tests for each instruction are given
354 positive argument, this shows that this instruction gives better
/linux-4.1.27/arch/blackfin/
DKconfig755 into L1 instruction memory. (less latency)
763 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
772 into L1 instruction memory. (less latency)
780 into L1 instruction memory. (less latency)
788 into L1 instruction memory. (less latency)
796 into L1 instruction memory. (less latency)
804 into L1 instruction memory. (less latency)
812 into L1 instruction memory. (less latency)
820 into L1 instruction memory. (less latency)
828 into L1 instruction memory. (less latency)
[all …]
DKconfig.debug60 instruction address is stored in RETX, where the next kernel
64 - The excepting instruction is not committed.
65 - All writebacks from the instruction are prevented.
70 this option, you are skipping over the faulting instruction, and
111 path of how it got to the offending instruction.
/linux-4.1.27/arch/arm/lib/
Dbacktrace.S72 teq r3, r2, lsr #10 @ instruction
89 ldr r3, .Ldsi @ instruction exists,
/linux-4.1.27/Documentation/frv/
Dkernel-ABI.txt176 instruction is really fast. This use of the ICC2 only occurs within the
200 unlikely BEQ instruction.
210 A TIHI #2 instruction (trap #2 if condition HI - Z==0 && C==0) would
236 A TIHI #2 instruction would be used to again assay the current state,
244 A TIHI #2 instruction again issued to assay the current state would
Datomic-ops.txt6 instruction. Unfortunately, this alone can't be used to implement the following operations:
27 the LL/SC instruction pairs supported on a number of platforms.
Dfeatures.txt138 Userspace EFAULT errors can be trapped by issuing a MEMBAR instruction and
152 (2) Breakpoint via the FR-V "BREAK" instruction.
154 (3) Breakpoint via the FR-V "TIRA GR0, #1" instruction.
Dconfiguring.txt22 The register and instruction sets at the core of the processor. This can
Dgdbstub.txt121 (*) Setting a software breakpoint. This sets a break instruction at the
/linux-4.1.27/lib/raid6/
Daltivec.uc16 * $#-way unrolled portable integer math RAID-6 instruction set
35 * instruction.
Dneon.uc21 * $#-way unrolled NEON intrinsics math RAID-6 instruction set
Dint.uc16 * $#-way unrolled portable integer math RAID-6 instruction set
/linux-4.1.27/arch/unicore32/lib/
Dbacktrace.S67 cxor.a r3, r2 >> #14 @ instruction
87 ldw r3, .Ldsi @ instruction exists,
/linux-4.1.27/arch/m68k/math-emu/
Dfp_util.S57 | illegal instruction
61 | completed instruction
Dfp_entry.S60 | emulate the instruction
112 | instruction decoding, otherwise the stack pointer is incorrect
Dfp_scan.S64 | normal fpu instruction? (this excludes fsave/frestore)
74 | first two instruction words are kept in %d2
/linux-4.1.27/arch/ia64/include/asm/
Dasmmacro.h129 # define dv_serialize_instruction .serialize.instruction
/linux-4.1.27/arch/powerpc/platforms/
DKconfig.cputype277 bool "Support for PowerPC icswx coprocessor instruction"
283 Coprocessor Store Word (icswx) coprocessor instruction on POWER7
287 the icswx coprocessor instruction. It does not have any effect
288 on processors without the icswx coprocessor instruction.
308 illegal instruction signal or should it be silent as
/linux-4.1.27/drivers/staging/slicoss/
Dslicoss.c378 u32 instruction; in slic_card_download_gbrcv() local
423 instruction = *(u32 *)(fw->data + index); in slic_card_download_gbrcv()
426 slic_reg32_write(&slic_regs->slic_rcv_wcs, instruction, FLUSH); in slic_card_download_gbrcv()
428 instruction = *(u8 *)(fw->data + index); in slic_card_download_gbrcv()
431 slic_reg32_write(&slic_regs->slic_rcv_wcs, (u8)instruction, in slic_card_download_gbrcv()
453 u32 instruction; in slic_card_download() local
488 instruction = *(u32 *)(fw->data + index); in slic_card_download()
500 instruction, FLUSH); in slic_card_download()
501 instruction = *(u32 *)(fw->data + index); in slic_card_download()
506 instruction, FLUSH); in slic_card_download()
[all …]
/linux-4.1.27/Documentation/ia64/
Dfsys.txt12 Using the "epc" instruction effectively introduces a new mode of
129 o Fsyscall-handlers MUST NOT use the "alloc" instruction or perform
172 "br.ret" instruction that lowers the privilege level, a trap will
178 The "epc" instruction doesn't change the contents of PSR at all. This
184 PSR.be Cleared when entering fsys-mode. A srlz.d instruction is used
186 load/store instruction is executed. PSR.be is normally NOT
/linux-4.1.27/scripts/
Ddecodecode84 echo Code starting with the faulting instruction > $T.aa
/linux-4.1.27/arch/m68k/
DKconfig.cpu9 the full 68000 processor instruction set.
14 processor instruction set.
327 needs to be executed whether a floating-point instruction in the
456 Use all of the ColdFire CPU cache memory as an instruction cache.
466 Split the ColdFire CPU cache, and use half as an instruction cache
/linux-4.1.27/arch/ia64/hp/sim/boot/
Dbootloader.lds19 /* We want the small data sections together, so single-instruction offsets
/linux-4.1.27/Documentation/prctl/
Dseccomp_filter.txt99 will show the address of the system call instruction, and
103 instruction). The return value register will contain an arch-
197 'syscall' instruction. Any code which wants to restart the call
198 should be aware that (a) a ret instruction has been emulated and (b)
/linux-4.1.27/arch/mips/kvm/
D00README.txt25 LL/TLBP/SC. Since the TLBP instruction causes a trap the reservation gets cleared
/linux-4.1.27/arch/score/kernel/
Dentry.S122 ENTRY(handle_adelinsn) # AdEL-instruction #2
135 ENTRY(handle_ibe) # BusEL-instruction #5
180 ENTRY(handle_adedata) # AdES-instruction #12
/linux-4.1.27/arch/alpha/lib/
Dev6-memset.S138 addq $5, 8, $4 # E : Initial wh64 address (filler instruction)
315 addq $5, 8, $4 # E : Initial wh64 address (filler instruction)
502 addq $5, 8, $4 # E : Initial wh64 address (filler instruction)
/linux-4.1.27/Documentation/xtensa/
Datomctl.txt2 This register determines the effect of using a S32C1I instruction
Dmmu.txt32 that corresponds to next instruction to execute in this code.
/linux-4.1.27/Documentation/devicetree/bindings/arm/msm/
Dqcom,idle-state.txt14 When the WFI instruction is executed the ARM core would gate its internal
15 clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
/linux-4.1.27/crypto/
DKconfig358 instruction. This option will create 'crc32c-intel' module,
359 which will enable any routine to use the CRC32 instruction to
389 instruction. This option will create 'crc32-plcmul' module,
408 accelerated PCLMULQDQ instruction. This option will create
587 using powerpc SPE SIMD instruction set.
624 implemented using powerpc SPE SIMD instruction set.
1034 sixteen blocks parallel using the AVX instruction set.
1060 eight blocks parallel using the AVX instruction set.
1192 blocks parallel using SSE2 instruction set.
1214 blocks parallel using SSE2 instruction set.
[all …]
/linux-4.1.27/Documentation/powerpc/
Dtransactional_memory.txt45 The 'tbegin' instruction denotes the start point, and 'tend' the end point.
123 determine, for example, the address of the instruction causing the SIGSEGV.
141 "crashy instruction was at 0x%llx\n",
Dcpu_features.txt10 split instruction and data caches, and if the CPU supports the DOZE and NAP
/linux-4.1.27/Documentation/cpu-freq/
Damd-powernow.txt14 is detected with the cpuid instruction.
/linux-4.1.27/arch/parisc/kernel/
Dperf_asm.S154 blr %r1,%r0 ; branch to 8-instruction sequence
1356 ;* Then the STDIAG instruction for the RDR # in arg0 is called
1391 blr %r1,%r0 ; branch to 8-instruction sequence
/linux-4.1.27/tools/perf/Documentation/
Dperf-annotate.txt78 Show raw instruction encoding of assembly instructions.
Dperf-report.txt259 Show raw instruction encoding of assembly instructions.
271 Use the addresses of sampled taken branches instead of the instruction
298 Use the data addresses of samples in addition to instruction addresses
Dperf-trace.txt132 - ip.symbol shows symbol for instruction pointer (the code that generated the
Dperf-list.txt36 The 'p' modifier can be used for specifying how precise the instruction
Dperf-top.txt158 Show raw instruction encoding of assembly instructions.
/linux-4.1.27/drivers/hwtracing/coresight/
DKconfig59 This is primarily useful for instruction level tracing. Depending
/linux-4.1.27/arch/sh/include/asm/
Duaccess.h208 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
/linux-4.1.27/arch/parisc/math-emu/
Dfloat.h477 #define Set_exceptiontype_and_instr_field(exception,instruction,object) \
478 object = exception << 26 | instruction
/linux-4.1.27/arch/mn10300/mm/
Dcache.inc15 # Invalidate the instruction cache.
/linux-4.1.27/arch/sh/
DKconfig.cpu73 This enables support for a speculative instruction fetch for
DKconfig.debug56 the faulting instruction as a debugging aid. As this does grow
/linux-4.1.27/arch/x86/
DKconfig.debug190 bool "x86 instruction decoder selftest"
194 Perform x86 instruction decoder selftests at build time.
195 This option is useful for checking the sanity of x86 instruction
DKconfig.cpu55 assume the RDTSC (Read Time Stamp Counter) instruction.
62 Time Stamp Counter) instruction for benchmarking.
/linux-4.1.27/Documentation/s390/
DDebugging390.txt76 in a single instruction. To change address translation,
177 z/Architecture in absolute storage by the set prefix instruction during Linux
271 the mvcos instruction is not available or if a compare-and-swap (futex)
272 instruction on a user space address is performed.
292 e.g. the mvcp instruction to access user space. However the kernel
293 will stay in home space mode if the mvcos instruction is available
299 to contain the gmap asce before the SIE instruction gets executed. When
300 the SIE instruction is finished, cr1 will be switched back to contain the
600 4) The basr ( branch relative & save ) trick works as follows the instruction
601 has a special case with r0,r0 with some instruction operands is understood as
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/arm/
Dpsci.txt18 Note that the immediate field of the trapping instruction must be set
/linux-4.1.27/arch/sh/include/mach-kfr2r09/mach/
Dpartner-jet-setup.txt19 LIST "invalidate instruction cache"
/linux-4.1.27/arch/arm64/
DKconfig343 write instruction at the same time as a processor in another
422 order to avoid the use of the ADRP instruction, which can cause
663 bool "Emulate SETEND instruction"
665 The SETEND instruction alters the data-endianness of the
668 Say Y here to enable software emulation of the instruction
/linux-4.1.27/Documentation/filesystems/
Dspufs.txt153 with the numeric value of the next instruction to be executed. These
298 uled to a physical SPU, it starts execution at the instruction pointer
307 When spu_run returns, the current value of the SPU instruction pointer
331 optionally a 14 bit code returned from the stop-and-signal instruction
342 0x20 SPU has tried to execute an invalid instruction.
/linux-4.1.27/Documentation/trace/
Dmmiotrace.txt111 fault handler. The instruction that faulted is executed and debug trap is
112 entered. Here mmiotrace again marks the page as not present. The instruction
Dcoresight.txt21 "Sources" generate a compressed stream representing the processor instruction
212 comparator with "_stext" and "_etext", essentially tracing any instruction
Duprobetracer.txt91 Following example shows how to dump the instruction pointer and %ax register
Dftrace-design.txt355 people will be using a "call" type instruction while others will be using a
356 "branch" type instruction. Specifically, the function is:
/linux-4.1.27/arch/metag/lib/
Ddivsi3.S71 !! Calculate alignment using FFB instruction
/linux-4.1.27/arch/c6x/
DKconfig42 The C6X function call instruction has a limited range of +/- 2MiB.
/linux-4.1.27/tools/perf/util/
Dparse-events.l211 L1-icache|l1-i|l1i|L1-instruction |
/linux-4.1.27/arch/cris/arch-v10/kernel/
Dentry.S117 ;; The system_call is called by a BREAK instruction, which works like
435 move $brp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame
591 subq 2, $r0 ; Set to address of previous instruction.
/linux-4.1.27/Documentation/acpi/apei/
Doutput_format.txt55 instruction execution
/linux-4.1.27/arch/
DKconfig63 instruction. When the condition flag is toggled to true, the
64 nop will be converted to a jump instruction to execute the
250 some of them have separate registers for data and instruction
/linux-4.1.27/arch/arm/include/asm/
Dassembler.h366 @ explicit IT instruction needed because of the label
/linux-4.1.27/arch/arm/mach-omap1/
Dsleep.S108 @ disable instruction cache
/linux-4.1.27/drivers/clocksource/
DKconfig120 the wfe instruction at a frequency represented as a power-of-2
/linux-4.1.27/include/acpi/
Dactbl1.h110 u8 instruction; member
Dactbl2.h1178 u8 instruction; member
/linux-4.1.27/arch/mips/kernel/
Dscall64-64.S46 daddiu t1, 4 # skip to next instruction
Dscall64-n32.S40 daddiu t1, 4 # skip to next instruction
/linux-4.1.27/arch/frv/mm/
Dtlb-miss.S122 # Kernel instruction TLB miss handler
/linux-4.1.27/arch/m32r/mm/
Dmmu.S40 bnez r1, 1f ; instruction TLB miss?
/linux-4.1.27/arch/metag/
DKconfig167 This option uses the LOCK1 instruction for atomicity. This is mainly
/linux-4.1.27/arch/microblaze/
DKconfig195 If non-zero, a jump instruction to this address, will be written
/linux-4.1.27/drivers/net/ppp/
DKconfig129 which contains instruction on how to use this driver (under
/linux-4.1.27/arch/arm/
DKconfig1017 instruction
1023 Executing a SWP instruction to read-only memory does not set bit 11
1063 the L1 caching of the NEON accesses and disables the PLD instruction
1086 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1090 instruction to behave as a DSB, ensuring the correct behaviour of
1200 system. This workaround adds a DSB instruction before the
1724 cores where a 8-word STM instruction give significantly higher

12