1This file documents some of the kernel entries in
2arch/x86/kernel/entry_64.S.  A lot of this explanation is adapted from
3an email from Ingo Molnar:
4
5http://lkml.kernel.org/r/<20110529191055.GC9835%40elte.hu>
6
7The x86 architecture has quite a few different ways to jump into
8kernel code.  Most of these entry points are registered in
9arch/x86/kernel/traps.c and implemented in arch/x86/kernel/entry_64.S
10for 64-bit, arch/x86/kernel/entry_32.S for 32-bit and finally
11arch/x86/ia32/ia32entry.S which implements the 32-bit compatibility
12syscall entry points and thus provides for 32-bit processes the
13ability to execute syscalls when running on 64-bit kernels.
14
15The IDT vector assignments are listed in arch/x86/include/asm/irq_vectors.h.
16
17Some of these entries are:
18
19 - system_call: syscall instruction from 64-bit code.
20
21 - ia32_syscall: int 0x80 from 32-bit or 64-bit code; compat syscall
22   either way.
23
24 - ia32_syscall, ia32_sysenter: syscall and sysenter from 32-bit
25   code
26
27 - interrupt: An array of entries.  Every IDT vector that doesn't
28   explicitly point somewhere else gets set to the corresponding
29   value in interrupts.  These point to a whole array of
30   magically-generated functions that make their way to do_IRQ with
31   the interrupt number as a parameter.
32
33 - APIC interrupts: Various special-purpose interrupts for things
34   like TLB shootdown.
35
36 - Architecturally-defined exceptions like divide_error.
37
38There are a few complexities here.  The different x86-64 entries
39have different calling conventions.  The syscall and sysenter
40instructions have their own peculiar calling conventions.  Some of
41the IDT entries push an error code onto the stack; others don't.
42IDT entries using the IST alternative stack mechanism need their own
43magic to get the stack frames right.  (You can find some
44documentation in the AMD APM, Volume 2, Chapter 8 and the Intel SDM,
45Volume 3, Chapter 6.)
46
47Dealing with the swapgs instruction is especially tricky.  Swapgs
48toggles whether gs is the kernel gs or the user gs.  The swapgs
49instruction is rather fragile: it must nest perfectly and only in
50single depth, it should only be used if entering from user mode to
51kernel mode and then when returning to user-space, and precisely
52so. If we mess that up even slightly, we crash.
53
54So when we have a secondary entry, already in kernel mode, we *must
55not* use SWAPGS blindly - nor must we forget doing a SWAPGS when it's
56not switched/swapped yet.
57
58Now, there's a secondary complication: there's a cheap way to test
59which mode the CPU is in and an expensive way.
60
61The cheap way is to pick this info off the entry frame on the kernel
62stack, from the CS of the ptregs area of the kernel stack:
63
64	xorl %ebx,%ebx
65	testl $3,CS+8(%rsp)
66	je error_kernelspace
67	SWAPGS
68
69The expensive (paranoid) way is to read back the MSR_GS_BASE value
70(which is what SWAPGS modifies):
71
72	movl $1,%ebx
73	movl $MSR_GS_BASE,%ecx
74	rdmsr
75	testl %edx,%edx
76	js 1f   /* negative -> in kernel */
77	SWAPGS
78	xorl %ebx,%ebx
791:	ret
80
81If we are at an interrupt or user-trap/gate-alike boundary then we can
82use the faster check: the stack will be a reliable indicator of
83whether SWAPGS was already done: if we see that we are a secondary
84entry interrupting kernel mode execution, then we know that the GS
85base has already been switched. If it says that we interrupted
86user-space execution then we must do the SWAPGS.
87
88But if we are in an NMI/MCE/DEBUG/whatever super-atomic entry context,
89which might have triggered right after a normal entry wrote CS to the
90stack but before we executed SWAPGS, then the only safe way to check
91for GS is the slower method: the RDMSR.
92
93Therefore, super-atomic entries (except NMI, which is handled separately)
94must use idtentry with paranoid=1 to handle gsbase correctly.  This
95triggers three main behavior changes:
96
97 - Interrupt entry will use the slower gsbase check.
98 - Interrupt entry from user mode will switch off the IST stack.
99 - Interrupt exit to kernel mode will not attempt to reschedule.
100
101We try to only use IST entries and the paranoid entry code for vectors
102that absolutely need the more expensive check for the GS base - and we
103generate all 'normal' entry points with the regular (faster) paranoid=0
104variant.
105